forked from dolphin-emu/dolphin
140 lines
3.3 KiB
C++
140 lines
3.3 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "Common/Common.h"
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class PointerWrap;
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namespace MMIO { class Mapping; }
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extern volatile bool g_bSkipCurrentFrame;
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extern u8* g_pVideoData;
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namespace SWCommandProcessor
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{
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// internal hardware addresses
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enum
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{
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STATUS_REGISTER = 0x00,
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CTRL_REGISTER = 0x02,
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CLEAR_REGISTER = 0x04,
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FIFO_TOKEN_REGISTER = 0x0E,
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FIFO_BOUNDING_BOX_LEFT = 0x10,
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FIFO_BOUNDING_BOX_RIGHT = 0x12,
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FIFO_BOUNDING_BOX_TOP = 0x14,
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FIFO_BOUNDING_BOX_BOTTOM = 0x16,
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FIFO_BASE_LO = 0x20,
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FIFO_BASE_HI = 0x22,
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FIFO_END_LO = 0x24,
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FIFO_END_HI = 0x26,
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FIFO_HI_WATERMARK_LO = 0x28,
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FIFO_HI_WATERMARK_HI = 0x2a,
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FIFO_LO_WATERMARK_LO = 0x2c,
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FIFO_LO_WATERMARK_HI = 0x2e,
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FIFO_RW_DISTANCE_LO = 0x30,
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FIFO_RW_DISTANCE_HI = 0x32,
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FIFO_WRITE_POINTER_LO = 0x34,
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FIFO_WRITE_POINTER_HI = 0x36,
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FIFO_READ_POINTER_LO = 0x38,
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FIFO_READ_POINTER_HI = 0x3A,
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FIFO_BP_LO = 0x3C,
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FIFO_BP_HI = 0x3E
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};
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// Fifo Status Register
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union UCPStatusReg
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{
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struct
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{
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u16 OverflowHiWatermark : 1;
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u16 UnderflowLoWatermark : 1;
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u16 ReadIdle : 1; // done reading
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u16 CommandIdle : 1; // done processing commands
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u16 Breakpoint : 1;
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u16 : 11;
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};
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u16 Hex;
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UCPStatusReg() {Hex = 0; }
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UCPStatusReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPCtrlReg
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{
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struct
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{
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u16 GPReadEnable : 1;
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u16 BPEnable : 1;
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u16 FifoOverflowIntEnable : 1;
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u16 FifoUnderflowIntEnable : 1;
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u16 GPLinkEnable : 1;
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u16 BreakPointIntEnable : 1;
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u16 : 10;
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};
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u16 Hex;
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UCPCtrlReg() {Hex = 0; }
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UCPCtrlReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPClearReg
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{
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struct
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{
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u16 ClearFifoOverflow : 1;
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u16 ClearFifoUnderflow : 1;
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u16 ClearMetrices : 1;
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u16 : 13;
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};
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u16 Hex;
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UCPClearReg() {Hex = 0; }
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UCPClearReg(u16 _hex) {Hex = _hex; }
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};
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struct CPReg
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{
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UCPStatusReg status; // 0x00
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UCPCtrlReg ctrl; // 0x02
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UCPClearReg clear; // 0x04
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u32 unk0; // 0x08
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u16 unk1; // 0x0c
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u16 token; // 0x0e
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u16 bboxleft; // 0x10
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u16 bboxtop; // 0x12
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u16 bboxright; // 0x14
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u16 bboxbottom; // 0x16
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u32 unk2; // 0x18
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u32 unk3; // 0x1c
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u32 fifobase; // 0x20
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u32 fifoend; // 0x24
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u32 hiwatermark; // 0x28
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u32 lowatermark; // 0x2c
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u32 rwdistance; // 0x30
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u32 writeptr; // 0x34
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u32 readptr; // 0x38
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u32 breakpt; // 0x3c
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};
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extern CPReg cpreg;
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// Init
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void Init();
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void Shutdown();
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void DoState(PointerWrap &p);
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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bool RunBuffer();
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void RunGpu();
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// for CGPFIFO
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void GatherPipeBursted();
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void UpdateInterrupts(u64 userdata);
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void UpdateInterruptsFromVideoBackend(u64 userdata);
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void SetRendering(bool enabled);
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} // end of namespace SWCommandProcessor
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