forked from dolphin-emu/dolphin
f316265973
MMIO registers are located at 0x0C000000 and 0x0D000000, not 0xCC000000. The 0xCC000000 addresses are just an artifact of address translation.
128 lines
3.5 KiB
C++
128 lines
3.5 KiB
C++
#include <unordered_set>
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#include <gtest/gtest.h>
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#include "Common/CommonTypes.h"
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#include "Core/HW/MMIO.h"
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// Tests that the UniqueID function returns a "unique enough" identifier
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// number: that is, it is unique in the address ranges we care about.
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TEST(UniqueID, UniqueEnough)
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{
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std::unordered_set<u32> ids;
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for (u32 i = 0x0C000000; i < 0x0C010000; ++i)
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{
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u32 unique_id = MMIO::UniqueID(i);
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EXPECT_EQ(ids.end(), ids.find(unique_id));
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ids.insert(unique_id);
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}
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for (u32 i = 0x0D000000; i < 0x0D010000; ++i)
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{
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u32 unique_id = MMIO::UniqueID(i);
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EXPECT_EQ(ids.end(), ids.find(unique_id));
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ids.insert(unique_id);
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}
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}
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TEST(IsMMIOAddress, SpecialAddresses)
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{
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SConfig::Init();
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SConfig::GetInstance().m_LocalCoreStartupParameter.bWii = true;
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// WG Pipe address, should not be handled by MMIO.
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EXPECT_FALSE(MMIO::IsMMIOAddress(0x0C008000));
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// Locked L1 cache allocation.
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EXPECT_FALSE(MMIO::IsMMIOAddress(0xE0000000));
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// Uncached mirror of MEM1, shouldn't be handled by MMIO
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EXPECT_FALSE(MMIO::IsMMIOAddress(0xC0000000));
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// Effective address of an MMIO register; MMIO only deals with physical
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// addresses.
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EXPECT_FALSE(MMIO::IsMMIOAddress(0xCC0000E0));
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// And lets check some valid addresses too
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EXPECT_TRUE(MMIO::IsMMIOAddress(0x0C0000E0)); // Gamecube MMIOs
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EXPECT_TRUE(MMIO::IsMMIOAddress(0x0D00008C)); // Wii MMIOs
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EXPECT_TRUE(MMIO::IsMMIOAddress(0x0D800F10)); // Mirror of Wii MMIOs
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SConfig::Shutdown();
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}
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class MappingTest : public testing::Test
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{
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protected:
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virtual void SetUp() override
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{
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m_mapping = new MMIO::Mapping();
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}
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virtual void TearDown() override
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{
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delete m_mapping;
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}
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MMIO::Mapping* m_mapping;
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};
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TEST_F(MappingTest, ReadConstant)
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{
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m_mapping->Register(0x0C001234, MMIO::Constant<u8>(0x42), MMIO::Nop<u8>());
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m_mapping->Register(0x0C001234, MMIO::Constant<u16>(0x1234), MMIO::Nop<u16>());
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m_mapping->Register(0x0C001234, MMIO::Constant<u32>(0xdeadbeef), MMIO::Nop<u32>());
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u8 val8 = m_mapping->Read<u8>(0x0C001234);
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u16 val16 = m_mapping->Read<u16>(0x0C001234);
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u32 val32 = m_mapping->Read<u32>(0x0C001234);
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EXPECT_EQ(0x42, val8);
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EXPECT_EQ(0x1234, val16);
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EXPECT_EQ(0xdeadbeef, val32);
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}
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TEST_F(MappingTest, ReadWriteDirect)
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{
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u8 target_8 = 0;
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u16 target_16 = 0;
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u32 target_32 = 0;
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m_mapping->Register(0x0C001234, MMIO::DirectRead<u8>(&target_8), MMIO::DirectWrite<u8>(&target_8));
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m_mapping->Register(0x0C001234, MMIO::DirectRead<u16>(&target_16), MMIO::DirectWrite<u16>(&target_16));
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m_mapping->Register(0x0C001234, MMIO::DirectRead<u32>(&target_32), MMIO::DirectWrite<u32>(&target_32));
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for (u32 i = 0; i < 100; ++i)
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{
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u8 val8 = m_mapping->Read<u8>(0x0C001234); EXPECT_EQ(i, val8);
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u16 val16 = m_mapping->Read<u16>(0x0C001234); EXPECT_EQ(i, val16);
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u32 val32 = m_mapping->Read<u32>(0x0C001234); EXPECT_EQ(i, val32);
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val8 += 1; m_mapping->Write(0x0C001234, val8);
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val16 += 1; m_mapping->Write(0x0C001234, val16);
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val32 += 1; m_mapping->Write(0x0C001234, val32);
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}
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}
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TEST_F(MappingTest, ReadWriteComplex)
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{
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bool read_called = false, write_called = false;
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m_mapping->Register(0x0C001234,
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MMIO::ComplexRead<u8>([&read_called](u32 addr) {
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EXPECT_EQ(0x0C001234, addr);
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read_called = true;
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return 0x12;
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}),
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MMIO::ComplexWrite<u8>([&write_called](u32 addr, u8 val) {
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EXPECT_EQ(0x0C001234, addr);
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EXPECT_EQ(0x34, val);
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write_called = true;
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})
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);
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u8 val = m_mapping->Read<u8>(0x0C001234); EXPECT_EQ(0x12, val);
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m_mapping->Write(0x0C001234, (u8)0x34);
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EXPECT_TRUE(read_called);
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EXPECT_TRUE(write_called);
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}
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