forked from dolphin-emu/dolphin
2f7da5d5d1
Applied the logic from r6691 to the LLE dec/add/sub functions so they work without ToMask. This should give a modest speedup for these. Pierre's AR inc was already perfect and I only adjusted its logic a bit for visual consistency between the interpreter and JIT code. Also applied Pierre's optimization from the LLE inc to the Int inc. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6707 8ced0084-cf51-0410-be5f-012b33b47a6e
387 lines
8.9 KiB
C
387 lines
8.9 KiB
C
/*====================================================================
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filename: gdsp_opcodes_helper.h
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project: GameCube DSP Tool (gcdsp)
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created: 2005.03.04
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mail: duddie@walla.com
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Copyright (c) 2005 Duddie
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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====================================================================*/
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#ifndef _DSP_INT_UTIL_H
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#define _DSP_INT_UTIL_H
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#include "Common.h"
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#include "DSPInterpreter.h"
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#include "DSPCore.h"
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#include "DSPMemoryMap.h"
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#include "DSPStacks.h"
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// ---------------------------------------------------------------------------------------
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// --- SR
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// ---------------------------------------------------------------------------------------
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inline void dsp_SR_set_flag(int flag)
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{
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g_dsp.r.sr |= flag;
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}
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inline bool dsp_SR_is_flag_set(int flag)
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{
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return (g_dsp.r.sr & flag) != 0;
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}
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// ---------------------------------------------------------------------------------------
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// --- AR increments, decrements
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// ---------------------------------------------------------------------------------------
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inline u16 dsp_increase_addr_reg(u16 reg, s16 _ix)
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{
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u32 ar = g_dsp.r.ar[reg];
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u32 wr = g_dsp.r.wr[reg];
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s32 ix = _ix;
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u32 mx = (wr | 1) << 1;
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u32 nar = ar + ix;
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u32 dar = (nar ^ ar ^ ix) & mx;
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if (ix >= 0)
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{
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if (dar > wr) //overflow
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nar -= wr + 1;
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}
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else
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{
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if ((((nar + wr + 1) ^ nar) & dar) <= wr) //underflow or below min for mask
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nar += wr + 1;
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}
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return nar;
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}
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inline u16 dsp_decrease_addr_reg(u16 reg, s16 _ix)
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{
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u32 ar = g_dsp.r.ar[reg];
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u32 wr = g_dsp.r.wr[reg];
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s32 ix = _ix;
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u32 mx = (wr | 1) << 1;
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u32 nar = ar - ix;
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u32 dar = (nar ^ ar ^ ~ix) & mx;
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if ((u32)ix > 0xFFFF8000) //(ix < 0 && ix != -0x8000)
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{
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if (dar > wr) //overflow
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nar -= wr + 1;
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}
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else
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{
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if ((((nar + wr + 1) ^ nar) & dar) <= wr) //underflow or below min for mask
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nar += wr + 1;
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}
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return nar;
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}
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inline u16 dsp_increment_addr_reg(u16 reg)
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{
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u32 ar = g_dsp.r.ar[reg];
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u32 wr = g_dsp.r.wr[reg];
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u32 nar = ar + 1;
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if ((nar ^ ar) > ((wr | 1) << 1))
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nar -= wr + 1;
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return nar;
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}
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inline u16 dsp_decrement_addr_reg(u16 reg)
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{
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u32 ar = g_dsp.r.ar[reg];
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u32 wr = g_dsp.r.wr[reg];
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u32 nar = ar + wr;
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if (((nar ^ ar) & ((wr | 1) << 1)) > wr)
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nar -= wr + 1;
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return nar;
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}
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// ---------------------------------------------------------------------------------------
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// --- reg
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// ---------------------------------------------------------------------------------------
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inline u16 dsp_op_read_reg(int reg)
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{
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switch (reg & 0x1f) {
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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case DSP_REG_ST2:
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case DSP_REG_ST3:
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return dsp_reg_load_stack(reg - DSP_REG_ST0);
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case DSP_REG_AR0:
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case DSP_REG_AR1:
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case DSP_REG_AR2:
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case DSP_REG_AR3:
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return g_dsp.r.ar[reg - DSP_REG_AR0];
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case DSP_REG_IX0:
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case DSP_REG_IX1:
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case DSP_REG_IX2:
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case DSP_REG_IX3:
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return g_dsp.r.ix[reg - DSP_REG_IX0];
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case DSP_REG_WR0:
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case DSP_REG_WR1:
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case DSP_REG_WR2:
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case DSP_REG_WR3:
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return g_dsp.r.wr[reg - DSP_REG_WR0];
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case DSP_REG_ACH0:
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case DSP_REG_ACH1:
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return g_dsp.r.ac[reg - DSP_REG_ACH0].h;
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case DSP_REG_CR: return g_dsp.r.cr;
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case DSP_REG_SR: return g_dsp.r.sr;
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case DSP_REG_PRODL: return g_dsp.r.prod.l;
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case DSP_REG_PRODM: return g_dsp.r.prod.m;
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case DSP_REG_PRODH: return g_dsp.r.prod.h;
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case DSP_REG_PRODM2: return g_dsp.r.prod.m2;
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case DSP_REG_AXL0:
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case DSP_REG_AXL1:
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return g_dsp.r.ax[reg - DSP_REG_AXL0].l;
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case DSP_REG_AXH0:
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case DSP_REG_AXH1:
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return g_dsp.r.ax[reg - DSP_REG_AXH0].h;
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case DSP_REG_ACL0:
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case DSP_REG_ACL1:
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return g_dsp.r.ac[reg - DSP_REG_ACL0].l;
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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return g_dsp.r.ac[reg - DSP_REG_ACM0].m;
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default:
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_assert_msg_(DSP_INT, 0, "cannot happen");
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return 0;
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}
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}
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inline void dsp_op_write_reg(int reg, u16 val)
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{
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switch (reg & 0x1f) {
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// 8-bit sign extended registers. Should look at prod.h too...
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case DSP_REG_ACH0:
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case DSP_REG_ACH1:
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// sign extend from the bottom 8 bits.
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g_dsp.r.ac[reg-DSP_REG_ACH0].h = (u16)(s16)(s8)(u8)val;
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break;
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// Stack registers.
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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case DSP_REG_ST2:
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case DSP_REG_ST3:
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dsp_reg_store_stack(reg - DSP_REG_ST0, val);
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break;
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case DSP_REG_AR0:
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case DSP_REG_AR1:
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case DSP_REG_AR2:
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case DSP_REG_AR3:
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g_dsp.r.ar[reg - DSP_REG_AR0] = val;
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break;
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case DSP_REG_IX0:
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case DSP_REG_IX1:
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case DSP_REG_IX2:
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case DSP_REG_IX3:
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g_dsp.r.ix[reg - DSP_REG_IX0] = val;
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break;
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case DSP_REG_WR0:
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case DSP_REG_WR1:
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case DSP_REG_WR2:
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case DSP_REG_WR3:
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g_dsp.r.wr[reg - DSP_REG_WR0] = val;
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break;
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case DSP_REG_CR: g_dsp.r.cr = val; break;
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case DSP_REG_SR: g_dsp.r.sr = val; break;
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case DSP_REG_PRODL: g_dsp.r.prod.l = val; break;
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case DSP_REG_PRODM: g_dsp.r.prod.m = val; break;
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case DSP_REG_PRODH: g_dsp.r.prod.h = val; break;
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case DSP_REG_PRODM2: g_dsp.r.prod.m2 = val; break;
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case DSP_REG_AXL0:
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case DSP_REG_AXL1:
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g_dsp.r.ax[reg - DSP_REG_AXL0].l = val;
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break;
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case DSP_REG_AXH0:
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case DSP_REG_AXH1:
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g_dsp.r.ax[reg - DSP_REG_AXH0].h = val;
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break;
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case DSP_REG_ACL0:
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case DSP_REG_ACL1:
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g_dsp.r.ac[reg - DSP_REG_ACL0].l = val;
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break;
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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g_dsp.r.ac[reg - DSP_REG_ACM0].m = val;
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break;
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}
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}
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inline void dsp_conditional_extend_accum(int reg)
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{
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switch (reg)
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{
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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if (g_dsp.r.sr & SR_40_MODE_BIT)
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{
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// Sign extend into whole accum.
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u16 val = g_dsp.r.ac[reg-DSP_REG_ACM0].m;
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g_dsp.r.ac[reg - DSP_REG_ACM0].h = (val & 0x8000) ? 0xFFFF : 0x0000;
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g_dsp.r.ac[reg - DSP_REG_ACM0].l = 0;
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}
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}
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}
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// ---------------------------------------------------------------------------------------
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// --- prod
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// ---------------------------------------------------------------------------------------
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inline s64 dsp_get_long_prod()
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{
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#if PROFILE
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ProfilerAddDelta(g_dsp.err_pc, 1);
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#endif
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s64 val = (s8)(u8)g_dsp.r.prod.h;
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val <<= 32;
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s64 low_prod = g_dsp.r.prod.m;
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low_prod += g_dsp.r.prod.m2;
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low_prod <<= 16;
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low_prod |= g_dsp.r.prod.l;
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val += low_prod;
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return val;
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}
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inline s64 dsp_get_long_prod_round_prodl()
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{
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s64 prod = dsp_get_long_prod();
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if (prod & 0x10000)
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prod = (prod + 0x8000) & ~0xffff;
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else
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prod = (prod + 0x7fff) & ~0xffff;
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return prod;
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}
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// For accurate emulation, this is wrong - but the real prod registers behave
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// in completely bizarre ways. Not needed to emulate them correctly for game ucodes.
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inline void dsp_set_long_prod(s64 val)
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{
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#if PROFILE
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ProfilerAddDelta(g_dsp.err_pc, 1);
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#endif
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g_dsp.r.prod.l = (u16)val;
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val >>= 16;
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g_dsp.r.prod.m = (u16)val;
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val >>= 16;
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g_dsp.r.prod.h = /*(s16)(s8)*/(u8)val;//todo: check expansion
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g_dsp.r.prod.m2 = 0;
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}
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// ---------------------------------------------------------------------------------------
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// --- ACC - main accumulators (40-bit)
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// ---------------------------------------------------------------------------------------
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inline s64 dsp_get_long_acc(int reg)
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{
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#if PROFILE
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ProfilerAddDelta(g_dsp.err_pc, 1);
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#endif
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s64 high = (s64)(s8)g_dsp.r.ac[reg].h << 32;
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u32 mid_low = ((u32)g_dsp.r.ac[reg].m << 16) | g_dsp.r.ac[reg].l;
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return high | mid_low;
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}
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inline void dsp_set_long_acc(int _reg, s64 val)
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{
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#if PROFILE
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ProfilerAddDelta(g_dsp.err_pc, 1);
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#endif
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g_dsp.r.ac[_reg].l = (u16)val;
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val >>= 16;
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g_dsp.r.ac[_reg].m = (u16)val;
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val >>= 16;
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g_dsp.r.ac[_reg].h = (u16)(s16)(s8)(u8)val;
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}
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inline s64 dsp_convert_long_acc(s64 val) // s64 -> s40
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{
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return ((s64)(s8)(val >> 32))<<32 | (u32)val;
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}
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inline s64 dsp_round_long_acc(s64 val)
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{
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if (val & 0x10000)
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val = (val + 0x8000) & ~0xffff;
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else
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val = (val + 0x7fff) & ~0xffff;
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return val;
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}
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inline s16 dsp_get_acc_l(int _reg)
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{
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return g_dsp.r.ac[_reg].l;
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}
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inline s16 dsp_get_acc_m(int _reg)
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{
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return g_dsp.r.ac[_reg].m;
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}
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inline s16 dsp_get_acc_h(int _reg)
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{
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return g_dsp.r.ac[_reg].h;
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}
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// ---------------------------------------------------------------------------------------
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// --- AX - extra accumulators (32-bit)
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// ---------------------------------------------------------------------------------------
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inline s32 dsp_get_long_acx(int _reg)
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{
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#if PROFILE
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ProfilerAddDelta(g_dsp.err_pc, 1);
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#endif
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return ((u32)g_dsp.r.ax[_reg].h << 16) | g_dsp.r.ax[_reg].l;
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}
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inline s16 dsp_get_ax_l(int _reg)
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{
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return (s16)g_dsp.r.ax[_reg].l;
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}
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inline s16 dsp_get_ax_h(int _reg)
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{
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return (s16)g_dsp.r.ax[_reg].h;
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}
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#endif
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