forked from dolphin-emu/dolphin
1151 lines
36 KiB
C++
1151 lines
36 KiB
C++
// Copyright 2015 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#pragma once
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#include <functional>
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#include "Common/ArmCommon.h"
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#include "Common/Assert.h"
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#include "Common/BitSet.h"
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#include "Common/CodeBlock.h"
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#include "Common/Common.h"
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namespace Arm64Gen
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{
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// X30 serves a dual purpose as a link register
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// Encoded as <u3:type><u5:reg>
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// Types:
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// 000 - 32bit GPR
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// 001 - 64bit GPR
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// 010 - VFP single precision
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// 100 - VFP double precision
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// 110 - VFP quad precision
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enum ARM64Reg
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{
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// 32bit registers
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W0 = 0,
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W1,
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W2,
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W3,
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W4,
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W5,
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W6,
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W7,
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W8,
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W9,
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W10,
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W11,
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W12,
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W13,
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W14,
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W15,
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W16,
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W17,
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W18,
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W19,
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W20,
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W21,
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W22,
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W23,
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W24,
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W25,
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W26,
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W27,
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W28,
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W29,
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W30,
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WSP, // 32bit stack pointer
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// 64bit registers
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X0 = 0x20,
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X1,
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X2,
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X3,
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X4,
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X5,
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X6,
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X7,
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X8,
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X9,
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X10,
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X11,
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X12,
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X13,
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X14,
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X15,
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X16,
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X17,
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X18,
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X19,
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X20,
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X21,
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X22,
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X23,
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X24,
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X25,
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X26,
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X27,
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X28,
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X29,
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X30,
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SP, // 64bit stack pointer
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// VFP single precision registers
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S0 = 0x40,
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S1,
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S2,
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S3,
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S4,
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S5,
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S6,
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S7,
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S8,
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S9,
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S10,
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S11,
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S12,
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S13,
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S14,
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S15,
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S16,
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S17,
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S18,
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S19,
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S20,
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S21,
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S22,
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S23,
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S24,
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S25,
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S26,
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S27,
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S28,
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S29,
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S30,
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S31,
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// VFP Double Precision registers
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D0 = 0x80,
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D1,
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D2,
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D3,
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D4,
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D5,
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D6,
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D7,
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D8,
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D9,
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D10,
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D11,
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D12,
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D13,
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D14,
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D15,
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D16,
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D17,
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D18,
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D19,
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D20,
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D21,
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D22,
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D23,
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D24,
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D25,
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D26,
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D27,
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D28,
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D29,
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D30,
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D31,
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// ASIMD Quad-Word registers
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Q0 = 0xC0,
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Q1,
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Q2,
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Q3,
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Q4,
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Q5,
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Q6,
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Q7,
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Q8,
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Q9,
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Q10,
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Q11,
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Q12,
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Q13,
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Q14,
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Q15,
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Q16,
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Q17,
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Q18,
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Q19,
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Q20,
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Q21,
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Q22,
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Q23,
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Q24,
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Q25,
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Q26,
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Q27,
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Q28,
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Q29,
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Q30,
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Q31,
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// For PRFM(prefetch memory) encoding
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// This is encoded in the Rt register
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// Data preload
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PLDL1KEEP = 0,
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PLDL1STRM,
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PLDL2KEEP,
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PLDL2STRM,
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PLDL3KEEP,
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PLDL3STRM,
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// Instruction preload
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PLIL1KEEP = 8,
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PLIL1STRM,
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PLIL2KEEP,
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PLIL2STRM,
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PLIL3KEEP,
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PLIL3STRM,
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// Prepare for store
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PLTL1KEEP = 16,
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PLTL1STRM,
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PLTL2KEEP,
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PLTL2STRM,
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PLTL3KEEP,
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PLTL3STRM,
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WZR = WSP,
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ZR = SP,
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INVALID_REG = 0xFFFFFFFF
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};
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constexpr bool Is64Bit(ARM64Reg reg)
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{
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return (reg & 0x20) != 0;
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}
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constexpr bool IsSingle(ARM64Reg reg)
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{
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return (reg & 0xC0) == 0x40;
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}
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constexpr bool IsDouble(ARM64Reg reg)
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{
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return (reg & 0xC0) == 0x80;
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}
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constexpr bool IsScalar(ARM64Reg reg)
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{
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return IsSingle(reg) || IsDouble(reg);
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}
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constexpr bool IsQuad(ARM64Reg reg)
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{
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return (reg & 0xC0) == 0xC0;
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}
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constexpr bool IsVector(ARM64Reg reg)
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{
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return (reg & 0xC0) != 0;
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}
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constexpr bool IsGPR(ARM64Reg reg)
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{
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return static_cast<int>(reg) < 0x40;
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}
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constexpr ARM64Reg DecodeReg(ARM64Reg reg)
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{
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return static_cast<ARM64Reg>(reg & 0x1F);
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}
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constexpr ARM64Reg EncodeRegTo64(ARM64Reg reg)
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{
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return static_cast<ARM64Reg>(reg | 0x20);
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}
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constexpr ARM64Reg EncodeRegToSingle(ARM64Reg reg)
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{
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return static_cast<ARM64Reg>(DecodeReg(reg) + S0);
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}
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constexpr ARM64Reg EncodeRegToDouble(ARM64Reg reg)
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{
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return static_cast<ARM64Reg>((reg & ~0xC0) | 0x80);
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}
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constexpr ARM64Reg EncodeRegToQuad(ARM64Reg reg)
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{
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return static_cast<ARM64Reg>(reg | 0xC0);
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}
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// For AND/TST/ORR/EOR etc
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bool IsImmLogical(uint64_t value, unsigned int width, unsigned int* n, unsigned int* imm_s,
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unsigned int* imm_r);
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// For ADD/SUB
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bool IsImmArithmetic(uint64_t input, u32* val, bool* shift);
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float FPImm8ToFloat(uint8_t bits);
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bool FPImm8FromFloat(float value, uint8_t* immOut);
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enum OpType
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{
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TYPE_IMM = 0,
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TYPE_REG,
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TYPE_IMMSREG,
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TYPE_RSR,
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TYPE_MEM
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};
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enum ShiftType
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{
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ST_LSL = 0,
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ST_LSR = 1,
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ST_ASR = 2,
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ST_ROR = 3,
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};
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enum IndexType
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{
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INDEX_UNSIGNED,
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INDEX_POST,
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INDEX_PRE,
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INDEX_SIGNED, // used in LDP/STP
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};
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enum ShiftAmount
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{
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SHIFT_0 = 0,
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SHIFT_16 = 1,
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SHIFT_32 = 2,
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SHIFT_48 = 3,
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};
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enum RoundingMode
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{
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ROUND_A, // round to nearest, ties to away
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ROUND_M, // round towards -inf
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ROUND_N, // round to nearest, ties to even
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ROUND_P, // round towards +inf
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ROUND_Z, // round towards zero
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};
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struct FixupBranch
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{
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u8* ptr;
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// Type defines
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// 0 = CBZ (32bit)
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// 1 = CBNZ (32bit)
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// 2 = B (conditional)
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// 3 = TBZ
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// 4 = TBNZ
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// 5 = B (unconditional)
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// 6 = BL (unconditional)
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u32 type;
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// Used with B.cond
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CCFlags cond;
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// Used with TBZ/TBNZ
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u8 bit;
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// Used with Test/Compare and Branch
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ARM64Reg reg;
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};
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enum PStateField
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{
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FIELD_SPSel = 0,
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FIELD_DAIFSet,
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FIELD_DAIFClr,
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FIELD_NZCV, // The only system registers accessible from EL0 (user space)
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FIELD_PMCR_EL0,
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FIELD_PMCCNTR_EL0,
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FIELD_FPCR = 0x340,
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FIELD_FPSR = 0x341,
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};
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enum SystemHint
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{
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HINT_NOP = 0,
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HINT_YIELD,
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HINT_WFE,
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HINT_WFI,
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HINT_SEV,
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HINT_SEVL,
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};
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enum BarrierType
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{
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OSHLD = 1,
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OSHST = 2,
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OSH = 3,
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NSHLD = 5,
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NSHST = 6,
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NSH = 7,
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ISHLD = 9,
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ISHST = 10,
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ISH = 11,
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LD = 13,
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ST = 14,
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SY = 15,
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};
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class ArithOption
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{
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public:
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enum WidthSpecifier
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{
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WIDTH_DEFAULT,
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WIDTH_32BIT,
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WIDTH_64BIT,
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};
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enum ExtendSpecifier
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{
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EXTEND_UXTB = 0x0,
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EXTEND_UXTH = 0x1,
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EXTEND_UXTW = 0x2, /* Also LSL on 32bit width */
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EXTEND_UXTX = 0x3, /* Also LSL on 64bit width */
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EXTEND_SXTB = 0x4,
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EXTEND_SXTH = 0x5,
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EXTEND_SXTW = 0x6,
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EXTEND_SXTX = 0x7,
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};
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enum TypeSpecifier
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{
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TYPE_EXTENDEDREG,
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TYPE_IMM,
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TYPE_SHIFTEDREG,
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};
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private:
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ARM64Reg m_destReg;
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WidthSpecifier m_width;
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ExtendSpecifier m_extend;
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TypeSpecifier m_type;
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ShiftType m_shifttype;
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u32 m_shift;
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public:
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ArithOption(ARM64Reg Rd, bool index = false)
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{
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// Indexed registers are a certain feature of AARch64
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// On Loadstore instructions that use a register offset
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// We can have the register as an index
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// If we are indexing then the offset register will
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// be shifted to the left so we are indexing at intervals
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// of the size of what we are loading
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// 8-bit: Index does nothing
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// 16-bit: Index LSL 1
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// 32-bit: Index LSL 2
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// 64-bit: Index LSL 3
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if (index)
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m_shift = 4;
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else
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m_shift = 0;
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m_destReg = Rd;
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m_type = TYPE_EXTENDEDREG;
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if (Is64Bit(Rd))
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{
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m_width = WIDTH_64BIT;
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m_extend = EXTEND_UXTX;
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}
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else
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{
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m_width = WIDTH_32BIT;
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m_extend = EXTEND_UXTW;
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}
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m_shifttype = ST_LSL;
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}
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ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
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{
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m_destReg = Rd;
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m_shift = shift;
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m_shifttype = shift_type;
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m_type = TYPE_SHIFTEDREG;
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if (Is64Bit(Rd))
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{
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m_width = WIDTH_64BIT;
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if (shift == 64)
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m_shift = 0;
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}
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else
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{
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m_width = WIDTH_32BIT;
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if (shift == 32)
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m_shift = 0;
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}
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}
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TypeSpecifier GetType() const { return m_type; }
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ARM64Reg GetReg() const { return m_destReg; }
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u32 GetData() const
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{
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switch (m_type)
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{
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case TYPE_EXTENDEDREG:
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return (m_extend << 13) | (m_shift << 10);
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break;
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case TYPE_SHIFTEDREG:
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return (m_shifttype << 22) | (m_shift << 10);
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break;
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default:
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_dbg_assert_msg_(DYNA_REC, false, "Invalid type in GetData");
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break;
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}
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return 0;
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}
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};
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class ARM64XEmitter
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{
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friend class ARM64FloatEmitter;
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private:
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u8* m_code;
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u8* m_lastCacheFlushEnd;
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void EncodeCompareBranchInst(u32 op, ARM64Reg Rt, const void* ptr);
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void EncodeTestBranchInst(u32 op, ARM64Reg Rt, u8 bits, const void* ptr);
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void EncodeUnconditionalBranchInst(u32 op, const void* ptr);
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void EncodeUnconditionalBranchInst(u32 opc, u32 op2, u32 op3, u32 op4, ARM64Reg Rn);
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void EncodeExceptionInst(u32 instenc, u32 imm);
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void EncodeSystemInst(u32 op0, u32 op1, u32 CRn, u32 CRm, u32 op2, ARM64Reg Rt);
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void EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm,
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ArithOption Option);
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void EncodeArithmeticCarryInst(u32 op, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EncodeCondCompareImmInst(u32 op, ARM64Reg Rn, u32 imm, u32 nzcv, CCFlags cond);
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void EncodeCondCompareRegInst(u32 op, ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond);
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void EncodeCondSelectInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
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void EncodeData1SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn);
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void EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm);
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void EncodeLoadStoreExcInst(u32 instenc, ARM64Reg Rs, ARM64Reg Rt2, ARM64Reg Rn, ARM64Reg Rt);
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void EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm);
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void EncodeLoadStoreIndexedInst(u32 op, u32 op2, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void EncodeLoadStoreIndexedInst(u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm, u8 size);
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void EncodeMOVWideInst(u32 op, ARM64Reg Rd, u32 imm, ShiftAmount pos);
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void EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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void EncodeAddSubImmInst(u32 op, bool flags, u32 shift, u32 imm, ARM64Reg Rn, ARM64Reg Rd);
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void EncodeLogicalImmInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, int n);
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void EncodeLoadStorePair(u32 op, u32 load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn,
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s32 imm);
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void EncodeAddressInst(u32 op, ARM64Reg Rd, s32 imm);
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void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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protected:
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void Write32(u32 value);
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public:
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ARM64XEmitter() : m_code(nullptr), m_lastCacheFlushEnd(nullptr) {}
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ARM64XEmitter(u8* code_ptr)
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{
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m_code = code_ptr;
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m_lastCacheFlushEnd = code_ptr;
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}
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virtual ~ARM64XEmitter() {}
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void SetCodePtr(u8* ptr);
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void SetCodePtrUnsafe(u8* ptr);
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void ReserveCodeSpace(u32 bytes);
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const u8* AlignCode16();
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const u8* AlignCodePage();
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const u8* GetCodePtr() const;
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void FlushIcache();
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void FlushIcacheSection(u8* start, u8* end);
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u8* GetWritableCodePtr();
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// FixupBranch branching
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void SetJumpTarget(FixupBranch const& branch);
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FixupBranch CBZ(ARM64Reg Rt);
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FixupBranch CBNZ(ARM64Reg Rt);
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FixupBranch B(CCFlags cond);
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FixupBranch TBZ(ARM64Reg Rt, u8 bit);
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FixupBranch TBNZ(ARM64Reg Rt, u8 bit);
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FixupBranch B();
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FixupBranch BL();
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// Compare and Branch
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void CBZ(ARM64Reg Rt, const void* ptr);
|
|
void CBNZ(ARM64Reg Rt, const void* ptr);
|
|
|
|
// Conditional Branch
|
|
void B(CCFlags cond, const void* ptr);
|
|
|
|
// Test and Branch
|
|
void TBZ(ARM64Reg Rt, u8 bits, const void* ptr);
|
|
void TBNZ(ARM64Reg Rt, u8 bits, const void* ptr);
|
|
|
|
// Unconditional Branch
|
|
void B(const void* ptr);
|
|
void BL(const void* ptr);
|
|
|
|
// Unconditional Branch (register)
|
|
void BR(ARM64Reg Rn);
|
|
void BLR(ARM64Reg Rn);
|
|
void RET(ARM64Reg Rn = X30);
|
|
void ERET();
|
|
void DRPS();
|
|
|
|
// Exception generation
|
|
void SVC(u32 imm);
|
|
void HVC(u32 imm);
|
|
void SMC(u32 imm);
|
|
void BRK(u32 imm);
|
|
void HLT(u32 imm);
|
|
void DCPS1(u32 imm);
|
|
void DCPS2(u32 imm);
|
|
void DCPS3(u32 imm);
|
|
|
|
// System
|
|
void _MSR(PStateField field, u8 imm);
|
|
|
|
void _MSR(PStateField field, ARM64Reg Rt);
|
|
void MRS(ARM64Reg Rt, PStateField field);
|
|
|
|
void HINT(SystemHint op);
|
|
void CLREX();
|
|
void DSB(BarrierType type);
|
|
void DMB(BarrierType type);
|
|
void ISB(BarrierType type);
|
|
|
|
// Add/Subtract (Extended/Shifted register)
|
|
void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
void CMN(ARM64Reg Rn, ARM64Reg Rm);
|
|
void CMN(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
void CMP(ARM64Reg Rn, ARM64Reg Rm);
|
|
void CMP(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option);
|
|
|
|
// Add/Subtract (with carry)
|
|
void ADC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void ADCS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SBC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SBCS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
|
|
// Conditional Compare (immediate)
|
|
void CCMN(ARM64Reg Rn, u32 imm, u32 nzcv, CCFlags cond);
|
|
void CCMP(ARM64Reg Rn, u32 imm, u32 nzcv, CCFlags cond);
|
|
|
|
// Conditional Compare (register)
|
|
void CCMN(ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond);
|
|
void CCMP(ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond);
|
|
|
|
// Conditional Select
|
|
void CSEL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
|
|
void CSINC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
|
|
void CSINV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
|
|
void CSNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
|
|
|
|
// Aliases
|
|
void CSET(ARM64Reg Rd, CCFlags cond)
|
|
{
|
|
ARM64Reg zr = Is64Bit(Rd) ? ZR : WZR;
|
|
CSINC(Rd, zr, zr, (CCFlags)((u32)cond ^ 1));
|
|
}
|
|
void CSETM(ARM64Reg Rd, CCFlags cond)
|
|
{
|
|
ARM64Reg zr = Is64Bit(Rd) ? ZR : WZR;
|
|
CSINV(Rd, zr, zr, (CCFlags)((u32)cond ^ 1));
|
|
}
|
|
void NEG(ARM64Reg Rd, ARM64Reg Rs) { SUB(Rd, Is64Bit(Rd) ? ZR : WZR, Rs); }
|
|
// Data-Processing 1 source
|
|
void RBIT(ARM64Reg Rd, ARM64Reg Rn);
|
|
void REV16(ARM64Reg Rd, ARM64Reg Rn);
|
|
void REV32(ARM64Reg Rd, ARM64Reg Rn);
|
|
void REV64(ARM64Reg Rd, ARM64Reg Rn);
|
|
void CLZ(ARM64Reg Rd, ARM64Reg Rn);
|
|
void CLS(ARM64Reg Rd, ARM64Reg Rn);
|
|
|
|
// Data-Processing 2 source
|
|
void UDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void LSLV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void LSRV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void ASRV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void RORV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32B(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32H(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32W(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32CB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32CH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32CW(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32X(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void CRC32CX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
|
|
// Data-Processing 3 source
|
|
void MADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void MSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void SMADDL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void SMULL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void SMSUBL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void SMULH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void UMADDL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void UMULL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void UMSUBL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
|
|
void UMULH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void MUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
void MNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
|
|
|
// Logical (shifted register)
|
|
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
|
|
|
|
// Wrap the above for saner syntax
|
|
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BIC(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORN(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EOR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EON(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ANDS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BICS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
|
|
// Convenience wrappers around ORR. These match the official convenience syntax.
|
|
void MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift);
|
|
void MOV(ARM64Reg Rd, ARM64Reg Rm);
|
|
void MVN(ARM64Reg Rd, ARM64Reg Rm);
|
|
|
|
// TODO: These are "slow" as they use arith+shift, should be replaced with UBFM/EXTR variants.
|
|
void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift);
|
|
void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift);
|
|
void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift);
|
|
void ROR(ARM64Reg Rd, ARM64Reg Rm, int shift);
|
|
|
|
// Logical (immediate)
|
|
void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
|
|
void ANDS(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
|
|
void EOR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
|
|
void ORR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
|
|
void TST(ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
|
|
void TST(ARM64Reg Rn, ARM64Reg Rm) { ANDS(Is64Bit(Rn) ? ZR : WZR, Rn, Rm); }
|
|
// Add/subtract (immediate)
|
|
void ADD(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
|
|
void ADDS(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
|
|
void SUB(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
|
|
void SUBS(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
|
|
void CMP(ARM64Reg Rn, u32 imm, bool shift = false);
|
|
|
|
// Data Processing (Immediate)
|
|
void MOVZ(ARM64Reg Rd, u32 imm, ShiftAmount pos = SHIFT_0);
|
|
void MOVN(ARM64Reg Rd, u32 imm, ShiftAmount pos = SHIFT_0);
|
|
void MOVK(ARM64Reg Rd, u32 imm, ShiftAmount pos = SHIFT_0);
|
|
|
|
// Bitfield move
|
|
void BFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
|
|
void SBFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
|
|
void UBFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
|
|
void BFI(ARM64Reg Rd, ARM64Reg Rn, u32 lsb, u32 width);
|
|
void UBFIZ(ARM64Reg Rd, ARM64Reg Rn, u32 lsb, u32 width);
|
|
|
|
// Extract register (ROR with two inputs, if same then faster on A67)
|
|
void EXTR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u32 shift);
|
|
|
|
// Aliases
|
|
void SXTB(ARM64Reg Rd, ARM64Reg Rn);
|
|
void SXTH(ARM64Reg Rd, ARM64Reg Rn);
|
|
void SXTW(ARM64Reg Rd, ARM64Reg Rn);
|
|
void UXTB(ARM64Reg Rd, ARM64Reg Rn);
|
|
void UXTH(ARM64Reg Rd, ARM64Reg Rn);
|
|
|
|
void UBFX(ARM64Reg Rd, ARM64Reg Rn, int lsb, int width) { UBFM(Rd, Rn, lsb, lsb + width - 1); }
|
|
// Load Register (Literal)
|
|
void LDR(ARM64Reg Rt, u32 imm);
|
|
void LDRSW(ARM64Reg Rt, u32 imm);
|
|
void PRFM(ARM64Reg Rt, u32 imm);
|
|
|
|
// Load/Store Exclusive
|
|
void STXRB(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void STLXRB(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDXRB(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDAXRB(ARM64Reg Rt, ARM64Reg Rn);
|
|
void STLRB(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDARB(ARM64Reg Rt, ARM64Reg Rn);
|
|
void STXRH(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void STLXRH(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDXRH(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDAXRH(ARM64Reg Rt, ARM64Reg Rn);
|
|
void STLRH(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDARH(ARM64Reg Rt, ARM64Reg Rn);
|
|
void STXR(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void STLXR(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);
|
|
void STXP(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn);
|
|
void STLXP(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn);
|
|
void LDXR(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDAXR(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDXP(ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn);
|
|
void LDAXP(ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn);
|
|
void STLR(ARM64Reg Rt, ARM64Reg Rn);
|
|
void LDAR(ARM64Reg Rt, ARM64Reg Rn);
|
|
|
|
// Load/Store no-allocate pair (offset)
|
|
void STNP(ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm);
|
|
void LDNP(ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm);
|
|
|
|
// Load/Store register (immediate indexed)
|
|
void STRB(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDRB(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDRSB(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void STRH(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDRH(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDRSH(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void STR(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDR(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDRSW(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
|
|
// Load/Store register (register offset)
|
|
void STRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDRSB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void STRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDRSH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void STR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void LDRSW(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
void PRFM(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
|
|
|
|
// Load/Store register (unscaled offset)
|
|
void STURB(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDURB(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDURSB(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void STURH(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDURH(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDURSH(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void STUR(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDUR(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
void LDURSW(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
|
|
|
// Load/Store pair
|
|
void LDP(IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
|
|
void LDPSW(IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
|
|
void STP(IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
|
|
|
|
// Address of label/page PC-relative
|
|
void ADR(ARM64Reg Rd, s32 imm);
|
|
void ADRP(ARM64Reg Rd, s32 imm);
|
|
|
|
// Wrapper around MOVZ+MOVK
|
|
void MOVI2R(ARM64Reg Rd, u64 imm, bool optimize = true);
|
|
bool MOVI2R2(ARM64Reg Rd, u64 imm1, u64 imm2);
|
|
template <class P>
|
|
void MOVP2R(ARM64Reg Rd, P* ptr)
|
|
{
|
|
_assert_msg_(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
|
|
MOVI2R(Rd, (uintptr_t)ptr);
|
|
}
|
|
|
|
// Wrapper around AND x, y, imm etc. If you are sure the imm will work, no need to pass a scratch
|
|
// register.
|
|
void ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void TSTI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG)
|
|
{
|
|
ANDSI2R(Is64Bit(Rn) ? ZR : WZR, Rn, imm, scratch);
|
|
}
|
|
void ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void CMPI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
|
|
void ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
|
|
ARM64Reg scratch);
|
|
void ADDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void ADDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void SUBI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
void SUBSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
|
|
|
|
bool TryADDI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
|
|
bool TrySUBI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
|
|
bool TryCMPI2R(ARM64Reg Rn, u32 imm);
|
|
|
|
bool TryANDI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
|
|
bool TryORRI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
|
|
bool TryEORI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
|
|
|
|
// ABI related
|
|
void ABI_PushRegisters(BitSet32 registers);
|
|
void ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask = BitSet32(0));
|
|
|
|
// Utility to generate a call to a std::function object.
|
|
//
|
|
// Unfortunately, calling operator() directly is undefined behavior in C++
|
|
// (this method might be a thunk in the case of multi-inheritance) so we
|
|
// have to go through a trampoline function.
|
|
template <typename T, typename... Args>
|
|
static T CallLambdaTrampoline(const std::function<T(Args...)>* f, Args... args)
|
|
{
|
|
return (*f)(args...);
|
|
}
|
|
|
|
// This function expects you to have set up the state.
|
|
// Overwrites X0 and X30
|
|
template <typename T, typename... Args>
|
|
ARM64Reg ABI_SetupLambda(const std::function<T(Args...)>* f)
|
|
{
|
|
auto trampoline = &ARM64XEmitter::CallLambdaTrampoline<T, Args...>;
|
|
MOVI2R(X30, (uintptr_t)trampoline);
|
|
MOVI2R(X0, (uintptr_t) const_cast<void*>((const void*)f));
|
|
return X30;
|
|
}
|
|
|
|
// Plain function call
|
|
void QuickCallFunction(ARM64Reg scratchreg, const void* func);
|
|
template <typename T>
|
|
void QuickCallFunction(ARM64Reg scratchreg, T func)
|
|
{
|
|
QuickCallFunction(scratchreg, (const void*)func);
|
|
}
|
|
};
|
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class ARM64FloatEmitter
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{
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public:
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ARM64FloatEmitter(ARM64XEmitter* emit) : m_emit(emit) {}
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void LDR(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void STR(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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// Loadstore unscaled
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void LDUR(u8 size, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void STUR(u8 size, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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// Loadstore single structure
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void LD1(u8 size, ARM64Reg Rt, u8 index, ARM64Reg Rn);
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void LD1(u8 size, ARM64Reg Rt, u8 index, ARM64Reg Rn, ARM64Reg Rm);
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void LD1R(u8 size, ARM64Reg Rt, ARM64Reg Rn);
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void LD2R(u8 size, ARM64Reg Rt, ARM64Reg Rn);
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void LD1R(u8 size, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);
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void LD2R(u8 size, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);
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void ST1(u8 size, ARM64Reg Rt, u8 index, ARM64Reg Rn);
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void ST1(u8 size, ARM64Reg Rt, u8 index, ARM64Reg Rn, ARM64Reg Rm);
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// Loadstore multiple structure
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void LD1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn);
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void LD1(u8 size, u8 count, IndexType type, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm = SP);
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void ST1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn);
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void ST1(u8 size, u8 count, IndexType type, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm = SP);
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// Loadstore paired
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void LDP(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
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void STP(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
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// Loadstore register offset
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void STR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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void LDR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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// Scalar - 1 Source
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void FABS(ARM64Reg Rd, ARM64Reg Rn);
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void FNEG(ARM64Reg Rd, ARM64Reg Rn);
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void FSQRT(ARM64Reg Rd, ARM64Reg Rn);
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void FMOV(ARM64Reg Rd, ARM64Reg Rn, bool top = false); // Also generalized move between GPR/FP
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// Scalar - 2 Source
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void FADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAXNM(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMINNM(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FNMUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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// Scalar - 3 Source. Note - the accumulator is last on ARM!
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void FMADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FMSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FNMADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FNMSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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// Scalar floating point immediate
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void FMOV(ARM64Reg Rd, uint8_t imm8);
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// Vector
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void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void BSL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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void FABS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAX(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLS(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMIN(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FCVTL(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTL2(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTZS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTZU(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FDIV(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void NOT(ARM64Reg Rd, ARM64Reg Rn);
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void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void MOV(ARM64Reg Rd, ARM64Reg Rn) { ORR(Rd, Rn, Rn); }
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void REV16(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void REV32(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void REV64(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void SQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void SQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void UQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void UQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void XTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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// Move
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void INS(u8 size, ARM64Reg Rd, u8 index, ARM64Reg Rn);
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void INS(u8 size, ARM64Reg Rd, u8 index1, ARM64Reg Rn, u8 index2);
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void UMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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void SMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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// One source
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void FCVT(u8 size_to, u8 size_from, ARM64Reg Rd, ARM64Reg Rn);
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// Scalar convert float to int, in a lot of variants.
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// Note that the scalar version of this operation has two encodings, one that goes to an integer
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// register
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// and one that outputs to a scalar fp register.
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void FCVTS(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round);
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void FCVTU(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round);
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// Scalar convert int to float. No rounding mode specifier necessary.
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void SCVTF(ARM64Reg Rd, ARM64Reg Rn);
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void UCVTF(ARM64Reg Rd, ARM64Reg Rn);
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// Scalar fixed point to float. scale is the number of fractional bits.
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void SCVTF(ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(ARM64Reg Rd, ARM64Reg Rn, int scale);
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// Float comparison
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void FCMP(ARM64Reg Rn, ARM64Reg Rm);
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void FCMP(ARM64Reg Rn);
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void FCMPE(ARM64Reg Rn, ARM64Reg Rm);
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void FCMPE(ARM64Reg Rn);
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void FCMEQ(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FCMEQ(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCMGE(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FCMGE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCMGT(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FCMGT(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCMLE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCMLT(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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// Conditional select
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void FCSEL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
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// Permute
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void UZP1(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void TRN1(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void ZIP1(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void UZP2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void TRN2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void ZIP2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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// Shift by immediate
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void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SSHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void USHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SHRN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
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void SXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
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void UXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
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void UXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
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// vector x indexed element
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void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
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void FMLA(u8 esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
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// Modified Immediate
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void MOVI(u8 size, ARM64Reg Rd, u64 imm, u8 shift = 0);
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void BIC(u8 size, ARM64Reg Rd, u8 imm, u8 shift = 0);
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void MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG, bool negate = false);
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void MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG);
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// ABI related
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void ABI_PushRegisters(BitSet32 registers, ARM64Reg tmp = INVALID_REG);
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void ABI_PopRegisters(BitSet32 registers, ARM64Reg tmp = INVALID_REG);
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private:
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ARM64XEmitter* m_emit;
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inline void Write32(u32 value) { m_emit->Write32(value); }
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// Emitting functions
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void EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void EmitScalar2Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn,
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ARM64Reg Rm);
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void EmitThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd, ARM64Reg Rn);
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void Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt,
|
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ARM64Reg Rn);
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void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt,
|
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ARM64Reg Rn, ARM64Reg Rm);
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void Emit1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitConversion(bool sf, bool S, u32 type, u32 rmode, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitConversion2(bool sf, bool S, bool direction, u32 type, u32 rmode, u32 opcode, int scale,
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ARM64Reg Rd, ARM64Reg Rn);
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void EmitCompare(bool M, bool S, u32 op, u32 opcode2, ARM64Reg Rn, ARM64Reg Rm);
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void EmitCondSelect(bool M, bool S, CCFlags cond, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EmitPermute(u32 size, u32 op, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64Reg Rd, u32 imm8);
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void EmitShiftImm(bool Q, bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitScalarShiftImm(bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitLoadStoreMultipleStructure(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn);
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void EmitLoadStoreMultipleStructurePost(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn,
|
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ARM64Reg Rm);
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void EmitScalar1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
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void EmitVectorxElement(bool U, u32 size, bool L, u32 opcode, bool H, ARM64Reg Rd, ARM64Reg Rn,
|
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ARM64Reg Rm);
|
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void EmitLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round, bool sign);
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void EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra,
|
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int opcode);
|
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void EncodeLoadStorePair(u32 size, bool load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2,
|
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ARM64Reg Rn, s32 imm);
|
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void EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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void EncodeModImm(bool Q, u8 op, u8 cmode, u8 o2, ARM64Reg Rd, u8 abcdefgh);
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void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
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void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
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void SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
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void SXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper);
|
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void UXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper);
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};
|
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|
|
class ARM64CodeBlock : public CodeBlock<ARM64XEmitter>
|
|
{
|
|
private:
|
|
void PoisonMemory() override
|
|
{
|
|
u32* ptr = (u32*)region;
|
|
u32* maxptr = (u32*)(region + region_size);
|
|
// If our memory isn't a multiple of u32 then this won't write the last remaining bytes with
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// anything
|
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// Less than optimal, but there would be nothing we could do but throw a runtime warning anyway.
|
|
// AArch64: 0xD4200000 = BRK 0
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while (ptr < maxptr)
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*ptr++ = 0xD4200000;
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}
|
|
};
|
|
}
|