forked from dolphin-emu/dolphin
f103234e2b
This should dramatically reduce code size in the case of blocks with lots of branches, and certainly doesn't hurt elsewhere either. This can probably be improved a good bit through smarter tracking of register usage, e.g. discarding registers that are going to be overwritten, but this is a good start and should help reduce code size and register pressure. Unlike that sort of change, this is a "safe" patch; it only flushes registers, which can't affect correctness, unlike actually discarding data. As part of this, refactor PPCAnalyst to support distinguishing between float and integer registers (to properly handle instructions that access both, like floating-point loads and stores). Also update every instruction in the interpreter flags table I could find that didn't have all the correct flags.
852 lines
24 KiB
C++
852 lines
24 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <queue>
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#include <string>
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#include "Common/StringUtil.h"
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#include "Core/ConfigManager.h"
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#include "Core/GeckoCode.h"
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#include "Core/HW/Memmap.h"
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#include "Core/PowerPC/JitInterface.h"
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#include "Core/PowerPC/PPCAnalyst.h"
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#include "Core/PowerPC/PPCSymbolDB.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/SignatureDB.h"
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#include "Core/PowerPC/JitCommon/JitCache.h"
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// Analyzes PowerPC code in memory to find functions
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// After running, for each function we will know what functions it calls
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// and what functions calls it. That is, we will have an incomplete call graph,
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// but only missing indirect branches.
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// The results of this analysis is displayed in the code browsing sections at the bottom left
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// of the disassembly window (debugger).
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// It is also useful for finding function boundaries so that we can find, fingerprint and detect library functions.
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// We don't do this much currently. Only for the special case Super Monkey Ball.
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namespace PPCAnalyst
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{
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static const int CODEBUFFER_SIZE = 32000;
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// 0 does not perform block merging
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static const u32 FUNCTION_FOLLOWING_THRESHOLD = 16;
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CodeBuffer::CodeBuffer(int size)
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{
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codebuffer = new PPCAnalyst::CodeOp[size];
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size_ = size;
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}
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CodeBuffer::~CodeBuffer()
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{
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delete[] codebuffer;
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}
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void AnalyzeFunction2(Symbol &func);
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u32 EvaluateBranchTarget(UGeckoInstruction instr, u32 pc);
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#define INVALID_TARGET ((u32)-1)
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u32 EvaluateBranchTarget(UGeckoInstruction instr, u32 pc)
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{
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switch (instr.OPCD)
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{
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case 18://branch instruction
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{
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u32 target = SignExt26(instr.LI<<2);
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if (!instr.AA)
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target += pc;
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return target;
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}
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default:
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return INVALID_TARGET;
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}
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}
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//To find the size of each found function, scan
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//forward until we hit blr. In the meantime, collect information
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//about which functions this function calls.
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//Also collect which internal branch goes the farthest
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//If any one goes farther than the blr, assume that there is more than
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//one blr, and keep scanning.
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bool AnalyzeFunction(u32 startAddr, Symbol &func, int max_size)
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{
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if (!func.name.size())
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func.name = StringFromFormat("zz_%07x_", startAddr & 0x0FFFFFF);
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if (func.analyzed >= 1)
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return true; // No error, just already did it.
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func.calls.clear();
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func.callers.clear();
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func.size = 0;
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func.flags = FFLAG_LEAF;
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u32 addr = startAddr;
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u32 farthestInternalBranchTarget = startAddr;
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int numInternalBranches = 0;
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while (true)
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{
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func.size += 4;
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if (func.size >= CODEBUFFER_SIZE * 4) //weird
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return false;
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UGeckoInstruction instr = (UGeckoInstruction)Memory::ReadUnchecked_U32(addr);
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if (max_size && func.size > max_size)
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{
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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if (PPCTables::IsValidInstruction(instr))
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{
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if (instr.hex == 0x4e800020) //4e800021 is blrl, not the end of a function
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{
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//BLR
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if (farthestInternalBranchTarget > addr)
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{
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//bah, not this one, continue..
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}
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else
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{
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//a final blr!
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//We're done! Looks like we have a neat valid function. Perfect.
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//Let's calc the checksum and get outta here
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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}
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/*
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else if ((instr.hex & 0xFC000000) == (0x4b000000 & 0xFC000000) && !instr.LK)
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{
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u32 target = addr + SignExt26(instr.LI << 2);
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if (target < startAddr || (max_size && target > max_size+startAddr))
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{
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//block ends by branching away. We're done!
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func.size *= 4; // into bytes
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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}*/
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else if (instr.hex == 0x4e800021 || instr.hex == 0x4e800420 || instr.hex == 0x4e800421)
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{
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func.flags &= ~FFLAG_LEAF;
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func.flags |= FFLAG_EVIL;
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}
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else if (instr.hex == 0x4c000064)
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{
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func.flags &= ~FFLAG_LEAF;
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func.flags |= FFLAG_RFI;
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}
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else
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{
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if (instr.OPCD == 16)
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{
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u32 target = SignExt16(instr.BD << 2);
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if (!instr.AA)
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target += addr;
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if (target > farthestInternalBranchTarget && !instr.LK)
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{
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farthestInternalBranchTarget = target;
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}
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numInternalBranches++;
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}
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else
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{
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u32 target = EvaluateBranchTarget(instr, addr);
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if (target != INVALID_TARGET && instr.LK)
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{
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//we found a branch-n-link!
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func.calls.push_back(SCall(target,addr));
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func.flags &= ~FFLAG_LEAF;
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}
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}
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}
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}
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else
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{
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return false;
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}
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addr += 4;
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}
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}
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// Second pass analysis, done after the first pass is done for all functions
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// so we have more information to work with
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static void AnalyzeFunction2(Symbol *func)
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{
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u32 flags = func->flags;
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bool nonleafcall = false;
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for (const SCall& c : func->calls)
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{
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Symbol *called_func = g_symbolDB.GetSymbolFromAddr(c.function);
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if (called_func && (called_func->flags & FFLAG_LEAF) == 0)
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{
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nonleafcall = true;
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break;
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}
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}
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if (nonleafcall && !(flags & FFLAG_EVIL) && !(flags & FFLAG_RFI))
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flags |= FFLAG_ONLYCALLSNICELEAFS;
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func->flags = flags;
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}
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static bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b)
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{
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const GekkoOPInfo *a_info = a.opinfo;
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const GekkoOPInfo *b_info = b.opinfo;
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int a_flags = a_info->flags;
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int b_flags = b_info->flags;
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if (b_flags & (FL_SET_CRx | FL_ENDBLOCK | FL_TIMER | FL_EVIL | FL_SET_OE))
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return false;
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if ((b_flags & (FL_RC_BIT | FL_RC_BIT_F)) && (b.inst.Rc))
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return false;
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if ((a_flags & (FL_SET_CA | FL_READ_CA)) && (b_flags & (FL_SET_CA | FL_READ_CA)))
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return false;
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switch (b.inst.OPCD)
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{
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case 16:
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case 18:
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//branches. Do not swap.
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case 17: //sc
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case 46: //lmw
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case 19: //table19 - lots of tricky stuff
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return false;
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}
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// For now, only integer ops acceptable. Any instruction which can raise an
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// interrupt is *not* a possible swap candidate: see [1] for an example of
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// a crash caused by this error.
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//
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// [1] https://code.google.com/p/dolphin-emu/issues/detail?id=5864#c7
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if (b_info->type != OPTYPE_INTEGER)
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return false;
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// Check that we have no register collisions.
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// That is, check that none of b's outputs matches any of a's inputs,
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// and that none of a's outputs matches any of b's inputs.
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// The latter does not apply if a is a cmp, of course, but doesn't hurt to check.
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for (int j = 0; j < 3; j++)
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{
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int regInA = a.regsIn[j];
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int regInB = b.regsIn[j];
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// register collision: b outputs to one of a's inputs
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if (regInA >= 0 && (b.regsOut[0] == regInA || b.regsOut[1] == regInA))
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return false;
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// register collision: a outputs to one of b's inputs
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if (regInB >= 0 && (a.regsOut[0] == regInB || a.regsOut[1] == regInB))
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return false;
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// register collision: b outputs to one of a's outputs (overwriting it)
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for (int k = 0; k < 2; k++)
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if (b.regsOut[k] >= 0 && (b.regsOut[k] == a.regsOut[0] || b.regsOut[k] == a.regsOut[1]))
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return false;
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}
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return true;
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}
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// Most functions that are relevant to analyze should be
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// called by another function. Therefore, let's scan the
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// entire space for bl operations and find what functions
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// get called.
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static void FindFunctionsFromBranches(u32 startAddr, u32 endAddr, SymbolDB *func_db)
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{
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for (u32 addr = startAddr; addr < endAddr; addr+=4)
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{
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UGeckoInstruction instr = (UGeckoInstruction)Memory::ReadUnchecked_U32(addr);
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if (PPCTables::IsValidInstruction(instr))
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{
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switch (instr.OPCD)
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{
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case 18://branch instruction
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{
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if (instr.LK) //bl
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{
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u32 target = SignExt26(instr.LI << 2);
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if (!instr.AA)
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target += addr;
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if (Memory::IsRAMAddress(target))
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{
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func_db->AddFunction(target);
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}
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}
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}
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break;
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default:
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break;
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}
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}
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}
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}
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static void FindFunctionsAfterBLR(PPCSymbolDB *func_db)
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{
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std::vector<u32> funcAddrs;
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for (const auto& func : func_db->Symbols())
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funcAddrs.push_back(func.second.address + func.second.size);
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for (u32& location : funcAddrs)
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{
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while (true)
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{
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if (PPCTables::IsValidInstruction(Memory::Read_Instruction(location)))
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{
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//check if this function is already mapped
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Symbol *f = func_db->AddFunction(location);
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if (!f)
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break;
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else
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location += f->size;
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}
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else
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break;
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}
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}
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}
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void FindFunctions(u32 startAddr, u32 endAddr, PPCSymbolDB *func_db)
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{
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//Step 1: Find all functions
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FindFunctionsFromBranches(startAddr, endAddr, func_db);
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FindFunctionsAfterBLR(func_db);
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//Step 2:
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func_db->FillInCallers();
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int numLeafs = 0, numNice = 0, numUnNice = 0;
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int numTimer = 0, numRFI = 0, numStraightLeaf = 0;
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int leafSize = 0, niceSize = 0, unniceSize = 0;
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for (auto& func : func_db->AccessSymbols())
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{
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if (func.second.address == 4)
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{
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WARN_LOG(OSHLE, "Weird function");
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continue;
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}
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AnalyzeFunction2(&(func.second));
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Symbol &f = func.second;
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if (f.name.substr(0, 3) == "zzz")
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{
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if (f.flags & FFLAG_LEAF)
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f.name += "_leaf";
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if (f.flags & FFLAG_STRAIGHT)
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f.name += "_straight";
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}
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if (f.flags & FFLAG_LEAF)
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{
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numLeafs++;
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leafSize += f.size;
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}
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else if (f.flags & FFLAG_ONLYCALLSNICELEAFS)
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{
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numNice++;
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niceSize += f.size;
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}
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else
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{
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numUnNice++;
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unniceSize += f.size;
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}
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if (f.flags & FFLAG_TIMERINSTRUCTIONS)
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numTimer++;
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if (f.flags & FFLAG_RFI)
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numRFI++;
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if ((f.flags & FFLAG_STRAIGHT) && (f.flags & FFLAG_LEAF))
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numStraightLeaf++;
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}
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if (numLeafs == 0)
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leafSize = 0;
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else
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leafSize /= numLeafs;
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if (numNice == 0)
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niceSize = 0;
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else
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niceSize /= numNice;
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if (numUnNice == 0)
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unniceSize = 0;
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else
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unniceSize /= numUnNice;
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INFO_LOG(OSHLE, "Functions analyzed. %i leafs, %i nice, %i unnice."
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"%i timer, %i rfi. %i are branchless leafs.", numLeafs,
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numNice, numUnNice, numTimer, numRFI, numStraightLeaf);
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INFO_LOG(OSHLE, "Average size: %i (leaf), %i (nice), %i(unnice)",
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leafSize, niceSize, unniceSize);
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}
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static bool isCmp(const CodeOp& a)
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{
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return (a.inst.OPCD == 10 || a.inst.OPCD == 11) || (a.inst.OPCD == 31 && (a.inst.SUBOP10 == 0 || a.inst.SUBOP10 == 32));
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}
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static bool isRlwinm_rc(const CodeOp& a)
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{
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return a.inst.OPCD == 21 && a.inst.Rc;
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}
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static bool isCarryOp(const CodeOp& a)
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{
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return (a.opinfo->flags & FL_SET_CA) && !(a.opinfo->flags & FL_SET_OE) && a.opinfo->type == OPTYPE_INTEGER;
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}
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void PPCAnalyzer::ReorderInstructionsCore(u32 instructions, CodeOp* code, bool reverse, ReorderType type)
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{
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// Bubbling an instruction sometimes reveals another opportunity to bubble an instruction, so do
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// multiple passes.
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while (true)
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{
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// Instruction Reordering Pass
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// Carry pass: bubble carry-using instructions as close to each other as possible, so we can avoid
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// storing the carry flag.
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// Compare pass: bubble compare instructions next to branches, so they can be merged.
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bool swapped = false;
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int increment = reverse ? -1 : 1;
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int start = reverse ? instructions - 1 : 0;
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int end = reverse ? 0 : instructions - 1;
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for (int i = start; i != end; i += increment)
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{
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CodeOp &a = code[i];
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CodeOp &b = code[i + increment];
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// Reorder integer compares, rlwinm., and carry-affecting ops
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// (if we add more merged branch instructions, add them here!)
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if ((type == REORDER_CARRY && isCarryOp(a)) || (type == REORDER_CMP && (isCmp(a) || isRlwinm_rc(a))))
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{
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// once we're next to a carry instruction, don't move away!
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if (type == REORDER_CARRY && i != start)
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{
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// if we read the CA flag, and the previous instruction sets it, don't move away.
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if (!reverse && (a.opinfo->flags & FL_READ_CA) && (code[i - increment].opinfo->flags & FL_SET_CA))
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continue;
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// if we set the CA flag, and the next instruction reads it, don't move away.
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if (reverse && (a.opinfo->flags & FL_SET_CA) && (code[i - increment].opinfo->flags & FL_READ_CA))
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continue;
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}
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if (CanSwapAdjacentOps(a, b))
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{
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// Alright, let's bubble it!
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std::swap(a, b);
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swapped = true;
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}
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}
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}
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if (!swapped)
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return;
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}
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}
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void PPCAnalyzer::ReorderInstructions(u32 instructions, CodeOp *code)
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{
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// For carry, bubble instructions *towards* each other; one direction often isn't enough
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// to get pairs like addc/adde next to each other.
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if (HasOption(OPTION_CARRY_MERGE))
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{
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ReorderInstructionsCore(instructions, code, true, REORDER_CARRY);
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ReorderInstructionsCore(instructions, code, false, REORDER_CARRY);
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}
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if (HasOption(OPTION_BRANCH_MERGE))
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ReorderInstructionsCore(instructions, code, false, REORDER_CMP);
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}
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void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInfo *opinfo, u32 index)
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{
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code->wantsCR0 = false;
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code->wantsCR1 = false;
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if (opinfo->flags & FL_USE_FPU)
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block->m_fpa->any = true;
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if (opinfo->flags & FL_TIMER)
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block->m_gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (opinfo->flags & FL_RC_BIT)
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code->outputCR0 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 0)
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code->outputCR0 = true;
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else
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code->outputCR0 = (opinfo->flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (opinfo->flags & FL_RC_BIT_F)
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code->outputCR1 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 1)
|
|
code->outputCR1 = true;
|
|
else
|
|
code->outputCR1 = (opinfo->flags & FL_SET_CR1) ? true : false;
|
|
|
|
code->wantsFPRF = (opinfo->flags & FL_READ_FPRF) ? true : false;
|
|
code->outputFPRF = (opinfo->flags & FL_SET_FPRF) ? true : false;
|
|
code->canEndBlock = (opinfo->flags & FL_ENDBLOCK) ? true : false;
|
|
|
|
code->wantsCA = (opinfo->flags & FL_READ_CA) ? true : false;
|
|
code->outputCA = (opinfo->flags & FL_SET_CA) ? true : false;
|
|
|
|
// We're going to try to avoid storing carry in XER if we can avoid it -- keep it in the x86 carry flag!
|
|
// If the instruction reads CA but doesn't write it, we still need to store CA in XER; we can't
|
|
// leave it in flags.
|
|
if (HasOption(OPTION_CARRY_MERGE))
|
|
code->wantsCAInFlags = code->wantsCA && code->outputCA && opinfo->type == OPTYPE_INTEGER;
|
|
else
|
|
code->wantsCAInFlags = false;
|
|
|
|
// mfspr/mtspr can affect/use XER, so be super careful here
|
|
// we need to note specifically that mfspr needs CA in XER, not in the x86 carry flag
|
|
if (code->inst.OPCD == 31 && code->inst.SUBOP10 == 339) // mfspr
|
|
code->wantsCA = ((code->inst.SPRU << 5) | (code->inst.SPRL & 0x1F)) == SPR_XER;
|
|
if (code->inst.OPCD == 31 && code->inst.SUBOP10 == 467) // mtspr
|
|
code->outputCA = ((code->inst.SPRU << 5) | (code->inst.SPRL & 0x1F)) == SPR_XER;
|
|
|
|
int numOut = 0;
|
|
int numIn = 0;
|
|
int numFloatIn = 0;
|
|
if (opinfo->flags & FL_OUT_A)
|
|
{
|
|
code->regsOut[numOut++] = code->inst.RA;
|
|
block->m_gpa->SetOutputRegister(code->inst.RA, index);
|
|
}
|
|
if (opinfo->flags & FL_OUT_D)
|
|
{
|
|
code->regsOut[numOut++] = code->inst.RD;
|
|
block->m_gpa->SetOutputRegister(code->inst.RD, index);
|
|
}
|
|
if (opinfo->flags & FL_OUT_S)
|
|
{
|
|
code->regsOut[numOut++] = code->inst.RS;
|
|
block->m_gpa->SetOutputRegister(code->inst.RS, index);
|
|
}
|
|
if ((opinfo->flags & FL_IN_A) || ((opinfo->flags & FL_IN_A0) && code->inst.RA != 0))
|
|
{
|
|
code->regsIn[numIn++] = code->inst.RA;
|
|
block->m_gpa->SetInputRegister(code->inst.RA, index);
|
|
}
|
|
if (opinfo->flags & FL_IN_B)
|
|
{
|
|
code->regsIn[numIn++] = code->inst.RB;
|
|
block->m_gpa->SetInputRegister(code->inst.RB, index);
|
|
}
|
|
if (opinfo->flags & FL_IN_C)
|
|
{
|
|
code->regsIn[numIn++] = code->inst.RC;
|
|
block->m_gpa->SetInputRegister(code->inst.RC, index);
|
|
}
|
|
if (opinfo->flags & FL_IN_S)
|
|
{
|
|
code->regsIn[numIn++] = code->inst.RS;
|
|
block->m_gpa->SetInputRegister(code->inst.RS, index);
|
|
}
|
|
|
|
code->fregOut = -1;
|
|
if (opinfo->flags & FL_OUT_FLOAT_D)
|
|
code->fregOut = code->inst.FD;
|
|
else if (opinfo->flags & FL_OUT_FLOAT_S)
|
|
code->fregOut = code->inst.FS;
|
|
if (opinfo->flags & FL_IN_FLOAT_A)
|
|
code->fregsIn[numFloatIn++] = code->inst.FA;
|
|
if (opinfo->flags & FL_IN_FLOAT_B)
|
|
code->fregsIn[numFloatIn++] = code->inst.FB;
|
|
if (opinfo->flags & FL_IN_FLOAT_C)
|
|
code->fregsIn[numFloatIn++] = code->inst.FC;
|
|
if (opinfo->flags & FL_IN_FLOAT_D)
|
|
code->fregsIn[numFloatIn++] = code->inst.FD;
|
|
if (opinfo->flags & FL_IN_FLOAT_S)
|
|
code->fregsIn[numFloatIn++] = code->inst.FS;
|
|
|
|
// Set remaining register slots as unused (-1)
|
|
for (int j = numIn; j < 3; j++)
|
|
code->regsIn[j] = -1;
|
|
for (int j = numOut; j < 2; j++)
|
|
code->regsOut[j] = -1;
|
|
for (int j = numFloatIn; j < 4; j++)
|
|
code->fregsIn[j] = -1;
|
|
|
|
switch (opinfo->type)
|
|
{
|
|
case OPTYPE_INTEGER:
|
|
case OPTYPE_LOAD:
|
|
case OPTYPE_STORE:
|
|
case OPTYPE_LOADFP:
|
|
case OPTYPE_STOREFP:
|
|
break;
|
|
case OPTYPE_SINGLEFP:
|
|
case OPTYPE_DOUBLEFP:
|
|
break;
|
|
case OPTYPE_BRANCH:
|
|
if (code->inst.hex == 0x4e800020)
|
|
{
|
|
// For analysis purposes, we can assume that blr eats opinfo->flags.
|
|
code->outputCR0 = true;
|
|
code->outputCR1 = true;
|
|
}
|
|
break;
|
|
case OPTYPE_SYSTEM:
|
|
case OPTYPE_SYSTEMFP:
|
|
break;
|
|
}
|
|
}
|
|
|
|
u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32 blockSize)
|
|
{
|
|
// Clear block stats
|
|
memset(block->m_stats, 0, sizeof(BlockStats));
|
|
|
|
// Clear register stats
|
|
block->m_gpa->any = true;
|
|
block->m_fpa->any = false;
|
|
|
|
block->m_gpa->Clear();
|
|
block->m_fpa->Clear();
|
|
|
|
// Set the blocks start address
|
|
block->m_address = address;
|
|
|
|
// Reset our block state
|
|
block->m_broken = false;
|
|
block->m_memory_exception = false;
|
|
block->m_num_instructions = 0;
|
|
|
|
if (address == 0)
|
|
{
|
|
// Memory exception occurred during instruction fetch
|
|
block->m_memory_exception = true;
|
|
return address;
|
|
}
|
|
|
|
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU && (address & JIT_ICACHE_VMEM_BIT))
|
|
{
|
|
if (!Memory::TranslateAddress(address, Memory::FLAG_OPCODE))
|
|
{
|
|
// Memory exception occurred during instruction fetch
|
|
block->m_memory_exception = true;
|
|
return address;
|
|
}
|
|
}
|
|
|
|
CodeOp *code = buffer->codebuffer;
|
|
|
|
bool found_exit = false;
|
|
u32 return_address = 0;
|
|
u32 numFollows = 0;
|
|
u32 num_inst = 0;
|
|
|
|
for (u32 i = 0; i < blockSize; ++i)
|
|
{
|
|
UGeckoInstruction inst = JitInterface::Read_Opcode_JIT(address);
|
|
|
|
if (inst.hex != 0)
|
|
{
|
|
num_inst++;
|
|
memset(&code[i], 0, sizeof(CodeOp));
|
|
GekkoOPInfo *opinfo = GetOpInfo(inst);
|
|
|
|
code[i].opinfo = opinfo;
|
|
code[i].address = address;
|
|
code[i].inst = inst;
|
|
code[i].branchTo = -1;
|
|
code[i].branchToIndex = -1;
|
|
code[i].skip = false;
|
|
block->m_stats->numCycles += opinfo->numCycles;
|
|
|
|
SetInstructionStats(block, &code[i], opinfo, i);
|
|
|
|
bool follow = false;
|
|
u32 destination = 0;
|
|
|
|
bool conditional_continue = false;
|
|
|
|
// Do we inline leaf functions?
|
|
if (HasOption(OPTION_LEAF_INLINE))
|
|
{
|
|
if (inst.OPCD == 18 && blockSize > 1)
|
|
{
|
|
//Is bx - should we inline? yes!
|
|
if (inst.AA)
|
|
destination = SignExt26(inst.LI << 2);
|
|
else
|
|
destination = address + SignExt26(inst.LI << 2);
|
|
if (destination != block->m_address)
|
|
follow = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
|
|
(inst.BO & (1 << 4)) && (inst.BO & (1 << 2)) &&
|
|
return_address != 0)
|
|
{
|
|
// bclrx with unconditional branch = return
|
|
follow = true;
|
|
destination = return_address;
|
|
return_address = 0;
|
|
|
|
if (inst.LK)
|
|
return_address = address + 4;
|
|
}
|
|
else if (inst.OPCD == 31 && inst.SUBOP10 == 467)
|
|
{
|
|
// mtspr
|
|
const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
|
|
if (index == SPR_LR)
|
|
{
|
|
// We give up to follow the return address
|
|
// because we have to check the register usage.
|
|
return_address = 0;
|
|
}
|
|
}
|
|
|
|
// TODO: Find the optimal value for FUNCTION_FOLLOWING_THRESHOLD.
|
|
// If it is small, the performance will be down.
|
|
// If it is big, the size of generated code will be big and
|
|
// cache clearning will happen many times.
|
|
// TODO: Investivate the reason why
|
|
// "0" is fastest in some games, MP2 for example.
|
|
if (numFollows > FUNCTION_FOLLOWING_THRESHOLD)
|
|
follow = false;
|
|
}
|
|
|
|
if (HasOption(OPTION_CONDITIONAL_CONTINUE))
|
|
{
|
|
if (inst.OPCD == 16 &&
|
|
((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
|
|
{
|
|
// bcx with conditional branch
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
|
|
((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
|
|
{
|
|
// bclrx with conditional branch
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 3 ||
|
|
(inst.OPCD == 31 && inst.SUBOP10 == 4))
|
|
{
|
|
// tw/twi tests and raises an exception
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 528 &&
|
|
(inst.BO_2 & BO_DONT_CHECK_CONDITION) == 0)
|
|
{
|
|
// Rare bcctrx with conditional branch
|
|
// Seen in NES games
|
|
conditional_continue = true;
|
|
}
|
|
}
|
|
|
|
if (!follow)
|
|
{
|
|
address += 4;
|
|
if (!conditional_continue && opinfo->flags & FL_ENDBLOCK) //right now we stop early
|
|
{
|
|
found_exit = true;
|
|
break;
|
|
}
|
|
}
|
|
// XXX: We don't support inlining yet.
|
|
#if 0
|
|
else
|
|
{
|
|
numFollows++;
|
|
// We don't "code[i].skip = true" here
|
|
// because bx may store a certain value to the link register.
|
|
// Instead, we skip a part of bx in Jit**::bx().
|
|
address = destination;
|
|
merged_addresses[size_of_merged_addresses++] = address;
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
// ISI exception or other critical memory exception occured (game over)
|
|
ERROR_LOG(DYNA_REC, "Instruction hex was 0!");
|
|
break;
|
|
}
|
|
}
|
|
|
|
block->m_num_instructions = num_inst;
|
|
|
|
if (block->m_num_instructions > 1)
|
|
ReorderInstructions(block->m_num_instructions, code);
|
|
|
|
if ((!found_exit && num_inst > 0) || blockSize == 1)
|
|
{
|
|
// We couldn't find an exit
|
|
block->m_broken = true;
|
|
}
|
|
|
|
// Scan for flag dependencies; assume the next block (or any branch that can leave the block)
|
|
// wants flags, to be safe.
|
|
bool wantsCR0 = true;
|
|
bool wantsCR1 = true;
|
|
bool wantsFPRF = true;
|
|
bool wantsCA = true;
|
|
u32 fregInUse = 0;
|
|
u32 regInUse = 0;
|
|
for (int i = block->m_num_instructions - 1; i >= 0; i--)
|
|
{
|
|
bool opWantsCR0 = code[i].wantsCR0;
|
|
bool opWantsCR1 = code[i].wantsCR1;
|
|
bool opWantsFPRF = code[i].wantsFPRF;
|
|
bool opWantsCA = code[i].wantsCA;
|
|
code[i].wantsCR0 = wantsCR0 || code[i].canEndBlock;
|
|
code[i].wantsCR1 = wantsCR1 || code[i].canEndBlock;
|
|
code[i].wantsFPRF = wantsFPRF || code[i].canEndBlock;
|
|
code[i].wantsCA = wantsCA || code[i].canEndBlock;
|
|
wantsCR0 |= opWantsCR0 || code[i].canEndBlock;
|
|
wantsCR1 |= opWantsCR1 || code[i].canEndBlock;
|
|
wantsFPRF |= opWantsFPRF || code[i].canEndBlock;
|
|
wantsCA |= opWantsCA || code[i].canEndBlock;
|
|
wantsCR0 &= !code[i].outputCR0 || opWantsCR0;
|
|
wantsCR1 &= !code[i].outputCR1 || opWantsCR1;
|
|
wantsFPRF &= !code[i].outputFPRF || opWantsFPRF;
|
|
wantsCA &= !code[i].outputCA || opWantsCA;
|
|
code[i].gprInUse = regInUse;
|
|
code[i].fprInUse = fregInUse;
|
|
// TODO: if there's no possible endblocks or exceptions in between, tell the regcache
|
|
// we can throw away a register if it's going to be overwritten later.
|
|
for (int j = 0; j < 3; j++)
|
|
if (code[i].regsIn[j] >= 0)
|
|
regInUse |= 1 << code[i].regsIn[j];
|
|
for (int j = 0; j < 4; j++)
|
|
if (code[i].fregsIn[j] >= 0)
|
|
fregInUse |= 1 << code[i].fregsIn[j];
|
|
// For now, we need to count output registers as "used" though; otherwise the flush
|
|
// will result in a redundant store (e.g. store to regcache, then store again to
|
|
// the same location later).
|
|
for (int j = 0; j < 2; j++)
|
|
if (code[i].regsOut[j] >= 0)
|
|
regInUse |= 1 << code[i].regsOut[j];
|
|
if (code[i].fregOut >= 0)
|
|
fregInUse |= 1 << code[i].fregOut;
|
|
}
|
|
return address;
|
|
}
|
|
|
|
|
|
} // namespace
|