diff --git a/components/esp_hw_support/cpu.c b/components/esp_hw_support/cpu.c
index 642c13e21d..1e629c25f9 100644
--- a/components/esp_hw_support/cpu.c
+++ b/components/esp_hw_support/cpu.c
@@ -167,6 +167,10 @@ static bool is_intr_num_resv(int intr_num)
     reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7);
 #endif
 
+#if SOC_INT_CLIC_SUPPORTED
+    //TODO: IDF-7795
+    return false;
+#endif
     if (reserved & BIT(intr_num)) {
         return true;
     }
diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h
index 524f71f173..125f6caef5 100644
--- a/components/riscv/include/riscv/rv_utils.h
+++ b/components/riscv/include/riscv/rv_utils.h
@@ -107,14 +107,52 @@ FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
     RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
 }
 
+//TODO: IDF-7795, clic related
+#if (SOC_CPU_CORES_NUM > 1)
+FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel(uint32_t restoreval)
+{
+    REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((restoreval << (8 - NLBITS))) | 0x1f);
+}
+
+FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel(uint32_t intlevel)
+{
+    uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
+    uint32_t old_thresh;
+
+    old_thresh = REG_READ(CLIC_INT_THRESH_REG);
+    old_thresh = old_thresh >> (24 + (8 - NLBITS));
+
+    REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((intlevel << (8 - NLBITS))) | 0x1f);
+    RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
+
+    return old_thresh;
+}
+#endif  //#if (SOC_CPU_CORES_NUM > 1)
+
 FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
 {
+//TODO: IDF-7795
+#if SOC_INT_CLIC_SUPPORTED
+    unsigned intr_ena_mask = 0;
+    unsigned intr_num;
+    for (intr_num = 0; intr_num < 32; intr_num++) {
+        if (REG_GET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_IE))
+            intr_ena_mask |= BIT(intr_num);
+    }
+    return intr_ena_mask;
+#else
     return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
+#endif
 }
 
 FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(unsigned int intr_num)
 {
+//TODO: IDF-7795
+#if SOC_INT_CLIC_SUPPORTED
+    REG_SET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET) , CLIC_INT_IP);
+#else
     REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
+#endif
 }
 
 FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
diff --git a/components/riscv/interrupt.c b/components/riscv/interrupt.c
index 5984d0d374..cf754dcbab 100644
--- a/components/riscv/interrupt.c
+++ b/components/riscv/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,12 +11,21 @@
 #include "soc/interrupt_reg.h"
 #include "riscv/csr.h"
 #include "esp_attr.h"
+#include "riscv/rv_utils.h"
+
+
+//TODO: IDF-7795, P4, see jira to know what changed and what need to be checked
+
 
 #define RV_INT_COUNT 32
 
 static inline void assert_valid_rv_int_num(int rv_int_num)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    assert(rv_int_num < RV_INT_COUNT && "Invalid CPU interrupt number");
+#else
     assert(rv_int_num != 0 && rv_int_num < RV_INT_COUNT && "Invalid CPU interrupt number");
+#endif
 }
 
 /*************************** Software interrupt dispatcher ***************************/
@@ -27,63 +36,132 @@ typedef struct {
     void *arg;
 } intr_handler_item_t;
 
+#if SOC_INT_CLIC_SUPPORTED
+static intr_handler_item_t s_intr_handlers_core0[48];
+static intr_handler_item_t s_intr_handlers_core1[48];
+#else
 static intr_handler_item_t s_intr_handlers[32];
+#endif
 
 void intr_handler_set(int int_no, intr_handler_t fn, void *arg)
 {
     assert_valid_rv_int_num(int_no);
 
+#if SOC_INT_CLIC_SUPPORTED
+    if (rv_utils_get_core_id() == 0) {
+        s_intr_handlers_core0[int_no + CLIC_EXT_INTR_NUM_OFFSET] = (intr_handler_item_t) {
+            .handler = fn,
+            .arg = arg,
+        };
+    } else {
+        s_intr_handlers_core1[int_no + CLIC_EXT_INTR_NUM_OFFSET] = (intr_handler_item_t) {
+            .handler = fn,
+            .arg = arg,
+        };
+    }
+#else
     s_intr_handlers[int_no] = (intr_handler_item_t) {
         .handler = fn,
         .arg = arg
     };
+#endif
 }
 
 intr_handler_t intr_handler_get(int rv_int_num)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    if (rv_utils_get_core_id() == 0)
+        return s_intr_handlers_core0[rv_int_num + CLIC_EXT_INTR_NUM_OFFSET].handler;
+    else
+        return s_intr_handlers_core1[rv_int_num + CLIC_EXT_INTR_NUM_OFFSET].handler;
+#else
     return s_intr_handlers[rv_int_num].handler;
+#endif
 }
 
 void *intr_handler_get_arg(int rv_int_num)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    if (rv_utils_get_core_id() == 0)
+        return s_intr_handlers_core0[rv_int_num + CLIC_EXT_INTR_NUM_OFFSET].arg;
+    else
+        return s_intr_handlers_core1[rv_int_num + CLIC_EXT_INTR_NUM_OFFSET].arg;
+#else
     return s_intr_handlers[rv_int_num].arg;
+#endif
 }
 
 /* called from vectors.S */
 void _global_interrupt_handler(intptr_t sp, int mcause)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    if (rv_utils_get_core_id() == 0) {
+        intr_handler_item_t it = s_intr_handlers_core0[mcause];
+        if (it.handler) {
+            (*it.handler)(it.arg);
+        }
+    } else {
+        intr_handler_item_t it = s_intr_handlers_core1[mcause];
+        if (it.handler) {
+            (*it.handler)(it.arg);
+        }
+    }
+#else
     intr_handler_item_t it = s_intr_handlers[mcause];
     if (it.handler) {
         (*it.handler)(it.arg);
     }
+#endif
 }
 
 /*************************** RISC-V interrupt enable/disable ***************************/
 
 void intr_matrix_route(int intr_src, int intr_num)
 {
+#if !SOC_INT_CLIC_SUPPORTED
     assert(intr_num != 0);
 
     REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num);
+#else
+    if (rv_utils_get_core_id() == 0)
+        REG_WRITE(DR_REG_INTERRUPT_CORE0_BASE + 4 * intr_src, intr_num + CLIC_EXT_INTR_NUM_OFFSET);
+    else
+        REG_WRITE(DR_REG_INTERRUPT_CORE1_BASE + 4 * intr_src, intr_num + CLIC_EXT_INTR_NUM_OFFSET);
+#endif
 }
 
+// CLIC for each interrupt line provides a IE register
+// this api is not used
+#if !SOC_INT_CLIC_SUPPORTED
 uint32_t esprv_intc_get_interrupt_unmask(void)
 {
     return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
 }
+#endif
 
 /*************************** ESP-RV Interrupt Controller ***************************/
 
 enum intr_type esprv_intc_int_get_type(int intr_num)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    uint32_t intr_type_reg = REG_GET_FIELD(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG);
+    return (intr_type_reg & 1) ? INTR_TYPE_EDGE : INTR_TYPE_LEVEL;
+    // May also support rising edge and falling edge.
+#else
     uint32_t intr_type_reg = REG_READ(INTERRUPT_CORE0_CPU_INT_TYPE_REG);
     return (intr_type_reg & (1 << intr_num)) ? INTR_TYPE_EDGE : INTR_TYPE_LEVEL;
+#endif
 }
 
 int esprv_intc_int_get_priority(int rv_int_num)
 {
+#if SOC_INT_CLIC_SUPPORTED
+    uint32_t intr_priority_reg = REG_GET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_CTL);
+    return (intr_priority_reg >> (8 - NLBITS));
+#else
     uint32_t intr_priority_reg = REG_READ(INTC_INT_PRIO_REG(rv_int_num));
     return intr_priority_reg;
+#endif
 }
 
 /*************************** Exception names. Used in .gdbinit file. ***************************/