From adc259cc79dc46bb2e69aa9743e67900145dc059 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 15 Dec 2022 15:12:40 +0800 Subject: [PATCH 1/2] efuse_table: update esp32c6 efuse block1 fields definition --- components/efuse/esp32c6/esp_efuse_table.c | 111 ++---------------- components/efuse/esp32c6/esp_efuse_table.csv | 26 +--- .../efuse/esp32c6/include/esp_efuse_table.h | 15 +-- 3 files changed, 14 insertions(+), 138 deletions(-) diff --git a/components/efuse/esp32c6/esp_efuse_table.c b/components/efuse/esp32c6/esp_efuse_table.c index 6dc42cd469..56245df052 100644 --- a/components/efuse/esp32c6/esp_efuse_table.c +++ b/components/efuse/esp32c6/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c +// md5_digest_table 19131923372be226ce98d85f5a13f16a // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -340,48 +340,9 @@ static const esp_efuse_desc_t MAC_FACTORY[] = { {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, +static const esp_efuse_desc_t MAC_EXT[] = { + {EFUSE_BLK1, 48, 8}, // Extend MAC addr [0], + {EFUSE_BLK1, 56, 8}, // Extend MAC addr [1], }; static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { @@ -397,10 +358,6 @@ static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, }; -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, -}; - static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, }; @@ -918,58 +875,9 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 +const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { + &MAC_EXT[0], // Extend MAC addr [0] + &MAC_EXT[1], // Extend MAC addr [1] NULL }; @@ -989,11 +897,6 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID NULL diff --git a/components/efuse/esp32c6/esp_efuse_table.csv b/components/efuse/esp32c6/esp_efuse_table.csv index 242a5c6fee..39b9423157 100644 --- a/components/efuse/esp32c6/esp_efuse_table.csv +++ b/components/efuse/esp32c6/esp_efuse_table.csv @@ -104,39 +104,23 @@ DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major -# MAC_SPI_SYS BLOCK# +# MAC_SYS_VERSION BLOCK # ####################### - # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2 MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] , EFUSE_BLK1, 32, 8, Factory MAC addr [1] , EFUSE_BLK1, 24, 8, Factory MAC addr [2] , EFUSE_BLK1, 16, 8, Factory MAC addr [3] , EFUSE_BLK1, 8, 8, Factory MAC addr [4] , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - - # RD_MAC_SPI_SYS_3 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + MAC_EXT, EFUSE_BLK1, 48, 8, Extend MAC addr [0] + , EFUSE_BLK1, 56, 8, Extend MAC addr [1] WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR - # RD_MAC_SPI_SYS_5 - # WAFER_VERSION_MINOR most significant bit - WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR - -# SYS_DATA_PART1 BLOCK# - System configuration +# SYS_DATA_PART1 BLOCK# - System configuration (TODO: IDF-6483) # ####################### # RD_SYS_PART1_DATA0 - rd_sys_part1_data3 OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID @@ -169,7 +153,7 @@ KEY4, EFUSE_BLK8, 0, 256, Key4 or us KEY5, EFUSE_BLK9, 0, 256, Key5 or user data SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration -# AUTO CONFIG DIG&RTC DBIAS# +# AUTO CONFIG DIG&RTC DBIAS (TODO: IDF-6483)# ################ K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO diff --git a/components/efuse/esp32c6/include/esp_efuse_table.h b/components/efuse/esp32c6/include/esp_efuse_table.h index fe437ad20e..963e3cb547 100644 --- a/components/efuse/esp32c6/include/esp_efuse_table.h +++ b/components/efuse/esp32c6/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c +// md5_digest_table 19131923372be226ce98d85f5a13f16a // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -97,21 +97,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; From 57a6abdad100755c35b8b7a1c8dd2740df475126 Mon Sep 17 00:00:00 2001 From: xiaqilin Date: Mon, 19 Dec 2022 20:29:52 +0800 Subject: [PATCH 2/2] ieee802154: add support ieee802154 for esp32c6 --- components/bt/controller/esp32c3/bt.c | 2 +- components/esp_phy/CMakeLists.txt | 4 +++ components/esp_phy/include/esp_phy_init.h | 10 ++++++++ components/esp_phy/include/esp_private/btbb.h | 23 +++++++++++++++++ .../esp_phy/include/{ => esp_private}/phy.h | 0 components/esp_phy/src/btbb_init.c | 25 +++++++++++++++++++ components/esp_phy/src/phy_init.c | 2 +- components/esp_phy/src/phy_init_esp32hxx.c | 2 +- components/esp_wifi/src/wifi_init.c | 2 +- components/ieee802154/Kconfig | 4 +-- components/ieee802154/lib | 2 +- .../soc/esp32c6/ld/esp32c6.peripherals.ld | 1 + 12 files changed, 70 insertions(+), 7 deletions(-) create mode 100644 components/esp_phy/include/esp_private/btbb.h rename components/esp_phy/include/{ => esp_private}/phy.h (100%) create mode 100644 components/esp_phy/src/btbb_init.c diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 5d98444792..1bab7da38c 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -38,7 +38,7 @@ #include "esp32c3/rom/rom_layout.h" #include "esp_timer.h" #include "esp_sleep.h" -#include "phy.h" +#include "esp_private/phy.h" #if CONFIG_BT_ENABLED diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index e9459c9a4b..28b060f024 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -21,6 +21,10 @@ else() list(APPEND srcs "src/phy_init.c") endif() +if(CONFIG_SOC_BT_SUPPORTED OR CONFIG_SOC_IEEE802154_SUPPORTED) + list(APPEND srcs "src/btbb_init.c") +endif() + idf_build_get_property(build_dir BUILD_DIR) if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN) diff --git a/components/esp_phy/include/esp_phy_init.h b/components/esp_phy/include/esp_phy_init.h index bcf3e289d3..4f30c7795f 100644 --- a/components/esp_phy/include/esp_phy_init.h +++ b/components/esp_phy/include/esp_phy_init.h @@ -170,6 +170,16 @@ void esp_phy_enable(void); */ void esp_phy_disable(void); +/** + * @brief Enable BTBB module + * + * BTBB module should be enabled in order to use IEEE802154 or BT. + * Now BTBB enabling job is done automatically when start IEEE802154 or BT. Users should not + * call this API in their application. + * + */ +void esp_btbb_enable(void); + /** * @brief Load calibration data from NVS and initialize PHY and RF module */ diff --git a/components/esp_phy/include/esp_private/btbb.h b/components/esp_phy/include/esp_private/btbb.h new file mode 100644 index 0000000000..74b0908723 --- /dev/null +++ b/components/esp_phy/include/esp_private/btbb.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set btbb enable for BT/ieee802154 + * @param[in] print_version enable btbb version print. + * @return NULL + */ +void bt_bb_v2_init_cmplx(int print_version); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_phy/include/phy.h b/components/esp_phy/include/esp_private/phy.h similarity index 100% rename from components/esp_phy/include/phy.h rename to components/esp_phy/include/esp_private/phy.h diff --git a/components/esp_phy/src/btbb_init.c b/components/esp_phy/src/btbb_init.c new file mode 100644 index 0000000000..5ae016391a --- /dev/null +++ b/components/esp_phy/src/btbb_init.c @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "freertos/FreeRTOS.h" +#include "esp_private/btbb.h" + +#define BTBB_ENABLE_VERSION_PRINT 1 + +static _lock_t s_btbb_access_lock; +/* Reference count of enabling BT BB */ +static uint8_t s_btbb_access_ref = 0; + +void esp_btbb_enable(void) +{ + _lock_acquire(&s_btbb_access_lock); + if (s_btbb_access_ref == 0) { + bt_bb_v2_init_cmplx(BTBB_ENABLE_VERSION_PRINT); + } + s_btbb_access_ref++; + _lock_release(&s_btbb_access_lock); +} diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 61f610b0c5..05d8e66b02 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -23,7 +23,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/portmacro.h" #include "endian.h" -#include "phy.h" +#include "esp_private/phy.h" #include "phy_init_data.h" #include "esp_coexist_internal.h" #include "esp_private/periph_ctrl.h" diff --git a/components/esp_phy/src/phy_init_esp32hxx.c b/components/esp_phy/src/phy_init_esp32hxx.c index 3c09b77cf2..db6c257fcd 100644 --- a/components/esp_phy/src/phy_init_esp32hxx.c +++ b/components/esp_phy/src/phy_init_esp32hxx.c @@ -7,7 +7,7 @@ #include "esp_attr.h" #include "freertos/portmacro.h" #include "esp_phy_init.h" -#include "phy.h" +#include "esp_private/phy.h" #define PHY_ENABLE_VERSION_PRINT 1 diff --git a/components/esp_wifi/src/wifi_init.c b/components/esp_wifi/src/wifi_init.c index e14f399087..437d1af2c6 100644 --- a/components/esp_wifi/src/wifi_init.c +++ b/components/esp_wifi/src/wifi_init.c @@ -17,7 +17,7 @@ #include "esp_netif.h" #include "esp_coexist_internal.h" #include "esp_phy_init.h" -#include "phy.h" +#include "esp_private/phy.h" #if (CONFIG_ESP32_WIFI_RX_BA_WIN > CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM) #error "WiFi configuration check: WARNING, WIFI_RX_BA_WIN should not be larger than WIFI_DYNAMIC_RX_BUFFER_NUM!" diff --git a/components/ieee802154/Kconfig b/components/ieee802154/Kconfig index 7112d2aa98..ecfffc9eb4 100644 --- a/components/ieee802154/Kconfig +++ b/components/ieee802154/Kconfig @@ -1,8 +1,8 @@ menu "IEEE 802.15.4" - visible if IDF_TARGET_ESP32H4 + visible if SOC_IEEE802154_SUPPORTED config IEEE802154_ENABLED bool - default "y" if IDF_TARGET_ESP32H4 + default "y" if SOC_IEEE802154_SUPPORTED endmenu # IEEE 802.15.4 diff --git a/components/ieee802154/lib b/components/ieee802154/lib index 5c51d657d4..7c691d705b 160000 --- a/components/ieee802154/lib +++ b/components/ieee802154/lib @@ -1 +1 @@ -Subproject commit 5c51d657d4d34f60890540587663925462ababa4 +Subproject commit 7c691d705b491c1dbb53fa6a15e23b1c4ccb287f diff --git a/components/soc/esp32c6/ld/esp32c6.peripherals.ld b/components/soc/esp32c6/ld/esp32c6.peripherals.ld index 2a9acb4b10..8635a430cb 100644 --- a/components/soc/esp32c6/ld/esp32c6.peripherals.ld +++ b/components/soc/esp32c6/ld/esp32c6.peripherals.ld @@ -74,3 +74,4 @@ PROVIDE ( LPPERI = 0x600B2800 ); PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( OTP_DEBUG = 0x600B3C00 ); +PROVIDE ( IEEE802154 = 0x600A3000 );