diff --git a/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe b/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe
index abfc89e440..e82a766cd3 100644
--- a/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe
+++ b/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe
@@ -1,4 +1,7 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y
+CONFIG_COMPILER_OPTIMIZATION_NONE=y
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
+# GPIO test uses IPC call, the default stack size of IPC task can satisfy the -O0 optimization
+CONFIG_ESP_IPC_TASK_STACK_SIZE=2048
diff --git a/components/driver/test_apps/sdm/sdkconfig.ci.iram_safe b/components/driver/test_apps/sdm/sdkconfig.ci.iram_safe
index 0986dcf2e6..3b48d167d1 100644
--- a/components/driver/test_apps/sdm/sdkconfig.ci.iram_safe
+++ b/components/driver/test_apps/sdm/sdkconfig.ci.iram_safe
@@ -1,5 +1,5 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_SDM_CTRL_FUNC_IN_IRAM=y
-
+CONFIG_COMPILER_OPTIMIZATION_NONE=y
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
index 9703099f30..062c3f5481 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c
@@ -33,8 +33,9 @@ static void rtc_clk_cpu_freq_to_8m(void);
 
 void rtc_clk_32k_enable_external(void)
 {
-    gpio_ll_input_enable(&GPIO, EXT_OSC_SLOW_GPIO_NUM);
-    gpio_ll_hold_en(&GPIO, EXT_OSC_SLOW_GPIO_NUM);
+    // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_0
+    PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG);
+    REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(EXT_OSC_SLOW_GPIO_NUM));
 }
 
 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h
index fc613b518e..841e0c9960 100644
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@@ -225,6 +225,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = (core_id == 0) ? hw->pcpu_int : hw->acpu_int;
@@ -237,6 +238,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->acpu_int1, intr);
@@ -248,6 +250,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc = mask;
@@ -259,6 +262,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask);
@@ -271,6 +275,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     if (core_id == 0) {
@@ -286,6 +291,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
@@ -420,6 +426,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h
index 6bf8e536e9..aa7577464e 100644
--- a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h
+++ b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h
@@ -18,28 +18,33 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
 {
     RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
 {
     RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
 {
     RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h
index 4666c65e24..eee81ebacc 100644
--- a/components/hal/esp32c2/include/hal/gpio_ll.h
+++ b/components/hal/esp32c2/include/hal/gpio_ll.h
@@ -93,6 +93,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int.procpu_int;
@@ -105,6 +106,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = 0; // Less than 32 GPIOs in ESP32-C2
@@ -116,6 +118,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc.status_w1tc = mask;
@@ -127,6 +130,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     // Less than 32 GPIOs in ESP32-C2. Do nothing.
@@ -139,6 +143,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
@@ -151,6 +156,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
@@ -232,6 +238,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h
index 6bf8e536e9..defab88dc2 100644
--- a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h
+++ b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h
@@ -18,6 +18,7 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
 {
     RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
@@ -28,18 +29,21 @@ static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
     RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
 {
     RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h
index 66e6f8996f..2a71eb55ab 100644
--- a/components/hal/esp32c3/include/hal/gpio_ll.h
+++ b/components/hal/esp32c3/include/hal/gpio_ll.h
@@ -95,6 +95,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int.intr;
@@ -107,6 +108,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = 0; // Less than 32 GPIOs in ESP32-C3
@@ -118,6 +120,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc.status_w1tc = mask;
@@ -129,6 +132,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     // Less than 32 GPIOs on ESP32-C3. Do nothing.
@@ -141,6 +145,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
@@ -153,6 +158,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
@@ -234,6 +240,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h
index 6bf8e536e9..aa7577464e 100644
--- a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h
+++ b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h
@@ -18,28 +18,33 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
 {
     RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
 {
     RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
 {
     uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
     return value;
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
 {
     RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
diff --git a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h
index 32543a1b2e..64274e845c 100644
--- a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h
+++ b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h
@@ -95,6 +95,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int.procpu_int;
@@ -107,6 +108,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int1.procpu_int1;
@@ -118,6 +120,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc.status_w1tc = mask;
@@ -129,6 +132,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status1_w1tc.status1_w1tc = mask;
@@ -141,6 +145,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
@@ -153,6 +158,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].pin_int_ena = 0;                             //disable GPIO intr
@@ -242,6 +248,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h
index 03544d946a..f414512cb4 100644
--- a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h
+++ b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h
@@ -95,6 +95,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int.procpu_int;
@@ -107,6 +108,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = 0; // Less than 32 GPIOs in ESP32-H2Beta2
@@ -118,6 +120,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc.status_w1tc = mask;
@@ -129,6 +132,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     // Less than 32 GPIOs in ESP32-H2Beta2. Do nothing.
@@ -141,6 +145,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
@@ -153,6 +158,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].pin_int_ena = 0;                             //disable GPIO intr
@@ -234,6 +240,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h
index eb29b57097..4ea9a31595 100644
--- a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h
+++ b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h
@@ -12,6 +12,7 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {
     uint32_t value = 0;
@@ -19,6 +20,7 @@ static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
     return value;
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
 {
     uint32_t value = 0;
@@ -26,11 +28,13 @@ static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
     return value;
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
 {
     asm volatile("wur.gpio_out %0"::"r"(value):);
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
 {
     asm volatile("wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):);
diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h
index 2cd96d3960..dbae67ea86 100644
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -95,6 +95,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int;
@@ -107,6 +108,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     *status = hw->pcpu_int1.intr;
@@ -118,6 +120,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc = mask;
@@ -129,6 +132,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status1_w1tc.intr_st = mask;
@@ -141,6 +145,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
@@ -153,6 +158,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
@@ -243,6 +249,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h
index 945d05dc19..b11330fbf6 100644
--- a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h
+++ b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h
@@ -21,6 +21,7 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {
     uint32_t value = 0;
@@ -28,6 +29,7 @@ static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
     return value;
 }
 
+__attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
 {
     uint32_t value = 0;
@@ -35,11 +37,13 @@ static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
     return value;
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
 {
     asm volatile("wur.gpio_out %0"::"r"(value):);
 }
 
+__attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
 {
     asm volatile("ee.wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):);
diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h
index 77282eca60..e98e0395a3 100644
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -96,6 +96,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
   * @param core_id interrupt core id
   * @param status interrupt status
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     // On ESP32S3, pcpu_int register represents GPIO0-31 interrupt status on both cores
@@ -110,6 +111,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   * @param core_id interrupt core id
   * @param status interrupt status high
   */
+__attribute__((always_inline))
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     // On ESP32S3, pcpu_int1 register represents GPIO32-48 interrupt status on both cores
@@ -123,6 +125,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status_w1tc = mask;
@@ -134,6 +137,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   * @param hw Peripheral GPIO hardware instance address.
   * @param mask interrupt status high clear mask
   */
+__attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
     hw->status1_w1tc.intr_st = mask;
@@ -146,6 +150,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
 {
     (void)core_id;
@@ -158,6 +163,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
@@ -248,6 +254,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
  * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  * @param  level Output level. 0: low ; 1: high
  */
+__attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {