From c079f30295f35f30b8a18490d4095b52c32e7b9b Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 16:36:02 +0800 Subject: [PATCH] refactor(soc): sort esp32c3 soc headers --- .../soc/esp32c3/include/soc/dport_access.h | 3 +- .../soc/esp32c3/include/soc/interrupt_reg.h | 2 +- components/soc/esp32c3/include/soc/soc.h | 2 +- components/soc/esp32c3/register/soc/.gitkeep | 0 .../{include => register}/soc/apb_ctrl_reg.h | 2 +- .../soc/apb_ctrl_struct.h | 0 .../soc/apb_saradc_reg.h | 20 ++++--------- .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 20 ++++--------- .../{include => register}/soc/efuse_reg.h | 4 +-- .../{include => register}/soc/efuse_struct.h | 2 +- .../{include => register}/soc/extmem_reg.h | 20 ++++--------- .../{include => register}/soc/gdma_reg.h | 0 .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 20 ++++--------- .../{include => register}/soc/gpio_sd_reg.h | 2 +- .../soc/gpio_sd_struct.h | 0 .../{include => register}/soc/gpio_struct.h | 18 ++++------- .../{include => register}/soc/i2c_reg.h | 20 ++++--------- .../{include => register}/soc/i2c_struct.h | 2 +- .../{include => register}/soc/i2s_reg.h | 4 +-- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/interrupt_core0_reg.h | 20 ++++--------- .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/ledc_reg.h | 20 ++++--------- .../{include => register}/soc/ledc_struct.h | 0 .../{include => register}/soc/nrx_reg.h | 18 ++++------- .../{include => register}/soc/reg_base.h | 2 +- .../{include => register}/soc/rmt_reg.h | 2 +- .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rtc_cntl_reg.h | 12 ++++---- .../soc/rtc_cntl_struct.h | 10 +++---- .../{include => register}/soc/rtc_i2c_reg.h | 20 ++++--------- .../soc/rtc_i2c_struct.h | 0 .../{include => register}/soc/sensitive_reg.h | 20 ++++--------- .../soc/sensitive_struct.h | 20 ++++--------- .../{include => register}/soc/spi_mem_reg.h | 22 +++++--------- .../soc/spi_mem_struct.h | 2 +- .../{include => register}/soc/spi_reg.h | 18 +++++------ .../{include => register}/soc/spi_struct.h | 4 +-- .../{include => register}/soc/syscon_reg.h | 4 +-- .../{include => register}/soc/syscon_struct.h | 0 .../{include => register}/soc/system_reg.h | 2 +- .../{include => register}/soc/system_struct.h | 2 +- .../{include => register}/soc/systimer_reg.h | 15 ++-------- .../soc/systimer_struct.h | 15 ++-------- .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 30 +++++++------------ .../{include => register}/soc/uart_struct.h | 10 +++---- .../{include => register}/soc/uhci_reg.h | 20 ++++--------- .../{include => register}/soc/uhci_struct.h | 0 .../soc/usb_serial_jtag_reg.h | 10 +++---- .../soc/usb_serial_jtag_struct.h | 20 ++++--------- .../{include => register}/soc/xts_aes_reg.h | 2 +- tools/ci/check_copyright_ignore.txt | 26 ---------------- 57 files changed, 159 insertions(+), 332 deletions(-) delete mode 100644 components/soc/esp32c3/register/soc/.gitkeep rename components/soc/esp32c3/{include => register}/soc/apb_ctrl_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/apb_ctrl_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/apb_saradc_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/assist_debug_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/extmem_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/gdma_reg.h (100%) rename components/soc/esp32c3/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/gpio_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/gpio_sd_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/gpio_sd_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/gpio_struct.h (94%) rename components/soc/esp32c3/{include => register}/soc/i2c_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/i2c_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/interrupt_core0_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/ledc_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/nrx_reg.h (67%) rename components/soc/esp32c3/{include => register}/soc/reg_base.h (97%) rename components/soc/esp32c3/{include => register}/soc/rmt_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/rtc_cntl_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/rtc_cntl_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/rtc_i2c_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/rtc_i2c_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/sensitive_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/sensitive_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_mem_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/spi_mem_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/syscon_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/syscon_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/system_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/system_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/systimer_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/systimer_struct.h (94%) rename components/soc/esp32c3/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c3/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/uart_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/uart_struct.h (98%) rename components/soc/esp32c3/{include => register}/soc/uhci_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/usb_serial_jtag_struct.h (96%) rename components/soc/esp32c3/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c3/include/soc/dport_access.h b/components/soc/esp32c3/include/soc/dport_access.h index 5a847ca484..e499a791bd 100644 --- a/components/soc/esp32c3/include/soc/dport_access.h +++ b/components/soc/esp32c3/include/soc/dport_access.h @@ -8,8 +8,7 @@ #define _DPORT_ACCESS_H_ #include -#include "soc.h" -#include "uart_reg.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/interrupt_reg.h b/components/soc/esp32c3/include/soc/interrupt_reg.h index 749a2e9216..d02c2d5c20 100644 --- a/components/soc/esp32c3/include/soc/interrupt_reg.h +++ b/components/soc/esp32c3/include/soc/interrupt_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "interrupt_core0_reg.h" +#include "soc/interrupt_core0_reg.h" #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG #define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index d661c4eb12..1b47dd70fb 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c3/register/soc/.gitkeep b/components/soc/esp32c3/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/apb_ctrl_reg.h rename to components/soc/esp32c3/register/soc/apb_ctrl_reg.h index cb1966505e..f7fb4f1ba9 100644 --- a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h @@ -11,7 +11,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) /* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/register/soc/apb_ctrl_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/apb_ctrl_struct.h rename to components/soc/esp32c3/register/soc/apb_ctrl_struct.h diff --git a/components/soc/esp32c3/include/soc/apb_saradc_reg.h b/components/soc/esp32c3/register/soc/apb_saradc_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/apb_saradc_reg.h rename to components/soc/esp32c3/register/soc/apb_saradc_reg.h index 69785ca84d..87deea2d3e 100644 --- a/components/soc/esp32c3/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32c3/register/soc/apb_saradc_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_APB_SARADC_REG_H_ #define _SOC_APB_SARADC_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ /*description: wait arbit signal stable after sar_done*/ diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/apb_saradc_struct.h rename to components/soc/esp32c3/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c3/include/soc/assist_debug_reg.h b/components/soc/esp32c3/register/soc/assist_debug_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/assist_debug_reg.h rename to components/soc/esp32c3/register/soc/assist_debug_reg.h index 2b13d1f5f4..615964bd74 100644 --- a/components/soc/esp32c3/include/soc/assist_debug_reg.h +++ b/components/soc/esp32c3/register/soc/assist_debug_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/efuse_reg.h rename to components/soc/esp32c3/register/soc/efuse_reg.h index 4d6781c976..39db7b9abb 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -2376,7 +2376,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register; + * eFuse operation mode configuration register; */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/efuse_struct.h rename to components/soc/esp32c3/register/soc/efuse_struct.h index 99f8c39ec5..f12563cebd 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/register/soc/efuse_struct.h @@ -2015,7 +2015,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register; + * eFuse operation mode configuration register; */ typedef union { struct { diff --git a/components/soc/esp32c3/include/soc/extmem_reg.h b/components/soc/esp32c3/register/soc/extmem_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/extmem_reg.h rename to components/soc/esp32c3/register/soc/extmem_reg.h index 71ab60f640..7a94ea7e66 100644 --- a/components/soc/esp32c3/include/soc/extmem_reg.h +++ b/components/soc/esp32c3/register/soc/extmem_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EXTMEM_REG_H_ #define _SOC_EXTMEM_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: The bit is used to activate the data cache. 0: disable 1: enable*/ diff --git a/components/soc/esp32c3/include/soc/gdma_reg.h b/components/soc/esp32c3/register/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32c3/include/soc/gdma_reg.h rename to components/soc/esp32c3/register/soc/gdma_reg.h diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/gdma_struct.h rename to components/soc/esp32c3/register/soc/gdma_struct.h diff --git a/components/soc/esp32c3/include/soc/gpio_reg.h b/components/soc/esp32c3/register/soc/gpio_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/gpio_reg.h rename to components/soc/esp32c3/register/soc/gpio_reg.h index a674277f99..b92e195e36 100644 --- a/components/soc/esp32c3/include/soc/gpio_reg.h +++ b/components/soc/esp32c3/register/soc/gpio_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_REG_H_ #define _SOC_GPIO_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define GPIO_PIN_CONFIG_MSB 12 #define GPIO_PIN_CONFIG_LSB 11 #define GPIO_PIN_CONFIG_MASK 0x00001800 diff --git a/components/soc/esp32c3/include/soc/gpio_sd_reg.h b/components/soc/esp32c3/register/soc/gpio_sd_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/gpio_sd_reg.h rename to components/soc/esp32c3/register/soc/gpio_sd_reg.h index 3c72df5d40..57d66a44c0 100644 --- a/components/soc/esp32c3/include/soc/gpio_sd_reg.h +++ b/components/soc/esp32c3/register/soc/gpio_sd_reg.h @@ -6,7 +6,7 @@ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/register/soc/gpio_sd_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/gpio_sd_struct.h rename to components/soc/esp32c3/register/soc/gpio_sd_struct.h diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/register/soc/gpio_struct.h similarity index 94% rename from components/soc/esp32c3/include/soc/gpio_struct.h rename to components/soc/esp32c3/register/soc/gpio_struct.h index 45f5e55412..1fbb0779b4 100644 --- a/components/soc/esp32c3/include/soc/gpio_struct.h +++ b/components/soc/esp32c3/register/soc/gpio_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_STRUCT_H_ #define _SOC_GPIO_STRUCT_H_ #include diff --git a/components/soc/esp32c3/include/soc/i2c_reg.h b/components/soc/esp32c3/register/soc/i2c_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/i2c_reg.h rename to components/soc/esp32c3/register/soc/i2c_reg.h index 6a45d00827..03ec35dad0 100644 --- a/components/soc/esp32c3/include/soc/i2c_reg.h +++ b/components/soc/esp32c3/register/soc/i2c_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_I2C_REG_H_ #define _SOC_I2C_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/register/soc/i2c_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2c_struct.h rename to components/soc/esp32c3/register/soc/i2c_struct.h index 1009fedd6e..eb32d5a9cf 100644 --- a/components/soc/esp32c3/include/soc/i2c_struct.h +++ b/components/soc/esp32c3/register/soc/i2c_struct.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct i2c_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2s_reg.h rename to components/soc/esp32c3/register/soc/i2s_reg.h index 2b3ed91f61..7412fe1a13 100644 --- a/components/soc/esp32c3/include/soc/i2s_reg.h +++ b/components/soc/esp32c3/register/soc/i2s_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ @@ -280,7 +280,7 @@ extern "C" { #define I2S_TX_LEFT_ALIGN_S 15 /* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ /*description: Set this bit to stop disable output BCK signal and WS signal - when tx FIFO is emtpy*/ + when tx FIFO is empty*/ #define I2S_TX_STOP_EN (BIT(13)) #define I2S_TX_STOP_EN_M (BIT(13)) #define I2S_TX_STOP_EN_V 0x1 diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2s_struct.h rename to components/soc/esp32c3/register/soc/i2s_struct.h index e0c10e91e9..29093ad2d9 100644 --- a/components/soc/esp32c3/include/soc/i2s_struct.h +++ b/components/soc/esp32c3/register/soc/i2s_struct.h @@ -95,7 +95,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ - uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/ uint32_t reserved14: 1; uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ diff --git a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/interrupt_core0_reg.h rename to components/soc/esp32c3/register/soc/interrupt_core0_reg.h index f606cdafca..f587f5c73c 100644 --- a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/io_mux_reg.h rename to components/soc/esp32c3/register/soc/io_mux_reg.h index f5abe8ee5e..a85a3434dd 100644 --- a/components/soc/esp32c3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c3/register/soc/io_mux_reg.h @@ -6,7 +6,7 @@ #ifndef _SOC_IO_MUX_REG_H_ #define _SOC_IO_MUX_REG_H_ -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32c3/include/soc/ledc_reg.h b/components/soc/esp32c3/register/soc/ledc_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/ledc_reg.h rename to components/soc/esp32c3/register/soc/ledc_reg.h index 0cc9334130..c956e9e7da 100644 --- a/components/soc/esp32c3/include/soc/ledc_reg.h +++ b/components/soc/esp32c3/register/soc/ledc_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_LEDC_REG_H_ #define _SOC_LEDC_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) /* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/ledc_struct.h rename to components/soc/esp32c3/register/soc/ledc_struct.h diff --git a/components/soc/esp32c3/include/soc/nrx_reg.h b/components/soc/esp32c3/register/soc/nrx_reg.h similarity index 67% rename from components/soc/esp32c3/include/soc/nrx_reg.h rename to components/soc/esp32c3/register/soc/nrx_reg.h index d80cb2a178..16e6e14849 100644 --- a/components/soc/esp32c3/include/soc/nrx_reg.h +++ b/components/soc/esp32c3/register/soc/nrx_reg.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32c3/include/soc/reg_base.h b/components/soc/esp32c3/register/soc/reg_base.h similarity index 97% rename from components/soc/esp32c3/include/soc/reg_base.h rename to components/soc/esp32c3/register/soc/reg_base.h index 4ec808f0ab..cf38bd9dbd 100644 --- a/components/soc/esp32c3/include/soc/reg_base.h +++ b/components/soc/esp32c3/register/soc/reg_base.h @@ -46,5 +46,5 @@ #define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 #define DR_REG_XTS_AES_BASE 0x600CC000 -/* For backward compatability with the older register names */ +/* For backward compatibility with the older register names */ #define DR_REG_AES_XTS_BASE DR_REG_XTS_AES_BASE diff --git a/components/soc/esp32c3/include/soc/rmt_reg.h b/components/soc/esp32c3/register/soc/rmt_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/rmt_reg.h rename to components/soc/esp32c3/register/soc/rmt_reg.h index 106fc78649..1ac39c2af3 100644 --- a/components/soc/esp32c3/include/soc/rmt_reg.h +++ b/components/soc/esp32c3/register/soc/rmt_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/rmt_struct.h rename to components/soc/esp32c3/register/soc/rmt_struct.h diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/rtc_cntl_reg.h rename to components/soc/esp32c3/register/soc/rtc_cntl_reg.h index 433ca196b3..e67f6ed93d 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h @@ -9,7 +9,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG @@ -567,7 +567,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 @@ -1712,7 +1712,7 @@ extern "C" { #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD*/ +/*description: disable SWD*/ #define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) #define RTC_CNTL_SWD_DISABLE_V 0x1 @@ -2138,7 +2138,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k*/ +/*description: cycles to wait to return normal xtal 32k*/ #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF @@ -2192,7 +2192,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 @@ -2248,7 +2248,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/rtc_cntl_struct.h rename to components/soc/esp32c3/register/soc/rtc_cntl_struct.h index 8b6bd3ad50..5c57701f69 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h @@ -195,7 +195,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal: 1; uint32_t reserved21: 11; }; @@ -498,7 +498,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ uint32_t swd_feed: 1; /*Sw feed swd*/ - uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_disable: 1; /*disable SWD*/ uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ }; uint32_t val; @@ -591,7 +591,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ union { struct { - uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return normal xtal 32k*/ uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ @@ -647,7 +647,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1ts: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal_w1ts: 1; uint32_t reserved21: 11; }; @@ -666,7 +666,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1tc: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal_w1tc: 1; uint32_t reserved21: 11; }; diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/rtc_i2c_reg.h rename to components/soc/esp32c3/register/soc/rtc_i2c_reg.h index 52bdefc0e5..eba7d42df6 100644 --- a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_I2C_REG_H_ #define _SOC_RTC_I2C_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) /* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ /*description: time period that scl = 0*/ diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/register/soc/rtc_i2c_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/rtc_i2c_struct.h rename to components/soc/esp32c3/register/soc/rtc_i2c_struct.h diff --git a/components/soc/esp32c3/include/soc/sensitive_reg.h b/components/soc/esp32c3/register/soc/sensitive_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/sensitive_reg.h rename to components/soc/esp32c3/register/soc/sensitive_reg.h index e1ce7d93ef..18fcf2e8db 100644 --- a/components/soc/esp32c3/include/soc/sensitive_reg.h +++ b/components/soc/esp32c3/register/soc/sensitive_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) /* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/register/soc/sensitive_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/sensitive_struct.h rename to components/soc/esp32c3/register/soc/sensitive_struct.h index ba860e45cd..d71d81fc4d 100644 --- a/components/soc/esp32c3/include/soc/sensitive_struct.h +++ b/components/soc/esp32c3/register/soc/sensitive_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_STRUCT_H_ #define _SOC_SENSITIVE_STRUCT_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct sensitive_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/spi_mem_reg.h b/components/soc/esp32c3/register/soc/spi_mem_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/spi_mem_reg.h rename to components/soc/esp32c3/register/soc/spi_mem_reg.h index fcf3e29248..22d6b26377 100644 --- a/components/soc/esp32c3/include/soc/spi_mem_reg.h +++ b/components/soc/esp32c3/register/soc/spi_mem_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ /*description: Read flash enable. Read flash operation will be triggered when @@ -270,7 +262,7 @@ extern "C" { #define SPI_MEM_CS_HOLD_DLY_RES_S 2 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ #define SPI_MEM_CLK_MODE 0x00000003 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) #define SPI_MEM_CLK_MODE_V 0x3 diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/register/soc/spi_mem_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_mem_struct.h rename to components/soc/esp32c3/register/soc/spi_mem_struct.h index d816a9a290..95a0aae1ec 100644 --- a/components/soc/esp32c3/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c3/register/soc/spi_mem_struct.h @@ -63,7 +63,7 @@ typedef volatile struct spi_mem_dev_s { } ctrl; union { struct { - uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ uint32_t cs_hold_dly_res: 10; /*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ uint32_t reserved2: 18; /*reserved*/ uint32_t rxfifo_rst: 1; /*SPI0 RX FIFO reset signal.*/ diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_reg.h rename to components/soc/esp32c3/register/soc/spi_reg.h index 361f58ba5c..e8e9fec283 100644 --- a/components/soc/esp32c3/include/soc/spi_reg.h +++ b/components/soc/esp32c3/register/soc/spi_reg.h @@ -6,7 +6,7 @@ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { @@ -138,7 +138,7 @@ be configured in CONF state..*/ #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst em clock. Can be configured in CONF state..*/ #define SPI_CLK_EQU_SYSCLK (BIT(31)) #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) @@ -175,15 +175,15 @@ e 0. Can be configured in CONF state..*/ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the command phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_COMMAND (BIT(31)) #define SPI_USR_COMMAND_M (BIT(31)) #define SPI_USR_COMMAND_V 0x1 #define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the address phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_ADDR (BIT(30)) #define SPI_USR_ADDR_M (BIT(30)) #define SPI_USR_ADDR_V 0x1 @@ -357,7 +357,7 @@ n be configured in CONF state..*/ #define SPI_USR_COMMAND_BITLEN_S 28 /* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ /*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m -aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error r is valid in GP-SPI master FD/HD-mode..*/ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) @@ -927,7 +927,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ #define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 #define SPI_SLV_CMD_ERR_INT_RAW_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others..*/ #define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) @@ -1370,7 +1370,7 @@ dge 0: output data at tsck posedge .*/ /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +ve 3: SPI clock is always on. Can be configured in CONF state..*/ #define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_struct.h rename to components/soc/esp32c3/register/soc/spi_struct.h index 8cb6a7ee97..88d7476caf 100644 --- a/components/soc/esp32c3/include/soc/spi_struct.h +++ b/components/soc/esp32c3/register/soc/spi_struct.h @@ -55,7 +55,7 @@ typedef volatile struct spi_dev_s { uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ }; uint32_t val; } clock; @@ -317,7 +317,7 @@ typedef volatile struct spi_dev_s { uint32_t reserved_dc; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ uint32_t reserved4 : 4; /*reserved*/ diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/register/soc/syscon_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/syscon_reg.h rename to components/soc/esp32c3/register/soc/syscon_reg.h index e61f84eda3..1aff9a5748 100644 --- a/components/soc/esp32c3/include/soc/syscon_reg.h +++ b/components/soc/esp32c3/register/soc/syscon_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ @@ -206,7 +206,7 @@ extern "C" { #define SYSTEM_MACPWR_RST BIT(8) #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ -#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ +#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Registers */ #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/register/soc/syscon_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/syscon_struct.h rename to components/soc/esp32c3/register/soc/syscon_struct.h diff --git a/components/soc/esp32c3/include/soc/system_reg.h b/components/soc/esp32c3/register/soc/system_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/system_reg.h rename to components/soc/esp32c3/register/soc/system_reg.h index 7bcb904214..7302066bbc 100644 --- a/components/soc/esp32c3/include/soc/system_reg.h +++ b/components/soc/esp32c3/register/soc/system_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/register/soc/system_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/system_struct.h rename to components/soc/esp32c3/register/soc/system_struct.h index f4cb995aa2..bc2c1b3a24 100644 --- a/components/soc/esp32c3/include/soc/system_struct.h +++ b/components/soc/esp32c3/register/soc/system_struct.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct system_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/register/soc/systimer_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/systimer_reg.h rename to components/soc/esp32c3/register/soc/systimer_reg.h index 4e9f64fffa..55316915df 100644 --- a/components/soc/esp32c3/include/soc/systimer_reg.h +++ b/components/soc/esp32c3/register/soc/systimer_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/register/soc/systimer_struct.h similarity index 94% rename from components/soc/esp32c3/include/soc/systimer_struct.h rename to components/soc/esp32c3/register/soc/systimer_struct.h index 47e7b7d30c..cf10afab1c 100644 --- a/components/soc/esp32c3/include/soc/systimer_struct.h +++ b/components/soc/esp32c3/register/soc/systimer_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c3/include/soc/timer_group_reg.h rename to components/soc/esp32c3/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c3/include/soc/timer_group_struct.h b/components/soc/esp32c3/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/timer_group_struct.h rename to components/soc/esp32c3/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c3/include/soc/twai_struct.h b/components/soc/esp32c3/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/twai_struct.h rename to components/soc/esp32c3/register/soc/twai_struct.h diff --git a/components/soc/esp32c3/include/soc/uart_reg.h b/components/soc/esp32c3/register/soc/uart_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/uart_reg.h rename to components/soc/esp32c3/register/soc/uart_reg.h index a0d6c72735..c26bab9938 100644 --- a/components/soc/esp32c3/include/soc/uart_reg.h +++ b/components/soc/esp32c3/register/soc/uart_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_UART_REG_H_ #define _SOC_UART_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ /*description: UART $n accesses FIFO via this register.*/ @@ -99,7 +91,7 @@ extern "C" { #define UART_SW_XOFF_INT_RAW_V 0x1 #define UART_SW_XOFF_INT_RAW_S 10 /* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver recevies +/*description: This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/ #define UART_SW_XON_INT_RAW (BIT(9)) #define UART_SW_XON_INT_RAW_M (BIT(9)) @@ -212,7 +204,7 @@ extern "C" { #define UART_TX_DONE_INT_ST_V 0x1 #define UART_TX_DONE_INT_ST_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena +/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) #define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) @@ -751,7 +743,7 @@ extern "C" { #define UART_IRDA_DPLX_V 0x1 #define UART_IRDA_DPLX_S 9 /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send NULL when the process +/*description: Set this bit to enable transmitter to send NULL when the process of sending data is done.*/ #define UART_TXD_BRK (BIT(8)) #define UART_TXD_BRK_M (BIT(8)) @@ -798,7 +790,7 @@ extern "C" { #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function.*/ +/*description: This is the enable bit for uart receiver's timeout function.*/ #define UART_RX_TOUT_EN (BIT(21)) #define UART_RX_TOUT_EN_M (BIT(21)) #define UART_RX_TOUT_EN_V 0x1 @@ -847,7 +839,7 @@ extern "C" { #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the value of the maxinum duration time +/*description: This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/ #define UART_HIGHPULSE_MIN_CNT 0x00000FFF #define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/register/soc/uart_struct.h similarity index 98% rename from components/soc/esp32c3/include/soc/uart_struct.h rename to components/soc/esp32c3/register/soc/uart_struct.h index b14191f3ff..8c76d475fb 100644 --- a/components/soc/esp32c3/include/soc/uart_struct.h +++ b/components/soc/esp32c3/register/soc/uart_struct.h @@ -28,7 +28,7 @@ typedef volatile struct uart_dev_s { uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/ uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/ @@ -58,7 +58,7 @@ typedef volatile struct uart_dev_s { uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ @@ -161,7 +161,7 @@ typedef volatile struct uart_dev_s { uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/ uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ - uint32_t txd_brk: 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ + uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send NULL when the process of sending data is done.*/ uint32_t irda_dplx: 1; /*Set this bit to enable IrDA loopback mode.*/ uint32_t irda_tx_en: 1; /*This is the start enable bit for IrDA transmitter.*/ uint32_t irda_wctl: 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ @@ -193,7 +193,7 @@ typedef volatile struct uart_dev_s { uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/ uint32_t rx_tout_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ uint32_t rx_flow_en: 1; /*This is the flow enable bit for UART receiver.*/ - uint32_t rx_tout_en: 1; /*This is the enble bit for uart receiver's timeout function.*/ + uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ uint32_t reserved22: 10; }; uint32_t val; @@ -207,7 +207,7 @@ typedef volatile struct uart_dev_s { } lowpulse; union { struct { - uint32_t min_cnt: 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ + uint32_t min_cnt: 12; /*This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/ uint32_t reserved12: 20; /*Reserved*/ }; uint32_t val; diff --git a/components/soc/esp32c3/include/soc/uhci_reg.h b/components/soc/esp32c3/register/soc/uhci_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/uhci_reg.h rename to components/soc/esp32c3/register/soc/uhci_reg.h index 3a41dedb80..f387de7963 100644 --- a/components/soc/esp32c3/include/soc/uhci_reg.h +++ b/components/soc/esp32c3/register/soc/uhci_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_UHCI_REG_H_ #define _SOC_UHCI_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: If this bit is set to 1 UHCI will end payload receive process diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/uhci_struct.h rename to components/soc/esp32c3/register/soc/uhci_struct.h diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h index f4cf387fe6..6d908baec1 100644 --- a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h @@ -1,9 +1,9 @@ - -/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. - * SPDX-License-Identifier: Apache-2.0 +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #include @@ -155,7 +155,7 @@ extern "C" { #define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001 #define USB_SERIAL_JTAG_TEST_ENABLE_S 0 /* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad oen in + * USB pad one in * test */ #define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h similarity index 96% rename from components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h index c1cfced04b..98b15060a4 100644 --- a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h @@ -1,16 +1,8 @@ -// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_ #define _SOC_USB_SERIAL_JTAG_STRUCT_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct usb_serial_jtag_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/xts_aes_reg.h b/components/soc/esp32c3/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/xts_aes_reg.h rename to components/soc/esp32c3/register/soc/xts_aes_reg.h index 9845d0b058..6a6e64539c 100644 --- a/components/soc/esp32c3/include/soc/xts_aes_reg.h +++ b/components/soc/esp32c3/register/soc/xts_aes_reg.h @@ -119,7 +119,7 @@ extern "C" { #define XTS_AES_DATE_V 0x3FFFFFFFU #define XTS_AES_DATE_S 0 -/* For backward compatability with the older register names */ +/* For backward compatibility with the older register names */ #define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM #define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG #define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index f605b7cd05..51fb864c98 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -524,32 +524,6 @@ components/soc/esp32/include/soc/touch_sensor_channel.h components/soc/esp32/include/soc/uart_pins.h components/soc/esp32/include/soc/wdev_reg.h components/soc/esp32/ledc_periph.c -components/soc/esp32c3/include/soc/apb_saradc_reg.h -components/soc/esp32c3/include/soc/assist_debug_reg.h -components/soc/esp32c3/include/soc/bb_reg.h -components/soc/esp32c3/include/soc/boot_mode.h -components/soc/esp32c3/include/soc/extmem_reg.h -components/soc/esp32c3/include/soc/fe_reg.h -components/soc/esp32c3/include/soc/gpio_reg.h -components/soc/esp32c3/include/soc/gpio_struct.h -components/soc/esp32c3/include/soc/i2c_reg.h -components/soc/esp32c3/include/soc/interrupt_core0_reg.h -components/soc/esp32c3/include/soc/ledc_reg.h -components/soc/esp32c3/include/soc/nrx_reg.h -components/soc/esp32c3/include/soc/reset_reasons.h -components/soc/esp32c3/include/soc/rtc_i2c_reg.h -components/soc/esp32c3/include/soc/sensitive_reg.h -components/soc/esp32c3/include/soc/sensitive_struct.h -components/soc/esp32c3/include/soc/soc_pins.h -components/soc/esp32c3/include/soc/spi_mem_reg.h -components/soc/esp32c3/include/soc/systimer_reg.h -components/soc/esp32c3/include/soc/systimer_struct.h -components/soc/esp32c3/include/soc/uart_pins.h -components/soc/esp32c3/include/soc/uart_reg.h -components/soc/esp32c3/include/soc/uhci_reg.h -components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h -components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h -components/soc/esp32c3/include/soc/wdev_reg.h components/soc/esp32c3/interrupts.c components/soc/esp32c3/ledc_periph.c components/soc/esp32s2/adc_periph.c