Merge branch 'feature/support_i2s_on_esp32c6' into 'master'

i2s: support i2s on esp32c6

See merge request espressif/esp-idf!19989

components/driver/deprecated/i2s_legacy.c

@@ -47,6 +47,7 @@
 #include "esp_efuse.h"
 #include "esp_rom_gpio.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/esp_clk.h"
 
 static const char *TAG = "i2s(legacy)";
 
@@ -624,6 +625,7 @@ err:
 /*-------------------------------------------------------------
                    I2S clock operation
   -------------------------------------------------------------*/
+  // [clk_tree] TODO: replace the following switch table by clk_tree API
 static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
 {
 #if SOC_I2S_SUPPORTS_APLL
@@ -650,12 +652,12 @@ static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint3
         /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
         return real_freq;
     }
-    return I2S_LL_BASE_CLK;
+    return esp_clk_apb_freq() * 2;
 #else
     if (use_apll) {
         ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source");
     }
-    return I2S_LL_BASE_CLK;
+    return esp_clk_apb_freq() * 2;
 #endif
 }
 

components/driver/i2s/i2s_common.c

@@ -35,6 +35,7 @@
 
 #include "esp_private/i2s_platform.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/esp_clk.h"
 
 #include "driver/gpio.h"
 #include "driver/i2s_common.h"
@@ -444,7 +445,7 @@ err:
 }
 
 #if SOC_I2S_SUPPORTS_APLL
-uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz)
+static uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz)
 {
     /* Calculate the expected APLL  */
     int mclk_div = (int)((SOC_APLL_MIN_HZ / mclk_freq_hz) + 1);
@@ -473,6 +474,25 @@ uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz)
 }
 #endif
 
+// [clk_tree] TODO: replace the following switch table by clk_tree API
+uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
+{
+    switch (clk_src)
+    {
+#if SOC_I2S_SUPPORTS_APLL
+    case I2S_CLK_SRC_APLL:
+        return i2s_set_get_apll_freq(mclk_freq_hz);
+#endif
+#if SOC_I2S_SUPPORTS_XTAL
+    case I2S_CLK_SRC_XTAL:
+        (void)mclk_freq_hz;
+        return esp_clk_xtal_freq();
+#endif
+    default: // I2S_CLK_SRC_PLL_160M
+        return esp_clk_apb_freq() * 2;
+    }
+}
+
 #if SOC_GDMA_SUPPORTED
 static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {

components/driver/i2s/i2s_pdm.c

@@ -38,11 +38,7 @@ static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_
     clk_info->bclk = rate * I2S_LL_PDM_BCK_FACTOR * pdm_tx_clk->up_sample_fp / pdm_tx_clk->up_sample_fs;
     clk_info->bclk_div = 8;
     clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
-#if SOC_I2S_SUPPORTS_APLL
+    clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
-    clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK;
-#else
-    clk_info->sclk = I2S_LL_BASE_CLK;
-#endif
     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
 
     /* Check if the configuration is correct */
@@ -326,11 +322,7 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_
     clk_info->bclk = rate * I2S_LL_PDM_BCK_FACTOR * (pdm_rx_clk->dn_sample_mode == I2S_PDM_DSR_16S ? 2 : 1);
     clk_info->bclk_div = 8;
     clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
-#if SOC_I2S_SUPPORTS_APLL
+    clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
-    clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK;
-#else
-    clk_info->sclk = I2S_LL_BASE_CLK;
-#endif
     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
 
     /* Check if the configuration is correct */

components/driver/i2s/i2s_private.h

@@ -161,16 +161,15 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu
  */
 uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uint32_t dma_frame_num);
 
-#if SOC_I2S_SUPPORTS_APLL
 /**
- * @brief Set mclk frequency and get the actuall APLL frequency
+ * @brief Get the frequency of the source clock
  *
+ * @param clk_src       clock source
  * @param mclk_freq_hz  Expected mclk frequenct in Hz
  * @return
- *  - Actuall APLL frequency
+ *      - Actual source clock frequency
  */
-uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz);
+uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz);
-#endif
 
 /**
  * @brief Check gpio validity and attach to corresponding signal

components/driver/i2s/i2s_std.c

@@ -45,11 +45,7 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
         clk_info->bclk = rate * handle->total_slot * slot_bits;
         clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
     }
-#if SOC_I2S_SUPPORTS_APLL
+    clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
-    clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK;
-#else
-    clk_info->sclk = I2S_LL_BASE_CLK;
-#endif
     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
 
     /* Check if the configuration is correct */

components/driver/i2s/i2s_tdm.c

@@ -54,12 +54,7 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm
         clk_info->bclk = rate * handle->total_slot * slot_bits;
         clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
     }
-
+    clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
-#if SOC_I2S_SUPPORTS_APLL
-    clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_APLL ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK;
-#else
-    clk_info->sclk = I2S_LL_BASE_CLK;
-#endif
     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
 
     /* Check if the configuration is correct */

components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c

@@ -751,7 +751,14 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c
                             32000, 44100, 48000, 64000, 88200, 96000,
                             128000, 144000, 196000};
     int real_pulse = 0;
-    for (int i = 0; i < 15; i++) {
+    int case_cnt = 15;
+#if SOC_I2S_HW_VERSION_2
+    // Can't support a very high sample rate while using XTAL as clock source
+    if (clk_cfg->clk_src == I2S_CLK_SRC_XTAL) {
+        case_cnt = 9;
+    }
+#endif
+    for (int i = 0; i < case_cnt; i++) {
         int expt_pulse = (int)((float)test_freq[i] * (TEST_I2S_PERIOD_MS / 1000.0));
         clk_cfg->sample_rate_hz = test_freq[i];
         TEST_ESP_OK(i2s_channel_reconfig_std_clock(rx_chan, clk_cfg));
@@ -789,6 +796,10 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
     TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
 
     i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
+#if SOC_I2S_HW_VERSION_2
+    std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_XTAL;
+    i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
+#endif
     TEST_ESP_OK(i2s_del_channel(rx_handle));
 }
 

components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h

@@ -44,7 +44,7 @@ extern "C" {
 #define SLAVE_WS_IO 15
 #define DATA_IN_IO 19
 #define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
 #define MASTER_MCK_IO 0
 #define MASTER_BCK_IO 4
 #define MASTER_WS_IO 5

components/hal/esp32/include/hal/i2s_ll.h

@@ -29,7 +29,6 @@ extern "C" {
 
 #define I2S_LL_AD_BCK_FACTOR           (2)
 #define I2S_LL_PDM_BCK_FACTOR          (64)
-#define I2S_LL_BASE_CLK                (2 * APB_CLK_FREQ)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (6)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
@@ -287,7 +286,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */
@@ -363,7 +362,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */

components/hal/esp32c3/include/hal/i2s_ll.h

@@ -14,6 +14,7 @@
 #pragma once
 #include <stdbool.h>
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/i2s_periph.h"
 #include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
@@ -23,11 +24,10 @@
 extern "C" {
 #endif
 
-#define I2S_LL_GET_HW(num)             (&I2S0)
+#define I2S_LL_GET_HW(num)             (((num) == 0)? (&I2S0) : NULL)
 
 #define I2S_LL_TDM_CH_MASK             (0xffff)
 #define I2S_LL_PDM_BCK_FACTOR          (64)
-#define I2S_LL_BASE_CLK                (2*APB_CLK_FREQ)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
@@ -193,18 +193,40 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
  */
 static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->tx_clkm_conf.tx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->tx_clkm_conf.tx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        hw->tx_clkm_conf.tx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
 
 /**
  * @brief Set RX source clock
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param src I2S source clock,  ESP32-C3 only support `I2S_CLK_SRC_PLL_160M`
+ * @param src I2S source clock
  */
 static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->rx_clkm_conf.rx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->rx_clkm_conf.rx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        hw->rx_clkm_conf.rx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
 
 /**
@@ -256,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */

components/hal/esp32h2/include/hal/i2s_ll.h

@@ -15,6 +15,7 @@
 #pragma once
 #include <stdbool.h>
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/i2s_periph.h"
 #include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
@@ -24,12 +25,10 @@
 extern "C" {
 #endif
 
-#define I2S_LL_GET_HW(num)             (&I2S0)
+#define I2S_LL_GET_HW(num)             (((num) == 0)? (&I2S0) : NULL)
 
 #define I2S_LL_TDM_CH_MASK             (0xffff)
 #define I2S_LL_PDM_BCK_FACTOR          (64)
-// [clk_tree] TODO: replace the following switch table by clk_tree API
-#define I2S_LL_BASE_CLK                (96*1000000)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
@@ -195,18 +194,40 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
  */
 static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->tx_clkm_conf.tx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->tx_clkm_conf.tx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_96M:
+        hw->tx_clkm_conf.tx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
 
 /**
  * @brief Set RX source clock
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param src I2S source clock, ESP32-H2 only support `I2S_CLK_SRC_PLL_96M` for now
+ * @param src I2S source clock
  */
 static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->rx_clkm_conf.rx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->rx_clkm_conf.rx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_96M:
+        hw->rx_clkm_conf.rx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
 
 /**
@@ -258,7 +279,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */

components/hal/esp32s2/include/hal/i2s_ll.h

@@ -28,8 +28,6 @@ extern "C" {
 // Get I2S hardware instance with giving i2s num
 #define I2S_LL_GET_HW(num)             (((num) == 0) ? (&I2S0) : NULL)
 
-#define I2S_LL_BASE_CLK                (2 * APB_CLK_FREQ)
-
 #define I2S_LL_BCK_MAX_PRESCALE  (64)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (6)
@@ -280,7 +278,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32S2 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */
@@ -356,7 +354,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32S2 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */

components/hal/esp32s3/include/hal/i2s_ll.h

@@ -14,6 +14,7 @@
 #pragma once
 #include <stdbool.h>
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/i2s_periph.h"
 #include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
@@ -28,7 +29,6 @@ extern "C" {
 
 #define I2S_LL_TDM_CH_MASK (0xffff)
 #define I2S_LL_PDM_BCK_FACTOR          (64)
-#define I2S_LL_BASE_CLK                (2*APB_CLK_FREQ)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
@@ -190,26 +190,45 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
  * @brief Set TX source clock
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param src I2S source clock,  ESP32-S3 only support `I2S_CLK_SRC_PLL_160M`
+ * @param src I2S source clock.
- *            TX and RX share the same clock setting
  */
 static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->tx_clkm_conf.tx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->tx_clkm_conf.tx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        hw->tx_clkm_conf.tx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
 
 /**
  * @brief Set RX source clock
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param src I2S source clock,  ESP32-S3 only support `I2S_CLK_SRC_PLL_160M`
+ * @param src I2S source clock
- *            TX and RX share the same clock setting
  */
 static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
-    hw->rx_clkm_conf.rx_clk_sel = 2;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        hw->rx_clkm_conf.rx_clk_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        hw->rx_clkm_conf.rx_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
 }
-
 /**
  * @brief Set I2S tx bck div num
  *
@@ -259,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
+ * @param sclk system clock
  * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
  */

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -363,6 +363,10 @@ config SOC_I2S_HW_VERSION_2
     bool
     default y
 
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32c3/include/soc/clk_tree_defs.h

@@ -206,7 +206,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief I2S clock source enum
@@ -214,6 +214,7 @@ typedef enum {
 typedef enum {
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
     I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
+    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
 } soc_periph_i2s_clk_src_t;
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

components/soc/esp32c3/include/soc/i2s_struct.h

@@ -140,7 +140,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t rx_clkm_div_num: 8;             /*Integral I2S clock divider value*/
             uint32_t reserved8:      18;             /*Reserved*/
             uint32_t rx_clk_active:   1;             /*I2S Rx module clock enable signal.*/
-            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t mclk_sel:        1;             /*0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
             uint32_t reserved30:      2;             /*Reserved*/
         };
@@ -151,7 +151,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t tx_clkm_div_num: 8;             /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
             uint32_t reserved8:      18;             /*Reserved*/
             uint32_t tx_clk_active:   1;             /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t clk_en:          1;             /*Set this bit to enable clk gate*/
             uint32_t reserved30:      2;             /*Reserved*/
         };

components/soc/esp32c3/include/soc/soc_caps.h

@@ -179,6 +179,7 @@
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_XTAL       (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32c6/CMakeLists.txt

@@ -20,7 +20,6 @@ list(REMOVE_ITEM srcs
         "adc_periph.c"                  # TODO: IDF-5310
         "dedic_gpio_periph.c"           # TODO: IDF-5331
         "ledc_periph.c"                 # TODO: IDF-5328
-        "i2s_periph.c"                  # TODO: IDF-5314
         "i2c_periph.c"                  # TODO: IDF-5326
         "temperature_sensor_periph.c"   # TODO: IDF-5322
         )

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
     bool
     default y
 
+config SOC_I2S_SUPPORTED
+    bool
+    default y
+
 config SOC_SYSTIMER_SUPPORTED
     bool
     default y
@@ -287,6 +291,10 @@ config SOC_I2S_HW_VERSION_2
     bool
     default y
 
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -215,14 +215,23 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
+#if CONFIG_IDF_ENV_FPGA
+#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
+#else
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
+#endif
 
 /**
  * @brief I2S clock source enum
  */
 typedef enum {
+#if CONFIG_IDF_ENV_FPGA
+    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
+#else
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
+#endif
     I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
+    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
 } soc_periph_i2s_clk_src_t;
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

components/soc/esp32c6/include/soc/i2s_struct.h

@@ -255,7 +255,7 @@ typedef union {
          */
         uint32_t rx_clk_active:1;
         /** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
-         *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+         *  Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
          */
         uint32_t rx_clk_sel:2;
         /** mclk_sel : R/W; bitpos: [29]; default: 0;
@@ -448,7 +448,7 @@ typedef union {
     uint32_t val;
 } i2s_rx_tdm_ctrl_reg_t;
 
-/** Type of rxeof_num register
+/** Type of rx_eof_num register
  *  I2S RX data number control register.
  */
 typedef union {
@@ -461,7 +461,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} i2s_rxeof_num_reg_t;
+} i2s_rx_eof_num_reg_t;
 
 
 /** Group: TX Control and configuration registers */
@@ -627,7 +627,7 @@ typedef union {
          */
         uint32_t tx_clk_active:1;
         /** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
-         *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+         *  Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
          *  I2S_MCLK_in.
          */
         uint32_t tx_clk_sel:2;
@@ -914,7 +914,7 @@ typedef union {
     uint32_t val;
 } i2s_lc_hung_conf_reg_t;
 
-/** Type of conf_sigle_data register
+/** Type of conf_single_data register
  *  I2S signal data register
  */
 typedef union {
@@ -925,7 +925,7 @@ typedef union {
         uint32_t single_data:32;
     };
     uint32_t val;
-} i2s_conf_sigle_data_reg_t;
+} i2s_conf_single_data_reg_t;
 
 
 /** Group: TX status registers */
@@ -1005,8 +1005,8 @@ typedef struct i2s_dev_t {
     volatile i2s_rx_timing_reg_t rx_timing;
     volatile i2s_tx_timing_reg_t tx_timing;
     volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rxeof_num_reg_t rxeof_num;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
-    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
     volatile i2s_state_reg_t state;
     volatile i2s_etm_conf_reg_t etm_conf;
     uint32_t reserved_074[3];

components/soc/esp32c6/include/soc/pcr_struct.h

@@ -607,7 +607,7 @@ typedef union {
          */
         uint32_t i2s_tx_clkm_div_num:8;
         /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+         *  Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
          *  I2S_MCLK_in.
          */
         uint32_t i2s_tx_clkm_sel:2;
@@ -661,7 +661,7 @@ typedef union {
          */
         uint32_t i2s_rx_clkm_div_num:8;
         /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+         *  Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
          */
         uint32_t i2s_rx_clkm_sel:2;
         /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;

components/soc/esp32c6/include/soc/soc_caps.h

@@ -40,7 +40,7 @@
 #define SOC_EFUSE_KEY_PURPOSE_FIELD     1
 #define SOC_RTC_FAST_MEM_SUPPORTED      1
 #define SOC_RTC_MEM_SUPPORTED           1
-// #define SOC_I2S_SUPPORTED               1 // TODO: IDF-5314
+#define SOC_I2S_SUPPORTED               1
 // #define SOC_RMT_SUPPORTED               1 // TODO: IDF-5320
 // #define SOC_SDM_SUPPORTED               1 // TODO: IDF-5318
 // #define SOC_LEDC_SUPPORTED              1 // TODO: IDF-5328
@@ -181,10 +181,10 @@
 #define SOC_I2C_SUPPORT_XTAL        (1)
 #define SOC_I2C_SUPPORT_RTC         (1)
 
-// TODO: IDF-5314 (Copy from esp32c3, need check)
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_XTAL       (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -339,6 +339,10 @@ config SOC_I2S_HW_VERSION_2
     bool
     default y
 
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -211,7 +211,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL}
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief I2S clock source enum
@@ -219,6 +219,7 @@ typedef enum {
 typedef enum {
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL,        /*!< Select SOC_MOD_CLK_PLL as the default source clock  */
     I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL,        /*!< Select PLL as the source clock */
+    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,          /*!< Select XTAL as the source clock */
 } soc_periph_i2s_clk_src_t;
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

components/soc/esp32h2/include/soc/i2s_struct.h

@@ -141,7 +141,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t rx_clkm_div_num: 8;             /*Integral I2S clock divider value*/
             uint32_t reserved8:      18;             /*Reserved*/
             uint32_t rx_clk_active:   1;             /*I2S Rx module clock enable signal.*/
-            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t mclk_sel:        1;             /*0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
             uint32_t reserved30:      2;             /*Reserved*/
         };
@@ -152,7 +152,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t tx_clkm_div_num: 8;             /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
             uint32_t reserved8:      18;             /*Reserved*/
             uint32_t tx_clk_active:   1;             /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t clk_en:          1;             /*Set this bit to enable clk gate*/
             uint32_t reserved30:      2;             /*Reserved*/
         };

components/soc/esp32h2/include/soc/soc_caps.h

@@ -184,6 +184,7 @@
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_XTAL       (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -431,6 +431,10 @@ config SOC_I2S_HW_VERSION_2
     bool
     default y
 
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -252,7 +252,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief I2S clock source enum
@@ -260,6 +260,7 @@ typedef enum {
 typedef enum {
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                    /*!< Select PLL_F160M as the default source clock  */
     I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,                   /*!< Select PLL_F160M as the source clock */
+    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                            /*!< Select XTAL as the source clock */
 } soc_periph_i2s_clk_src_t;
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

components/soc/esp32s3/include/soc/i2s_struct.h

@@ -142,7 +142,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t rx_clkm_div_num               :    8;  /*Integral I2S clock divider value*/
             uint32_t reserved8                     :    18;  /* Reserved*/
             uint32_t rx_clk_active                 :    1;  /*I2S Rx module clock enable signal.*/
-            uint32_t rx_clk_sel                    :    2;  /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t rx_clk_sel                    :    2;  /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t mclk_sel                      :    1;  /* 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT. */
             uint32_t reserved30                    :    2;  /* Reserved*/
         };
@@ -153,7 +153,7 @@ typedef volatile struct i2s_dev_s {
             uint32_t tx_clkm_div_num               :    8;  /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
             uint32_t reserved8                     :    18;  /* Reserved*/
             uint32_t tx_clk_active                 :    1;  /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel                    :    2;  /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t tx_clk_sel                    :    2;  /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
             uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
             uint32_t reserved30                    :    2;  /* Reserved*/
         };

components/soc/esp32s3/include/soc/soc_caps.h

@@ -182,6 +182,7 @@
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (2)
 #define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_XTAL       (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c

@@ -30,7 +30,7 @@
 #define EXAMPLE_SD_SPI_MOSI_IO     (17)
 #define EXAMPLE_SD_SPI_MISO_IO     (16)
 #define EXAMPLE_SD_SPI_CS_IO       (15)
-#elif CONFIG_IDF_TARGET_ESP32C3
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
 #define EXAMPLE_I2C_NUM            (0)
 #define EXAMPLE_I2C_SDA_IO         (3)
 #define EXAMPLE_I2C_SCL_IO         (2)