From 9ef152c2201e6d22605e276e5a83c9673a5dcbca Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 27 Feb 2025 20:17:09 +0800 Subject: [PATCH 1/2] feat(regi2c): add regi2c support for esp32h21 --- .../src/esp32c5/bootloader_esp32c5.c | 1 - .../src/esp32c61/bootloader_esp32c61.c | 1 - .../src/esp32h21/bootloader_esp32h21.c | 4 +- .../esp_rom/patches/esp_rom_regi2c_esp32h21.c | 134 ++---- .../hal/esp32/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32c2/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32c3/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32c5/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32c6/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32c61/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32h2/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32h21/include/hal/regi2c_ctrl_ll.h | 43 +- .../hal/esp32h4/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32p4/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32s2/include/hal/regi2c_ctrl_ll.h | 2 +- .../hal/esp32s3/include/hal/regi2c_ctrl_ll.h | 2 +- .../esp32h21/include/soc/Kconfig.soc_caps.in | 8 + .../soc/esp32h21/include/soc/regi2c_defs.h | 2 +- .../soc/esp32h21/include/soc/soc_caps.h | 4 +- .../esp32h21/register/soc/i2c_ana_mst_reg.h | 446 ++++++++++-------- .../soc/esp32h21/register/soc/reg_base.h | 2 +- 21 files changed, 356 insertions(+), 311 deletions(-) diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index ecbc0b037d..65478e671e 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader - regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this? regi2c_ctrl_ll_master_configure_clock(); } diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index adda192985..d797386ba5 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader - regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this? regi2c_ctrl_ll_master_configure_clock(); } diff --git a/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c b/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c index 65e49e1d90..096dcb1903 100644 --- a/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c +++ b/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c @@ -89,8 +89,8 @@ static inline void bootloader_hardware_init(void) CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL); - //TODO: [ESP32H21] IDF-11550, regi2c atomic clock - regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader + _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader + regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-11548 Remove this? regi2c_ctrl_ll_master_configure_clock(); } diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c b/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c index 3186c74d7b..dc64ed1e16 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,73 +8,16 @@ #include "soc/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" -/** - * BB - 0x67 - BIT0 - * TXRF - 0x6B - BIT1 - * SDM - 0x63 - BIT2 - * PLL - 0x62 - BIT3 - * BIAS - 0x6A - BIT4 - * BBPLL - 0x66 - BIT5 - * ULP - 0x61 - BIT6 - * SAR - 0x69 - BIT7 - * PMU - 0x6d - BIT8 -*/ - -#define REGI2C_BIAS_MST_SEL (BIT(8)) -#define REGI2C_BBPLL_MST_SEL (BIT(9)) -#define REGI2C_ULP_CAL_MST_SEL (BIT(10)) -#define REGI2C_SAR_I2C_MST_SEL (BIT(11)) -#define REGI2C_DIG_REG_MST_SEL (BIT(12)) - -#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M) -#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M) -#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M) -#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M) -#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M) - -#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG - -#define REGI2C_RTC_BUSY (BIT(25)) -#define REGI2C_RTC_BUSY_M (BIT(25)) -#define REGI2C_RTC_BUSY_V 0x1 -#define REGI2C_RTC_BUSY_S 25 - -#define REGI2C_RTC_WR_CNTL (BIT(24)) -#define REGI2C_RTC_WR_CNTL_M (BIT(24)) -#define REGI2C_RTC_WR_CNTL_V 0x1 -#define REGI2C_RTC_WR_CNTL_S 24 - -#define REGI2C_RTC_DATA 0x000000FF -#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) -#define REGI2C_RTC_DATA_V 0xFF -#define REGI2C_RTC_DATA_S 16 - -#define REGI2C_RTC_ADDR 0x000000FF -#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) -#define REGI2C_RTC_ADDR_V 0xFF -#define REGI2C_RTC_ADDR_S 8 - -#define REGI2C_RTC_SLAVE_ID 0x000000FF -#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) -#define REGI2C_RTC_SLAVE_ID_V 0xFF -#define REGI2C_RTC_SLAVE_ID_S 0 - /* SLAVE */ - -#define REGI2C_BBPLL (0x66) -#define REGI2C_BBPLL_HOSTID 0 - -#define REGI2C_BIAS (0x6a) -#define REGI2C_BIAS_HOSTID 0 - -#define REGI2C_PMU (0x6d) -#define REGI2C_PMU_HOSTID 0 - -#define REGI2C_ULP_CAL (0x61) -#define REGI2C_ULP_CAL_HOSTID 0 - -#define REGI2C_SAR_I2C (0x69) -#define REGI2C_SAR_I2C_HOSTID 0 +#define REGI2C_BBPLL 0x66 // regi2c_bbpll.h +#define REGI2C_BBTOP 0x67 +#define REGI2C_DCDC 0x6D // regi2c_pmu.h +#define REGI2C_PERIF 0x69 // regi2c_saradc.h +#define REGI2C_RFPLL 0x62 +#define REGI2C_SDM 0x63 +#define REGI2C_TXTOP 0x6B +#define REGI2C_ULP 0x61 // regi2c_lp_bias.h +#define REGI2C_BIAS 0x6A // regi2c_bias.h /* SLAVE END */ @@ -86,33 +29,44 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - regi2c_ctrl_ll_master_enable_clock(true); + assert(regi2c_ctrl_ll_master_is_clock_enabled()); /* Before config I2C register, enable corresponding slave. */ switch (block) { - case REGI2C_BBPLL : - i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); - REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); - break; - case REGI2C_BIAS : - i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); - REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); - break; - case REGI2C_PMU: - i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); - REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); - break; - case REGI2C_ULP_CAL: - i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); - REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); - break; - case REGI2C_SAR_I2C: - i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); - REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); - break; + case REGI2C_BBPLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_BBTOP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_DCDC: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PMU_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PMU_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_PERIF: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_RFPLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_SDM: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_TXTOP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_TXTOP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_TXTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_ULP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; } - - return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)(i2c_sel ? 0 : 1); } uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) diff --git a/components/hal/esp32/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32/include/hal/regi2c_ctrl_ll.h index 8cb46b0610..44323ae1b9 100644 --- a/components/hal/esp32/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32/include/hal/regi2c_ctrl_ll.h @@ -50,7 +50,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h index fe585f4e9c..99f35a1df4 100644 --- a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h @@ -69,7 +69,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h index 25ab558789..c73df19c0f 100644 --- a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h @@ -49,7 +49,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h index 8970fa6a21..393dfada9e 100644 --- a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h index de07a24569..36ee33c4f5 100644 --- a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -108,7 +108,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h index e4714efbe2..84f00bdb4f 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h index a5b948170a..000e7a6887 100644 --- a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h @@ -104,7 +104,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h index 56cc0582c3..dd1d3272ed 100644 --- a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h @@ -6,14 +6,14 @@ #pragma once +#include #include #include #include "soc/soc.h" #include "soc/regi2c_defs.h" #include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" - -//TODO: [ESP32H21] IDF-11550, inherit from h2 +#include "modem/modem_lpcon_struct.h" #ifdef __cplusplus extern "C" { @@ -22,25 +22,42 @@ extern "C" { /** * @brief Enable analog I2C master clock */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en) { - //TODO: [ESP32H21] IDF-11550 + MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__) + +/** + * @brief Check whether analog I2C master clock is enabled + */ +static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void) +{ + return MODEM_LPCON.clk_conf.clk_i2c_mst_en; } /** * @brief Reset analog I2C master */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void) { - //TODO: [ESP32H21] IDF-11550 + MODEM_LPCON.rst_conf.rst_i2c_mst = 1; + MODEM_LPCON.rst_conf.rst_i2c_mst = 0; } +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__) + /** * @brief Force enable analog I2C master clock */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en) { - //TODO: [ESP32H21] IDF-11550 + MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en; } /** @@ -56,8 +73,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); } /** @@ -65,8 +82,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); } /** @@ -76,7 +93,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) { - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } /** @@ -88,7 +105,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h index 33e0709bb2..bcf642a630 100644 --- a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h @@ -55,7 +55,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h index 862c416ef3..369ee4f608 100644 --- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -124,7 +124,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h index a7ddfff8c2..7a1df7cd88 100644 --- a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h @@ -48,7 +48,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h index 947eced598..50fff66aa2 100644 --- a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h @@ -41,7 +41,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) } /** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index d40758f3a1..4cd51001f0 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -99,6 +99,10 @@ config SOC_MODEM_CLOCK_SUPPORTED bool default y +config SOC_REG_I2C_SUPPORTED + bool + default y + config SOC_AES_SUPPORTED bool default y @@ -906,3 +910,7 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT config SOC_RCC_IS_INDEPENDENT bool default y + +config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE + bool + default y diff --git a/components/soc/esp32h21/include/soc/regi2c_defs.h b/components/soc/esp32h21/include/soc/regi2c_defs.h index c6f3e1e6d9..8742aa25a7 100644 --- a/components/soc/esp32h21/include/soc/regi2c_defs.h +++ b/components/soc/esp32h21/include/soc/regi2c_defs.h @@ -9,7 +9,7 @@ #include "esp_bit_defs.h" /* Analog function control register */ -// I2C_MST_ANA_CONF0_REG +// I2C_ANA_MST_ANA_CONF0_REG #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24)) diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index caf715af0b..102d90fe7a 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -64,7 +64,7 @@ #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526 // #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 #define SOC_MODEM_CLOCK_SUPPORTED 1 -// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550 +#define SOC_REG_I2C_SUPPORTED 1 // #define SOC_PHY_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566 // #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601 @@ -552,6 +552,8 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ +#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ // #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) // #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h index 01c003761a..1e17aa0d5b 100644 --- a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,213 +7,279 @@ #include #include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif -//TODO: [ESP32H21] IDF-11858 +#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_V 0x1 +#define I2C_ANA_MST_I2C0_BUSY_S 25 +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_S 0 -#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C0_CTRL 0x01FFFFFFU -#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S) -#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU -#define I2C_MST_I2C0_CTRL_S 0 -/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C0_BUSY (BIT(25)) -#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S) -#define I2C_MST_I2C0_BUSY_V 0x00000001U -#define I2C_MST_I2C0_BUSY_S 25 +#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_V 0x1 +#define I2C_ANA_MST_I2C1_BUSY_S 25 +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_S 0 -#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C1_CTRL 0x01FFFFFFU -#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S) -#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU -#define I2C_MST_I2C1_CTRL_S 0 -/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C1_BUSY (BIT(25)) -#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S) -#define I2C_MST_I2C1_BUSY_V 0x00000001U -#define I2C_MST_I2C1_BUSY_S 25 +#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_STATUS 0x000000FF +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_V 0xFF +#define I2C_ANA_MST_I2C0_STATUS_S 24 +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C0_CONF_S 0 -#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C0_CONF 0x00FFFFFFU -#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S) -#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU -#define I2C_MST_I2C0_CONF_S 0 -/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C0_STATUS 0x000000FFU -#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S) -#define I2C_MST_I2C0_STATUS_V 0x000000FFU -#define I2C_MST_I2C0_STATUS_S 24 +#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_STATUS 0x000000FF +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_V 0xFF +#define I2C_ANA_MST_I2C1_STATUS_S 24 +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C1_CONF_S 0 -#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) -/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C1_CONF 0x00FFFFFFU -#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S) -#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU -#define I2C_MST_I2C1_CONF_S 0 -/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C1_STATUS 0x000000FFU -#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S) -#define I2C_MST_I2C1_STATUS_V 0x000000FFU -#define I2C_MST_I2C1_STATUS_S 24 +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n * 4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG -#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_BURST_CTRL 0xFFFFFFFFU -#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S) -#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU -#define I2C_MST_BURST_CTRL_S 0 +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 -#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C_MST_BURST_DONE (BIT(0)) -#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S) -#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U -#define I2C_MST_I2C_MST_BURST_DONE_S 0 -/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) -#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S) -#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U -#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/ -/* description: .*/ -#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) -#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S) -#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U -#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/ -/* description: .*/ -#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU -#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S) -#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU -#define I2C_MST_BURST_TIMEOUT_CNT_S 3 +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 -#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) -/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_CONF0 0x00FFFFFFU -#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S) -#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU -#define I2C_MST_ANA_CONF0_S 0 -/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_STATUS0 0x000000FFU -#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S) -#define I2C_MST_ANA_STATUS0_V 0x000000FFU -#define I2C_MST_ANA_STATUS0_S 24 +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 -#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) -/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_CONF1 0x00FFFFFFU -#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S) -#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU -#define I2C_MST_ANA_CONF1_S 0 -/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_STATUS1 0x000000FFU -#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S) -#define I2C_MST_ANA_STATUS1_V 0x000000FFU -#define I2C_MST_ANA_STATUS1_S 24 +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 -#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) -/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_CONF2 0x00FFFFFFU -#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S) -#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU -#define I2C_MST_ANA_CONF2_S 0 -/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ANA_STATUS2 0x000000FFU -#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S) -#define I2C_MST_ANA_STATUS2_V 0x000000FFU -#define I2C_MST_ANA_STATUS2_S 24 +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 -#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ -/* description: .*/ -#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU -#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S) -#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0 -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ -/* description: .*/ -#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU -#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S) -#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6 +#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFF +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M ((I2C_ANA_MST_I2C_MST_BURST_CTRL_V)<<(I2C_ANA_MST_I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFF +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 -#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ -/* description: .*/ -#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU -#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S) -#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0 -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ -/* description: .*/ -#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU -#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S) -#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6 +#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFF +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0xFFF +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 +/* I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (BIT(2)) +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/* I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (BIT(1)) +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/* I2C_ANA_MST_I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) +#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (BIT(0)) +#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x1 +#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 -#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ -/* description: .*/ -#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU -#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S) -#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ -/* description: .*/ -#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU -#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S) -#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/ -/* description: .*/ -#define I2C_MST_ARBITER_DIS (BIT(11)) -#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S) -#define I2C_MST_ARBITER_DIS_V 0x00000001U -#define I2C_MST_ARBITER_DIS_S 11 +#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_ANA_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS0 0x000000FF +#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_ANA_STATUS0_V)<<(I2C_ANA_MST_ANA_STATUS0_S)) +#define I2C_ANA_MST_ANA_STATUS0_V 0xFF +#define I2C_ANA_MST_ANA_STATUS0_S 24 +/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) +#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF0_S 0 -#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/ -/* description: .*/ -#define I2C_MST_NOUSE 0xFFFFFFFFU -#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S) -#define I2C_MST_NOUSE_V 0xFFFFFFFFU -#define I2C_MST_NOUSE_S 0 +#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) +/* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS1 0x000000FF +#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_ANA_STATUS1_V)<<(I2C_ANA_MST_ANA_STATUS1_S)) +#define I2C_ANA_MST_ANA_STATUS1_V 0xFF +#define I2C_ANA_MST_ANA_STATUS1_S 24 +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) +#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF1_S 0 +/* bit0 : test_i2c + bit1 : ana_dig_ch0 + bit2 : BB_TOP_I2C + bit3 : TXTOP_I2C + bit4 : SDM_I2C + bit5 : PLL_I2C + bit6 : BIAS_I2C + bit7 : BB_PLL_I2C + bit8 : ULP_I2C + bit9 : PERIF_I2C + bit10 : PMU_I2C + */ +#define REGI2C_CONF1_BBTOP_SEL (BIT(2)) +#define REGI2C_CONF1_TXTOP_SEL (BIT(3)) +#define REGI2C_CONF1_SDM_SEL (BIT(4)) +#define REGI2C_CONF1_PLL_SEL (BIT(5)) +#define REGI2C_CONF1_BIAS_SEL (BIT(6)) +#define REGI2C_CONF1_BBPLL_SEL (BIT(7)) +#define REGI2C_CONF1_ULP_SEL (BIT(8)) +#define REGI2C_CONF1_PERIF_SEL (BIT(9)) +#define REGI2C_CONF1_PMU_SEL (BIT(10)) -#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/ -/* description: .*/ -#define I2C_MST_DATE 0x0FFFFFFFU -#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S) -#define I2C_MST_DATE_V 0x0FFFFFFFU -#define I2C_MST_DATE_S 0 -/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/ -/* description: .*/ -#define I2C_MST_CLK_EN (BIT(28)) -#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S) -#define I2C_MST_CLK_EN_V 0x00000001U -#define I2C_MST_CLK_EN_S 28 +#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_ANA_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS2 0x000000FF +#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_ANA_STATUS2_V)<<(I2C_ANA_MST_ANA_STATUS2_S)) +#define I2C_ANA_MST_ANA_STATUS2_V 0xFF +#define I2C_ANA_MST_ANA_STATUS2_S 24 +/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S)) +#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF2_S 0 +/* bit4 : BB_TOP_I2C + bit5 : TXTOP_I2C + bit6 : SDM_I2C + bit7 : PLL_I2C + bit8 : BIAS_I2C + bit9 : BB_PLL_I2C + bit10 : ULP_I2C + bit11 : PERIF_I2C + bit12 : PMU_I2C + */ +#define REGI2C_CONF2_BBTOP_SEL (BIT(4)) +#define REGI2C_CONF2_TXTOP_SEL (BIT(5)) +#define REGI2C_CONF2_SDM_SEL (BIT(6)) +#define REGI2C_CONF2_PLL_SEL (BIT(7)) +#define REGI2C_CONF2_BIAS_SEL (BIT(8)) +#define REGI2C_CONF2_BBPLL_SEL (BIT(9)) +#define REGI2C_CONF2_ULP_SEL (BIT(10)) +#define REGI2C_CONF2_PERIF_SEL (BIT(11)) +#define REGI2C_CONF2_PMU_SEL (BIT(12)) + +#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_V 0x1 +#define I2C_ANA_MST_ARBITER_DIS_S 11 +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_ANA_MST_I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFF +#define I2C_ANA_MST_I2C_MST_NOUSE_M ((I2C_ANA_MST_I2C_MST_NOUSE_V)<<(I2C_ANA_MST_I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFF +#define I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +#define I2C_ANA_MST_I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_ANA_MST_I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) +#define I2C_ANA_MST_I2C_MST_CLK_EN_M (BIT(28)) +#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x1 +#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28 +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/*description: .*/ +#define I2C_ANA_MST_DATE 0x0FFFFFFF +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) +#define I2C_ANA_MST_DATE_V 0xFFFFFFF +#define I2C_ANA_MST_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h index 916f629504..2a162986b2 100644 --- a/components/soc/esp32h21/register/soc/reg_base.h +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -47,6 +47,7 @@ #define DR_REG_TEE_BASE 0x60098000 #define DR_REG_HP_APM_BASE 0x60099000 #define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 @@ -61,5 +62,4 @@ #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_CACHE_BASE 0x600C8000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 //TODO: [ESP32H21] IDF-11550, need check #define PWDET_CONF_REG 0x600A0810 //TODO: [ESP32H21] IDF-11589, IDF-11592, need check From 8262915e2844ecb1c8127e06e333e451756cc7a8 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 16 May 2025 14:59:30 +0800 Subject: [PATCH 2/2] refactor(regi2c): remove regi2c_defs.h from some targets --- .../include/esp_private/regi2c_ctrl.h | 8 +- .../lowpower/port/esp32c5/sleep_clock.c | 1 - .../lowpower/port/esp32c6/sleep_clock.c | 20 +- .../lowpower/port/esp32c61/sleep_clock.c | 1 - .../lowpower/port/esp32h2/sleep_clock.c | 2 - .../lowpower/port/esp32h21/sleep_clock.c | 22 +- .../esp_hw_support/port/esp32p4/rtc_clk.c | 6 - components/esp_hw_support/regi2c_ctrl.c | 10 +- components/esp_hw_support/sleep_modes.c | 6 +- .../hal/esp32c2/include/hal/regi2c_ctrl_ll.h | 7 + .../hal/esp32c3/include/hal/regi2c_ctrl_ll.h | 7 + .../hal/esp32c5/include/hal/regi2c_ctrl_ll.h | 3 +- .../hal/esp32c6/include/hal/regi2c_ctrl_ll.h | 14 +- .../hal/esp32c61/include/hal/regi2c_ctrl_ll.h | 3 +- .../hal/esp32h2/include/hal/regi2c_ctrl_ll.h | 10 +- .../hal/esp32h21/include/hal/regi2c_ctrl_ll.h | 3 +- .../hal/esp32p4/include/hal/clk_tree_ll.h | 3 + .../hal/esp32p4/include/hal/regi2c_ctrl_ll.h | 3 +- .../hal/esp32s2/include/hal/regi2c_ctrl_ll.h | 7 + .../hal/esp32s3/include/hal/clk_tree_ll.h | 1 - .../hal/esp32s3/include/hal/regi2c_ctrl_ll.h | 7 + .../soc/esp32c2/include/soc/regi2c_defs.h | 9 +- .../soc/esp32c3/include/soc/regi2c_defs.h | 9 +- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32c5/include/soc/regi2c_defs.h | 15 - components/soc/esp32c5/include/soc/soc_caps.h | 2 - .../esp32c5/register/soc/i2c_ana_mst_reg.h | 4 + .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32c6/include/soc/regi2c_defs.h | 15 - components/soc/esp32c6/include/soc/soc_caps.h | 2 - .../esp32c6/register/soc/i2c_ana_mst_reg.h | 4 + .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32c61/include/soc/regi2c_defs.h | 15 - .../soc/esp32c61/include/soc/soc_caps.h | 2 - .../esp32c61/register/soc/i2c_ana_mst_reg.h | 4 + .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32h2/include/soc/regi2c_defs.h | 22 - components/soc/esp32h2/include/soc/soc_caps.h | 2 - .../esp32h2/register/soc/i2c_ana_mst_reg.h | 4 + .../esp32h21/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32h21/include/soc/regi2c_defs.h | 15 - .../soc/esp32h21/include/soc/soc_caps.h | 2 - .../esp32h21/register/soc/i2c_ana_mst_reg.h | 4 + .../soc/esp32h21/register/soc/lp_peri_reg.h | 388 ------------------ .../esp32h21/register/soc/lp_peri_struct.h | 352 ---------------- .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32p4/include/soc/regi2c_defs.h | 8 - components/soc/esp32p4/include/soc/soc_caps.h | 2 - .../soc/esp32s2/include/soc/regi2c_defs.h | 9 +- .../soc/esp32s3/include/soc/regi2c_defs.h | 9 +- 50 files changed, 112 insertions(+), 954 deletions(-) delete mode 100644 components/soc/esp32c5/include/soc/regi2c_defs.h delete mode 100644 components/soc/esp32c6/include/soc/regi2c_defs.h delete mode 100644 components/soc/esp32c61/include/soc/regi2c_defs.h delete mode 100644 components/soc/esp32h2/include/soc/regi2c_defs.h delete mode 100644 components/soc/esp32h21/include/soc/regi2c_defs.h delete mode 100644 components/soc/esp32h21/register/soc/lp_peri_reg.h delete mode 100644 components/soc/esp32h21/register/soc/lp_peri_struct.h delete mode 100644 components/soc/esp32p4/include/soc/regi2c_defs.h diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h index fcdebb41ac..c8f95ce881 100644 --- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h +++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h @@ -9,7 +9,6 @@ #include #include "sdkconfig.h" #include "esp_rom_regi2c.h" -#include "soc/regi2c_defs.h" #include "soc/soc_caps.h" #include "esp_private/periph_ctrl.h" #include "hal/regi2c_ctrl_ll.h" @@ -20,13 +19,13 @@ extern "C" { #ifdef BOOTLOADER_BUILD -// For bootloader, the strategy is to keep the analog i2c master clock always enabled if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (in bootloader_hardware_init()) +// For bootloader, the strategy is to keep the analog i2c master clock always enabled if ANA_I2C_MST_CLK_HAS_ROOT_GATING (in bootloader_hardware_init()) #define ANALOG_CLOCK_ENABLE() #define ANALOG_CLOCK_DISABLE() #else // !BOOTLOADER_BUILD -#if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE +#if ANA_I2C_MST_CLK_HAS_ROOT_GATING // This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc. // Use reference count to manage the analog i2c master clock #define ANALOG_CLOCK_ENABLE() \ @@ -70,6 +69,7 @@ extern "C" { #define regi2c_ctrl_read_reg_mask regi2c_read_reg_mask_raw #define regi2c_ctrl_write_reg regi2c_write_reg_raw #define regi2c_ctrl_write_reg_mask regi2c_write_reg_mask_raw + #define REGI2C_ENTER_CRITICAL() #define REGI2C_EXIT_CRITICAL() #else @@ -106,7 +106,7 @@ void regi2c_exit_critical(void); * Restore regi2c analog calibration related configuration registers. * This is a workaround, and is fixed on later chips */ -#if REGI2C_ANA_CALI_PD_WORKAROUND +#if REGI2C_LL_ANA_CALI_PD_WORKAROUND void regi2c_analog_cali_reg_read(void); void regi2c_analog_cali_reg_write(void); #endif //#if ADC_CALI_PD_WORKAROUND diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c index b1843a958e..4fede4f136 100644 --- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c @@ -12,7 +12,6 @@ #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/regi2c_defs.h" #include "soc/chip_revision.h" #include "hal/efuse_hal.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c index c8064423fe..269178b969 100644 --- a/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,7 @@ #include "esp_private/sleep_clock.h" #include "soc/pcr_reg.h" #include "soc/pmu_reg.h" -#include "soc/regi2c_defs.h" +#include "soc/i2c_ana_mst_reg.h" #include "modem/modem_lpcon_reg.h" #include "modem/modem_syscon_reg.h" @@ -19,18 +19,18 @@ esp_err_t sleep_clock_system_retention_init(void *arg) const static sleep_retention_entries_config_t pcr_regs_retention[] = { /* Enable i2c master clock */ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, /* Start BBPLL self-calibration */ - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, /* Wait calibration done */ - [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, /* Stop BBPLL self-calibration */ - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, /* Clock configuration retention */ - [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c index 3e6117ddff..5d15ff99b2 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c @@ -9,7 +9,6 @@ #include "soc/pcr_reg.h" #include "soc/pmu_reg.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/regi2c_defs.h" #include "modem/modem_lpcon_reg.h" #include "modem/modem_syscon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c index 476d4ca9d4..94fb2886fe 100644 --- a/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c @@ -6,9 +6,7 @@ #include "esp_private/sleep_clock.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/regi2c_defs.h" #include "soc/pcr_reg.h" -#include "soc/regi2c_defs.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c index 8e26bbc6be..74ec50da5c 100644 --- a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c @@ -6,9 +6,7 @@ #include "esp_private/sleep_clock.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/regi2c_defs.h" #include "soc/pcr_reg.h" -#include "soc/regi2c_defs.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" @@ -21,20 +19,20 @@ esp_err_t sleep_clock_system_retention_init(void *arg) const static sleep_retention_entries_config_t pcr_regs_retention[] = { /* Enable i2c master clock */ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, /* Start BBPLL self-calibration */ - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, /* Wait calibration done */ - [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, /* Stop BBPLL self-calibration */ - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, /* Clock configuration retention */ - [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index d6e1db2779..6a3f9adc97 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -599,9 +599,6 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_ _regi2c_ctrl_ll_master_enable_clock(true); } else { ANALOG_CLOCK_ENABLE(); -#if !BOOTLOADER_BUILD - regi2c_enter_critical(); -#endif } /* MPLL calibration start */ regi2c_ctrl_ll_mpll_calibration_start(); @@ -614,9 +611,6 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_ if (thread_safe) { _regi2c_ctrl_ll_master_enable_clock(false); } else { -#if !BOOTLOADER_BUILD - regi2c_exit_critical(); -#endif ANALOG_CLOCK_DISABLE(); } s_cur_mpll_freq = mpll_freq; diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c index 812f5ea9a3..9dabbc3a94 100644 --- a/components/esp_hw_support/regi2c_ctrl.c +++ b/components/esp_hw_support/regi2c_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -70,21 +70,21 @@ void regi2c_exit_critical(void) * Restore regi2c analog calibration related configuration registers. * This is a workaround, and is fixed on later chips */ -#if REGI2C_ANA_CALI_PD_WORKAROUND +#if REGI2C_LL_ANA_CALI_PD_WORKAROUND #include "soc/regi2c_saradc.h" -static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM]; +static DRAM_ATTR uint8_t reg_val[REGI2C_LL_ANA_CALI_BYTE_NUM]; void IRAM_ATTR regi2c_analog_cali_reg_read(void) { - for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) { + for (int i = 0; i < REGI2C_LL_ANA_CALI_BYTE_NUM; i++) { reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i); } } void IRAM_ATTR regi2c_analog_cali_reg_write(void) { - for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) { + for (int i = 0; i < REGI2C_LL_ANA_CALI_BYTE_NUM; i++) { regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]); } } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c90ca42df1..3866cf9f10 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -57,7 +57,7 @@ #include "hal/rtc_hal.h" #include "soc/rtc.h" -#include "regi2c_ctrl.h" //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp +#include "regi2c_ctrl.h" //For `REGI2C_LL_ANA_CALI_PD_WORKAROUND`, temp #include "hal/cache_ll.h" #include "hal/clk_tree_ll.h" @@ -733,7 +733,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool Cache_WriteBack_All(); } #endif -#if REGI2C_ANA_CALI_PD_WORKAROUND +#if REGI2C_LL_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_read(); #endif #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION @@ -786,7 +786,7 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags) clk_ll_soc_root_clk_auto_gating_bypass(true); # endif #endif -#if REGI2C_ANA_CALI_PD_WORKAROUND +#if REGI2C_LL_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_write(); #endif #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION diff --git a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h index 99f35a1df4..b31be65e4b 100644 --- a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h @@ -15,6 +15,13 @@ extern "C" { #endif +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 + /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ diff --git a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h index c73df19c0f..fb86a52fb2 100644 --- a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h @@ -14,6 +14,13 @@ extern "C" { #endif +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 + /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h index 393dfada9e..b94df77429 100644 --- a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" #include "soc/i2c_ana_mst_reg.h" @@ -19,6 +18,8 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /** * @brief Enable analog I2C master clock */ diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h index 36ee33c4f5..c1009ca32b 100644 --- a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -9,7 +9,7 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" +#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -17,6 +17,8 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /** * @brief Enable analog I2C master clock */ @@ -71,8 +73,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); } /** @@ -80,8 +82,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); } /** @@ -91,7 +93,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) { - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } /** diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h index 84f00bdb4f..bf29390c5b 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" @@ -19,6 +18,8 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /** * @brief Enable analog I2C master clock */ diff --git a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h index 000e7a6887..cd86dd626c 100644 --- a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" #include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -18,6 +17,15 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 + /** * @brief Enable analog I2C master clock */ diff --git a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h index dd1d3272ed..68a0b93384 100644 --- a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h @@ -10,7 +10,6 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" #include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -19,6 +18,8 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /** * @brief Enable analog I2C master clock */ diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index 7ecf2068bf..03a147a73b 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -446,6 +446,8 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_ { HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M); + // There are sequential regi2c operations in `clk_ll_mpll_set_config`, use the raw regi2c API with one lock wrapper to save time. + REGI2C_ENTER_CRITICAL(); uint8_t mpll_dhref_val = esp_rom_regi2c_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF); esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF, mpll_dhref_val | (3 << I2C_MPLL_DHREF_LSB)); uint8_t mpll_rstb_val = esp_rom_regi2c_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB); @@ -457,6 +459,7 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_ uint8_t div = mpll_freq_mhz / 20 - 1; uint8_t val = ((div << 3) | ref_div); esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DIV_REG_ADDR, val); + REGI2C_EXIT_CRITICAL(); } /** diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h index 369ee4f608..a548826eb9 100644 --- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/regi2c_defs.h" #include "soc/hp_sys_clkrst_reg.h" #include "soc/lpperi_struct.h" #include "soc/i2c_ana_mst_struct.h" @@ -19,6 +18,8 @@ extern "C" { #endif +#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ + /** * @brief Enable analog I2C master clock */ diff --git a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h index 7a1df7cd88..98404fdb4d 100644 --- a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h @@ -14,6 +14,13 @@ extern "C" { #endif +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 + /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h index 69261902eb..a4326ccacb 100644 --- a/components/hal/esp32s3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s3/include/hal/clk_tree_ll.h @@ -11,7 +11,6 @@ #include "soc/clk_tree_defs.h" #include "soc/system_reg.h" #include "soc/rtc_cntl_reg.h" -#include "soc/regi2c_defs.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" #include "hal/assert.h" diff --git a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h index 50fff66aa2..b5869c875f 100644 --- a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h @@ -15,6 +15,13 @@ extern "C" { #endif +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 + /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ diff --git a/components/soc/esp32c2/include/soc/regi2c_defs.h b/components/soc/esp32c2/include/soc/regi2c_defs.h index cb2698641b..b91a4fd2e1 100644 --- a/components/soc/esp32c2/include/soc/regi2c_defs.h +++ b/components/soc/esp32c2/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,10 +25,3 @@ #define ANA_CONFIG2_M BIT(18) #define ANA_I2C_SAR_FORCE_PU BIT(16) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32c3/include/soc/regi2c_defs.h b/components/soc/esp32c3/include/soc/regi2c_defs.h index 874da75e26..461a410506 100644 --- a/components/soc/esp32c3/include/soc/regi2c_defs.h +++ b/components/soc/esp32c3/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,10 +24,3 @@ #define ANA_CONFIG2_M BIT(18) #define ANA_I2C_SAR_FORCE_PU BIT(16) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index a1e3df010c..abd3d54ea9 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1663,10 +1663,6 @@ config SOC_RCC_IS_INDEPENDENT bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32c5/include/soc/regi2c_defs.h b/components/soc/esp32c5/include/soc/regi2c_defs.h deleted file mode 100644 index 546da9fee6..0000000000 --- a/components/soc/esp32c5/include/soc/regi2c_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -// I2C_ANA_MST_ANA_CONF0_REG -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index d289171725..74e44e1c22 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -656,8 +656,6 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h index 6e38d22574..a3d43b4bc7 100644 --- a/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h @@ -116,6 +116,10 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF0_S 0 +/* specifically */ +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) /* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 42894c67c7..ad161377a5 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1543,10 +1543,6 @@ config SOC_RCC_IS_INDEPENDENT bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32c6/include/soc/regi2c_defs.h b/components/soc/esp32c6/include/soc/regi2c_defs.h deleted file mode 100644 index 20e3aa1078..0000000000 --- a/components/soc/esp32c6/include/soc/regi2c_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -#define I2C_MST_ANA_CONF0_REG 0x600AF818 -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 933801224c..13981837e8 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -602,8 +602,6 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h index 0f28b3a7a3..44e2f8d0d8 100644 --- a/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h @@ -116,6 +116,10 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF0_S 0 +/* specifically */ +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) /* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index b231b665ed..6dfcfb6605 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -1195,10 +1195,6 @@ config SOC_RCC_IS_INDEPENDENT bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32c61/include/soc/regi2c_defs.h b/components/soc/esp32c61/include/soc/regi2c_defs.h deleted file mode 100644 index a3eb90d9c7..0000000000 --- a/components/soc/esp32c61/include/soc/regi2c_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -// I2C_ANA_MST_ANA_CONF0_REG -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index ce5c8596cd..499c1bda59 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -490,8 +490,6 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h index 08aea2d8c9..42ce233218 100644 --- a/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h @@ -116,6 +116,10 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF0_S 0 +/* specifically */ +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) /* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 5a0267d036..9685668843 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1523,10 +1523,6 @@ config SOC_RCC_IS_INDEPENDENT bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32h2/include/soc/regi2c_defs.h b/components/soc/esp32h2/include/soc/regi2c_defs.h deleted file mode 100644 index cb109945b3..0000000000 --- a/components/soc/esp32h2/include/soc/regi2c_defs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -// I2C_MST_ANA_CONF0_REG -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 3dee435248..7ee8c84c1d 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -608,8 +608,6 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h index 2f0e9c8996..640006a01b 100644 --- a/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h @@ -114,6 +114,10 @@ extern "C" { #define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S) #define I2C_MST_ANA_STATUS0_V 0x000000FFU #define I2C_MST_ANA_STATUS0_S 24 +/* specifically */ +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) /* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/ diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 4cd51001f0..073b66ed79 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -910,7 +910,3 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT config SOC_RCC_IS_INDEPENDENT bool default y - -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y diff --git a/components/soc/esp32h21/include/soc/regi2c_defs.h b/components/soc/esp32h21/include/soc/regi2c_defs.h deleted file mode 100644 index 8742aa25a7..0000000000 --- a/components/soc/esp32h21/include/soc/regi2c_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -// I2C_ANA_MST_ANA_CONF0_REG -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 102d90fe7a..8b06f9c559 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -552,8 +552,6 @@ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ // #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) // #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) diff --git a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h index 1e17aa0d5b..7fc5991117 100644 --- a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h @@ -142,6 +142,10 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF0_S 0 +/* specifically */ +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) /* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ diff --git a/components/soc/esp32h21/register/soc/lp_peri_reg.h b/components/soc/esp32h21/register/soc/lp_peri_reg.h deleted file mode 100644 index 593e87e2e1..0000000000 --- a/components/soc/esp32h21/register/soc/lp_peri_reg.h +++ /dev/null @@ -1,388 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LPPERI_CLK_EN_REG register - * need_des - */ -#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) -/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define LPPERI_RNG_CK_EN (BIT(24)) -#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) -#define LPPERI_RNG_CK_EN_V 0x00000001U -#define LPPERI_RNG_CK_EN_S 24 -/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; - * need_des - */ -#define LPPERI_OTP_DBG_CK_EN (BIT(25)) -#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) -#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U -#define LPPERI_OTP_DBG_CK_EN_S 25 -/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; - * need_des - */ -#define LPPERI_LP_UART_CK_EN (BIT(26)) -#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) -#define LPPERI_LP_UART_CK_EN_V 0x00000001U -#define LPPERI_LP_UART_CK_EN_S 26 -/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; - * need_des - */ -#define LPPERI_LP_IO_CK_EN (BIT(27)) -#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) -#define LPPERI_LP_IO_CK_EN_V 0x00000001U -#define LPPERI_LP_IO_CK_EN_S 27 -/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; - * need_des - */ -#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) -#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) -#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U -#define LPPERI_LP_EXT_I2C_CK_EN_S 28 -/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; - * need_des - */ -#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) -#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) -#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U -#define LPPERI_LP_ANA_I2C_CK_EN_S 29 -/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define LPPERI_EFUSE_CK_EN (BIT(30)) -#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) -#define LPPERI_EFUSE_CK_EN_V 0x00000001U -#define LPPERI_EFUSE_CK_EN_S 30 -/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LPPERI_LP_CPU_CK_EN (BIT(31)) -#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) -#define LPPERI_LP_CPU_CK_EN_V 0x00000001U -#define LPPERI_LP_CPU_CK_EN_S 31 - -/** LPPERI_RESET_EN_REG register - * need_des - */ -#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) -/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; - * need_des - */ -#define LPPERI_BUS_RESET_EN (BIT(23)) -#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) -#define LPPERI_BUS_RESET_EN_V 0x00000001U -#define LPPERI_BUS_RESET_EN_S 23 -/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) -#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) -#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U -#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 -/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) -#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) -#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U -#define LPPERI_OTP_DBG_RESET_EN_S 25 -/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define LPPERI_LP_UART_RESET_EN (BIT(26)) -#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) -#define LPPERI_LP_UART_RESET_EN_V 0x00000001U -#define LPPERI_LP_UART_RESET_EN_S 26 -/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; - * need_des - */ -#define LPPERI_LP_IO_RESET_EN (BIT(27)) -#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) -#define LPPERI_LP_IO_RESET_EN_V 0x00000001U -#define LPPERI_LP_IO_RESET_EN_S 27 -/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) -#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) -#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U -#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 -/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) -#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) -#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U -#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 -/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LPPERI_EFUSE_RESET_EN (BIT(30)) -#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) -#define LPPERI_EFUSE_RESET_EN_V 0x00000001U -#define LPPERI_EFUSE_RESET_EN_S 30 -/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; - * need_des - */ -#define LPPERI_LP_CPU_RESET_EN (BIT(31)) -#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) -#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U -#define LPPERI_LP_CPU_RESET_EN_S 31 - -/** LPPERI_RNG_CFG_REG register - * need_des - */ -#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) -/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) -#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) -#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U -#define LPPERI_RNG_SAMPLE_ENABLE_S 0 -/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; - * need des - */ -#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU -#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) -#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU -#define LPPERI_RNG_TIMER_PSCALE_S 1 -/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; - * need des - */ -#define LPPERI_RNG_TIMER_EN (BIT(9)) -#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) -#define LPPERI_RNG_TIMER_EN_V 0x00000001U -#define LPPERI_RNG_TIMER_EN_S 9 -/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; - * need des - */ -#define LPPERI_RTC_TIMER_EN 0x00000003U -#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) -#define LPPERI_RTC_TIMER_EN_V 0x00000003U -#define LPPERI_RTC_TIMER_EN_S 10 -/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU -#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) -#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU -#define LPPERI_RNG_SAMPLE_CNT_S 24 - -/** LPPERI_RNG_DATA_REG register - * need_des - */ -#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc) -/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LPPERI_RND_DATA 0xFFFFFFFFU -#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) -#define LPPERI_RND_DATA_V 0xFFFFFFFFU -#define LPPERI_RND_DATA_S 0 - -/** LPPERI_CPU_REG register - * need_des - */ -#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10) -/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; - * need_des - */ -#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) -#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) -#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U -#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 - -/** LPPERI_BUS_TIMEOUT_REG register - * need_des - */ -#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14) -/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; - * need_des - */ -#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU -#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) -#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU -#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 -/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) -#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) -#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U -#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 -/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; - * need_des - */ -#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) -#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) -#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U -#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 - -/** LPPERI_BUS_TIMEOUT_ADDR_REG register - * need_des - */ -#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18) -/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU -#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) -#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU -#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 - -/** LPPERI_BUS_TIMEOUT_UID_REG register - * need_des - */ -#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c) -/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; - * need_des - */ -#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU -#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) -#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU -#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 - -/** LPPERI_MEM_CTRL_REG register - * need_des - */ -#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20) -/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; - * need_des - */ -#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) -#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) -#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U -#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 -/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ -#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) -#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) -#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U -#define LPPERI_UART_WAKEUP_FLAG_S 1 -/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LPPERI_UART_WAKEUP_EN (BIT(29)) -#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) -#define LPPERI_UART_WAKEUP_EN_V 0x00000001U -#define LPPERI_UART_WAKEUP_EN_S 29 -/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) -#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) -#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U -#define LPPERI_UART_MEM_FORCE_PD_S 30 -/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; - * need_des - */ -#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) -#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) -#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U -#define LPPERI_UART_MEM_FORCE_PU_S 31 - -/** LPPERI_INTERRUPT_SOURCE_REG register - * need_des - */ -#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24) -/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; - * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, - * lp_io_int - */ -#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU -#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) -#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU -#define LPPERI_LP_INTERRUPT_SOURCE_S 0 - -/** LPPERI_DEBUG_SEL0_REG register - * need des - */ -#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28) -/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; - * need des - */ -#define LPPERI_DEBUG_SEL0 0x0000007FU -#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) -#define LPPERI_DEBUG_SEL0_V 0x0000007FU -#define LPPERI_DEBUG_SEL0_S 0 -/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; - * need des - */ -#define LPPERI_DEBUG_SEL1 0x0000007FU -#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) -#define LPPERI_DEBUG_SEL1_V 0x0000007FU -#define LPPERI_DEBUG_SEL1_S 7 -/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; - * need des - */ -#define LPPERI_DEBUG_SEL2 0x0000007FU -#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) -#define LPPERI_DEBUG_SEL2_V 0x0000007FU -#define LPPERI_DEBUG_SEL2_S 14 -/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; - * need des - */ -#define LPPERI_DEBUG_SEL3 0x0000007FU -#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) -#define LPPERI_DEBUG_SEL3_V 0x0000007FU -#define LPPERI_DEBUG_SEL3_S 21 - -/** LPPERI_DEBUG_SEL1_REG register - * need des - */ -#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c) -/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; - * need des - */ -#define LPPERI_DEBUG_SEL4 0x0000007FU -#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) -#define LPPERI_DEBUG_SEL4_V 0x0000007FU -#define LPPERI_DEBUG_SEL4_S 0 - -/** LPPERI_RNG_DATA_SYNC_REG register - * rng result sync register - */ -#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30) -/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; - * get rng sync result - */ -#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU -#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) -#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU -#define LPPERI_RND_SYNC_DATA_S 0 - -/** LPPERI_DATE_REG register - * need_des - */ -#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) -/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793; - * need_des - */ -#define LPPERI_LPPERI_DATE 0x7FFFFFFFU -#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) -#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU -#define LPPERI_LPPERI_DATE_S 0 -/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LPPERI_CLK_EN (BIT(31)) -#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) -#define LPPERI_CLK_EN_V 0x00000001U -#define LPPERI_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h21/register/soc/lp_peri_struct.h b/components/soc/esp32h21/register/soc/lp_peri_struct.h deleted file mode 100644 index 4ccec691b9..0000000000 --- a/components/soc/esp32h21/register/soc/lp_peri_struct.h +++ /dev/null @@ -1,352 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of clk_en register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** rng_ck_en : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t rng_ck_en:1; - /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; - * need_des - */ - uint32_t otp_dbg_ck_en:1; - /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; - * need_des - */ - uint32_t lp_uart_ck_en:1; - /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t lp_io_ck_en:1; - /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; - * need_des - */ - uint32_t lp_ext_i2c_ck_en:1; - /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; - * need_des - */ - uint32_t lp_ana_i2c_ck_en:1; - /** efuse_ck_en : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t efuse_ck_en:1; - /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_ck_en:1; - }; - uint32_t val; -} lpperi_clk_en_reg_t; - -/** Type of reset_en register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** bus_reset_en : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t bus_reset_en:1; - /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t lp_ble_timer_reset_en:1; - /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t otp_dbg_reset_en:1; - /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_uart_reset_en:1; - /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_io_reset_en:1; - /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_ext_i2c_reset_en:1; - /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_ana_i2c_reset_en:1; - /** efuse_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t efuse_reset_en:1; - /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_reset_en:1; - }; - uint32_t val; -} lpperi_reset_en_reg_t; - -/** Type of rng_cfg register - * need_des - */ -typedef union { - struct { - /** rng_sample_enable : R/W; bitpos: [0]; default: 0; - * need des - */ - uint32_t rng_sample_enable:1; - /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; - * need des - */ - uint32_t rng_timer_pscale:8; - /** rng_timer_en : R/W; bitpos: [9]; default: 1; - * need des - */ - uint32_t rng_timer_en:1; - /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; - * need des - */ - uint32_t rtc_timer_en:2; - uint32_t reserved_12:12; - /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; - * need des - */ - uint32_t rng_sample_cnt:8; - }; - uint32_t val; -} lpperi_rng_cfg_reg_t; - -/** Type of rng_data register - * need_des - */ -typedef union { - struct { - /** rnd_data : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t rnd_data:32; - }; - uint32_t val; -} lpperi_rng_data_reg_t; - -/** Type of cpu register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lpcore_dbgm_unavaliable:1; - }; - uint32_t val; -} lpperi_cpu_reg_t; - -/** Type of bus_timeout register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; - * need_des - */ - uint32_t lp_peri_timeout_thres:16; - /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_int_clear:1; - /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_peri_timeout_protect_en:1; - }; - uint32_t val; -} lpperi_bus_timeout_reg_t; - -/** Type of bus_timeout_addr register - * need_des - */ -typedef union { - struct { - /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_addr:32; - }; - uint32_t val; -} lpperi_bus_timeout_addr_reg_t; - -/** Type of bus_timeout_uid register - * need_des - */ -typedef union { - struct { - /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_uid:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} lpperi_bus_timeout_uid_reg_t; - -/** Type of mem_ctrl register - * need_des - */ -typedef union { - struct { - /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t uart_wakeup_flag_clr:1; - /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ - uint32_t uart_wakeup_flag:1; - uint32_t reserved_2:27; - /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t uart_wakeup_en:1; - /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t uart_mem_force_pd:1; - /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t uart_mem_force_pu:1; - }; - uint32_t val; -} lpperi_mem_ctrl_reg_t; - -/** Type of interrupt_source register - * need_des - */ -typedef union { - struct { - /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; - * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, - * lp_io_int - */ - uint32_t lp_interrupt_source:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} lpperi_interrupt_source_reg_t; - -/** Type of debug_sel0 register - * need des - */ -typedef union { - struct { - /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel0:7; - /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; - * need des - */ - uint32_t debug_sel1:7; - /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; - * need des - */ - uint32_t debug_sel2:7; - /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; - * need des - */ - uint32_t debug_sel3:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} lpperi_debug_sel0_reg_t; - -/** Type of debug_sel1 register - * need des - */ -typedef union { - struct { - /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel4:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} lpperi_debug_sel1_reg_t; - -/** Type of rng_data_sync register - * rng result sync register - */ -typedef union { - struct { - /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; - * get rng sync result - */ - uint32_t rnd_sync_data:32; - }; - uint32_t val; -} lpperi_rng_data_sync_reg_t; - - -/** Group: Version register */ -/** Type of date register - * need_des - */ -typedef union { - struct { - /** lpperi_date : R/W; bitpos: [30:0]; default: 37781793; - * need_des - */ - uint32_t lpperi_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lpperi_date_reg_t; - - -typedef struct { - volatile lpperi_clk_en_reg_t clk_en; - volatile lpperi_reset_en_reg_t reset_en; - volatile lpperi_rng_cfg_reg_t rng_cfg; - volatile lpperi_rng_data_reg_t rng_data; - volatile lpperi_cpu_reg_t cpu; - volatile lpperi_bus_timeout_reg_t bus_timeout; - volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; - volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; - volatile lpperi_mem_ctrl_reg_t mem_ctrl; - volatile lpperi_interrupt_source_reg_t interrupt_source; - volatile lpperi_debug_sel0_reg_t debug_sel0; - volatile lpperi_debug_sel1_reg_t debug_sel1; - volatile lpperi_rng_data_sync_reg_t rng_data_sync; - uint32_t reserved_034[242]; - volatile lpperi_date_reg_t date; -} lpperi_dev_t; - -extern lpperi_dev_t LPPERI; - -#ifndef __cplusplus -_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index a5e2bdbb1e..e42f5fb016 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -2107,10 +2107,6 @@ config SOC_PERIPH_CLK_CTRL_SHARED bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT bool default y diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h deleted file mode 100644 index 1eb30d014e..0000000000 --- a/components/soc/esp32p4/include/soc/regi2c_defs.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once -#include "esp_bit_defs.h" diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index e36cb1b11e..c12ec46237 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -778,8 +778,6 @@ #define SOC_PERIPH_CLK_CTRL_SHARED (1) /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT (1) #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) diff --git a/components/soc/esp32s2/include/soc/regi2c_defs.h b/components/soc/esp32s2/include/soc/regi2c_defs.h index 034e8569b0..399e55b08e 100644 --- a/components/soc/esp32s2/include/soc/regi2c_defs.h +++ b/components/soc/esp32s2/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,10 +21,3 @@ #define ANA_CONFIG2_REG 0x6000E048 #define ANA_SAR_CFG2_M (BIT(16)) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32s3/include/soc/regi2c_defs.h b/components/soc/esp32s3/include/soc/regi2c_defs.h index e6a6e9cb72..3008d8bfd1 100644 --- a/components/soc/esp32s3/include/soc/regi2c_defs.h +++ b/components/soc/esp32s3/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,10 +24,3 @@ #define ANA_CONFIG2_REG 0x6000E048 #define ANA_SAR_CFG2_M (BIT(16)) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8