From 89d566bb9c0463c8516b76dab1b32c13a7eac7b3 Mon Sep 17 00:00:00 2001 From: armando Date: Fri, 25 Apr 2025 10:08:35 +0800 Subject: [PATCH 1/2] fix(psram): fixed psram init state not in low speed mode issue on c5 c61 --- .../esp_psram/device/esp_psram_impl_ap_quad.c | 20 +++++++++++++------ .../hal/esp32c5/include/hal/psram_ctrlr_ll.h | 13 ++++++++++++ .../hal/esp32c61/include/hal/psram_ctrlr_ll.h | 13 ++++++++++++ 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 7cc6fde42a..11176146be 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -247,16 +247,22 @@ static void psram_gpio_config(void) } #if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING -static void s_config_psram_clock(void) +static void s_config_psram_clock(bool init_state) { - // This function can be extended if we have other psram frequency uint32_t clock_conf = 0; + if (init_state) { + clock_conf = psram_ctrlr_ll_calculate_clock_reg(4); + psram_ctrlr_ll_set_spi1_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_1, clock_conf); + } else { + // This function can be extended if we have other psram frequency + #if (CONFIG_SPIRAM_SPEED == 80) - clock_conf = psram_ctrlr_ll_calculate_clock_reg(1); + clock_conf = psram_ctrlr_ll_calculate_clock_reg(1); #elif (CONFIG_SPIRAM_SPEED == 40) - clock_conf = psram_ctrlr_ll_calculate_clock_reg(2); + clock_conf = psram_ctrlr_ll_calculate_clock_reg(2); #endif - psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf); + psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf); + } } #endif //#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING @@ -289,6 +295,8 @@ esp_err_t esp_psram_impl_enable(void) #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING //enter MSPI slow mode to init PSRAM device registers mspi_timing_enter_low_speed_mode(true); +#else + s_config_psram_clock(true); #endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING uint32_t psram_id = 0; @@ -339,7 +347,7 @@ esp_err_t esp_psram_impl_enable(void) //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly mspi_timing_enter_high_speed_mode(true); #else - s_config_psram_clock(); + s_config_psram_clock(false); //Configure SPI0 PSRAM related SPI Phases config_psram_spi_phases(); #endif diff --git a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h index 868dcee35c..1be6f3ca7d 100644 --- a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h @@ -126,6 +126,19 @@ static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock SPIMEM0.mem_sram_clk.val = clock_conf; } +/** + * @brief Set SPI1 bus clock to initialise PSRAM + * + * @param mspi_id mspi_id + * @param clock_conf Configuration value for psram clock + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_spi1_bus_clock(uint32_t mspi_id, uint32_t clock_conf) +{ + HAL_ASSERT(mspi_id == PSRAM_CTRLR_LL_MSPI_ID_1); + SPIMEM1.clock.val = clock_conf; +} + /** * Calculate spi_flash clock frequency division parameters for register. * diff --git a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h index 868dcee35c..1be6f3ca7d 100644 --- a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h @@ -126,6 +126,19 @@ static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock SPIMEM0.mem_sram_clk.val = clock_conf; } +/** + * @brief Set SPI1 bus clock to initialise PSRAM + * + * @param mspi_id mspi_id + * @param clock_conf Configuration value for psram clock + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_spi1_bus_clock(uint32_t mspi_id, uint32_t clock_conf) +{ + HAL_ASSERT(mspi_id == PSRAM_CTRLR_LL_MSPI_ID_1); + SPIMEM1.clock.val = clock_conf; +} + /** * Calculate spi_flash clock frequency division parameters for register. * From 00e256d34313e706d28493f63caa8987a3168c82 Mon Sep 17 00:00:00 2001 From: armando Date: Fri, 25 Apr 2025 10:09:02 +0800 Subject: [PATCH 2/2] fix(psram): fixecd wrong ap density check --- .../esp_psram/device/esp_psram_impl_ap_quad.c | 31 ++++++++++++++----- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 11176146be..e677f81684 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -267,17 +267,33 @@ static void s_config_psram_clock(bool init_state) #endif //#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING /** - * For certain wafer version and 8MB case, we consider it as 4MB mode as it uses 2T mode + * For mrj069000aa, this wafer version and 8MB case, we consider it as 4MB mode as it uses 2T mode */ -bool s_check_aps3204_2tmode(void) +static bool s_check_mrj069000aa_2tmode(uint32_t eid_47_16) +{ + bool is_2t = false; + ESP_EARLY_LOGD(TAG, "(eid_47_16 >> 5) & 0xfffff: 0x%"PRIx32, (eid_47_16 >> 5) & 0xfffff); + if (((eid_47_16 >> 5) & 0xfffff) == 0x8a445) { + is_2t = true; + } + + return is_2t; +} + +static bool s_check_2tmode(void) { uint64_t full_eid = 0; psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_QUAD_EID_BITS_NUM); bool is_2t = false; uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX); - ESP_EARLY_LOGD(TAG, "full_eid: 0x%" PRIx64", eid_47_16: 0x%"PRIx32", (eid_47_16 >> 5) & 0xfffff: 0x%"PRIx32, full_eid, eid_47_16, (eid_47_16 >> 5) & 0xfffff); - if (((eid_47_16 >> 5) & 0xfffff) == 0x8a445) { + ESP_EARLY_LOGD(TAG, "full_eid: 0x%" PRIx64", eid_47_16: 0x%"PRIx32", (eid_47_16 >> 25) & 0x1: 0x%"PRIx32, full_eid, eid_47_16, (eid_47_16 >> 25) & 0x1); + //EID[41]: 0 for 2t mode; 1 for non-2t mode + if (((eid_47_16 >> 25) & 0x1) == 0) { + is_2t = true; + } + + if (s_check_mrj069000aa_2tmode(eid_47_16)) { is_2t = true; } @@ -328,10 +344,11 @@ esp_err_t esp_psram_impl_enable(void) * that are 16MB or 32MB to be interpreted as QEMU PSRAM devices */ eid == PSRAM_QUAD_QEMU_16MB_ID ? PSRAM_SIZE_16MB : eid == PSRAM_QUAD_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0; - } - if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) { - s_psram_size = PSRAM_SIZE_4MB; + if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_2tmode()) { + //2t mode is only valid for EID[47:45] == 0x10 chips + s_psram_size = s_psram_size / 2; + } } //SPI1: send psram reset command