diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml index 1dbe91f913..cfeda3b74d 100644 --- a/components/bootloader_support/test_apps/.build-test-rules.yml +++ b/components/bootloader_support/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section: enable: - if: SOC_RTC_MEM_SUPPORTED == 1 reason: this feature is supported on chips that have RTC memory + disable: + - if: IDF_TARGET == "esp32h21" + temporary: true + reason: IDF-11534 diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..1804b910c1 --- /dev/null +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,692 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_PMU_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_32M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 5 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default y + +config SOC_CPU_HAS_CSR_PC + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x80000000 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_CPU_PMP_REGION_GRANULARITY + int + default 4 + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_AHB_GDMA_VERSION + int + default 1 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 3 + +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 28 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_LP_IO_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_GPIO_IN_RANGE_MAX + int + default 27 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 27 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000000FFF807F + +config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX + bool + default y + +config SOC_CLOCKOUT_HAS_SOURCE_GATE + bool + default y + +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_ANA_CMPR_NUM + int + default 1 + +config SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO + bool + default y + +config SOC_MPI_MEM_BLOCKS_NUM + int + default 4 + +config SOC_MPI_OPERATIONS_NUM + int + default 3 + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_SPI_SUPPORT_CLK_PLL_F48M + bool + default y + +config SOC_SPI_SUPPORT_CLK_RC_FAST + bool + default y + +config SOC_SPI_SCT_SUPPORTED + bool + default y + +config SOC_SPI_SCT_REG_NUM + int + default 14 + +config SOC_SPI_SCT_BUFFER_NUM_MAX + bool + default y + +config SOC_SPI_SCT_CONF_BITLEN_MAX + hex + default 0x3FFFA + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_SPI_MEM_SUPPORT_WRAP + bool + default y + +config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_RC_FAST + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_MWDT_SUPPORT_XTAL + bool + default y + +config SOC_EFUSE_DIS_PAD_JTAG + bool + default y + +config SOC_EFUSE_DIS_USB_JTAG + bool + default y + +config SOC_EFUSE_DIS_DIRECT_BOOT + bool + default y + +config SOC_EFUSE_SOFT_DIS_JTAG + bool + default y + +config SOC_EFUSE_DIS_ICACHE + bool + default y + +config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK + bool + default y + +config SOC_EFUSE_ECDSA_USE_HARDWARE_K + bool + default y + +config SOC_EFUSE_ECDSA_KEY + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default y + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_APM_CTRL_FILTER_SUPPORTED + bool + default y + +config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED + bool + default y + +config SOC_ECDSA_USES_MPI + bool + default y + +config SOC_UART_NUM + int + default 2 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_RTC_CLK + bool + default y + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_EXTERNAL_COEX_ADVANCE + bool + default y + +config SOC_EXTERNAL_COEX_LEADER_TX_LINE + bool + default n + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_TOP_PD + bool + default y + +config SOC_PM_PAU_LINK_NUM + int + default 4 + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_CLK_LP_FAST_SUPPORT_LP_PLL + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y diff --git a/components/soc/esp32h21/include/soc/boot_mode.h b/components/soc/esp32h21/include/soc/boot_mode.h new file mode 100644 index 0000000000..6f4e3d408c --- /dev/null +++ b/components/soc/esp32h21/include/soc/boot_mode.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h new file mode 100644 index 0000000000..cf93f78736 --- /dev/null +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -0,0 +1,266 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32H21 Root Clock Source **************************** + * 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 32MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO13 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_FLASH_PLL = 3, /*!< Select FLASH_PLL_CLK as CPU_CLK source (FLASH_PLL_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ + + SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */ + +} soc_rtc_fast_clk_src_t; + +/** + * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */ +} soc_lp_pll_clk_src_t; + +/** + * @brief Possible main XTAL frequency options on the target + * @note Enum values equal to the frequency value in MHz + * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for + * the supported ones. + */ +typedef enum { + SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */ +} soc_xtal_freq_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or FLASH_PLL by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */ + SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */ + SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */ + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */ +} soc_periph_tg_clk_src_legacy_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of UART + */ +#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */ +} soc_periph_uart_clk_src_legacy_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ + SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of MSPI digital controller + */ +#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} +/** + * @brief MSPI digital controller clock source + */ +typedef enum { + MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ + MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ + MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_mspi_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/dport_access.h b/components/soc/esp32h21/include/soc/dport_access.h new file mode 100644 index 0000000000..72eb538c6b --- /dev/null +++ b/components/soc/esp32h21/include/soc/dport_access.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/efuse_defs.h b/components/soc/esp32h21/include/soc/efuse_defs.h new file mode 100644 index 0000000000..48cc4ce65d --- /dev/null +++ b/components/soc/esp32h21/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/ext_mem_defs.h b/components/soc/esp32h21/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..1d4f57afbd --- /dev/null +++ b/components/soc/esp32h21/include/soc/ext_mem_defs.h @@ -0,0 +1,131 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) + +#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range + +#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH + +#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW +#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH + +#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr) +#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr) +#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr) +#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr) + +#define SOC_MMU_ACCESS_FLASH 0 +#define SOC_MMU_VALID BIT(9) +#define SOC_MMU_SENSITIVE BIT(10) +#define SOC_MMU_INVALID_MASK BIT(9) +#define SOC_MMU_INVALID 0 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define SOC_MMU_VALID_VAL_MASK 0x1ff +/** + * Max MMU available paddr page num. + * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define SOC_MMU_MAX_PADDR_PAGE_NUM 256 +//MMU entry num +#define SOC_MMU_ENTRY_NUM 256 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & SOC_MMU_VADDR_MASK + */ +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) + +#define SOC_MMU_DBUS_VADDR_BASE 0x42000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x42000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +#if (SOC_MMU_PAGE_SIZE == 0x10000) +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x7F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x8000) +/** + * - 32KB MMU page size: the last 0x7FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x3F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x4000) +/** + * - 16KB MMU page size: the last 0x3FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x1F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF +#endif //SOC_MMU_PAGE_SIZE + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +#ifndef __cplusplus +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/gpio_num.h b/components/soc/esp32h21/include/soc/gpio_num.h new file mode 100644 index 0000000000..68f53c6214 --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_num.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO number + */ +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_MAX, +} gpio_num_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/gpio_pins.h b/components/soc/esp32h21/include/soc/gpio_pins.h new file mode 100644 index 0000000000..69bbf244a7 --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_pins.h @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11611 +#define GPIO_MATRIX_CONST_ONE_INPUT (0x20) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30) +#define GPIO_MATRIX_INVALID (0x3A) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/periph_defs.h b/components/soc/esp32h21/include/soc/periph_defs.h new file mode 100644 index 0000000000..9044603a06 --- /dev/null +++ b/components/soc/esp32h21/include/soc/periph_defs.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-11855 +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_RNG_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_ECDSA_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_ETM_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/regi2c_bbpll.h b/components/soc/esp32h21/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..04b76a40e2 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_bbpll.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DIV 3 +#define I2C_BBPLL_OC_DIV_MSB 5 +#define I2C_BBPLL_OC_DIV_LSB 0 + +#define I2C_BBPLL_OC_DHREF_SEL 5 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 5 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 diff --git a/components/soc/esp32h21/include/soc/regi2c_bias.h b/components/soc/esp32h21/include/soc/regi2c_bias.h new file mode 100644 index 0000000000..64ed52017b --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_bias.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32h21.c. + */ + +#define I2C_BIAS 0X6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_0P8 0 +#define I2C_BIAS_DREG_0P8_MSB 7 +#define I2C_BIAS_DREG_0P8_LSB 4 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32h21/include/soc/regi2c_defs.h b/components/soc/esp32h21/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..d00fd070b4 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_defs.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +// I2C_MST_ANA_CONF0_REG +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + +// I2C_MST_ANA_CONF1_REG +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + +// I2C_MST_ANA_CONF2_REG +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32h21/include/soc/regi2c_lp_bias.h b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h new file mode 100644 index 0000000000..dea8e75263 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 diff --git a/components/soc/esp32h21/include/soc/regi2c_pmu.h b/components/soc/esp32h21/include/soc/regi2c_pmu.h new file mode 100644 index 0000000000..d6fabdb26e --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_pmu.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_pmu.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_PMU 0x6d +#define I2C_PMU_HOSTID 0 + +#define I2C_PMU_EN_I2C_RTC_DREG 8 +#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0 +#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0 + +#define I2C_PMU_EN_I2C_DIG_DREG 8 +#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1 +#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1 + +#define I2C_PMU_EN_I2C_RTC_DREG_SLP 8 +#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2 +#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2 + +#define I2C_PMU_EN_I2C_DIG_DREG_SLP 8 +#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3 +#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3 + +#define I2C_PMU_OR_XPD_RTC_REG 9 +#define I2C_PMU_OR_XPD_RTC_REG_MSB 4 +#define I2C_PMU_OR_XPD_RTC_REG_LSB 4 + +#define I2C_PMU_OR_XPD_DIG_REG 9 +#define I2C_PMU_OR_XPD_DIG_REG_MSB 5 +#define I2C_PMU_OR_XPD_DIG_REG_LSB 5 + +#define I2C_PMU_OC_SCK_DCAP 14 +#define I2C_PMU_OC_SCK_DCAP_MSB 7 +#define I2C_PMU_OC_SCK_DCAP_LSB 0 + +#define I2C_PMU_OR_XPD_TRX 15 +#define I2C_PMU_OR_XPD_TRX_MSB 2 +#define I2C_PMU_OR_XPD_TRX_LSB 2 + +#define I2C_PMU_SEL_PLL8M_REF 21 +#define I2C_PMU_SEL_PLL8M_REF_MSB 6 +#define I2C_PMU_SEL_PLL8M_REF_LSB 6 diff --git a/components/soc/esp32h21/include/soc/regi2c_saradc.h b/components/soc/esp32h21/include/soc/regi2c_saradc.h new file mode 100644 index 0000000000..ad40af74ae --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_saradc.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 diff --git a/components/soc/esp32h21/include/soc/reset_reasons.h b/components/soc/esp32h21/include/soc/reset_reasons.h new file mode 100644 index 0000000000..039f95ba42 --- /dev/null +++ b/components/soc/esp32h21/include/soc/reset_reasons.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core + RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 +} soc_reset_reason_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/soc.h b/components/soc/esp32h21/include/soc/soc.h new file mode 100644 index 0000000000..7befaf79a8 --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +// TODO: IDF-11856 +#define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define DR_REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) +#define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21 +#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) +#define DR_REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI +#define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define APB_CLK_FREQ ( 32*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x43000000 +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40020000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40020000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40850000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40850000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H21 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50001000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50001000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50001000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40850000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40850000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40850000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40850000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40850000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 + +//TODO: [ESP32H21] IDF-11857 +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4084f380 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h new file mode 100644 index 0000000000..320d7a2c4c --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -0,0 +1,557 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11589, IDF-11592 +// #define SOC_ANA_CMPR_SUPPORTED 1 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11621 +#define SOC_UART_SUPPORTED 1 //TODO: [ESP32H21] IDF-11618 +// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 +// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 +// #define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11594 +// #define SOC_BT_SUPPORTED 1 +// #define SOC_IEEE802154_SUPPORTED 1 +// #define SOC_IEEE802154_BLE_ONLY 1 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11616 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32H21] IDF-11624 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_ULP_SUPPORTED 1 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507 +// #define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548 +// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608 +// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573 +// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11583, IDF-11584, IDF-11587 +// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568 +// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11578, IDF-11580 +#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598 +// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501 +// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495 +// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497 +// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502 +// #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502 +// #define SOC_ECDSA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11496 +#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11499 +// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11500 +// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530 +// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494 +#define SOC_PMU_SUPPORTED 1 //TODO: [ESP32H21] IDf-11522 +// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11512 +// #define SOC_LP_AON_SUPPORTED 1 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11521 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11545 +// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528 +#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526 +// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 +// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550 +// #define SOC_PHY_SUPPORTED 1 +// #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566 +// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601 +// #define SOC_TWAI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11574 +// #define SOC_ETM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11576 +// #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572 +// #define SOC_RMT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11622 +// #define SOC_AES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11504 +// #define SOC_SDIO_SLAVE_SUPPORTED 1 +// #define SOC_PAU_SUPPORTED 1 +// #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11517, IDF-11520 +// #define SOC_DEEP_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11514 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 +// #define SOC_PM_SUPPORTED 1 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_32M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller +#define SOC_CPU_HAS_CSR_PC 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 +#define SOC_CPU_PMP_REGION_GRANULARITY 4 + +/*-------------------------- MMU CAPS ----------------------------------------*/ +// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) +// #define SOC_MMU_PAGE_SIZE_8KB_SUPPORTED (1) +#define SOC_MMU_PERIPH_NUM (1U) +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) +#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */ + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS --------------------------------------*/ +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-H21 has 1 GPIO peripheral +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 28 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 +// #define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 + +// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) +// Digital IOs have their own registers to control pullup/down/capability +// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) + +// LP IO peripherals have independent clock gating to manage +#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1) +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK + +#define SOC_GPIO_IN_RANGE_MAX 27 +#define SOC_GPIO_OUT_RANGE_MAX 27 + +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL + +// Support to force hold all IOs +// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// Support to hold a single digital I/O when the digital domain is powered off +// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) + +// The Clock Out signal is route to the pin by GPIO matrix +#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported + * for hold, wake & 32kHz crystal functions - via LP_AON registers */ +// #define SOC_RTCIO_PIN_COUNT (8U) +// #define SOC_RTCIO_HOLD_SUPPORTED (1) +// #define SOC_RTCIO_VALID_RTCIO_MASK (0x7F80) + +/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ +#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ +#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ +#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ + +/*------------------------- Analog Comparator CAPS ---------------------------*/ +#define SOC_ANA_CMPR_NUM (1U) +#define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1) + +/*-------------------------- I2C CAPS ----------------------------------------*/ +// ESP32-H21 has 2 I2C +// #define SOC_I2C_NUM (2U) +// #define SOC_HP_I2C_NUM (2U) + +// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ +// #define SOC_I2C_SUPPORT_SLAVE (1) + +// #define SOC_I2C_SUPPORT_HW_FSM_RST (1) +// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) + +// #define SOC_I2C_SUPPORT_XTAL (1) +// #define SOC_I2C_SUPPORT_RTC (1) +// #define SOC_I2C_SUPPORT_10BIT_ADDR (1) +// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1) +// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1) +// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) +// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) +// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) + +/*-------------------------- I2S CAPS ----------------------------------------*/ +// #define SOC_I2S_NUM (1U) +// #define SOC_I2S_HW_VERSION_2 (1) +// // #define SOC_I2S_SUPPORTS_ETM (1) +// #define SOC_I2S_SUPPORTS_XTAL (1) +// #define SOC_I2S_SUPPORTS_PLL_F96M (1) +// #define SOC_I2S_SUPPORTS_PLL_F64M (1) +// #define SOC_I2S_SUPPORTS_PCM (1) +// #define SOC_I2S_SUPPORTS_PDM (1) +// #define SOC_I2S_SUPPORTS_PDM_TX (1) +// #define SOC_I2S_PDM_MAX_TX_LINES (2) +// #define SOC_I2S_SUPPORTS_TDM (1) +// #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ + +/*-------------------------- LEDC CAPS ---------------------------------------*/ +// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +// #define SOC_LEDC_CHANNEL_NUM (6) +// #define SOC_LEDC_TIMER_BIT_WIDTH (20) +// #define SOC_LEDC_SUPPORT_FADE_STOP (1) +// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) +// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) +// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) + +/*-------------------------- MPU CAPS ----------------------------------------*/ +// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +// #define SOC_MPU_MIN_REGION_SIZE 0x20000000U +// #define SOC_MPU_REGIONS_MAX_NUM 8 +// #define SOC_MPU_REGION_RO_SUPPORTED 0 +// #define SOC_MPU_REGION_WO_SUPPORTED 0 + +/*-------------------------- PCNT CAPS ---------------------------------------*/ +// #define SOC_PCNT_GROUPS 1U +// #define SOC_PCNT_UNITS_PER_GROUP 4 +// #define SOC_PCNT_CHANNELS_PER_UNIT 2 +// #define SOC_PCNT_THRES_POINT_PER_UNIT 2 +// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 + +/*--------------------------- RMT CAPS ---------------------------------------*/ +// #define SOC_RMT_GROUPS 1U /*!< One RMT group */ +// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */ +// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */ +// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */ +// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ +// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ +// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ +// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ +// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ +// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ +// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ +// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ +// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ +// #define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */ + +/*-------------------------- MCPWM CAPS --------------------------------------*/ +// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has +// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has +// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output +// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) +// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers + +/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ +// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 + +/*-------------------------- PARLIO CAPS --------------------------------------*/ +// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ +// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ +// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ +// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */ +// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */ +// #define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */ +// #define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ +// #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ +// #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ + +/*--------------------------- MPI CAPS ---------------------------------------*/ +#define SOC_MPI_MEM_BLOCKS_NUM (4) +#define SOC_MPI_OPERATIONS_NUM (3) + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 +#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1 +#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_SPI_SCT_SUPPORTED 1 +#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer +#define SOC_SPI_SCT_REG_NUM 14 +#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs +#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +#define SOC_SPI_MEM_SUPPORT_WRAP (1) + +#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed to 2 when clock source is XTAL +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) +// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +#define SOC_MWDT_SUPPORT_XTAL (1) +// #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 1UL +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +#define SOC_EFUSE_DIS_PAD_JTAG 1 +#define SOC_EFUSE_DIS_USB_JTAG 1 +#define SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define SOC_EFUSE_SOFT_DIS_JTAG 1 +#define SOC_EFUSE_DIS_ICACHE 1 +#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block +#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA +#define SOC_EFUSE_ECDSA_KEY 1 + +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 1 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*-------------------------- APM CAPS ----------------------------------------*/ +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*------------------------- ECDSA CAPS -------------------------*/ +#define SOC_ECDSA_USES_MPI (1) + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-H21 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// #define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */ + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_BT_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! #include "soc/soc.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif /** EFUSE_PGM_DATA0_REG register - * Represents pgm_data0 + * Register 0 that stores data to be programmed. */ #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; @@ -24,11 +25,11 @@ extern "C" { #define EFUSE_PGM_DATA_0_S 0 /** EFUSE_PGM_DATA1_REG register - * Represents pgm_data1 + * Register 1 that stores data to be programmed. */ #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th 32-bit data to be programmed. + * Configures the 1st 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) @@ -36,11 +37,11 @@ extern "C" { #define EFUSE_PGM_DATA_1_S 0 /** EFUSE_PGM_DATA2_REG register - * Represents pgm_data2 + * Register 2 that stores data to be programmed. */ #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th 32-bit data to be programmed. + * Configures the 2nd 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) @@ -48,11 +49,11 @@ extern "C" { #define EFUSE_PGM_DATA_2_S 0 /** EFUSE_PGM_DATA3_REG register - * Represents pgm_data3 + * Register 3 that stores data to be programmed. */ #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th 32-bit data to be programmed. + * Configures the 3rd 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_3 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) @@ -60,7 +61,7 @@ extern "C" { #define EFUSE_PGM_DATA_3_S 0 /** EFUSE_PGM_DATA4_REG register - * Represents pgm_data4 + * Register 4 that stores data to be programmed. */ #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; @@ -72,7 +73,7 @@ extern "C" { #define EFUSE_PGM_DATA_4_S 0 /** EFUSE_PGM_DATA5_REG register - * Represents pgm_data5 + * Register 5 that stores data to be programmed. */ #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; @@ -84,7 +85,7 @@ extern "C" { #define EFUSE_PGM_DATA_5_S 0 /** EFUSE_PGM_DATA6_REG register - * Represents pgm_data6 + * Register 6 that stores data to be programmed. */ #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; @@ -96,7 +97,7 @@ extern "C" { #define EFUSE_PGM_DATA_6_S 0 /** EFUSE_PGM_DATA7_REG register - * Represents pgm_data7 + * Register 7 that stores data to be programmed. */ #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; @@ -108,11 +109,11 @@ extern "C" { #define EFUSE_PGM_DATA_7_S 0 /** EFUSE_PGM_CHECK_VALUE0_REG register - * Represents pgm_check_value0 + * Register 0 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. + * Configures the 0th 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) @@ -120,11 +121,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_0_S 0 /** EFUSE_PGM_CHECK_VALUE1_REG register - * Represents pgm_check_value1 + * Register 1 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th RS code to be programmed. + * Configures the 1st 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) @@ -132,11 +133,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_1_S 0 /** EFUSE_PGM_CHECK_VALUE2_REG register - * Represents pgm_check_value2 + * Register 2 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th RS code to be programmed. + * Configures the 2nd 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) @@ -144,14 +145,12 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_S 0 /** EFUSE_RD_WR_DIS_REG register - * Represents rd_wr_dis + * BLOCK0 data register 0. */ #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: Disabled. 0 Enabled. */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -159,243 +158,219 @@ extern "C" { #define EFUSE_WR_DIS_S 0 /** EFUSE_RD_REPEAT_DATA0_REG register - * Represents rd_repeat_data + * BLOCK0 data register 1. */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 -/** EFUSE_PVT_GLITCH_EN : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable +/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ -#define EFUSE_PVT_GLITCH_EN (BIT(7)) -#define EFUSE_PVT_GLITCH_EN_M (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S) -#define EFUSE_PVT_GLITCH_EN_V 0x00000001U -#define EFUSE_PVT_GLITCH_EN_S 7 +#define EFUSE_RPT4_RESERVED0_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_4_M (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S) +#define EFUSE_RPT4_RESERVED0_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_4_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) #define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. */ #define EFUSE_POWERGLITCH_EN (BIT(10)) #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) #define EFUSE_POWERGLITCH_EN_V 0x00000001U #define EFUSE_POWERGLITCH_EN_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) #define EFUSE_DIS_TWAI_V 0x00000001U #define EFUSE_DIS_TWAI_S 14 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) #define EFUSE_USB_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_S 25 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. */ #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_ECDSA_CURVE_MODE : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 +/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. */ -#define EFUSE_ECDSA_CURVE_MODE 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_M (EFUSE_ECDSA_CURVE_MODE_V << EFUSE_ECDSA_CURVE_MODE_S) -#define EFUSE_ECDSA_CURVE_MODE_V 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_S 27 -/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled +#define EFUSE_RPT4_RESERVED0_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_M (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S) +#define EFUSE_RPT4_RESERVED0_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_S 27 +/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0; + * Reserved. */ -#define EFUSE_ECC_FORCE_CONST_TIME (BIT(29)) -#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) -#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_S 29 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. +#define EFUSE_RPT4_RESERVED0_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_1_M (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S) +#define EFUSE_RPT4_RESERVED0_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_1_S 29 +/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 30 +#define EFUSE_RPT4_RESERVED0_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S) +#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_S 30 /** EFUSE_RD_REPEAT_DATA1_REG register - * Represents rd_repeat_data + * BLOCK0 data register 2. */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_IO_LDO_ADJUST : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. +/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. */ -#define EFUSE_IO_LDO_ADJUST 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_M (EFUSE_IO_LDO_ADJUST_V << EFUSE_IO_LDO_ADJUST_S) -#define EFUSE_IO_LDO_ADJUST_V 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_S 0 -/** EFUSE_VDD_SPI_LDO_ADJUST : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. - */ -#define EFUSE_VDD_SPI_LDO_ADJUST 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_M (EFUSE_VDD_SPI_LDO_ADJUST_V << EFUSE_VDD_SPI_LDO_ADJUST_S) -#define EFUSE_VDD_SPI_LDO_ADJUST_V 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_S 8 +#define EFUSE_RPT4_RESERVED1_1 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_M (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S) +#define EFUSE_RPT4_RESERVED1_1_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_S 0 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + * Represents the purpose of Key0. */ #define EFUSE_KEY_PURPOSE_0 0x0000000FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_S 24 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. + * Represents the purpose of Key1. */ #define EFUSE_KEY_PURPOSE_1 0x0000000FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) @@ -403,105 +378,85 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_S 28 /** EFUSE_RD_REPEAT_DATA2_REG register - * Represents rd_repeat_data + * BLOCK0 data register 3. */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. + * Represents the purpose of Key2. */ #define EFUSE_KEY_PURPOSE_2 0x0000000FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. + * Represents the purpose of Key3. */ #define EFUSE_KEY_PURPOSE_3 0x0000000FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_S 4 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. + * Represents the purpose of Key4. */ #define EFUSE_KEY_PURPOSE_4 0x0000000FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_S 8 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. + * Represents the purpose of Key5. */ #define EFUSE_KEY_PURPOSE_5 0x0000000FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_S 12 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. + * Represents the spa secure level by configuring the clock random divide mode. */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_IO_LDO_1P8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V +/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. */ -#define EFUSE_IO_LDO_1P8 (BIT(18)) -#define EFUSE_IO_LDO_1P8_M (EFUSE_IO_LDO_1P8_V << EFUSE_IO_LDO_1P8_S) -#define EFUSE_IO_LDO_1P8_V 0x00000001U -#define EFUSE_IO_LDO_1P8_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K (BIT(18)) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V 0x00000001U +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. */ #define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) #define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_S 19 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_POWERGLITCH_EN1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. +/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. */ -#define EFUSE_POWERGLITCH_EN1 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S) -#define EFUSE_POWERGLITCH_EN1_V 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_S 22 -/** EFUSE_DCDC_CCM_EN : RO; bitpos: [27]; default: 0; - * Represents whether change DCDC to CCM mode. - */ -#define EFUSE_DCDC_CCM_EN (BIT(27)) -#define EFUSE_DCDC_CCM_EN_M (EFUSE_DCDC_CCM_EN_V << EFUSE_DCDC_CCM_EN_S) -#define EFUSE_DCDC_CCM_EN_V 0x00000001U -#define EFUSE_DCDC_CCM_EN_S 27 +#define EFUSE_RPT4_RESERVED2_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S) +#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_S 22 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -509,96 +464,87 @@ extern "C" { #define EFUSE_FLASH_TPUW_S 28 /** EFUSE_RD_REPEAT_DATA3_REG register - * Represents rd_repeat_data + * BLOCK0 data register 4. */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled + * Set this bit to disable USB-Serial-JTAG print during rom boot. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) +#define EFUSE_RPT4_RESERVED3_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_5_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only UART is supported for - * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. + * Represents the version used by ESP-IDF anti-rollback feature. */ #define EFUSE_SECURE_VERSION 0x0000FFFFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) #define EFUSE_SECURE_VERSION_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD0~5 */ #define EFUSE_HYS_EN_PAD0 0x0000003FU #define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) @@ -606,267 +552,443 @@ extern "C" { #define EFUSE_HYS_EN_PAD0_S 26 /** EFUSE_RD_REPEAT_DATA4_REG register - * Represents rd_repeat_data + * BLOCK0 data register 5. */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD6~27 */ #define EFUSE_HYS_EN_PAD1 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) #define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_S 0 -/** EFUSE_FLASH_LDO_POWER_SEL : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. +/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ -#define EFUSE_FLASH_LDO_POWER_SEL (BIT(22)) -#define EFUSE_FLASH_LDO_POWER_SEL_M (EFUSE_FLASH_LDO_POWER_SEL_V << EFUSE_FLASH_LDO_POWER_SEL_S) -#define EFUSE_FLASH_LDO_POWER_SEL_V 0x00000001U -#define EFUSE_FLASH_LDO_POWER_SEL_S 22 +#define EFUSE_RPT4_RESERVED4_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) +#define EFUSE_RPT4_RESERVED4_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_S 22 +/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) +#define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_S 24 -/** EFUSE_RD_MAC_SYS0_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. + * Stores the low 32 bits of MAC address. */ #define EFUSE_MAC_0 0xFFFFFFFFU #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) #define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -/** EFUSE_RD_MAC_SYS1_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. + * Stores the high 16 bits of MAC address. */ #define EFUSE_MAC_1 0x0000FFFFU #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 /** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. + * Stores the extended bits of MAC address. */ #define EFUSE_MAC_EXT 0x0000FFFFU #define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) #define EFUSE_MAC_EXT_V 0x0000FFFFU #define EFUSE_MAC_EXT_S 16 -/** EFUSE_RD_MAC_SYS2_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. */ -#define EFUSE_MAC_RESERVED_0 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_S 0 -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. +#define EFUSE_RXIQ_VERSION 0x00000007U +#define EFUSE_RXIQ_VERSION_M (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S) +#define EFUSE_RXIQ_VERSION_V 0x00000007U +#define EFUSE_RXIQ_VERSION_S 0 +/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. */ -#define EFUSE_MAC_RESERVED_1 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_S 14 +#define EFUSE_RXIQ_0 0x0000007FU +#define EFUSE_RXIQ_0_M (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S) +#define EFUSE_RXIQ_0_V 0x0000007FU +#define EFUSE_RXIQ_0_S 3 +/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. + */ +#define EFUSE_RXIQ_1 0x0000007FU +#define EFUSE_RXIQ_1_M (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S) +#define EFUSE_RXIQ_1_V 0x0000007FU +#define EFUSE_RXIQ_1_S 10 +/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. + */ +#define EFUSE_ACTIVE_HP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_S 17 +/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ +#define EFUSE_ACTIVE_LP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_S 22 +/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ +#define EFUSE_DSLP_DBIAS 0x0000000FU +#define EFUSE_DSLP_DBIAS_M (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S) +#define EFUSE_DSLP_DBIAS_V 0x0000000FU +#define EFUSE_DSLP_DBIAS_S 27 +/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE1 (BIT(31)) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_M (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_VALUE1_S 31 -/** EFUSE_RD_MAC_SYS3_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [3:0]; default: 0; +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE2 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_M (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE2_V 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_S 0 +/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_SIGN (BIT(3)) +#define EFUSE_DBIAS_VOL_GAP_SIGN_M (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S) +#define EFUSE_DBIAS_VOL_GAP_SIGN_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_SIGN_S 3 +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0; * Reserved. */ -#define EFUSE_MAC_RESERVED_2 0x0000000FU +#define EFUSE_MAC_RESERVED_2 0x00003FFFU #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0000000FU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_PVT_CELL_SELECT : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. +#define EFUSE_MAC_RESERVED_2_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_2_S 4 +/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. */ -#define EFUSE_PVT_CELL_SELECT 0x0000007FU -#define EFUSE_PVT_CELL_SELECT_M (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S) -#define EFUSE_PVT_CELL_SELECT_V 0x0000007FU -#define EFUSE_PVT_CELL_SELECT_S 4 -/** EFUSE_MAC_RESERVED_3 : RO; bitpos: [17:11]; default: 0; - * Reserved. +#define EFUSE_WAFER_VERSION_MINOR 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_S 18 +/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. */ -#define EFUSE_MAC_RESERVED_3 0x0000007FU -#define EFUSE_MAC_RESERVED_3_M (EFUSE_MAC_RESERVED_3_V << EFUSE_MAC_RESERVED_3_S) -#define EFUSE_MAC_RESERVED_3_V 0x0000007FU -#define EFUSE_MAC_RESERVED_3_S 11 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 21 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23 +/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 24 +/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ +#define EFUSE_FLASH_TEMP 0x00000003U +#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) +#define EFUSE_FLASH_TEMP_V 0x00000003U +#define EFUSE_FLASH_TEMP_S 27 +/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 29 -/** EFUSE_RD_MAC_SYS4_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_PVT_LIMIT : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0; + * Package version */ -#define EFUSE_PVT_LIMIT 0x0000FFFFU -#define EFUSE_PVT_LIMIT_M (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S) -#define EFUSE_PVT_LIMIT_V 0x0000FFFFU -#define EFUSE_PVT_LIMIT_S 5 -/** EFUSE_PVT_GLITCH_CHARGE_RESET : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 0 +/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0; + * reserved */ -#define EFUSE_PVT_GLITCH_CHARGE_RESET (BIT(21)) -#define EFUSE_PVT_GLITCH_CHARGE_RESET_M (EFUSE_PVT_GLITCH_CHARGE_RESET_V << EFUSE_PVT_GLITCH_CHARGE_RESET_S) -#define EFUSE_PVT_GLITCH_CHARGE_RESET_V 0x00000001U -#define EFUSE_PVT_GLITCH_CHARGE_RESET_S 21 -/** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. - */ -#define EFUSE_PVT_GLITCH_MODE 0x00000003U -#define EFUSE_PVT_GLITCH_MODE_M (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S) -#define EFUSE_PVT_GLITCH_MODE_V 0x00000003U -#define EFUSE_PVT_GLITCH_MODE_S 22 -/** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. - */ -#define EFUSE_PVT_PUMP_LIMIT 0x000000FFU -#define EFUSE_PVT_PUMP_LIMIT_M (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S) -#define EFUSE_PVT_PUMP_LIMIT_V 0x000000FFU -#define EFUSE_PVT_PUMP_LIMIT_S 24 +#define EFUSE_RESERVED_1_131 0x1FFFFFFFU +#define EFUSE_RESERVED_1_131_M (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S) +#define EFUSE_RESERVED_1_131_V 0x1FFFFFFFU +#define EFUSE_RESERVED_1_131_S 3 -/** EFUSE_RD_MAC_SYS5_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. */ -#define EFUSE_PUMP_DRV 0x0000000FU -#define EFUSE_PUMP_DRV_M (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S) -#define EFUSE_PUMP_DRV_V 0x0000000FU -#define EFUSE_PUMP_DRV_S 0 -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_2 0x0FFFFFFFU +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0x0FFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 4 +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 /** EFUSE_RD_SYS_PART1_DATA0_REG register - * Represents rd_sys_part1_data0 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register - * Represents rd_sys_part1_data1 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register - * Represents rd_sys_part1_data2 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register - * Represents rd_sys_part1_data3 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register - * Represents rd_sys_part1_data4 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0; + * reserved */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_RESERVED_2_128 0x00000003U +#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) +#define EFUSE_RESERVED_2_128_V 0x00000003U +#define EFUSE_RESERVED_2_128_S 0 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0; + * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 2 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 5 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 +/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 8 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 /** EFUSE_RD_SYS_PART1_DATA5_REG register - * Represents rd_sys_part1_data5 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; + * ADC1 calibration data */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15 +/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 /** EFUSE_RD_SYS_PART1_DATA6_REG register - * Represents rd_sys_part1_data6 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration data */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 +/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 +/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 +/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 /** EFUSE_RD_SYS_PART1_DATA7_REG register - * Represents rd_sys_part1_data7 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration data */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 +/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 +/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 +/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 +/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 +/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17 +/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_245 0x000007FFU +#define EFUSE_RESERVED_2_245_M (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S) +#define EFUSE_RESERVED_2_245_V 0x000007FFU +#define EFUSE_RESERVED_2_245_S 21 /** EFUSE_RD_USR_DATA0_REG register - * Represents rd_usr_data0 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the zeroth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA0 0xFFFFFFFFU #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) @@ -874,11 +996,11 @@ extern "C" { #define EFUSE_USR_DATA0_S 0 /** EFUSE_RD_USR_DATA1_REG register - * Represents rd_usr_data1 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the first 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA1 0xFFFFFFFFU #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) @@ -886,11 +1008,11 @@ extern "C" { #define EFUSE_USR_DATA1_S 0 /** EFUSE_RD_USR_DATA2_REG register - * Represents rd_usr_data2 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the second 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA2 0xFFFFFFFFU #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) @@ -898,11 +1020,11 @@ extern "C" { #define EFUSE_USR_DATA2_S 0 /** EFUSE_RD_USR_DATA3_REG register - * Represents rd_usr_data3 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the third 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA3 0xFFFFFFFFU #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) @@ -910,11 +1032,11 @@ extern "C" { #define EFUSE_USR_DATA3_S 0 /** EFUSE_RD_USR_DATA4_REG register - * Represents rd_usr_data4 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the fourth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA4 0xFFFFFFFFU #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) @@ -922,11 +1044,11 @@ extern "C" { #define EFUSE_USR_DATA4_S 0 /** EFUSE_RD_USR_DATA5_REG register - * Represents rd_usr_data5 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the fifth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA5 0xFFFFFFFFU #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) @@ -934,35 +1056,49 @@ extern "C" { #define EFUSE_USR_DATA5_S 0 /** EFUSE_RD_USR_DATA6_REG register - * Represents rd_usr_data6 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register - * Represents rd_usr_data7 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register - * Represents rd_key0_data0 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the zeroth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA0 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) @@ -970,11 +1106,11 @@ extern "C" { #define EFUSE_KEY0_DATA0_S 0 /** EFUSE_RD_KEY0_DATA1_REG register - * Represents rd_key0_data1 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the first 32 bits of KEY0. */ #define EFUSE_KEY0_DATA1 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) @@ -982,11 +1118,11 @@ extern "C" { #define EFUSE_KEY0_DATA1_S 0 /** EFUSE_RD_KEY0_DATA2_REG register - * Represents rd_key0_data2 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the second 32 bits of KEY0. */ #define EFUSE_KEY0_DATA2 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) @@ -994,11 +1130,11 @@ extern "C" { #define EFUSE_KEY0_DATA2_S 0 /** EFUSE_RD_KEY0_DATA3_REG register - * Represents rd_key0_data3 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the third 32 bits of KEY0. */ #define EFUSE_KEY0_DATA3 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) @@ -1006,11 +1142,11 @@ extern "C" { #define EFUSE_KEY0_DATA3_S 0 /** EFUSE_RD_KEY0_DATA4_REG register - * Represents rd_key0_data4 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the fourth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA4 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) @@ -1018,11 +1154,11 @@ extern "C" { #define EFUSE_KEY0_DATA4_S 0 /** EFUSE_RD_KEY0_DATA5_REG register - * Represents rd_key0_data5 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the fifth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA5 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) @@ -1030,11 +1166,11 @@ extern "C" { #define EFUSE_KEY0_DATA5_S 0 /** EFUSE_RD_KEY0_DATA6_REG register - * Represents rd_key0_data6 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the sixth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA6 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) @@ -1042,11 +1178,11 @@ extern "C" { #define EFUSE_KEY0_DATA6_S 0 /** EFUSE_RD_KEY0_DATA7_REG register - * Represents rd_key0_data7 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the seventh 32 bits of KEY0. */ #define EFUSE_KEY0_DATA7 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) @@ -1054,11 +1190,11 @@ extern "C" { #define EFUSE_KEY0_DATA7_S 0 /** EFUSE_RD_KEY1_DATA0_REG register - * Represents rd_key1_data0 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the zeroth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA0 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) @@ -1066,11 +1202,11 @@ extern "C" { #define EFUSE_KEY1_DATA0_S 0 /** EFUSE_RD_KEY1_DATA1_REG register - * Represents rd_key1_data1 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the first 32 bits of KEY1. */ #define EFUSE_KEY1_DATA1 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) @@ -1078,11 +1214,11 @@ extern "C" { #define EFUSE_KEY1_DATA1_S 0 /** EFUSE_RD_KEY1_DATA2_REG register - * Represents rd_key1_data2 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the second 32 bits of KEY1. */ #define EFUSE_KEY1_DATA2 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) @@ -1090,11 +1226,11 @@ extern "C" { #define EFUSE_KEY1_DATA2_S 0 /** EFUSE_RD_KEY1_DATA3_REG register - * Represents rd_key1_data3 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the third 32 bits of KEY1. */ #define EFUSE_KEY1_DATA3 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) @@ -1102,11 +1238,11 @@ extern "C" { #define EFUSE_KEY1_DATA3_S 0 /** EFUSE_RD_KEY1_DATA4_REG register - * Represents rd_key1_data4 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the fourth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA4 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) @@ -1114,11 +1250,11 @@ extern "C" { #define EFUSE_KEY1_DATA4_S 0 /** EFUSE_RD_KEY1_DATA5_REG register - * Represents rd_key1_data5 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the fifth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA5 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) @@ -1126,11 +1262,11 @@ extern "C" { #define EFUSE_KEY1_DATA5_S 0 /** EFUSE_RD_KEY1_DATA6_REG register - * Represents rd_key1_data6 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the sixth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA6 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) @@ -1138,11 +1274,11 @@ extern "C" { #define EFUSE_KEY1_DATA6_S 0 /** EFUSE_RD_KEY1_DATA7_REG register - * Represents rd_key1_data7 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the seventh 32 bits of KEY1. */ #define EFUSE_KEY1_DATA7 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) @@ -1150,11 +1286,11 @@ extern "C" { #define EFUSE_KEY1_DATA7_S 0 /** EFUSE_RD_KEY2_DATA0_REG register - * Represents rd_key2_data0 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the zeroth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA0 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) @@ -1162,11 +1298,11 @@ extern "C" { #define EFUSE_KEY2_DATA0_S 0 /** EFUSE_RD_KEY2_DATA1_REG register - * Represents rd_key2_data1 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the first 32 bits of KEY2. */ #define EFUSE_KEY2_DATA1 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) @@ -1174,11 +1310,11 @@ extern "C" { #define EFUSE_KEY2_DATA1_S 0 /** EFUSE_RD_KEY2_DATA2_REG register - * Represents rd_key2_data2 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the second 32 bits of KEY2. */ #define EFUSE_KEY2_DATA2 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) @@ -1186,11 +1322,11 @@ extern "C" { #define EFUSE_KEY2_DATA2_S 0 /** EFUSE_RD_KEY2_DATA3_REG register - * Represents rd_key2_data3 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the third 32 bits of KEY2. */ #define EFUSE_KEY2_DATA3 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) @@ -1198,11 +1334,11 @@ extern "C" { #define EFUSE_KEY2_DATA3_S 0 /** EFUSE_RD_KEY2_DATA4_REG register - * Represents rd_key2_data4 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the fourth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA4 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) @@ -1210,11 +1346,11 @@ extern "C" { #define EFUSE_KEY2_DATA4_S 0 /** EFUSE_RD_KEY2_DATA5_REG register - * Represents rd_key2_data5 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the fifth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA5 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) @@ -1222,11 +1358,11 @@ extern "C" { #define EFUSE_KEY2_DATA5_S 0 /** EFUSE_RD_KEY2_DATA6_REG register - * Represents rd_key2_data6 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the sixth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA6 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) @@ -1234,11 +1370,11 @@ extern "C" { #define EFUSE_KEY2_DATA6_S 0 /** EFUSE_RD_KEY2_DATA7_REG register - * Represents rd_key2_data7 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the seventh 32 bits of KEY2. */ #define EFUSE_KEY2_DATA7 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) @@ -1246,11 +1382,11 @@ extern "C" { #define EFUSE_KEY2_DATA7_S 0 /** EFUSE_RD_KEY3_DATA0_REG register - * Represents rd_key3_data0 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the zeroth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA0 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) @@ -1258,11 +1394,11 @@ extern "C" { #define EFUSE_KEY3_DATA0_S 0 /** EFUSE_RD_KEY3_DATA1_REG register - * Represents rd_key3_data1 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the first 32 bits of KEY3. */ #define EFUSE_KEY3_DATA1 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) @@ -1270,11 +1406,11 @@ extern "C" { #define EFUSE_KEY3_DATA1_S 0 /** EFUSE_RD_KEY3_DATA2_REG register - * Represents rd_key3_data2 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the second 32 bits of KEY3. */ #define EFUSE_KEY3_DATA2 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) @@ -1282,11 +1418,11 @@ extern "C" { #define EFUSE_KEY3_DATA2_S 0 /** EFUSE_RD_KEY3_DATA3_REG register - * Represents rd_key3_data3 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the third 32 bits of KEY3. */ #define EFUSE_KEY3_DATA3 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) @@ -1294,11 +1430,11 @@ extern "C" { #define EFUSE_KEY3_DATA3_S 0 /** EFUSE_RD_KEY3_DATA4_REG register - * Represents rd_key3_data4 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the fourth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA4 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) @@ -1306,11 +1442,11 @@ extern "C" { #define EFUSE_KEY3_DATA4_S 0 /** EFUSE_RD_KEY3_DATA5_REG register - * Represents rd_key3_data5 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the fifth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA5 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) @@ -1318,11 +1454,11 @@ extern "C" { #define EFUSE_KEY3_DATA5_S 0 /** EFUSE_RD_KEY3_DATA6_REG register - * Represents rd_key3_data6 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the sixth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA6 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) @@ -1330,11 +1466,11 @@ extern "C" { #define EFUSE_KEY3_DATA6_S 0 /** EFUSE_RD_KEY3_DATA7_REG register - * Represents rd_key3_data7 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the seventh 32 bits of KEY3. */ #define EFUSE_KEY3_DATA7 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) @@ -1342,11 +1478,11 @@ extern "C" { #define EFUSE_KEY3_DATA7_S 0 /** EFUSE_RD_KEY4_DATA0_REG register - * Represents rd_key4_data0 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the zeroth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA0 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) @@ -1354,11 +1490,11 @@ extern "C" { #define EFUSE_KEY4_DATA0_S 0 /** EFUSE_RD_KEY4_DATA1_REG register - * Represents rd_key4_data1 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the first 32 bits of KEY4. */ #define EFUSE_KEY4_DATA1 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) @@ -1366,11 +1502,11 @@ extern "C" { #define EFUSE_KEY4_DATA1_S 0 /** EFUSE_RD_KEY4_DATA2_REG register - * Represents rd_key4_data2 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the second 32 bits of KEY4. */ #define EFUSE_KEY4_DATA2 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) @@ -1378,11 +1514,11 @@ extern "C" { #define EFUSE_KEY4_DATA2_S 0 /** EFUSE_RD_KEY4_DATA3_REG register - * Represents rd_key4_data3 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the third 32 bits of KEY4. */ #define EFUSE_KEY4_DATA3 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) @@ -1390,11 +1526,11 @@ extern "C" { #define EFUSE_KEY4_DATA3_S 0 /** EFUSE_RD_KEY4_DATA4_REG register - * Represents rd_key4_data4 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the fourth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA4 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) @@ -1402,11 +1538,11 @@ extern "C" { #define EFUSE_KEY4_DATA4_S 0 /** EFUSE_RD_KEY4_DATA5_REG register - * Represents rd_key4_data5 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the fifth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA5 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) @@ -1414,11 +1550,11 @@ extern "C" { #define EFUSE_KEY4_DATA5_S 0 /** EFUSE_RD_KEY4_DATA6_REG register - * Represents rd_key4_data6 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the sixth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA6 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) @@ -1426,11 +1562,11 @@ extern "C" { #define EFUSE_KEY4_DATA6_S 0 /** EFUSE_RD_KEY4_DATA7_REG register - * Represents rd_key4_data7 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the seventh 32 bits of KEY4. */ #define EFUSE_KEY4_DATA7 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) @@ -1438,11 +1574,11 @@ extern "C" { #define EFUSE_KEY4_DATA7_S 0 /** EFUSE_RD_KEY5_DATA0_REG register - * Represents rd_key5_data0 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the zeroth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA0 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) @@ -1450,11 +1586,11 @@ extern "C" { #define EFUSE_KEY5_DATA0_S 0 /** EFUSE_RD_KEY5_DATA1_REG register - * Represents rd_key5_data1 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the first 32 bits of KEY5. */ #define EFUSE_KEY5_DATA1 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) @@ -1462,11 +1598,11 @@ extern "C" { #define EFUSE_KEY5_DATA1_S 0 /** EFUSE_RD_KEY5_DATA2_REG register - * Represents rd_key5_data2 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the second 32 bits of KEY5. */ #define EFUSE_KEY5_DATA2 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) @@ -1474,11 +1610,11 @@ extern "C" { #define EFUSE_KEY5_DATA2_S 0 /** EFUSE_RD_KEY5_DATA3_REG register - * Represents rd_key5_data3 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the third 32 bits of KEY5. */ #define EFUSE_KEY5_DATA3 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) @@ -1486,11 +1622,11 @@ extern "C" { #define EFUSE_KEY5_DATA3_S 0 /** EFUSE_RD_KEY5_DATA4_REG register - * Represents rd_key5_data4 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the fourth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA4 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) @@ -1498,11 +1634,11 @@ extern "C" { #define EFUSE_KEY5_DATA4_S 0 /** EFUSE_RD_KEY5_DATA5_REG register - * Represents rd_key5_data5 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the fifth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA5 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) @@ -1510,11 +1646,11 @@ extern "C" { #define EFUSE_KEY5_DATA5_S 0 /** EFUSE_RD_KEY5_DATA6_REG register - * Represents rd_key5_data6 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the sixth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA6 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) @@ -1522,11 +1658,11 @@ extern "C" { #define EFUSE_KEY5_DATA6_S 0 /** EFUSE_RD_KEY5_DATA7_REG register - * Represents rd_key5_data7 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the seventh 32 bits of KEY5. */ #define EFUSE_KEY5_DATA7 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) @@ -1534,11 +1670,11 @@ extern "C" { #define EFUSE_KEY5_DATA7_S 0 /** EFUSE_RD_SYS_PART2_DATA0_REG register - * Represents rd_sys_part2_data0 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) @@ -1546,11 +1682,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_0_S 0 /** EFUSE_RD_SYS_PART2_DATA1_REG register - * Represents rd_sys_part2_data1 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) @@ -1558,11 +1694,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_1_S 0 /** EFUSE_RD_SYS_PART2_DATA2_REG register - * Represents rd_sys_part2_data2 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) @@ -1570,11 +1706,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_2_S 0 /** EFUSE_RD_SYS_PART2_DATA3_REG register - * Represents rd_sys_part2_data3 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) @@ -1582,11 +1718,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_3_S 0 /** EFUSE_RD_SYS_PART2_DATA4_REG register - * Represents rd_sys_part2_data4 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -1594,11 +1730,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_4_S 0 /** EFUSE_RD_SYS_PART2_DATA5_REG register - * Represents rd_sys_part2_data5 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -1606,11 +1742,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_5_S 0 /** EFUSE_RD_SYS_PART2_DATA6_REG register - * Represents rd_sys_part2_data6 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) @@ -1618,629 +1754,600 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_6_S 0 /** EFUSE_RD_SYS_PART2_DATA7_REG register - * Represents rd_sys_part2_data7 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -/** EFUSE_RD_REPEAT_DATA_ERR0_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS + * Indicates a programming error of RD_DIS. */ #define EFUSE_RD_DIS_ERR 0x0000007FU #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_PVT_GLITCH_EN_ERR : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_EN +/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ -#define EFUSE_PVT_GLITCH_EN_ERR (BIT(7)) -#define EFUSE_PVT_GLITCH_EN_ERR_M (EFUSE_PVT_GLITCH_EN_ERR_V << EFUSE_PVT_GLITCH_EN_ERR_S) -#define EFUSE_PVT_GLITCH_EN_ERR_V 0x00000001U -#define EFUSE_PVT_GLITCH_EN_ERR_S 7 +#define EFUSE_RPT4_RESERVED0_ERR_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_ERR_4_M (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S) +#define EFUSE_RPT4_RESERVED0_ERR_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_4_S 7 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE + * Indicates a programming error of DIS_ICACHE. */ #define EFUSE_DIS_ICACHE_ERR (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U #define EFUSE_DIS_ICACHE_ERR_S 8 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG + * Indicates a programming error of DIS_USB_JTAG. */ #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 /** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN + * Indicates a programming error of POWERGLITCH_EN. */ #define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U #define EFUSE_POWERGLITCH_EN_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + * Indicates a programming error of DIS_FORCE_DOWNLOAD. */ #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI + * Indicates a programming error of DIS_CAN. */ #define EFUSE_DIS_TWAI_ERR (BIT(14)) #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) #define EFUSE_DIS_TWAI_ERR_V 0x00000001U #define EFUSE_DIS_TWAI_ERR_S 14 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + * Indicates a programming error of JTAG_SEL_ENABLE. */ #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG + * Indicates a programming error of SOFT_DIS_JTAG. */ #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG + * Indicates a programming error of DIS_PAD_JTAG. */ #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_ERR_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS + * Indicates a programming error of USB_EXCHG_PINS. */ #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_ERR_S 25 /** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + * Indicates a programming error of VDD_SPI_AS_GPIO. */ #define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) #define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/** EFUSE_ECDSA_CURVE_MODE_ERR : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_ECDSA_CURVE_MODE +/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. */ -#define EFUSE_ECDSA_CURVE_MODE_ERR 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_ERR_M (EFUSE_ECDSA_CURVE_MODE_ERR_V << EFUSE_ECDSA_CURVE_MODE_ERR_S) -#define EFUSE_ECDSA_CURVE_MODE_ERR_V 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_ERR_S 27 -/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME +#define EFUSE_RPT4_RESERVED0_ERR_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_M (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S) +#define EFUSE_RPT4_RESERVED0_ERR_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_S 27 +/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0; + * Reserved. */ -#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(29)) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 29 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [31:30]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL +#define EFUSE_RPT4_RESERVED0_ERR_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_ERR_1_M (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S) +#define EFUSE_RPT4_RESERVED0_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_1_S 29 +/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 30 +#define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) +#define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_S 30 -/** EFUSE_RD_REPEAT_DATA_ERR1_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_IO_LDO_ADJUST_ERR : RO; bitpos: [7:0]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_ADJUST +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. */ -#define EFUSE_IO_LDO_ADJUST_ERR 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_ERR_M (EFUSE_IO_LDO_ADJUST_ERR_V << EFUSE_IO_LDO_ADJUST_ERR_S) -#define EFUSE_IO_LDO_ADJUST_ERR_V 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_ERR_S 0 -/** EFUSE_VDD_SPI_LDO_ADJUST_ERR : RO; bitpos: [15:8]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST - */ -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_M (EFUSE_VDD_SPI_LDO_ADJUST_ERR_V << EFUSE_VDD_SPI_LDO_ADJUST_ERR_S) -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_V 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_S 8 +#define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) +#define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_S 0 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL + * Indicates a programming error of WDT_DELAY_SEL. */ #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 + * Indicates a programming error of KEY_PURPOSE_0. */ #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 + * Indicates a programming error of KEY_PURPOSE_1. */ #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/** EFUSE_RD_REPEAT_DATA_ERR2_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 + * Indicates a programming error of KEY_PURPOSE_2. */ #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 + * Indicates a programming error of KEY_PURPOSE_3. */ #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 + * Indicates a programming error of KEY_PURPOSE_4. */ #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 + * Indicates a programming error of KEY_PURPOSE_5. */ #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL + * Indicates a programming error of SEC_DPA_LEVEL. */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_IO_LDO_1P8_ERR : RO; bitpos: [18]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_1P8 +/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; + * Reserved. */ -#define EFUSE_IO_LDO_1P8_ERR (BIT(18)) -#define EFUSE_IO_LDO_1P8_ERR_M (EFUSE_IO_LDO_1P8_ERR_V << EFUSE_IO_LDO_1P8_ERR_S) -#define EFUSE_IO_LDO_1P8_ERR_V 0x00000001U -#define EFUSE_IO_LDO_1P8_ERR_S 18 +#define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) +#define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) +#define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED2_ERR_1_S 18 /** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE + * Indicates a programming error of CRYPT_DPA_ENABLE. */ #define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) #define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN + * Indicates a programming error of SECURE_BOOT_EN. */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_POWERGLITCH_EN1_ERR : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN1 +/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. */ -#define EFUSE_POWERGLITCH_EN1_ERR 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_ERR_M (EFUSE_POWERGLITCH_EN1_ERR_V << EFUSE_POWERGLITCH_EN1_ERR_S) -#define EFUSE_POWERGLITCH_EN1_ERR_V 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_ERR_S 22 -/** EFUSE_DCDC_CCM_EN_ERR : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_DCDC_CCM_EN - */ -#define EFUSE_DCDC_CCM_EN_ERR (BIT(27)) -#define EFUSE_DCDC_CCM_EN_ERR_M (EFUSE_DCDC_CCM_EN_ERR_V << EFUSE_DCDC_CCM_EN_ERR_S) -#define EFUSE_DCDC_CCM_EN_ERR_V 0x00000001U -#define EFUSE_DCDC_CCM_EN_ERR_S 27 +#define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) +#define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_S 22 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW + * Indicates a programming error of FLASH_TPUW. */ #define EFUSE_FLASH_TPUW_ERR 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_S 28 -/** EFUSE_RD_REPEAT_DATA_ERR3_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + * Indicates a programming error of DIS_DOWNLOAD_MODE. */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + * Indicates a programming error of DIS_DIRECT_BOOT. */ #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +#define EFUSE_USB_PRINT_ERR (BIT(2)) +#define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) +#define EFUSE_USB_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_PRINT_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) +#define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_5_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL + * Indicates a programming error of UART_PRINT_CONTROL. */ #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME + * Indicates a programming error of FORCE_SEND_RESUME. */ #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION + * Indicates a programming error of SECURE VERSION. */ #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 /** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD0 + * Indicates a programming error of HYS_EN_PAD0. */ #define EFUSE_HYS_EN_PAD0_ERR 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_M (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S) #define EFUSE_HYS_EN_PAD0_ERR_V 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_S 26 -/** EFUSE_RD_REPEAT_DATA_ERR4_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD1 + * Indicates a programming error of HYS_EN_PAD1. */ #define EFUSE_HYS_EN_PAD1_ERR 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_M (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S) #define EFUSE_HYS_EN_PAD1_ERR_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_S 0 -/** EFUSE_FLASH_LDO_POWER_SEL_ERR : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL +/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ -#define EFUSE_FLASH_LDO_POWER_SEL_ERR (BIT(22)) -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_M (EFUSE_FLASH_LDO_POWER_SEL_ERR_V << EFUSE_FLASH_LDO_POWER_SEL_ERR_S) -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_V 0x00000001U -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_S 22 +#define EFUSE_RPT4_RESERVED4_ERR_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) +#define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_S 22 +/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) +#define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_S 24 -/** EFUSE_RD_RS_DATA_ERR0_REG register - * Represents rd_rs_data_err +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. */ -#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) -/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) -#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ -#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) -#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_RD_MAC_SYS_FAIL_S 3 -/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ -#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 -/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) -#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 -/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. */ -#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) -#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) -#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_USR_DATA_FAIL_S 11 -/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 -/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) -#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) -#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY0_DATA_FAIL_S 15 -/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 -/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) -#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) -#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY1_DATA_FAIL_S 19 -/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 -/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) -#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) -#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY2_DATA_FAIL_S 23 -/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 -/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) -#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) -#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY3_DATA_FAIL_S 27 -/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 -/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) -#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) -#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY4_DATA_FAIL_S 31 +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -/** EFUSE_RD_RS_DATA_ERR1_REG register - * Represents rd_rs_data_err +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. */ -#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) -/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 -/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. */ -#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) -#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) -#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY5_DATA_FAIL_S 3 -/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. */ -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ -#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 - -/** EFUSE_DATE_REG register - * eFuse version register. - */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37814560; - * Represents eFuse version. Date:2024-10-12 12:09:57, - * ScriptRev:892332a1019d3a17987b08c6835edce28f46e261 - */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 /** EFUSE_CLK_REG register * eFuse clcok configuration register. */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into power-saving mode. */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Set this bit and force to activate clock signal of eFuse SRAM. */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into working mode. */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Set this bit to force enable eFuse register configuration clock signal. */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2252,91 +2359,109 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * 0x5A5A: programming operation command 0x5AA5: read operation command. */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) #define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_L_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key low part output. +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. */ -#define EFUSE_CFG_ECDSA_L_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_L_BLK_M (EFUSE_CFG_ECDSA_L_BLK_V << EFUSE_CFG_ECDSA_L_BLK_S) -#define EFUSE_CFG_ECDSA_L_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_L_BLK_S 16 -/** EFUSE_CFG_ECDSA_H_BLK : R/W; bitpos: [23:20]; default: 0; - * Configures which block to use for ECDSA key high part output. - */ -#define EFUSE_CFG_ECDSA_H_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_H_BLK_M (EFUSE_CFG_ECDSA_H_BLK_V << EFUSE_CFG_ECDSA_H_BLK_S) -#define EFUSE_CFG_ECDSA_H_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_H_BLK_S 20 +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 /** EFUSE_STATUS_REG register * eFuse status register. */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Indicates the state of the eFuse state machine. */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. + * Indicates the number of block valid bit. */ #define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_L_BLK : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA key low part output. +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. */ -#define EFUSE_CUR_ECDSA_L_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_L_BLK_M (EFUSE_CUR_ECDSA_L_BLK_V << EFUSE_CUR_ECDSA_L_BLK_S) -#define EFUSE_CUR_ECDSA_L_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_L_BLK_S 20 -/** EFUSE_CUR_ECDSA_H_BLK : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA key high part output. - */ -#define EFUSE_CUR_ECDSA_H_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_H_BLK_M (EFUSE_CUR_ECDSA_H_BLK_V << EFUSE_CUR_ECDSA_H_BLK_S) -#define EFUSE_CUR_ECDSA_H_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_H_BLK_S 24 +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 /** EFUSE_CMD_REG register * eFuse command register. */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Set this bit to send read command. */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Set this bit to send programming command. */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) #define EFUSE_PGM_CMD_V 0x00000001U #define EFUSE_PGM_CMD_S 1 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. */ #define EFUSE_BLK_NUM 0x0000000FU #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) @@ -2348,14 +2473,14 @@ extern "C" { */ #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. + * The raw bit signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 /** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. + * The raw bit signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) @@ -2367,14 +2492,14 @@ extern "C" { */ #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. + * The status signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) #define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. + * The status signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) @@ -2386,14 +2511,14 @@ extern "C" { */ #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. + * The enable signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. + * The enable signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) @@ -2405,14 +2530,14 @@ extern "C" { */ #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. + * The clear signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. + * The clear signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) @@ -2423,8 +2548,8 @@ extern "C" { * Controls the eFuse programming voltage. */ #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. */ #define EFUSE_DAC_CLK_DIV 0x000000FFU #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) @@ -2438,17 +2563,14 @@ extern "C" { #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U #define EFUSE_DAC_CLK_PAD_SEL_S 8 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. + * Controls the rising period of the programming voltage. */ #define EFUSE_DAC_NUM 0x000000FFU #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Reduces the power supply of the programming voltage. */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2460,29 +2582,28 @@ extern "C" { */ #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read hold time. */ #define EFUSE_THR_A 0x000000FFU #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) #define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read time. */ #define EFUSE_TRD 0x000000FFU #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) #define EFUSE_TRD_V 0x000000FFU #define EFUSE_TRD_S 8 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read setup time. */ #define EFUSE_TSUR_A 0x000000FFU #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) #define EFUSE_TSUR_A_V 0x000000FFU #define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. */ #define EFUSE_READ_INIT_NUM 0x000000FFU #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) @@ -2494,24 +2615,21 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the programming setup time. */ #define EFUSE_TSUP_A 0x000000FFU #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) #define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power up time for VDDQ. */ #define EFUSE_PWR_ON_NUM 0x0000FFFFU #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 /** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. + * Configures the programming hold time. */ #define EFUSE_THP_A 0x000000FFU #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) @@ -2523,16 +2641,14 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power outage time for VDDQ. */ #define EFUSE_PWR_OFF_NUM 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 /** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the active programming time. */ #define EFUSE_TPGM 0x0000FFFFU #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) @@ -2545,39 +2661,46 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Set this bit to bypass reed solomon correction step. */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) #define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U #define EFUSE_BYPASS_RS_CORRECTION_S 0 /** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. + * Configures block number of programming twice operation. */ #define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Set this bit to update multi-bit register signals. */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) #define EFUSE_UPDATE_V 0x00000001U #define EFUSE_UPDATE_S 12 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the inactive programming time. */ #define EFUSE_TPGM_INACTIVE 0x000000FFU #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) #define EFUSE_TPGM_INACTIVE_V 0x000000FFU #define EFUSE_TPGM_INACTIVE_S 13 +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h21/register/soc/efuse_struct.h b/components/soc/esp32h21/register/soc/efuse_struct.h index 477270f821..ab4c17e475 100644 --- a/components/soc/esp32h21/register/soc/efuse_struct.h +++ b/components/soc/esp32h21/register/soc/efuse_struct.h @@ -10,45 +10,160 @@ extern "C" { #endif -/** Group: program_data registers */ -/** Type of pgm_datan register - * Represents pgm_datan +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. */ typedef union { struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. */ - uint32_t pgm_data_n:32; + uint32_t pgm_data_0:32; }; uint32_t val; -} efuse_pgm_datan_reg_t; +} efuse_pgm_data0_reg_t; -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. */ typedef union { struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. */ - uint32_t pgm_rs_data_n:32; + uint32_t pgm_data_1:32; }; uint32_t val; -} efuse_pgm_check_valuen_reg_t; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; -/** Group: block0 registers */ +/** Group: Read Data Register */ /** Type of rd_wr_dis register - * Represents rd_wr_dis + * BLOCK0 data register 0. */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: Disabled. 0 Enabled. */ uint32_t wr_dis:32; }; @@ -56,175 +171,143 @@ typedef union { } efuse_rd_wr_dis_reg_t; /** Type of rd_repeat_data0 register - * Represents rd_repeat_data + * BLOCK0 data register 1. */ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: disabled. 0: enabled. */ uint32_t rd_dis:7; - /** pvt_glitch_en : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable + /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ - uint32_t pvt_glitch_en:1; + uint32_t rpt4_reserved0_4:1; /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. */ uint32_t dis_usb_jtag:1; /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. */ uint32_t powerglitch_en:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. */ uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:4; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. */ uint32_t vdd_spi_as_gpio:1; - /** ecdsa_curve_mode : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 + /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. */ - uint32_t ecdsa_curve_mode:2; - /** ecc_force_const_time : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled + uint32_t rpt4_reserved0_2:2; + /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0; + * Reserved. */ - uint32_t ecc_force_const_time:1; - /** xts_dpa_pseudo_level : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. + uint32_t rpt4_reserved0_1:1; + /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. */ - uint32_t xts_dpa_pseudo_level:2; + uint32_t rpt4_reserved0_0:2; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; /** Type of rd_repeat_data1 register - * Represents rd_repeat_data + * BLOCK0 data register 2. */ typedef union { struct { - /** io_ldo_adjust : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. + /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. */ - uint32_t io_ldo_adjust:8; - /** vdd_spi_ldo_adjust : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. - */ - uint32_t vdd_spi_ldo_adjust:8; + uint32_t rpt4_reserved1_1:16; /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ uint32_t secure_boot_key_revoke2:1; /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + * Represents the purpose of Key0. */ uint32_t key_purpose_0:4; /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. + * Represents the purpose of Key1. */ uint32_t key_purpose_1:4; }; @@ -232,73 +315,56 @@ typedef union { } efuse_rd_repeat_data1_reg_t; /** Type of rd_repeat_data2 register - * Represents rd_repeat_data + * BLOCK0 data register 3. */ typedef union { struct { /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. + * Represents the purpose of Key2. */ uint32_t key_purpose_2:4; /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. + * Represents the purpose of Key3. */ uint32_t key_purpose_3:4; /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. + * Represents the purpose of Key4. */ uint32_t key_purpose_4:4; /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. + * Represents the purpose of Key5. */ uint32_t key_purpose_5:4; /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. + * Represents the spa secure level by configuring the clock random divide mode. */ uint32_t sec_dpa_level:2; - /** io_ldo_1p8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V + /** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. */ - uint32_t io_ldo_1p8:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled + uint32_t ecdsa_force_use_hardware_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. */ uint32_t crypt_dpa_enable:1; /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. */ uint32_t secure_boot_aggressive_revoke:1; - /** powerglitch_en1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. + /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. */ - uint32_t powerglitch_en1:5; - /** dcdc_ccm_en : RO; bitpos: [27]; default: 0; - * Represents whether change DCDC to CCM mode. - */ - uint32_t dcdc_ccm_en:1; + uint32_t rpt4_reserved2_0:6; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. */ uint32_t flash_tpuw:4; }; @@ -306,71 +372,58 @@ typedef union { } efuse_rd_repeat_data2_reg_t; /** Type of rd_repeat_data3 register - * Represents rd_repeat_data + * BLOCK0 data register 4. */ typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled + * Set this bit to disable USB-Serial-JTAG print during rom boot. */ uint32_t dis_usb_serial_jtag_rom_print:1; - uint32_t reserved_3:1; + /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_5:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only UART is supported for - * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. */ uint32_t force_send_resume:1; /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. + * Represents the version used by ESP-IDF anti-rollback feature. */ uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD0~5 */ uint32_t hys_en_pad0:6; }; @@ -378,719 +431,1574 @@ typedef union { } efuse_rd_repeat_data3_reg_t; /** Type of rd_repeat_data4 register - * Represents rd_repeat_data + * BLOCK0 data register 5. */ typedef union { struct { /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD6~27 */ uint32_t hys_en_pad1:22; - /** flash_ldo_power_sel : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. + /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ - uint32_t flash_ldo_power_sel:1; - uint32_t reserved_23:9; + uint32_t rpt4_reserved4_1:2; + /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_0:8; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; - -/** Group: block1 registers */ -/** Type of rd_mac_sys0 register - * Represents rd_mac_sys +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. */ typedef union { struct { /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. + * Stores the low 32 bits of MAC address. */ uint32_t mac_0:32; }; uint32_t val; -} efuse_rd_mac_sys0_reg_t; +} efuse_rd_mac_sys_0_reg_t; -/** Type of rd_mac_sys1 register - * Represents rd_mac_sys +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. */ typedef union { struct { /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. + * Stores the high 16 bits of MAC address. */ uint32_t mac_1:16; /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. + * Stores the extended bits of MAC address. */ uint32_t mac_ext:16; }; uint32_t val; -} efuse_rd_mac_sys1_reg_t; +} efuse_rd_mac_sys_1_reg_t; -/** Type of rd_mac_sys2 register - * Represents rd_mac_sys +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. */ typedef union { struct { - /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; + /** rxiq_version : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. + */ + uint32_t rxiq_version:3; + /** rxiq_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. + */ + uint32_t rxiq_0:7; + /** rxiq_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. + */ + uint32_t rxiq_1:7; + /** active_hp_dbias : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. + */ + uint32_t active_hp_dbias:5; + /** active_lp_dbias : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ + uint32_t active_lp_dbias:5; + /** dslp_dbias : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ + uint32_t dslp_dbias:4; + /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value1:1; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value2:3; + /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_sign:1; + /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0; * Reserved. */ - uint32_t mac_reserved_0:14; - /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. + uint32_t mac_reserved_2:14; + /** wafer_version_minor : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. */ - uint32_t mac_reserved_1:18; + uint32_t wafer_version_minor:3; + /** wafer_version_major : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. + */ + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. + */ + uint32_t disable_wafer_version_major:1; + /** flash_cap : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. + */ + uint32_t flash_cap:3; + /** flash_temp : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ + uint32_t flash_temp:2; + /** flash_vendor : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ + uint32_t flash_vendor:3; }; uint32_t val; -} efuse_rd_mac_sys2_reg_t; +} efuse_rd_mac_sys_3_reg_t; -/** Type of rd_mac_sys3 register - * Represents rd_mac_sys +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [3:0]; default: 0; - * Reserved. + /** pkg_version : R; bitpos: [2:0]; default: 0; + * Package version */ - uint32_t mac_reserved_2:4; - /** pvt_cell_select : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. + uint32_t pkg_version:3; + /** reserved_1_131 : R; bitpos: [31:3]; default: 0; + * reserved */ - uint32_t pvt_cell_select:7; - /** mac_reserved_3 : RO; bitpos: [17:11]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_3:7; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; + uint32_t reserved_1_131:29; }; uint32_t val; -} efuse_rd_mac_sys3_reg_t; +} efuse_rd_mac_sys_4_reg_t; -/** Type of rd_mac_sys4 register - * Represents rd_mac_sys +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. */ typedef union { struct { - uint32_t reserved_0:5; - /** pvt_limit : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. */ - uint32_t pvt_limit:16; - /** pvt_glitch_charge_reset : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset - */ - uint32_t pvt_glitch_charge_reset:1; - /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. - */ - uint32_t pvt_glitch_mode:2; - /** pvt_pump_limit : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. - */ - uint32_t pvt_pump_limit:8; + uint32_t sys_data_part0_2:32; }; uint32_t val; -} efuse_rd_mac_sys4_reg_t; +} efuse_rd_mac_sys_5_reg_t; -/** Type of rd_mac_sys5 register - * Represents rd_mac_sys +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** pump_drv : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t pump_drv:4; - /** sys_data_part0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_2:28; + uint32_t optional_unique_id:32; }; uint32_t val; -} efuse_rd_mac_sys5_reg_t; +} efuse_rd_sys_part1_data0_reg_t; - -/** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_n:32; + uint32_t optional_unique_id_1:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data1_reg_t; - -/** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t usr_datan:32; + uint32_t optional_unique_id_2:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_sys_part1_data2_reg_t; - -/** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t key0_datan:32; + uint32_t optional_unique_id_3:32; }; uint32_t val; -} efuse_rd_key0_datan_reg_t; +} efuse_rd_sys_part1_data3_reg_t; - -/** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + /** reserved_2_128 : R; bitpos: [1:0]; default: 0; + * reserved */ - uint32_t key1_datan:32; + uint32_t reserved_2_128:2; + /** blk_version_minor : R; bitpos: [4:2]; default: 0; + * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [6:5]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** disable_blk_version_major : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** temp_calib : R; bitpos: [16:8]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten0:10; + /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten1:5; }; uint32_t val; -} efuse_rd_key1_datan_reg_t; +} efuse_rd_sys_part1_data4_reg_t; - -/** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; + * ADC1 calibration data */ - uint32_t key2_datan:32; + uint32_t adc1_ave_initcode_atten1_1:5; + /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten2:10; + /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten3:10; + /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten0:7; }; uint32_t val; -} efuse_rd_key2_datan_reg_t; +} efuse_rd_sys_part1_data5_reg_t; - -/** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration data */ - uint32_t key3_datan:32; + uint32_t adc1_hi_dout_atten0_1:3; + /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten1:10; + /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten2:10; + /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten3:9; }; uint32_t val; -} efuse_rd_key3_datan_reg_t; +} efuse_rd_sys_part1_data6_reg_t; - -/** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). */ typedef union { struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration data */ - uint32_t key4_datan:32; + uint32_t adc1_hi_dout_atten3_1:1; + /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch0_atten0_initcode_diff:4; + /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch1_atten0_initcode_diff:4; + /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch2_atten0_initcode_diff:4; + /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch3_atten0_initcode_diff:4; + /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch4_atten0_initcode_diff:4; + /** reserved_2_245 : R; bitpos: [31:21]; default: 0; + * reserved + */ + uint32_t reserved_2_245:11; }; uint32_t val; -} efuse_rd_key4_datan_reg_t; +} efuse_rd_sys_part1_data7_reg_t; - -/** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). */ typedef union { struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). */ - uint32_t key5_datan:32; + uint32_t usr_data0:32; }; uint32_t val; -} efuse_rd_key5_datan_reg_t; +} efuse_rd_usr_data0_reg_t; - -/** Group: block10 registers */ -/** Type of rd_sys_part2_datan register - * Represents rd_sys_part2_datan +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). */ typedef union { struct { - /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). */ - uint32_t sys_data_part2_n:32; + uint32_t usr_data1:32; }; uint32_t val; -} efuse_rd_sys_part2_datan_reg_t; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; -/** Group: block0 error report registers */ -/** Type of rd_repeat_data_err0 register - * Represents rd_repeat_data_err +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. */ typedef union { struct { /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS + * Indicates a programming error of RD_DIS. */ uint32_t rd_dis_err:7; - /** pvt_glitch_en_err : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_EN + /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ - uint32_t pvt_glitch_en_err:1; + uint32_t rpt4_reserved0_err_4:1; /** dis_icache_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE + * Indicates a programming error of DIS_ICACHE. */ uint32_t dis_icache_err:1; /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG + * Indicates a programming error of DIS_USB_JTAG. */ uint32_t dis_usb_jtag_err:1; /** powerglitch_en_err : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN + * Indicates a programming error of POWERGLITCH_EN. */ uint32_t powerglitch_en_err:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ + uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + * Indicates a programming error of DIS_FORCE_DOWNLOAD. */ uint32_t dis_force_download_err:1; /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ uint32_t spi_download_mspi_dis_err:1; /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI + * Indicates a programming error of DIS_CAN. */ uint32_t dis_twai_err:1; /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + * Indicates a programming error of JTAG_SEL_ENABLE. */ uint32_t jtag_sel_enable_err:1; /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG + * Indicates a programming error of SOFT_DIS_JTAG. */ uint32_t soft_dis_jtag_err:3; /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG + * Indicates a programming error of DIS_PAD_JTAG. */ uint32_t dis_pad_jtag_err:1; /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:4; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ + uint32_t usb_drefl_err:2; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS + * Indicates a programming error of USB_EXCHG_PINS. */ uint32_t usb_exchg_pins_err:1; /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + * Indicates a programming error of VDD_SPI_AS_GPIO. */ uint32_t vdd_spi_as_gpio_err:1; - /** ecdsa_curve_mode_err : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_ECDSA_CURVE_MODE + /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. */ - uint32_t ecdsa_curve_mode_err:2; - /** ecc_force_const_time_err : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + uint32_t rpt4_reserved0_err_2:2; + /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; + * Reserved. */ - uint32_t ecc_force_const_time_err:1; - /** xts_dpa_pseudo_level_err : RO; bitpos: [31:30]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + uint32_t rpt4_reserved0_err_1:1; + /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. */ - uint32_t xts_dpa_pseudo_level_err:2; + uint32_t rpt4_reserved0_err_0:2; }; uint32_t val; -} efuse_rd_repeat_data_err0_reg_t; +} efuse_rd_repeat_err0_reg_t; -/** Type of rd_repeat_data_err1 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. */ typedef union { struct { - /** io_ldo_adjust_err : RO; bitpos: [7:0]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_ADJUST + /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. */ - uint32_t io_ldo_adjust_err:8; - /** vdd_spi_ldo_adjust_err : RO; bitpos: [15:8]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST - */ - uint32_t vdd_spi_ldo_adjust_err:8; + uint32_t rpt4_reserved1_err_0:16; /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL + * Indicates a programming error of WDT_DELAY_SEL. */ uint32_t wdt_delay_sel_err:2; /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ uint32_t spi_boot_crypt_cnt_err:3; /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ uint32_t secure_boot_key_revoke0_err:1; /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ uint32_t secure_boot_key_revoke1_err:1; /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ uint32_t secure_boot_key_revoke2_err:1; /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 + * Indicates a programming error of KEY_PURPOSE_0. */ uint32_t key_purpose_0_err:4; /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 + * Indicates a programming error of KEY_PURPOSE_1. */ uint32_t key_purpose_1_err:4; }; uint32_t val; -} efuse_rd_repeat_data_err1_reg_t; +} efuse_rd_repeat_err1_reg_t; -/** Type of rd_repeat_data_err2 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. */ typedef union { struct { /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 + * Indicates a programming error of KEY_PURPOSE_2. */ uint32_t key_purpose_2_err:4; /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 + * Indicates a programming error of KEY_PURPOSE_3. */ uint32_t key_purpose_3_err:4; /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 + * Indicates a programming error of KEY_PURPOSE_4. */ uint32_t key_purpose_4_err:4; /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 + * Indicates a programming error of KEY_PURPOSE_5. */ uint32_t key_purpose_5_err:4; /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL + * Indicates a programming error of SEC_DPA_LEVEL. */ uint32_t sec_dpa_level_err:2; - /** io_ldo_1p8_err : RO; bitpos: [18]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_1P8 + /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; + * Reserved. */ - uint32_t io_ldo_1p8_err:1; + uint32_t rpt4_reserved2_err_1:1; /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE + * Indicates a programming error of CRYPT_DPA_ENABLE. */ uint32_t crypt_dpa_enable_err:1; /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN + * Indicates a programming error of SECURE_BOOT_EN. */ uint32_t secure_boot_en_err:1; /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ uint32_t secure_boot_aggressive_revoke_err:1; - /** powerglitch_en1_err : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN1 + /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. */ - uint32_t powerglitch_en1_err:5; - /** dcdc_ccm_en_err : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_DCDC_CCM_EN - */ - uint32_t dcdc_ccm_en_err:1; + uint32_t rpt4_reserved2_err_0:6; /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW + * Indicates a programming error of FLASH_TPUW. */ uint32_t flash_tpuw_err:4; }; uint32_t val; -} efuse_rd_repeat_data_err2_reg_t; +} efuse_rd_repeat_err2_reg_t; -/** Type of rd_repeat_data_err3 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. */ typedef union { struct { /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + * Indicates a programming error of DIS_DOWNLOAD_MODE. */ uint32_t dis_download_mode_err:1; /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + * Indicates a programming error of DIS_DIRECT_BOOT. */ uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + /** usb_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - uint32_t reserved_3:1; + uint32_t usb_print_err:1; + /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_5:1; /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ uint32_t dis_usb_serial_jtag_download_mode_err:1; /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ uint32_t enable_security_download_err:1; /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL + * Indicates a programming error of UART_PRINT_CONTROL. */ uint32_t uart_print_control_err:2; /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME + * Indicates a programming error of FORCE_SEND_RESUME. */ uint32_t force_send_resume_err:1; /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION + * Indicates a programming error of SECURE VERSION. */ uint32_t secure_version_err:16; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ uint32_t secure_boot_disable_fast_wake_err:1; /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD0 + * Indicates a programming error of HYS_EN_PAD0. */ uint32_t hys_en_pad0_err:6; }; uint32_t val; -} efuse_rd_repeat_data_err3_reg_t; +} efuse_rd_repeat_err3_reg_t; -/** Type of rd_repeat_data_err4 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. */ typedef union { struct { /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD1 + * Indicates a programming error of HYS_EN_PAD1. */ uint32_t hys_en_pad1_err:22; - /** flash_ldo_power_sel_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL + /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ - uint32_t flash_ldo_power_sel_err:1; - uint32_t reserved_23:9; + uint32_t rpt4_reserved4_err_1:2; + /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err_0:8; }; uint32_t val; -} efuse_rd_repeat_data_err4_reg_t; +} efuse_rd_repeat_err4_reg_t; - -/** Group: RS block error report registers */ -/** Type of rd_rs_data_err0 register - * Represents rd_rs_data_err +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. */ typedef union { struct { - /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_mac_sys_err_num:3; - /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ - uint32_t rd_mac_sys_fail:1; - /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_sys_part1_data_err_num:3; - /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ - uint32_t rd_sys_part1_data_fail:1; - /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_usr_data_err_num:3; - /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. */ - uint32_t rd_usr_data_fail:1; - /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key0_data_err_num:3; - /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. */ - uint32_t rd_key0_data_fail:1; - /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key1_data_err_num:3; - /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. */ - uint32_t rd_key1_data_fail:1; - /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key2_data_err_num:3; - /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. */ - uint32_t rd_key2_data_fail:1; - /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key3_data_err_num:3; - /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. */ - uint32_t rd_key3_data_fail:1; - /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key4_data_err_num:3; - /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. */ - uint32_t rd_key4_data_fail:1; + uint32_t key4_fail:1; }; uint32_t val; -} efuse_rd_rs_data_err0_reg_t; +} efuse_rd_rs_err0_reg_t; -/** Type of rd_rs_data_err1 register - * Represents rd_rs_data_err +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. */ typedef union { struct { - /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_key5_data_err_num:3; - /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. */ - uint32_t rd_key5_data_fail:1; - /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t rd_sys_part2_data_err_num:3; - /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. */ - uint32_t rd_sys_part2_data_fail:1; + uint32_t sys_part2_fail:1; uint32_t reserved_8:24; }; uint32_t val; -} efuse_rd_rs_data_err1_reg_t; +} efuse_rd_rs_err1_reg_t; -/** Group: EFUSE Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37814560; - * Represents eFuse version. Date:2024-10-12 12:09:57, - * ScriptRev:892332a1019d3a17987b08c6835edce28f46e261 - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -/** Group: EFUSE Clock Registers */ +/** Group: Configuration Register */ /** Type of clk register * eFuse clcok configuration register. */ typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into power-saving mode. */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Set this bit and force to activate clock signal of eFuse SRAM. */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into working mode. */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Set this bit to force enable eFuse register configuration clock signal. */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -1098,40 +2006,54 @@ typedef union { uint32_t val; } efuse_clk_reg_t; - -/** Group: EFUSE Configure Registers */ /** Type of conf register * eFuse operation mode configuration register */ typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * 0x5A5A: programming operation command 0x5AA5: read operation command. */ uint32_t op_code:16; - /** cfg_ecdsa_l_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key low part output. + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. */ - uint32_t cfg_ecdsa_l_blk:4; - /** cfg_ecdsa_h_blk : R/W; bitpos: [23:20]; default: 0; - * Configures which block to use for ECDSA key high part output. - */ - uint32_t cfg_ecdsa_h_blk:4; - uint32_t reserved_24:8; + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; }; uint32_t val; } efuse_conf_reg_t; +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + /** Type of dac_conf register * Controls the eFuse programming voltage. */ typedef union { struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. */ uint32_t dac_clk_div:8; /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; @@ -1139,14 +2061,11 @@ typedef union { */ uint32_t dac_clk_pad_sel:1; /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. + * Controls the rising period of the programming voltage. */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Reduces the power supply of the programming voltage. */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -1160,20 +2079,19 @@ typedef union { typedef union { struct { /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read hold time. */ uint32_t thr_a:8; /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read time. */ uint32_t trd:8; /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read setup time. */ uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. */ uint32_t read_init_num:8; }; @@ -1186,18 +2104,15 @@ typedef union { typedef union { struct { /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the programming setup time. */ uint32_t tsup_a:8; /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power up time for VDDQ. */ uint32_t pwr_on_num:16; /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. + * Configures the programming hold time. */ uint32_t thp_a:8; }; @@ -1210,13 +2125,11 @@ typedef union { typedef union { struct { /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power outage time for VDDQ. */ uint32_t pwr_off_num:16; /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the active programming time. */ uint32_t tpgm:16; }; @@ -1230,24 +2143,19 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Set this bit to bypass reed solomon correction step. */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. + * Configures block number of programming twice operation. */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Set this bit to update multi-bit register signals. */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the inactive programming time. */ uint32_t tpgm_inactive:8; uint32_t reserved_21:11; @@ -1256,79 +2164,66 @@ typedef union { } efuse_wr_tim_conf0_rs_bypass_reg_t; -/** Group: EFUSE Status Registers */ +/** Group: Status Register */ /** Type of status register * eFuse status register. */ typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Indicates the state of the eFuse state machine. */ uint32_t state:4; - uint32_t reserved_4:6; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. + * Indicates the number of block valid bit. */ uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_l_blk : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA key low part output. + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. */ - uint32_t cur_ecdsa_l_blk:4; - /** cur_ecdsa_h_blk : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA key high part output. - */ - uint32_t cur_ecdsa_h_blk:4; - uint32_t reserved_28:4; + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; }; uint32_t val; } efuse_status_reg_t; -/** Group: EFUSE Command Registers */ -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - - -/** Group: Interrupt Registers */ +/** Group: Interrupt Register */ /** Type of int_raw register * eFuse raw interrupt register. */ typedef union { struct { /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. + * The raw bit signal for read_done interrupt. */ uint32_t read_done_int_raw:1; /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. + * The raw bit signal for pgm_done interrupt. */ uint32_t pgm_done_int_raw:1; uint32_t reserved_2:30; @@ -1342,11 +2237,11 @@ typedef union { typedef union { struct { /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. + * The status signal for read_done interrupt. */ uint32_t read_done_int_st:1; /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. + * The status signal for pgm_done interrupt. */ uint32_t pgm_done_int_st:1; uint32_t reserved_2:30; @@ -1360,11 +2255,11 @@ typedef union { typedef union { struct { /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. + * The enable signal for read_done interrupt. */ uint32_t read_done_int_ena:1; /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. + * The enable signal for pgm_done interrupt. */ uint32_t pgm_done_int_ena:1; uint32_t reserved_2:30; @@ -1378,11 +2273,11 @@ typedef union { typedef union { struct { /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. + * The clear signal for read_done interrupt. */ uint32_t read_done_int_clr:1; /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. + * The clear signal for pgm_done interrupt. */ uint32_t pgm_done_int_clr:1; uint32_t reserved_2:30; @@ -1391,39 +2286,126 @@ typedef union { } efuse_int_clr_reg_t; +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; volatile efuse_rd_wr_dis_reg_t rd_wr_dis; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; - volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; - volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; - volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; - volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; - volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; - volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; - volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; - volatile efuse_date_reg_t date; - uint32_t reserved_19c[11]; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; volatile efuse_clk_reg_t clk; volatile efuse_conf_reg_t conf; volatile efuse_status_reg_t status; @@ -1437,12 +2419,13 @@ typedef struct { volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; #ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x1fc, "Invalid size of efuse_dev_t structure"); +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/gdma_reg.h b/components/soc/esp32h21/register/soc/gdma_reg.h new file mode 100644 index 0000000000..1142b45dc8 --- /dev/null +++ b/components/soc/esp32h21/register/soc/gdma_reg.h @@ -0,0 +1,3161 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0. + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0. + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0. + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0. + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1. + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 1. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 1. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 1. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 1. + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1. + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1. + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2. + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 2. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 2. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 2. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 2. + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2. + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2. + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0. + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0. + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0. + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0. + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1. + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 1. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 1. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 1. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 1. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 1. + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1. + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1. + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2. + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 2. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 2. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 2. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 2. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 2. + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2. + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2. + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0. + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0. + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0. + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0. + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0. + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0. + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0. + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0. + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel $n. + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0. + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0. + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0. + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0. + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0. + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0. + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 1. + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 1 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 1. + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 1. + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 1. + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 1. + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 1. + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 1. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 1. + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 1. + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1. + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 1. + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 1. + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 1. + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 1. + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 1. + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 1. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 1. + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 1. + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 2. + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 2 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 2. + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 2. + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 2. + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 2. + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 2. + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 2. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 2. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 2. + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 2. + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 2. + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 2 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 2. + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 2. + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 2. + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 2. + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 2. + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 2. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 2. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 2. + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 2. + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/gdma_struct.h b/components/soc/esp32h21/register/soc/gdma_struct.h new file mode 100644 index 0000000000..abb3738f67 --- /dev/null +++ b/components/soc/esp32h21/register/soc/gdma_struct.h @@ -0,0 +1,1090 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel n. + */ + uint32_t in_done_chn_int_raw:1; + /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel n. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel n. + */ + uint32_t in_suc_eof_chn_int_raw:1; + /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel n. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_chn_int_raw:1; + /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel n. + */ + uint32_t in_dscr_err_chn_int_raw:1; + /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel n. + */ + uint32_t in_dscr_empty_chn_int_raw:1; + /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is + * overflow. + */ + uint32_t infifo_ovf_chn_int_raw:1; + /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is + * underflow. + */ + uint32_t infifo_udf_chn_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_st:1; + /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_st:1; + /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_st:1; + /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_st:1; + /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_st:1; + /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_st:1; + /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_ena:1; + /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_ena:1; + /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_ena:1; + /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_ena:1; + /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_ena:1; + /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_ena:1; + /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_clr:1; + /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_clr:1; + /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_clr:1; + /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_clr:1; + /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_clr:1; + /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_clr:1; + /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + +/** Type of out_int_raw_chn register + * Raw status interrupt of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel n. + */ + uint32_t out_done_chn_int_raw:1; + /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel n. + */ + uint32_t out_eof_chn_int_raw:1; + /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel n. + */ + uint32_t out_dscr_err_chn_int_raw:1; + /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel n. + */ + uint32_t out_total_eof_chn_int_raw:1; + /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is + * overflow. + */ + uint32_t outfifo_ovf_chn_int_raw:1; + /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is + * underflow. + */ + uint32_t outfifo_udf_chn_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_st:1; + /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_st:1; + /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_st:1; + /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_st:1; + /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_st:1; + /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_ena:1; + /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_ena:1; + /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_ena:1; + /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_ena:1; + /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_ena:1; + /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_clr:1; + /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_clr:1; + /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_clr:1; + /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_clr:1; + /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_clr:1; + /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel n. + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel n Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel n reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel n receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel n is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel n. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel n. + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel n. + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of out_conf0_ch0 register + * Configure 0 register of Tx channel 0. + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_ch0:1; + /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_ch0:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel n. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel n. + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel n. + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel n. + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Status Registers */ +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel n. + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel n. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel n. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel n. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel n. + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel n. + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel n. + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel n. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel n. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel n. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel n. + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel n. + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + + +/** Group: Priority Registers */ +/** Type of in_pri_chn register + * Priority register of Rx channel n. + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel n. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel n. + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel n. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel n. + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel n. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel n. + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel n. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; + volatile gdma_in_pop_chn_reg_t in_pop_ch0; + volatile gdma_in_link_chn_reg_t in_link_ch0; + volatile gdma_in_state_chn_reg_t in_state_ch0; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; + volatile gdma_in_pri_chn_reg_t in_pri_ch0; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[11]; + volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; + volatile gdma_out_push_chn_reg_t out_push_ch0; + volatile gdma_out_link_chn_reg_t out_link_ch0; + volatile gdma_out_state_chn_reg_t out_state_ch0; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; + volatile gdma_out_pri_chn_reg_t out_pri_ch0; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + uint32_t reserved_104[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; + volatile gdma_in_pop_chn_reg_t in_pop_ch1; + volatile gdma_in_link_chn_reg_t in_link_ch1; + volatile gdma_in_state_chn_reg_t in_state_ch1; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; + volatile gdma_in_pri_chn_reg_t in_pri_ch1; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; + uint32_t reserved_164[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; + volatile gdma_out_push_chn_reg_t out_push_ch1; + volatile gdma_out_link_chn_reg_t out_link_ch1; + volatile gdma_out_state_chn_reg_t out_state_ch1; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; + volatile gdma_out_pri_chn_reg_t out_pri_ch1; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; + volatile gdma_in_pop_chn_reg_t in_pop_ch2; + volatile gdma_in_link_chn_reg_t in_link_ch2; + volatile gdma_in_state_chn_reg_t in_state_ch2; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; + volatile gdma_in_pri_chn_reg_t in_pri_ch2; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; + uint32_t reserved_224[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; + volatile gdma_out_push_chn_reg_t out_push_ch2; + volatile gdma_out_link_chn_reg_t out_link_ch2; + volatile gdma_out_state_chn_reg_t out_state_ch2; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; + volatile gdma_out_pri_chn_reg_t out_pri_ch2; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x284, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h new file mode 100644 index 0000000000..01c003761a --- /dev/null +++ b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11858 + +#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_CTRL 0x01FFFFFFU +#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S) +#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU +#define I2C_MST_I2C0_CTRL_S 0 +/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_BUSY (BIT(25)) +#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S) +#define I2C_MST_I2C0_BUSY_V 0x00000001U +#define I2C_MST_I2C0_BUSY_S 25 + +#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_CTRL 0x01FFFFFFU +#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S) +#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU +#define I2C_MST_I2C1_CTRL_S 0 +/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_BUSY (BIT(25)) +#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S) +#define I2C_MST_I2C1_BUSY_V 0x00000001U +#define I2C_MST_I2C1_BUSY_S 25 + +#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_CONF 0x00FFFFFFU +#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S) +#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU +#define I2C_MST_I2C0_CONF_S 0 +/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_STATUS 0x000000FFU +#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S) +#define I2C_MST_I2C0_STATUS_V 0x000000FFU +#define I2C_MST_I2C0_STATUS_S 24 + +#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) +/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_CONF 0x00FFFFFFU +#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S) +#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU +#define I2C_MST_I2C1_CONF_S 0 +/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_STATUS 0x000000FFU +#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S) +#define I2C_MST_I2C1_STATUS_V 0x000000FFU +#define I2C_MST_I2C1_STATUS_S 24 + +#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_BURST_CTRL 0xFFFFFFFFU +#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S) +#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU +#define I2C_MST_BURST_CTRL_S 0 + +#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST_BURST_DONE (BIT(0)) +#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S) +#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U +#define I2C_MST_I2C_MST_BURST_DONE_S 0 +/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S) +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S) +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/ +/* description: .*/ +#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU +#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S) +#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU +#define I2C_MST_BURST_TIMEOUT_CNT_S 3 + +#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF0 0x00FFFFFFU +#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S) +#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF0_S 0 +/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS0 0x000000FFU +#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S) +#define I2C_MST_ANA_STATUS0_V 0x000000FFU +#define I2C_MST_ANA_STATUS0_S 24 + +#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) +/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF1 0x00FFFFFFU +#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S) +#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF1_S 0 +/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS1 0x000000FFU +#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S) +#define I2C_MST_ANA_STATUS1_V 0x000000FFU +#define I2C_MST_ANA_STATUS1_S 24 + +#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF2 0x00FFFFFFU +#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S) +#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF2_S 0 +/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS2 0x000000FFU +#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S) +#define I2C_MST_ANA_STATUS2_V 0x000000FFU +#define I2C_MST_ANA_STATUS2_S 24 + +#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S) +#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0 +/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S) +#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6 + +#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S) +#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0 +/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S) +#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6 + +#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) +/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S) +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0 +/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S) +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ARBITER_DIS (BIT(11)) +#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S) +#define I2C_MST_ARBITER_DIS_V 0x00000001U +#define I2C_MST_ARBITER_DIS_S 11 + +#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_NOUSE 0xFFFFFFFFU +#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S) +#define I2C_MST_NOUSE_V 0xFFFFFFFFU +#define I2C_MST_NOUSE_S 0 + +#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/ +/* description: .*/ +#define I2C_MST_DATE 0x0FFFFFFFU +#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S) +#define I2C_MST_DATE_V 0x0FFFFFFFU +#define I2C_MST_DATE_S 0 +/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/ +/* description: .*/ +#define I2C_MST_CLK_EN (BIT(28)) +#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S) +#define I2C_MST_CLK_EN_V 0x00000001U +#define I2C_MST_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h index ce4890cf34..020976f85f 100644 --- a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h @@ -5,7 +5,6 @@ */ #pragma once -#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32h21/register/soc/interrupt_reg.h b/components/soc/esp32h21/register/soc/interrupt_reg.h new file mode 100644 index 0000000000..9d685cddd6 --- /dev/null +++ b/components/soc/esp32h21/register/soc/interrupt_reg.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "interrupt_matrix_reg.h" +#include "plic_reg.h" +#include "soc/soc_caps.h" + +#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG + +/** + * ESP32H21 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y) + * Keep the following macros for backward compatibility reasons + */ +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG +#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32h21/register/soc/io_mux_reg.h b/components/soc/esp32h21/register/soc/io_mux_reg.h new file mode 100644 index 0000000000..076b9c3c4e --- /dev/null +++ b/components/soc/esp32h21/register/soc/io_mux_reg.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "soc/soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 + +/* HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. + * 1: Hysteresis enabled. 0: Hysteresis disabled. + */ +#define HYS_EN (BIT(16)) +#define HYS_EN_M (HYS_EN_V << HYS_EN_S) +#define HYS_EN_V 0x00000001 +#define HYS_EN_S 16 +/* HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. + * 1: Select enabling signal from software. + * 0: Select enabling signal from efuse hardware. + */ +#define HYS_SEL (BIT(17)) +#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S) +#define HYS_SEL_V 0x00000001 +#define HYS_SEL_S 17 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) +#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL) +#define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL) +#define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN) +#define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_MTMS +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_MTDO +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_MTCK +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTDI +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_GPIO4 +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_GPIO5 +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6 +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14 +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_U0RXD +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_U0TXD +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17 +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18 +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICS0 +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPIQ +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_SPIWP +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_SPIHD +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_SPICLK +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_SPID + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U0RXD_GPIO_NUM 15 +#define U0TXD_GPIO_NUM 16 + +#define SPI_HD_GPIO_NUM 23 +#define SPI_WP_GPIO_NUM 22 +#define SPI_CS0_GPIO_NUM 20 +#define SPI_CLK_GPIO_NUM 24 +#define SPI_D_GPIO_NUM 25 +#define SPI_Q_GPIO_NUM 21 + +#define USB_INT_PHY0_DM_GPIO_NUM 26 +#define USB_INT_PHY0_DP_GPIO_NUM 27 + +#define EXT_OSC_SLOW_GPIO_NUM 13 + + +#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function +#define MAX_PAD_GPIO_NUM 25 +#define MAX_GPIO_NUM 29 +#define HIGH_IO_HOLD_BIT_SHIFT 32 + +#define GPIO_NUM_IN_INVALID 0x28 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 IO_MUX_CLK_OUT3 +#define CLK_OUT3_V IO_MUX_CLK_OUT3_V +#define CLK_OUT3_S IO_MUX_CLK_OUT3_S +#define CLK_OUT3_M IO_MUX_CLK_OUT3_M +#define CLK_OUT2 IO_MUX_CLK_OUT2 +#define CLK_OUT2_V IO_MUX_CLK_OUT2_V +#define CLK_OUT2_S IO_MUX_CLK_OUT2_S +#define CLK_OUT2_M IO_MUX_CLK_OUT2_M +#define CLK_OUT1 IO_MUX_CLK_OUT1 +#define CLK_OUT1_V IO_MUX_CLK_OUT1_V +#define CLK_OUT1_S IO_MUX_CLK_OUT1_S +#define CLK_OUT1_M IO_MUX_CLK_OUT1_M +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTMS_FSPIWP 2 +#define FUNC_MTMS_GPIO0 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x4) +#define FUNC_MTDO_FSPIHD 2 +#define FUNC_MTDO_GPIO1 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x8) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO2 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0xC) +#define FUNC_MTDI_FSPID 2 +#define FUNC_MTDI_GPIO3 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x10) +#define FUNC_GPIO4_FSPIQ 2 +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x14) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x18) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x28) +#define FUNC_XTAL_32K_N_GPIO10 1 +#define FUNC_XTAL_32K_N_GPIO10_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x2C) +#define FUNC_XTAL_32K_P_GPIO11 1 +#define FUNC_XTAL_32K_P_GPIO11_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO12_FSPICS0 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x3C) +#define FUNC_U0RXD_GPIO15 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x40) +#define FUNC_U0TXD_GPIO16 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x44) +#define FUNC_GPIO17_GPIO17 1 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x48) +#define FUNC_GPIO18_GPIO18 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x4C) +#define FUNC_VDD_SPI_GPIO19 1 +#define FUNC_VDD_SPI_GPIO19_0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x50) +#define FUNC_SPICS0_GPIO20 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x54) +#define FUNC_SPIQ_GPIO21 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x58) +#define FUNC_SPIWP_GPIO22 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x5C) +#define FUNC_SPIHD_GPIO23 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x60) +#define FUNC_SPICLK_GPIO24 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x64) +#define FUNC_SPID_GPIO25 1 +#define FUNC_SPID_SPID 0 + +/** IO_MUX_PIN_CTRL_REG register + * Clock Output Configuration + * Register + */ +#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0) +/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register + * to 0x0. CLK_OUT_out1 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT1 0x0000001F +#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) +#define IO_MUX_CLK_OUT1_V 0x0000001F +#define IO_MUX_CLK_OUT1_S 0 +/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register + * to 0x0. CLK_OUT_out2 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT2 0x0000001F +#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) +#define IO_MUX_CLK_OUT2_V 0x0000001F +#define IO_MUX_CLK_OUT2_S 5 +/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register + * to 0x0. CLK_OUT_out3 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT3 0x0000001F +#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) +#define IO_MUX_CLK_OUT3_V 0x0000001F +#define IO_MUX_CLK_OUT3_S 10 + +/** IO_MUX_MODEM_DIAG_EN_REG register + * GPIO MATRIX Configure Register for modem + * diag + */ +#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc) +/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0; + * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] + * into gpio matrix. 0:enable other signals into gpio + * matrix + */ +#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S) +#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_S 0 + + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC) +/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2409110 ; */ +/*description: Version control register.*/ +#define IO_MUX_REG_DATE 0x0FFFFFFF +#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S)) +#define IO_MUX_REG_DATE_V 0xFFFFFFF +#define IO_MUX_REG_DATE_S 0 diff --git a/components/soc/esp32h21/register/soc/lp_timer_reg.h b/components/soc/esp32h21/register/soc/lp_timer_reg.h new file mode 100644 index 0000000000..4b3d82ef15 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_timer_reg.h @@ -0,0 +1,242 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 27 +/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28)) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 37785904; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_timer_struct.h b/components/soc/esp32h21/register/soc/lp_timer_struct.h new file mode 100644 index 0000000000..942322114f --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_timer_struct.h @@ -0,0 +1,258 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of timer_tar0_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of timer_tar0_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of timer_update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** timer_main_timer_update : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t timer_main_timer_update:1; + /** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ + uint32_t timer_main_timer_regdma_work:1; + /** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t timer_main_timer_xtal_off:1; + /** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_main_timer_sys_stall:1; + /** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of timer_main_buf0_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of timer_main_buf0_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of timer_main_buf1_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of timer_main_buf1_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of timer_main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** timer_main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of timer_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_raw:1; + /** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of timer_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_st:1; + /** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of timer_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_ena:1; + /** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of timer_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_clr:1; + /** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of timer_date register + * need_des + */ +typedef union { + struct { + /** timer_date : R/W; bitpos: [30:0]; default: 37785904; + * need_des + */ + uint32_t timer_date:31; + /** timer_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t timer_tar0_low; + volatile lp_timer_tar0_high_reg_t timer_tar0_high; + uint32_t reserved_008[2]; + volatile lp_timer_update_reg_t timer_update; + volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high; + volatile lp_timer_main_overflow_reg_t timer_main_overflow; + volatile lp_timer_int_raw_reg_t timer_int_raw; + volatile lp_timer_int_st_reg_t timer_int_st; + volatile lp_timer_int_ena_reg_t timer_int_ena; + volatile lp_timer_int_clr_reg_t timer_int_clr; + uint32_t reserved_038[241]; + volatile lp_timer_date_reg_t timer_date; +} lp_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_dev_t) == 0x400, "Invalid size of lp_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lpperi_reg.h b/components/soc/esp32h21/register/soc/lpperi_reg.h new file mode 100644 index 0000000000..593e87e2e1 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lpperi_reg.h @@ -0,0 +1,388 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) +#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) +#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U +#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * need des + */ +#define LPPERI_RTC_TIMER_EN 0x00000003U +#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) +#define LPPERI_RTC_TIMER_EN_V 0x00000003U +#define LPPERI_RTC_TIMER_EN_S 10 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DEBUG_SEL0_REG register + * need des + */ +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL0 0x0000007FU +#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) +#define LPPERI_DEBUG_SEL0_V 0x0000007FU +#define LPPERI_DEBUG_SEL0_S 0 +/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL1 0x0000007FU +#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) +#define LPPERI_DEBUG_SEL1_V 0x0000007FU +#define LPPERI_DEBUG_SEL1_S 7 +/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL2 0x0000007FU +#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) +#define LPPERI_DEBUG_SEL2_V 0x0000007FU +#define LPPERI_DEBUG_SEL2_S 14 +/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL3 0x0000007FU +#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) +#define LPPERI_DEBUG_SEL3_V 0x0000007FU +#define LPPERI_DEBUG_SEL3_S 21 + +/** LPPERI_DEBUG_SEL1_REG register + * need des + */ +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c) +/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL4 0x0000007FU +#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) +#define LPPERI_DEBUG_SEL4_V 0x0000007FU +#define LPPERI_DEBUG_SEL4_S 0 + +/** LPPERI_RNG_DATA_SYNC_REG register + * rng result sync register + */ +#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30) +/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ +#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) +#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lpperi_struct.h b/components/soc/esp32h21/register/soc/lpperi_struct.h new file mode 100644 index 0000000000..4ccec691b9 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lpperi_struct.h @@ -0,0 +1,352 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * need des + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + +/** Type of rng_data_sync register + * rng result sync register + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} lpperi_rng_data_sync_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + volatile lpperi_rng_data_sync_reg_t rng_data_sync; + uint32_t reserved_034[242]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/pcr_struct.h b/components/soc/esp32h21/register/soc/pcr_struct.h index e658e903b2..7e3c68bc9c 100644 --- a/components/soc/esp32h21/register/soc/pcr_struct.h +++ b/components/soc/esp32h21/register/soc/pcr_struct.h @@ -1784,12 +1784,12 @@ typedef union { * This field indicates which one 32KHz clock will be used by timergroup. 1: XTAL32K * (default), 2/3: 32KHz from pad GPIO0. */ - uint32_t 32k_sel:2; + uint32_t clk_32k_sel:2; /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 1; * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 1: * XTAL32K(default), 2/3: 32KHz from pad GPIO0. */ - uint32_t 32k_modem_sel:2; + uint32_t clk_32k_modem_sel:2; uint32_t reserved_4:28; }; uint32_t val; diff --git a/components/soc/esp32h21/register/soc/plic_reg.h b/components/soc/esp32h21/register/soc/plic_reg.h new file mode 100644 index 0000000000..c9baf66064 --- /dev/null +++ b/components/soc/esp32h21/register/soc/plic_reg.h @@ -0,0 +1,635 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11859 + +#define DR_REG_PLIC_MX_BASE ( 0x20001000 ) +#define DR_REG_PLIC_UX_BASE ( 0x20001400 ) +#define PLIC_MXINT_CONF_REG ( 0x200013FC ) +#define PLIC_UXINT_CONF_REG ( 0x200017FC ) + +#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) + +/*PLIC MX*/ +#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) +/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S)) +#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_S 0 + +#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) +/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S)) +#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_S 0 + +#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) +/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S)) +#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_S 0 + +#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) +/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT0_PRI 0x0000000F +#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S)) +#define PLIC_CPU_MXINT0_PRI_V 0xF +#define PLIC_CPU_MXINT0_PRI_S 0 + +#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14) +/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT1_PRI 0x0000000F +#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S)) +#define PLIC_CPU_MXINT1_PRI_V 0xF +#define PLIC_CPU_MXINT1_PRI_S 0 + +#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18) +/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT2_PRI 0x0000000F +#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S)) +#define PLIC_CPU_MXINT2_PRI_V 0xF +#define PLIC_CPU_MXINT2_PRI_S 0 + +#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C) +/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT3_PRI 0x0000000F +#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S)) +#define PLIC_CPU_MXINT3_PRI_V 0xF +#define PLIC_CPU_MXINT3_PRI_S 0 + +#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20) +/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT4_PRI 0x0000000F +#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S)) +#define PLIC_CPU_MXINT4_PRI_V 0xF +#define PLIC_CPU_MXINT4_PRI_S 0 + +#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24) +/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT5_PRI 0x0000000F +#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S)) +#define PLIC_CPU_MXINT5_PRI_V 0xF +#define PLIC_CPU_MXINT5_PRI_S 0 + +#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28) +/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT6_PRI 0x0000000F +#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S)) +#define PLIC_CPU_MXINT6_PRI_V 0xF +#define PLIC_CPU_MXINT6_PRI_S 0 + +#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C) +/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT7_PRI 0x0000000F +#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S)) +#define PLIC_CPU_MXINT7_PRI_V 0xF +#define PLIC_CPU_MXINT7_PRI_S 0 + +#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30) +/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT8_PRI 0x0000000F +#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S)) +#define PLIC_CPU_MXINT8_PRI_V 0xF +#define PLIC_CPU_MXINT8_PRI_S 0 + +#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34) +/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT9_PRI 0x0000000F +#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S)) +#define PLIC_CPU_MXINT9_PRI_V 0xF +#define PLIC_CPU_MXINT9_PRI_S 0 + +#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38) +/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT10_PRI 0x0000000F +#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S)) +#define PLIC_CPU_MXINT10_PRI_V 0xF +#define PLIC_CPU_MXINT10_PRI_S 0 + +#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C) +/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT11_PRI 0x0000000F +#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S)) +#define PLIC_CPU_MXINT11_PRI_V 0xF +#define PLIC_CPU_MXINT11_PRI_S 0 + +#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40) +/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT12_PRI 0x0000000F +#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S)) +#define PLIC_CPU_MXINT12_PRI_V 0xF +#define PLIC_CPU_MXINT12_PRI_S 0 + +#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44) +/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT13_PRI 0x0000000F +#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S)) +#define PLIC_CPU_MXINT13_PRI_V 0xF +#define PLIC_CPU_MXINT13_PRI_S 0 + +#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48) +/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT14_PRI 0x0000000F +#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S)) +#define PLIC_CPU_MXINT14_PRI_V 0xF +#define PLIC_CPU_MXINT14_PRI_S 0 + +#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C) +/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT15_PRI 0x0000000F +#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S)) +#define PLIC_CPU_MXINT15_PRI_V 0xF +#define PLIC_CPU_MXINT15_PRI_S 0 + +#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50) +/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT16_PRI 0x0000000F +#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S)) +#define PLIC_CPU_MXINT16_PRI_V 0xF +#define PLIC_CPU_MXINT16_PRI_S 0 + +#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54) +/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT17_PRI 0x0000000F +#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S)) +#define PLIC_CPU_MXINT17_PRI_V 0xF +#define PLIC_CPU_MXINT17_PRI_S 0 + +#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58) +/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT18_PRI 0x0000000F +#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S)) +#define PLIC_CPU_MXINT18_PRI_V 0xF +#define PLIC_CPU_MXINT18_PRI_S 0 + +#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C) +/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT19_PRI 0x0000000F +#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S)) +#define PLIC_CPU_MXINT19_PRI_V 0xF +#define PLIC_CPU_MXINT19_PRI_S 0 + +#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60) +/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT20_PRI 0x0000000F +#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S)) +#define PLIC_CPU_MXINT20_PRI_V 0xF +#define PLIC_CPU_MXINT20_PRI_S 0 + +#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64) +/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT21_PRI 0x0000000F +#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S)) +#define PLIC_CPU_MXINT21_PRI_V 0xF +#define PLIC_CPU_MXINT21_PRI_S 0 + +#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68) +/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT22_PRI 0x0000000F +#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S)) +#define PLIC_CPU_MXINT22_PRI_V 0xF +#define PLIC_CPU_MXINT22_PRI_S 0 + +#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C) +/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT23_PRI 0x0000000F +#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S)) +#define PLIC_CPU_MXINT23_PRI_V 0xF +#define PLIC_CPU_MXINT23_PRI_S 0 + +#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70) +/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT24_PRI 0x0000000F +#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S)) +#define PLIC_CPU_MXINT24_PRI_V 0xF +#define PLIC_CPU_MXINT24_PRI_S 0 + +#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74) +/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT25_PRI 0x0000000F +#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S)) +#define PLIC_CPU_MXINT25_PRI_V 0xF +#define PLIC_CPU_MXINT25_PRI_S 0 + +#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78) +/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT26_PRI 0x0000000F +#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S)) +#define PLIC_CPU_MXINT26_PRI_V 0xF +#define PLIC_CPU_MXINT26_PRI_S 0 + +#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C) +/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT27_PRI 0x0000000F +#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S)) +#define PLIC_CPU_MXINT27_PRI_V 0xF +#define PLIC_CPU_MXINT27_PRI_S 0 + +#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80) +/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT28_PRI 0x0000000F +#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S)) +#define PLIC_CPU_MXINT28_PRI_V 0xF +#define PLIC_CPU_MXINT28_PRI_S 0 + +#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84) +/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT29_PRI 0x0000000F +#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S)) +#define PLIC_CPU_MXINT29_PRI_V 0xF +#define PLIC_CPU_MXINT29_PRI_S 0 + +#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88) +/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT30_PRI 0x0000000F +#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S)) +#define PLIC_CPU_MXINT30_PRI_V 0xF +#define PLIC_CPU_MXINT30_PRI_S 0 + +#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C) +/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT31_PRI 0x0000000F +#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S)) +#define PLIC_CPU_MXINT31_PRI_V 0xF +#define PLIC_CPU_MXINT31_PRI_S 0 + +#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) +/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_THRESH 0x000000FF +#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S)) +#define PLIC_CPU_MXINT_THRESH_V 0xFF +#define PLIC_CPU_MXINT_THRESH_S 0 + +#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94) +/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/ +#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S)) +#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_S 0 + +/*PLIC UX*/ +#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0) +/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S)) +#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_S 0 + +#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4) +/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S)) +#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_S 0 + +#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8) +/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S)) +#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_S 0 + +#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10) +/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT0_PRI 0x0000000F +#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S)) +#define PLIC_CPU_UXINT0_PRI_V 0xF +#define PLIC_CPU_UXINT0_PRI_S 0 + +#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14) +/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT1_PRI 0x0000000F +#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S)) +#define PLIC_CPU_UXINT1_PRI_V 0xF +#define PLIC_CPU_UXINT1_PRI_S 0 + +#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18) +/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT2_PRI 0x0000000F +#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S)) +#define PLIC_CPU_UXINT2_PRI_V 0xF +#define PLIC_CPU_UXINT2_PRI_S 0 + +#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C) +/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT3_PRI 0x0000000F +#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S)) +#define PLIC_CPU_UXINT3_PRI_V 0xF +#define PLIC_CPU_UXINT3_PRI_S 0 + +#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20) +/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT4_PRI 0x0000000F +#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S)) +#define PLIC_CPU_UXINT4_PRI_V 0xF +#define PLIC_CPU_UXINT4_PRI_S 0 + +#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24) +/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT5_PRI 0x0000000F +#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S)) +#define PLIC_CPU_UXINT5_PRI_V 0xF +#define PLIC_CPU_UXINT5_PRI_S 0 + +#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28) +/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT6_PRI 0x0000000F +#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S)) +#define PLIC_CPU_UXINT6_PRI_V 0xF +#define PLIC_CPU_UXINT6_PRI_S 0 + +#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C) +/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT7_PRI 0x0000000F +#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S)) +#define PLIC_CPU_UXINT7_PRI_V 0xF +#define PLIC_CPU_UXINT7_PRI_S 0 + +#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30) +/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT8_PRI 0x0000000F +#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S)) +#define PLIC_CPU_UXINT8_PRI_V 0xF +#define PLIC_CPU_UXINT8_PRI_S 0 + +#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34) +/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT9_PRI 0x0000000F +#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S)) +#define PLIC_CPU_UXINT9_PRI_V 0xF +#define PLIC_CPU_UXINT9_PRI_S 0 + +#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38) +/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT10_PRI 0x0000000F +#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S)) +#define PLIC_CPU_UXINT10_PRI_V 0xF +#define PLIC_CPU_UXINT10_PRI_S 0 + +#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C) +/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT11_PRI 0x0000000F +#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S)) +#define PLIC_CPU_UXINT11_PRI_V 0xF +#define PLIC_CPU_UXINT11_PRI_S 0 + +#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40) +/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT12_PRI 0x0000000F +#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S)) +#define PLIC_CPU_UXINT12_PRI_V 0xF +#define PLIC_CPU_UXINT12_PRI_S 0 + +#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44) +/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT13_PRI 0x0000000F +#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S)) +#define PLIC_CPU_UXINT13_PRI_V 0xF +#define PLIC_CPU_UXINT13_PRI_S 0 + +#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48) +/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT14_PRI 0x0000000F +#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S)) +#define PLIC_CPU_UXINT14_PRI_V 0xF +#define PLIC_CPU_UXINT14_PRI_S 0 + +#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C) +/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT15_PRI 0x0000000F +#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S)) +#define PLIC_CPU_UXINT15_PRI_V 0xF +#define PLIC_CPU_UXINT15_PRI_S 0 + +#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50) +/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT16_PRI 0x0000000F +#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S)) +#define PLIC_CPU_UXINT16_PRI_V 0xF +#define PLIC_CPU_UXINT16_PRI_S 0 + +#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54) +/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT17_PRI 0x0000000F +#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S)) +#define PLIC_CPU_UXINT17_PRI_V 0xF +#define PLIC_CPU_UXINT17_PRI_S 0 + +#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58) +/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT18_PRI 0x0000000F +#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S)) +#define PLIC_CPU_UXINT18_PRI_V 0xF +#define PLIC_CPU_UXINT18_PRI_S 0 + +#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C) +/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT19_PRI 0x0000000F +#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S)) +#define PLIC_CPU_UXINT19_PRI_V 0xF +#define PLIC_CPU_UXINT19_PRI_S 0 + +#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60) +/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT20_PRI 0x0000000F +#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S)) +#define PLIC_CPU_UXINT20_PRI_V 0xF +#define PLIC_CPU_UXINT20_PRI_S 0 + +#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64) +/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT21_PRI 0x0000000F +#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S)) +#define PLIC_CPU_UXINT21_PRI_V 0xF +#define PLIC_CPU_UXINT21_PRI_S 0 + +#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68) +/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT22_PRI 0x0000000F +#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S)) +#define PLIC_CPU_UXINT22_PRI_V 0xF +#define PLIC_CPU_UXINT22_PRI_S 0 + +#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C) +/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT23_PRI 0x0000000F +#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S)) +#define PLIC_CPU_UXINT23_PRI_V 0xF +#define PLIC_CPU_UXINT23_PRI_S 0 + +#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70) +/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT24_PRI 0x0000000F +#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S)) +#define PLIC_CPU_UXINT24_PRI_V 0xF +#define PLIC_CPU_UXINT24_PRI_S 0 + +#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74) +/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT25_PRI 0x0000000F +#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S)) +#define PLIC_CPU_UXINT25_PRI_V 0xF +#define PLIC_CPU_UXINT25_PRI_S 0 + +#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78) +/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT26_PRI 0x0000000F +#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S)) +#define PLIC_CPU_UXINT26_PRI_V 0xF +#define PLIC_CPU_UXINT26_PRI_S 0 + +#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C) +/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT27_PRI 0x0000000F +#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S)) +#define PLIC_CPU_UXINT27_PRI_V 0xF +#define PLIC_CPU_UXINT27_PRI_S 0 + +#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80) +/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT28_PRI 0x0000000F +#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S)) +#define PLIC_CPU_UXINT28_PRI_V 0xF +#define PLIC_CPU_UXINT28_PRI_S 0 + +#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84) +/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT29_PRI 0x0000000F +#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S)) +#define PLIC_CPU_UXINT29_PRI_V 0xF +#define PLIC_CPU_UXINT29_PRI_S 0 + +#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88) +/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT30_PRI 0x0000000F +#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S)) +#define PLIC_CPU_UXINT30_PRI_V 0xF +#define PLIC_CPU_UXINT30_PRI_S 0 + +#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C) +/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT31_PRI 0x0000000F +#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S)) +#define PLIC_CPU_UXINT31_PRI_V 0xF +#define PLIC_CPU_UXINT31_PRI_S 0 + +#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90) +/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_THRESH 0x000000FF +#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S)) +#define PLIC_CPU_UXINT_THRESH_V 0xFF +#define PLIC_CPU_UXINT_THRESH_S 0 + +#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94) +/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S)) +#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/pmu_reg.h b/components/soc/esp32h21/register/soc/pmu_reg.h index abb9c04174..4394e9e124 100644 --- a/components/soc/esp32h21/register/soc/pmu_reg.h +++ b/components/soc/esp32h21/register/soc/pmu_reg.h @@ -15,13 +15,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) -/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_VDD_FLASH_MODE 0x0000000FU -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S) -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V 0x0000000FU -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S 18 +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -43,13 +43,6 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 -/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -199,48 +192,6 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) -/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_HP_ACTIVE_DCDC_CCM_ENB (BIT(9)) -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S) -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V 0x00000001U -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S 9 -/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S) -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S 10 -/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3; - * need_des - */ -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S) -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6; - * need_des - */ -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S) -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S 13 -/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU -#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) -#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU -#define PMU_HP_ACTIVE_DCM_VSET_S 17 -/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U -#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) -#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U -#define PMU_HP_ACTIVE_DCM_MODE_S 22 /** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -255,13 +206,6 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BIAS_S 25 -/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S) -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S 29 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -295,6 +239,27 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -309,19 +274,19 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 -/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0; +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; * need_des */ -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 18 -/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0; +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -401,14 +366,14 @@ extern "C" { #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 -/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 17; * need_des */ #define PMU_LP_DBIAS_VOL 0x0000001FU #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) #define PMU_LP_DBIAS_VOL_V 0x0000001FU #define PMU_LP_DBIAS_VOL_S 4 -/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 16; * need_des */ #define PMU_HP_DBIAS_VOL 0x0000001FU @@ -488,13 +453,6 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) -/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_HP_ACTIVE_XPD_XTALX2 (BIT(30)) -#define PMU_HP_ACTIVE_XPD_XTALX2_M (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S) -#define PMU_HP_ACTIVE_XPD_XTALX2_V 0x00000001U -#define PMU_HP_ACTIVE_XPD_XTALX2_S 30 /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -503,17 +461,404 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_XTAL_S 31 +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_TRX (BIT(24)) +#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S) +#define PMU_HP_MODEM_XPD_TRX_V 0x00000001U +#define PMU_HP_MODEM_XPD_TRX_S 24 +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + /** PMU_HP_SLEEP_DIG_POWER_REG register * need_des */ #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) -/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; * need_des */ -#define PMU_HP_SLEEP_VDD_FLASH_MODE 0x0000000FU -#define PMU_HP_SLEEP_VDD_FLASH_MODE_M (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S) -#define PMU_HP_SLEEP_VDD_FLASH_MODE_V 0x0000000FU -#define PMU_HP_SLEEP_VDD_FLASH_MODE_S 18 +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -535,13 +880,6 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 -/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -691,48 +1029,6 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) -/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_DCDC_CCM_ENB (BIT(9)) -#define PMU_HP_SLEEP_DCDC_CCM_ENB_M (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S) -#define PMU_HP_SLEEP_DCDC_CCM_ENB_V 0x00000001U -#define PMU_HP_SLEEP_DCDC_CCM_ENB_S 9 -/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S) -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S 10 -/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S) -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; - * need_des - */ -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S) -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S 13 -/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU -#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) -#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU -#define PMU_HP_SLEEP_DCM_VSET_S 17 -/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DCM_MODE 0x00000003U -#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) -#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U -#define PMU_HP_SLEEP_DCM_MODE_S 22 /** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -747,13 +1043,6 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_HP_SLEEP_XPD_BIAS_S 25 -/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S) -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -787,6 +1076,27 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; * need_des */ @@ -801,20 +1111,20 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 -/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 20 -/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0; +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; * need_des */ -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 25 +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -952,13 +1262,6 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) -/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_XPD_XTALX2 (BIT(30)) -#define PMU_HP_SLEEP_XPD_XTALX2_M (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S) -#define PMU_HP_SLEEP_XPD_XTALX2_V 0x00000001U -#define PMU_HP_SLEEP_XPD_XTALX2_S 30 /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -992,7 +1295,7 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; * need_des */ #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1012,17 +1315,22 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + /** PMU_HP_SLEEP_LP_DIG_POWER_REG register * need_des */ #define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) -/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_VDD_IO_MODE 0x0000000FU -#define PMU_HP_SLEEP_VDD_IO_MODE_M (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S) -#define PMU_HP_SLEEP_VDD_IO_MODE_V 0x0000000FU -#define PMU_HP_SLEEP_VDD_IO_MODE_S 23 /** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1092,6 +1400,18 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + /** PMU_LP_SLEEP_LP_REGULATOR0_REG register * need_des */ @@ -1117,7 +1437,7 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; * need_des */ #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1141,13 +1461,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) -/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_XPD_XTALX2 (BIT(30)) -#define PMU_LP_SLEEP_XPD_XTALX2_M (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S) -#define PMU_LP_SLEEP_XPD_XTALX2_V 0x00000001U -#define PMU_LP_SLEEP_XPD_XTALX2_S 30 /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1160,13 +1473,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) -/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_VDD_IO_MODE 0x0000000FU -#define PMU_LP_SLEEP_VDD_IO_MODE_M (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S) -#define PMU_LP_SLEEP_VDD_IO_MODE_V 0x0000000FU -#define PMU_LP_SLEEP_VDD_IO_MODE_S 23 /** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1240,48 +1546,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) -/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_DCDC_CCM_ENB (BIT(9)) -#define PMU_LP_SLEEP_DCDC_CCM_ENB_M (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S) -#define PMU_LP_SLEEP_DCDC_CCM_ENB_V 0x00000001U -#define PMU_LP_SLEEP_DCDC_CCM_ENB_S 9 -/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S) -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S 10 -/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S) -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; - * need_des - */ -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S) -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S 13 -/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_LP_SLEEP_DCM_VSET 0x0000001FU -#define PMU_LP_SLEEP_DCM_VSET_M (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S) -#define PMU_LP_SLEEP_DCM_VSET_V 0x0000001FU -#define PMU_LP_SLEEP_DCM_VSET_S 17 -/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DCM_MODE 0x00000003U -#define PMU_LP_SLEEP_DCM_MODE_M (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S) -#define PMU_LP_SLEEP_DCM_MODE_V 0x00000003U -#define PMU_LP_SLEEP_DCM_MODE_S 22 /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; * need_des */ @@ -1289,13 +1553,6 @@ extern "C" { #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_LP_SLEEP_XPD_BIAS_S 25 -/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S) -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1364,34 +1621,6 @@ extern "C" { #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U #define PMU_TIE_LOW_XPD_XTAL_S 6 -/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG (BIT(7)) -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S) -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V 0x00000001U -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S 7 -/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_XPD_XTALX2 (BIT(8)) -#define PMU_TIE_LOW_XPD_XTALX2_M (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S) -#define PMU_TIE_LOW_XPD_XTALX2_V 0x00000001U -#define PMU_TIE_LOW_XPD_XTALX2_S 8 -/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_XTALX2 (BIT(23)) -#define PMU_TIE_HIGH_XTALX2_M (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S) -#define PMU_TIE_HIGH_XTALX2_V 0x00000001U -#define PMU_TIE_HIGH_XTALX2_S 23 -/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG (BIT(24)) -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S) -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V 0x00000001U -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S 24 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; * need_des */ @@ -1534,20 +1763,6 @@ extern "C" { * need_des */ #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) -/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL (BIT(26)) -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S) -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V 0x00000001U -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S 26 -/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL (BIT(27)) -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S) -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V 0x00000001U -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S 27 /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; * need_des */ @@ -1614,77 +1829,44 @@ extern "C" { #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_S 14 -/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU -#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) -#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_HP_PD_WAIT_TIMER_S 23 +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER1_REG register * need_des */ #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) -/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; * need_des */ #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_S 9 -/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; * need_des */ #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_S 16 -/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU -#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) -#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_LP_PD_WAIT_TIMER_S 23 - -/** PMU_POWER_WAIT_TIMER2_REG register - * need_des - */ -#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) -/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; - * need_des - */ -#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU -#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) -#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 -/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; - * need_des - */ -#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU -#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) -#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_LP_RST_WAIT_TIMER_S 8 -/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; - * need_des - */ -#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU -#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) -#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 -/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; - * need_des - */ -#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU -#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) -#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_HP_RST_WAIT_TIMER_S 24 +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 /** PMU_POWER_PD_TOP_CNTL_REG register * need_des */ -#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1745,7 +1927,7 @@ extern "C" { /** PMU_POWER_PD_HPAON_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1806,7 +1988,7 @@ extern "C" { /** PMU_POWER_PD_HPCPU_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1867,68 +2049,19 @@ extern "C" { /** PMU_POWER_PD_HPPERI_RESERVE_REG register * need_des */ -#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104) -/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; * need_des */ -#define PMU_FORCE_HP_PERI_RESET (BIT(0)) -#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) -#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U -#define PMU_FORCE_HP_PERI_RESET_S 0 -/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_FORCE_HP_PERI_ISO (BIT(1)) -#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) -#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U -#define PMU_FORCE_HP_PERI_ISO_S 1 -/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_PU (BIT(2)) -#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) -#define PMU_FORCE_HP_PERI_PU_V 0x00000001U -#define PMU_FORCE_HP_PERI_PU_S 2 -/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) -#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) -#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U -#define PMU_FORCE_HP_PERI_NO_RESET_S 3 -/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) -#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) -#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U -#define PMU_FORCE_HP_PERI_NO_ISO_S 4 -/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FORCE_HP_PERI_PD (BIT(5)) -#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) -#define PMU_FORCE_HP_PERI_PD_V 0x00000001U -#define PMU_FORCE_HP_PERI_PD_S 5 -/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des - */ -#define PMU_PD_HP_PERI_MASK 0x0000001FU -#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) -#define PMU_PD_HP_PERI_MASK_V 0x0000001FU -#define PMU_PD_HP_PERI_MASK_S 6 -/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des - */ -#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU -#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) -#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU -#define PMU_PD_HP_PERI_PD_MASK_S 27 +#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) +#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_S 0 /** PMU_POWER_PD_HPWIFI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1989,7 +2122,7 @@ extern "C" { /** PMU_POWER_PD_LPPERI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2036,7 +2169,7 @@ extern "C" { /** PMU_POWER_PD_MEM_CNTL_REG register * need_des */ -#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; * need_des */ @@ -2069,7 +2202,7 @@ extern "C" { /** PMU_POWER_PD_MEM_MASK_REG register * need_des */ -#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; * need_des */ @@ -2116,7 +2249,7 @@ extern "C" { /** PMU_POWER_HP_PAD_REG register * need_des */ -#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2132,350 +2265,36 @@ extern "C" { #define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 -/** PMU_POWER_FLASH1P8_LDO_REG register +/** PMU_POWER_VDD_SPI_CNTL_REG register * need_des */ -#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c) -/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1; +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; * need_des */ -#define PMU_FLASH1P8_LDO_RDY (BIT(0)) -#define PMU_FLASH1P8_LDO_RDY_M (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S) -#define PMU_FLASH1P8_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P8_LDO_RDY_S 0 -/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0; +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; * need_des */ -#define PMU_FLASH1P8_SW_EN_XPD (BIT(1)) -#define PMU_FLASH1P8_SW_EN_XPD_M (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S) -#define PMU_FLASH1P8_SW_EN_XPD_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_XPD_S 1 -/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0; +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; * need_des */ -#define PMU_FLASH1P8_SW_EN_THRU (BIT(2)) -#define PMU_FLASH1P8_SW_EN_THRU_M (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S) -#define PMU_FLASH1P8_SW_EN_THRU_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_THRU_S 2 -/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_STANDBY (BIT(3)) -#define PMU_FLASH1P8_SW_EN_STANDBY_M (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S) -#define PMU_FLASH1P8_SW_EN_STANDBY_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_STANDBY_S 3 -/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST (BIT(4)) -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S) -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S 4 -/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_ENDET (BIT(5)) -#define PMU_FLASH1P8_SW_EN_ENDET_M (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S) -#define PMU_FLASH1P8_SW_EN_ENDET_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_ENDET_S 5 -/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_BYPASS_LDO_RDY (BIT(22)) -#define PMU_FLASH1P8_BYPASS_LDO_RDY_M (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S) -#define PMU_FLASH1P8_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P8_BYPASS_LDO_RDY_S 22 -/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_XPD (BIT(23)) -#define PMU_FLASH1P8_XPD_M (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S) -#define PMU_FLASH1P8_XPD_V 0x00000001U -#define PMU_FLASH1P8_XPD_S 23 -/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_FLASH1P8_THRU (BIT(24)) -#define PMU_FLASH1P8_THRU_M (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S) -#define PMU_FLASH1P8_THRU_V 0x00000001U -#define PMU_FLASH1P8_THRU_S 24 -/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_STANDBY (BIT(25)) -#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) -#define PMU_FLASH1P8_STANDBY_V 0x00000001U -#define PMU_FLASH1P8_STANDBY_S 25 -/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU -#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) -#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU -#define PMU_FLASH1P8_POWER_ADJUST_S 26 -/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_ENDET (BIT(31)) -#define PMU_FLASH1P8_ENDET_M (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S) -#define PMU_FLASH1P8_ENDET_V 0x00000001U -#define PMU_FLASH1P8_ENDET_S 31 - -/** PMU_POWER_FLASH1P2_LDO_REG register - * need_des - */ -#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120) -/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_FLASH1P2_LDO_RDY (BIT(0)) -#define PMU_FLASH1P2_LDO_RDY_M (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S) -#define PMU_FLASH1P2_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P2_LDO_RDY_S 0 -/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_XPD (BIT(1)) -#define PMU_FLASH1P2_SW_EN_XPD_M (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S) -#define PMU_FLASH1P2_SW_EN_XPD_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_XPD_S 1 -/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_THRU (BIT(2)) -#define PMU_FLASH1P2_SW_EN_THRU_M (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S) -#define PMU_FLASH1P2_SW_EN_THRU_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_THRU_S 2 -/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_STANDBY (BIT(3)) -#define PMU_FLASH1P2_SW_EN_STANDBY_M (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S) -#define PMU_FLASH1P2_SW_EN_STANDBY_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_STANDBY_S 3 -/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST (BIT(4)) -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S) -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S 4 -/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_ENDET (BIT(5)) -#define PMU_FLASH1P2_SW_EN_ENDET_M (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S) -#define PMU_FLASH1P2_SW_EN_ENDET_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_ENDET_S 5 -/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_BYPASS_LDO_RDY (BIT(22)) -#define PMU_FLASH1P2_BYPASS_LDO_RDY_M (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S) -#define PMU_FLASH1P2_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P2_BYPASS_LDO_RDY_S 22 -/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_XPD (BIT(23)) -#define PMU_FLASH1P2_XPD_M (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S) -#define PMU_FLASH1P2_XPD_V 0x00000001U -#define PMU_FLASH1P2_XPD_S 23 -/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_FLASH1P2_THRU (BIT(24)) -#define PMU_FLASH1P2_THRU_M (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S) -#define PMU_FLASH1P2_THRU_V 0x00000001U -#define PMU_FLASH1P2_THRU_S 24 -/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_STANDBY (BIT(25)) -#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) -#define PMU_FLASH1P2_STANDBY_V 0x00000001U -#define PMU_FLASH1P2_STANDBY_S 25 -/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU -#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) -#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU -#define PMU_FLASH1P2_POWER_ADJUST_S 26 -/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_ENDET (BIT(31)) -#define PMU_FLASH1P2_ENDET_M (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S) -#define PMU_FLASH1P2_ENDET_V 0x00000001U -#define PMU_FLASH1P2_ENDET_S 31 - -/** PMU_POWER_VDD_FLASH_REG register - * need_des - */ -#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124) -/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_SW_EN_TIEL (BIT(22)) -#define PMU_FLASH_LDO_SW_EN_TIEL_M (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S) -#define PMU_FLASH_LDO_SW_EN_TIEL_V 0x00000001U -#define PMU_FLASH_LDO_SW_EN_TIEL_S 22 -/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_POWER_SEL (BIT(23)) -#define PMU_FLASH_LDO_POWER_SEL_M (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S) -#define PMU_FLASH_LDO_POWER_SEL_V 0x00000001U -#define PMU_FLASH_LDO_POWER_SEL_S 23 -/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_SW_EN_POWER_SEL (BIT(24)) -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S) -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V 0x00000001U -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S 24 -/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15; - * need_des - */ -#define PMU_FLASH_LDO_WAIT_TARGET 0x0000000FU -#define PMU_FLASH_LDO_WAIT_TARGET_M (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S) -#define PMU_FLASH_LDO_WAIT_TARGET_V 0x0000000FU -#define PMU_FLASH_LDO_WAIT_TARGET_S 25 -/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_TIEL_EN (BIT(29)) -#define PMU_FLASH_LDO_TIEL_EN_M (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S) -#define PMU_FLASH_LDO_TIEL_EN_V 0x00000001U -#define PMU_FLASH_LDO_TIEL_EN_S 29 -/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_TIEL (BIT(30)) -#define PMU_FLASH_LDO_TIEL_M (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S) -#define PMU_FLASH_LDO_TIEL_V 0x00000001U -#define PMU_FLASH_LDO_TIEL_S 30 -/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_SW_UPDATE (BIT(31)) -#define PMU_FLASH_LDO_SW_UPDATE_M (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S) -#define PMU_FLASH_LDO_SW_UPDATE_V 0x00000001U -#define PMU_FLASH_LDO_SW_UPDATE_S 31 - -/** PMU_POWER_IO_LDO_REG register - * need_des - */ -#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128) -/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_IO_LDO_RDY (BIT(0)) -#define PMU_IO_LDO_RDY_M (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S) -#define PMU_IO_LDO_RDY_V 0x00000001U -#define PMU_IO_LDO_RDY_S 0 -/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_XPD (BIT(1)) -#define PMU_IO_SW_EN_XPD_M (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S) -#define PMU_IO_SW_EN_XPD_V 0x00000001U -#define PMU_IO_SW_EN_XPD_S 1 -/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_THRU (BIT(3)) -#define PMU_IO_SW_EN_THRU_M (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S) -#define PMU_IO_SW_EN_THRU_V 0x00000001U -#define PMU_IO_SW_EN_THRU_S 3 -/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_STANDBY (BIT(4)) -#define PMU_IO_SW_EN_STANDBY_M (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S) -#define PMU_IO_SW_EN_STANDBY_V 0x00000001U -#define PMU_IO_SW_EN_STANDBY_S 4 -/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_POWER_ADJUST (BIT(5)) -#define PMU_IO_SW_EN_POWER_ADJUST_M (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S) -#define PMU_IO_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_IO_SW_EN_POWER_ADJUST_S 5 -/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_ENDET (BIT(6)) -#define PMU_IO_SW_EN_ENDET_M (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S) -#define PMU_IO_SW_EN_ENDET_V 0x00000001U -#define PMU_IO_SW_EN_ENDET_S 6 -/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_IO_BYPASS_LDO_RDY (BIT(22)) -#define PMU_IO_BYPASS_LDO_RDY_M (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S) -#define PMU_IO_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_IO_BYPASS_LDO_RDY_S 22 -/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_IO_XPD (BIT(23)) -#define PMU_IO_XPD_M (PMU_IO_XPD_V << PMU_IO_XPD_S) -#define PMU_IO_XPD_V 0x00000001U -#define PMU_IO_XPD_S 23 -/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_IO_THRU (BIT(24)) -#define PMU_IO_THRU_M (PMU_IO_THRU_V << PMU_IO_THRU_S) -#define PMU_IO_THRU_V 0x00000001U -#define PMU_IO_THRU_S 24 -/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_IO_STANDBY (BIT(25)) -#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) -#define PMU_IO_STANDBY_V 0x00000001U -#define PMU_IO_STANDBY_S 25 -/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_IO_POWER_ADJUST 0x0000001FU -#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) -#define PMU_IO_POWER_ADJUST_V 0x0000001FU -#define PMU_IO_POWER_ADJUST_S 26 -/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_IO_ENDET (BIT(31)) -#define PMU_IO_ENDET_M (PMU_IO_ENDET_V << PMU_IO_ENDET_S) -#define PMU_IO_ENDET_V 0x00000001U -#define PMU_IO_ENDET_S 31 - -/** PMU_POWER_VDD_IO_REG register - * need_des - */ -#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c) -/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_IO_LDO_POWER_SEL (BIT(23)) -#define PMU_IO_LDO_POWER_SEL_M (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S) -#define PMU_IO_LDO_POWER_SEL_V 0x00000001U -#define PMU_IO_LDO_POWER_SEL_S 23 -/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define PMU_IO_LDO_SW_EN_POWER_SEL (BIT(24)) -#define PMU_IO_LDO_SW_EN_POWER_SEL_M (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S) -#define PMU_IO_LDO_SW_EN_POWER_SEL_V 0x00000001U -#define PMU_IO_LDO_SW_EN_POWER_SEL_S 24 +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 /** PMU_POWER_CK_WAIT_CNTL_REG register * need_des */ -#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; * need_des */ @@ -2494,7 +2313,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL0_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134) +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; * need_des */ @@ -2506,7 +2325,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL1_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138) +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; * need_des */ @@ -2525,7 +2344,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL2_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c) +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; * need_des */ @@ -2537,7 +2356,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL3_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140) +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; * need_des */ @@ -2563,7 +2382,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL4_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144) +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; * need_des */ @@ -2575,7 +2394,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL5_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148) +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2594,7 +2413,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL6_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c) +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2613,14 +2432,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL7_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150) -/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0; - * need_des - */ -#define PMU_ANA_WAIT_CLK_SEL (BIT(15)) -#define PMU_ANA_WAIT_CLK_SEL_M (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S) -#define PMU_ANA_WAIT_CLK_SEL_V 0x00000001U -#define PMU_ANA_WAIT_CLK_SEL_S 15 +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; * need_des */ @@ -2632,7 +2444,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS0_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154) +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2644,7 +2456,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS1_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158) +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2656,7 +2468,7 @@ extern "C" { /** PMU_HP_CK_POWERON_REG register * need_des */ -#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c) +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) /** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; * need_des */ @@ -2668,7 +2480,7 @@ extern "C" { /** PMU_HP_CK_CNTL_REG register * need_des */ -#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160) +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; * need_des */ @@ -2687,8 +2499,8 @@ extern "C" { /** PMU_POR_STATUS_REG register * need_des */ -#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164) -/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; * need_des */ #define PMU_POR_DONE (BIT(31)) @@ -2699,14 +2511,7 @@ extern "C" { /** PMU_RF_PWC_REG register * need_des */ -#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168) -/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define PMU_XPD_FORCE_RFTX (BIT(26)) -#define PMU_XPD_FORCE_RFTX_M (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S) -#define PMU_XPD_FORCE_RFTX_V 0x00000001U -#define PMU_XPD_FORCE_RFTX_S 26 +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; * need_des */ @@ -2746,7 +2551,7 @@ extern "C" { /** PMU_VDDBAT_CFG_REG register * need_des */ -#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c) +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x158) /** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; * need_des */ @@ -2765,7 +2570,7 @@ extern "C" { /** PMU_BACKUP_CFG_REG register * need_des */ -#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170) +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; * need_des */ @@ -2777,7 +2582,7 @@ extern "C" { /** PMU_INT_RAW_REG register * need_des */ -#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; * need_des */ @@ -2817,7 +2622,7 @@ extern "C" { /** PMU_HP_INT_ST_REG register * need_des */ -#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; * need_des */ @@ -2857,7 +2662,7 @@ extern "C" { /** PMU_HP_INT_ENA_REG register * need_des */ -#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; * need_des */ @@ -2897,7 +2702,7 @@ extern "C" { /** PMU_HP_INT_CLR_REG register * need_des */ -#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; * need_des */ @@ -2937,7 +2742,7 @@ extern "C" { /** PMU_LP_INT_RAW_REG register * need_des */ -#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184) +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; * need_des */ @@ -3026,7 +2831,7 @@ extern "C" { /** PMU_LP_INT_ST_REG register * need_des */ -#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188) +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; * need_des */ @@ -3115,7 +2920,7 @@ extern "C" { /** PMU_LP_INT_ENA_REG register * need_des */ -#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c) +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; * need_des */ @@ -3204,7 +3009,7 @@ extern "C" { /** PMU_LP_INT_CLR_REG register * need_des */ -#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190) +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; * need_des */ @@ -3293,7 +3098,7 @@ extern "C" { /** PMU_LP_CPU_PWR0_REG register * need_des */ -#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194) +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) /** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; * need_des */ @@ -3361,7 +3166,7 @@ extern "C" { /** PMU_LP_CPU_PWR1_REG register * need_des */ -#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198) +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) /** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -3380,7 +3185,7 @@ extern "C" { /** PMU_HP_LP_CPU_COMM_REG register * need_des */ -#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) /** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; * need_des */ @@ -3399,7 +3204,7 @@ extern "C" { /** PMU_HP_REGULATOR_CFG_REG register * need_des */ -#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; * need_des */ @@ -3411,8 +3216,8 @@ extern "C" { /** PMU_MAIN_STATE_REG register * need_des */ -#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) -/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256; +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; * need_des */ #define PMU_MAIN_LAST_ST_STATE 0x0000007FU @@ -3426,7 +3231,7 @@ extern "C" { #define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) #define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU #define PMU_MAIN_TAR_ST_STATE_S 18 -/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; * need_des */ #define PMU_MAIN_CUR_ST_STATE 0x0000007FU @@ -3437,7 +3242,7 @@ extern "C" { /** PMU_PWR_STATE_REG register * need_des */ -#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) /** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; * need_des */ @@ -3463,15 +3268,15 @@ extern "C" { /** PMU_CLK_STATE0_REG register * need_des */ -#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) -/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0; +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; * need_des */ #define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) #define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) #define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U #define PMU_STABLE_XPD_BBPLL_STATE_S 0 -/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0; +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; * need_des */ #define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) @@ -3499,7 +3304,7 @@ extern "C" { #define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) #define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U #define PMU_SYS_CLK_NO_DIV_STATE_S 18 -/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1; +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; * need_des */ #define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) @@ -3576,7 +3381,7 @@ extern "C" { #define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) #define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U #define PMU_ANA_XPD_BBPLL_STATE_S 30 -/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; * need_des */ #define PMU_ANA_XPD_XTAL_STATE (BIT(31)) @@ -3587,7 +3392,7 @@ extern "C" { /** PMU_CLK_STATE1_REG register * need_des */ -#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) /** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3599,7 +3404,7 @@ extern "C" { /** PMU_CLK_STATE2_REG register * need_des */ -#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) /** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3608,112 +3413,23 @@ extern "C" { #define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU #define PMU_ICG_APB_EN_STATE_S 0 -/** PMU_DCM_CTRL_REG register +/** PMU_VDD_SPI_STATUS_REG register * need_des */ -#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8) -/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1; +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; * need_des */ -#define PMU_DSFMOS_USE_POR (BIT(0)) -#define PMU_DSFMOS_USE_POR_M (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S) -#define PMU_DSFMOS_USE_POR_V 0x00000001U -#define PMU_DSFMOS_USE_POR_S 0 -/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_DCDC_DCM_UPDATE (BIT(22)) -#define PMU_DCDC_DCM_UPDATE_M (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S) -#define PMU_DCDC_DCM_UPDATE_V 0x00000001U -#define PMU_DCDC_DCM_UPDATE_S 22 -/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1; - * need_des - */ -#define PMU_DCDC_PCUR_LIMIT 0x00000007U -#define PMU_DCDC_PCUR_LIMIT_M (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S) -#define PMU_DCDC_PCUR_LIMIT_V 0x00000007U -#define PMU_DCDC_PCUR_LIMIT_S 23 -/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1; - * need_des - */ -#define PMU_DCDC_BIAS_CAL_DONE (BIT(26)) -#define PMU_DCDC_BIAS_CAL_DONE_M (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S) -#define PMU_DCDC_BIAS_CAL_DONE_V 0x00000001U -#define PMU_DCDC_BIAS_CAL_DONE_S 26 -/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0; - * need_des - */ -#define PMU_DCDC_CCM_SW_EN (BIT(27)) -#define PMU_DCDC_CCM_SW_EN_M (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S) -#define PMU_DCDC_CCM_SW_EN_V 0x00000001U -#define PMU_DCDC_CCM_SW_EN_S 27 -/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_DCDC_VCM_ENB (BIT(28)) -#define PMU_DCDC_VCM_ENB_M (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S) -#define PMU_DCDC_VCM_ENB_V 0x00000001U -#define PMU_DCDC_VCM_ENB_S 28 -/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_DCDC_CCM_RDY (BIT(29)) -#define PMU_DCDC_CCM_RDY_M (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S) -#define PMU_DCDC_CCM_RDY_V 0x00000001U -#define PMU_DCDC_CCM_RDY_S 29 -/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_DCDC_VCM_RDY (BIT(30)) -#define PMU_DCDC_VCM_RDY_M (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S) -#define PMU_DCDC_VCM_RDY_V 0x00000001U -#define PMU_DCDC_VCM_RDY_S 30 -/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_DCDC_RDY_CLR (BIT(31)) -#define PMU_DCDC_RDY_CLR_M (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S) -#define PMU_DCDC_RDY_CLR_V 0x00000001U -#define PMU_DCDC_RDY_CLR_S 31 - -/** PMU_TOUCH_PWR_CTRL_REG register - * need_des - */ -#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) -/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU -#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) -#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU -#define PMU_TOUCH_SLEEP_CYCLES_S 0 -/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0; - * need_des - */ -#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU -#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) -#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU -#define PMU_TOUCH_WAIT_CYCLES_S 21 -/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(30)) -#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) -#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U -#define PMU_TOUCH_SLEEP_TIMER_EN_S 30 -/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_TOUCH_FORCE_DONE (BIT(31)) -#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) -#define PMU_TOUCH_FORCE_DONE_V 0x00000001U -#define PMU_TOUCH_FORCE_DONE_S 31 +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35688960; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/pmu_struct.h b/components/soc/esp32h21/register/soc/pmu_struct.h index 92561a1d4f..178613d23b 100644 --- a/components/soc/esp32h21/register/soc/pmu_struct.h +++ b/components/soc/esp32h21/register/soc/pmu_struct.h @@ -6,2946 +6,765 @@ #pragma once #include +#include "soc/pmu_reg.h" #ifdef __cplusplus extern "C" { #endif -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:18; - /** hp_active_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_active_vdd_flash_mode:4; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:4; - /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_wifi_pd_en:1; - /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_peri_pd_en:1; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_aon_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; -} pmu_hp_active_dig_power_reg_t; +} pmu_hp_dig_power_reg_t; -/** Type of hp_active_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; + uint32_t reserved0: 30; + uint32_t code : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; +} pmu_hp_icg_modem_reg_t; -/** Type of hp_active_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; + uint32_t reserved0 : 24; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; +} pmu_hp_sys_cntl_reg_t; -/** Type of hp_active_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; + uint32_t reserved0 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved1 : 1; }; uint32_t val; -} pmu_hp_active_icg_modem_reg_t; +} pmu_hp_clk_power_reg_t; -/** Type of hp_active_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; + uint32_t reserved0 : 24; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; +} pmu_hp_bias_reg_t; -/** Type of hp_active_hp_ck_power register - * need_des - */ typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bb_i2c:1; - /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll_i2c:1; - /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll:1; - uint32_t reserved_31:1; + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 2; + uint32_t hp_active_retention_mode : 1; + uint32_t hp_sleep2active_retention_en : 1; + uint32_t hp_modem2active_retention_en : 1; + uint32_t reserved2 : 1; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t reserved3 : 2; + uint32_t hp_sleep2active_backup_mode : 3; + uint32_t hp_modem2active_backup_mode : 3; + uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved5 : 1; + }; + struct { /* HP: Modem State */ + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code : 2; + uint32_t reserved7 : 4; + uint32_t hp_modem_retention_mode : 1; + uint32_t hp_sleep2modem_retention_en : 1; + uint32_t reserved8 : 2; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved9 : 4; + uint32_t hp_sleep2modem_backup_mode : 3; + uint32_t reserved10 : 6; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved11 : 2; + }; + struct { /* HP: Sleep State */ + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t hp_sleep_retention_mode : 1; + uint32_t reserved13 : 1; + uint32_t hp_modem2sleep_retention_en : 1; + uint32_t hp_active2sleep_retention_en : 1; + uint32_t reserved14 : 2; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t reserved15 : 3; + uint32_t hp_modem2sleep_backup_mode : 3; + uint32_t hp_active2sleep_backup_mode : 3; + uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; +} pmu_hp_backup_reg_t; -/** Type of hp_active_bias register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** hp_active_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_active_dcdc_ccm_enb:1; - /** hp_active_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_dcdc_clear_rdy:1; - /** hp_active_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 3; - * need_des - */ - uint32_t hp_active_dig_pmu_dpcur_bias:2; - /** hp_active_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 6; - * need_des - */ - uint32_t hp_active_dig_pmu_dsfmos:4; - /** hp_active_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_active_dcm_vset:5; - /** hp_active_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_active_dcm_mode:2; - /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_trx:1; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_active_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_discnnt_dig_rtc:1; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; }; uint32_t val; -} pmu_hp_active_bias_reg_t; +} pmu_hp_sysclk_reg_t; -/** Type of hp_active_backup register - * need_des - */ typedef union { struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:6; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:5; - /** hp_modem2active_backup_mode : R/W; bitpos: [27:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:5; - uint32_t reserved_28:1; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; + uint32_t power_det_bypass : 1; + uint32_t reserved0 : 3; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias : 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_backup_reg_t; +} pmu_hp_regulator0_reg_t; -/** Type of hp_active_backup_clk register - * need_des - */ typedef union { struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; + uint32_t reserved0: 8; + uint32_t drv_b : 24; }; uint32_t val; -} pmu_hp_active_backup_clk_reg_t; +} pmu_hp_regulator1_reg_t; -/** Type of hp_active_sysclk register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_sysclk_reg_t; +} pmu_hp_xtal_reg_t; -/** Type of hp_active_hp_regulator0 register - * need_des - */ +typedef struct pmu_hp_hw_regmap_t{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; + +/** */ typedef union { struct { - /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_active_hp_power_det_bypass:1; - uint32_t reserved_1:3; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; +} pmu_lp_regulator0_reg_t; -/** Type of hp_active_hp_regulator1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:8; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:24; + uint32_t reserved0: 28; + uint32_t drv_b : 4; }; uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; +} pmu_lp_regulator1_reg_t; -/** Type of hp_active_xtal register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_active_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtalx2:1; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_xtal_reg_t; +} pmu_lp_xtal_reg_t; -/** Type of hp_sleep_dig_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:18; - /** hp_sleep_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_flash_mode:4; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:4; - /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_wifi_pd_en:1; - /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_peri_pd_en:1; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_aon_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; + uint32_t reserved0 : 27; + uint32_t bod_source_sel : 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en : 1; }; uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; +} pmu_lp_dig_power_reg_t; -/** Type of hp_sleep_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; + uint32_t reserved0 : 27; + uint32_t xpd_lppll : 1; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; }; uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; +} pmu_lp_clk_power_reg_t; -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; +} pmu_lp_bias_reg_t; + +typedef struct pmu_lp_hw_regmap_t{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +} pmu_lp_hw_regmap_t; + -/** Type of hp_sleep_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t reserved0 : 18; + uint32_t tie_high_global_bbpll_icg: 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; +} pmu_imm_hp_clk_power_reg_t; -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; - -/** Type of hp_sleep_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bb_i2c:1; - /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll_i2c:1; - /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; - -/** Type of hp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** hp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_sleep_dcdc_ccm_enb:1; - /** hp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcdc_clear_rdy:1; - /** hp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dpcur_bias:2; - /** hp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dsfmos:4; - /** hp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_sleep_dcm_vset:5; - /** hp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcm_mode:2; - /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_trx:1; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_discnnt_dig_rtc:1; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - uint32_t reserved_10:6; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [24:20]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:5; - /** hp_active2sleep_backup_mode : R/W; bitpos: [29:25]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:5; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; - }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; - -/** Type of hp_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; - -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ -typedef union { - struct { - /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_power_det_bypass:1; - uint32_t reserved_1:15; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; - -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; - -/** Type of hp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtalx2:1; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_sleep_xtal_reg_t; - -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; - -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; - -/** Type of hp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** hp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_io_mode:4; - /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_bod_source_sel:1; - /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_vddbat_mode:2; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; - -/** Type of hp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_lppll:1; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; - -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; - -/** Type of lp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtalx2:1; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_lp_sleep_xtal_reg_t; - -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** lp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t lp_sleep_vdd_io_mode:4; - /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_bod_source_sel:1; - /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_vddbat_mode:2; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; - -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_lppll:1; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** lp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t lp_sleep_dcdc_ccm_enb:1; - /** lp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcdc_clear_rdy:1; - /** lp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dpcur_bias:2; - /** lp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dsfmos:4; - /** lp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t lp_sleep_dcm_vset:5; - /** lp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcm_mode:2; - uint32_t reserved_24:1; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** lp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_discnnt_dig_rtc:1; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_lp_sleep_bias_reg_t; - -/** Type of imm_hp_ck_power register - * need_des - */ -typedef union { - struct { - /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_global_bbpll_icg:1; - /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bb_i2c:1; - /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll_i2c:1; - /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll:1; - /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - /** tie_low_global_xtalx2_icg : WT; bitpos: [7]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtalx2_icg:1; - /** tie_low_xpd_xtalx2 : WT; bitpos: [8]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtalx2:1; - uint32_t reserved_9:14; - /** tie_high_xtalx2 : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t tie_high_xtalx2:1; - /** tie_high_global_xtalx2_icg : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtalx2_icg:1; - /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t tie_high_global_bbpll_icg:1; - /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bb_i2c:1; - /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll_i2c:1; - /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll:1; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; }; uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -/** Type of imm_hp_func_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -/** Type of imm_hp_apb_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -/** Type of imm_modem_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -/** Type of imm_lp_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; }; uint32_t val; } pmu_imm_lp_icg_reg_t; -/** Type of imm_pad_hold_all register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** tie_high_dig_pad_slp_sel : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_dig_pad_slp_sel:1; - /** tie_low_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_low_dig_pad_slp_sel:1; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; + uint32_t reserved0 : 28; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; }; uint32_t val; } pmu_imm_pad_hold_all_reg_t; -/** Type of imm_i2c_iso register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; }; uint32_t val; -} pmu_imm_i2c_iso_reg_t; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap_t{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; -/** Type of power_wait_timer0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_pd_wait_timer:9; + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer0_reg_t; -/** Type of power_wait_timer1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; - * need_des - */ - uint32_t dg_lp_powerdown_timer:7; - /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; - * need_des - */ - uint32_t dg_lp_powerup_timer:7; - /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_pd_wait_timer:9; + uint32_t reserved0 : 9; + uint32_t powerdown_timer: 7; + uint32_t powerup_timer : 7; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer1_reg_t; -/** Type of power_wait_timer2 register - * need_des - */ typedef union { struct { - /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; - * need_des - */ - uint32_t dg_lp_iso_wait_timer:8; - /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; - * need_des - */ - uint32_t dg_lp_rst_wait_timer:8; - /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; - * need_des - */ - uint32_t dg_hp_iso_wait_timer:8; - /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; - * need_des - */ - uint32_t dg_hp_rst_wait_timer:8; + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; -} pmu_power_wait_timer2_reg_t; +} pmu_power_domain_cntl_reg_t; -/** Type of power_pd_top_cntl register - * need_des - */ typedef union { struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - uint32_t reserved_11:16; - /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_pd_mask:5; + uint32_t force_hp_mem_iso : 4; + uint32_t force_hp_mem_pd : 4; + uint32_t reserved0 : 16; + uint32_t force_hp_mem_no_iso: 4; + uint32_t force_hp_mem_pu : 4; }; uint32_t val; -} pmu_power_pd_top_cntl_reg_t; +} pmu_power_memory_cntl_reg_t; -/** Type of power_pd_hpaon_cntl register - * need_des - */ typedef union { struct { - /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_aon_reset:1; - /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_aon_iso:1; - /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_aon_pu:1; - /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_reset:1; - /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_iso:1; - /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_aon_pd:1; - /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_mask:5; - uint32_t reserved_11:16; - /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_pd_mask:5; + uint32_t mem2_pd_mask: 5; + uint32_t mem1_pd_mask: 5; + uint32_t mem0_pd_mask: 5; + uint32_t reserved0 : 2; + uint32_t mem2_mask : 5; + uint32_t mem1_mask : 5; + uint32_t mem0_mask : 5; }; uint32_t val; -} pmu_power_pd_hpaon_cntl_reg_t; +} pmu_power_memory_mask_reg_t; -/** Type of power_pd_hpcpu_cntl register - * need_des - */ typedef union { struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - uint32_t reserved_11:16; - /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpcpu_cntl_reg_t; - -/** Type of power_pd_hpperi_reserve register - * need_des - */ -typedef union { - struct { - /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_peri_reset:1; - /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_peri_iso:1; - /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_peri_pu:1; - /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_reset:1; - /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_iso:1; - /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_peri_pd:1; - /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_mask:5; - uint32_t reserved_11:16; - /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpperi_reserve_reg_t; - -/** Type of power_pd_hpwifi_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_reset:1; - /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_iso:1; - /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_pu:1; - /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_reset:1; - /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_iso:1; - /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_pd:1; - /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_mask:5; - uint32_t reserved_11:16; - /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpwifi_cntl_reg_t; - -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_mem_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:4; - /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:4; - uint32_t reserved_8:16; - /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; - * need_des - */ - uint32_t force_hp_mem_no_iso:4; - /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; - * need_des - */ - uint32_t force_hp_mem_pu:4; - }; - uint32_t val; -} pmu_power_pd_mem_cntl_reg_t; - -/** Type of power_pd_mem_mask register - * need_des - */ -typedef union { - struct { - /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_pd_mask:5; - /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_pd_mask:5; - /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_pd_mask:5; - uint32_t reserved_15:2; - /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_mask:5; - /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_mask:5; - /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_mask:5; - }; - uint32_t val; -} pmu_power_pd_mem_mask_reg_t; - -/** Type of power_hp_pad register - * need_des - */ -typedef union { - struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; }; uint32_t val; } pmu_power_hp_pad_reg_t; -/** Type of power_flash1p8_ldo register - * need_des - */ typedef union { struct { - /** flash1p8_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p8_ldo_rdy:1; - /** flash1p8_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_xpd:1; - /** flash1p8_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_thru:1; - /** flash1p8_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_standby:1; - /** flash1p8_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_power_adjust:1; - /** flash1p8_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p8_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p8_bypass_ldo_rdy:1; - /** flash1p8_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p8_xpd:1; - /** flash1p8_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p8_thru:1; - /** flash1p8_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p8_standby:1; - /** flash1p8_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t flash1p8_power_adjust:5; - /** flash1p8_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p8_endet:1; + uint32_t reserved0 : 18; + uint32_t pwr_wait : 11; + uint32_t pwr_sw : 2; + uint32_t pwr_sel_sw: 1; }; uint32_t val; -} pmu_power_flash1p8_ldo_reg_t; +} pmu_power_vdd_spi_cntl_reg_t; -/** Type of power_flash1p2_ldo register - * need_des - */ typedef union { struct { - /** flash1p2_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p2_ldo_rdy:1; - /** flash1p2_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_xpd:1; - /** flash1p2_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_thru:1; - /** flash1p2_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_standby:1; - /** flash1p2_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_power_adjust:1; - /** flash1p2_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p2_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p2_bypass_ldo_rdy:1; - /** flash1p2_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p2_xpd:1; - /** flash1p2_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p2_thru:1; - /** flash1p2_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p2_standby:1; - /** flash1p2_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t flash1p2_power_adjust:5; - /** flash1p2_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p2_endet:1; + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; }; uint32_t val; -} pmu_power_flash1p2_ldo_reg_t; +} pmu_power_clk_wait_cntl_reg_t; + +typedef struct pmu_power_hw_regmap_t{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_domain_cntl_reg_t hp_pd[5]; + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_vdd_spi_cntl_reg_t vdd_spi; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; -/** Type of power_vdd_flash register - * need_des - */ typedef union { struct { - uint32_t reserved_0:22; - /** flash_ldo_sw_en_tiel : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_tiel:1; - /** flash_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash_ldo_power_sel:1; - /** flash_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_power_sel:1; - /** flash_ldo_wait_target : R/W; bitpos: [28:25]; default: 15; - * need_des - */ - uint32_t flash_ldo_wait_target:4; - /** flash_ldo_tiel_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel_en:1; - /** flash_ldo_tiel : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel:1; - /** flash_ldo_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_update:1; - }; - uint32_t val; -} pmu_power_vdd_flash_reg_t; - -/** Type of power_io_ldo register - * need_des - */ -typedef union { - struct { - /** io_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t io_ldo_rdy:1; - /** io_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t io_sw_en_xpd:1; - uint32_t reserved_2:1; - /** io_sw_en_thru : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t io_sw_en_thru:1; - /** io_sw_en_standby : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t io_sw_en_standby:1; - /** io_sw_en_power_adjust : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t io_sw_en_power_adjust:1; - /** io_sw_en_endet : R/W; bitpos: [6]; default: 0; - * need_des - */ - uint32_t io_sw_en_endet:1; - uint32_t reserved_7:15; - /** io_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t io_bypass_ldo_rdy:1; - /** io_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_xpd:1; - /** io_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t io_thru:1; - /** io_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t io_standby:1; - /** io_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t io_power_adjust:5; - /** io_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t io_endet:1; - }; - uint32_t val; -} pmu_power_io_ldo_reg_t; - -/** Type of power_vdd_io register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** io_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_ldo_power_sel:1; - /** io_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t io_ldo_sw_en_power_sel:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} pmu_power_vdd_io_reg_t; - -/** Type of power_ck_wait_cntl register - * need_des - */ -typedef union { - struct { - /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; - * need_des - */ - uint32_t wait_xtl_stable:16; - /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t wait_pll_stable:16; - }; - uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; - -/** Type of slp_wakeup_cntl0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; + uint32_t reserved0: 31; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -/** Type of slp_wakeup_cntl1 register - * need_des - */ typedef union { struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -/** Type of slp_wakeup_cntl2 register - * need_des - */ typedef union { struct { - /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:32; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; }; uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -/** Type of slp_wakeup_cntl4 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -/** Type of slp_wakeup_cntl5 register - * need_des - */ typedef union { struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:4; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; }; uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -/** Type of slp_wakeup_cntl6 register - * need_des - */ typedef union { struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; }; uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -/** Type of slp_wakeup_cntl7 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:15; - /** ana_wait_clk_sel : R/W; bitpos: [15]; default: 0; - * need_des - */ - uint32_t ana_wait_clk_sel:1; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; + uint32_t reserved0 : 16; + uint32_t ana_wait_target: 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -/** Type of slp_wakeup_status0 register - * need_des - */ +typedef struct pmu_wakeup_hw_regmap_t{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; +} pmu_wakeup_hw_regmap_t; + typedef union { struct { - /** wakeup_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:32; + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; }; uint32_t val; -} pmu_slp_wakeup_status0_reg_t; +} pmu_hp_clk_poweron_reg_t; -/** Type of slp_wakeup_status1 register - * need_des - */ typedef union { struct { - /** reject_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t reject_cause:32; + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; }; uint32_t val; -} pmu_slp_wakeup_status1_reg_t; +} pmu_hp_clk_cntl_reg_t; -/** Type of hp_ck_poweron register - * need_des - */ typedef union { struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} pmu_hp_ck_poweron_reg_t; - -/** Type of hp_ck_cntl register - * need_des - */ -typedef union { - struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} pmu_hp_ck_cntl_reg_t; - -/** Type of por_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t por_done:1; + uint32_t reserved0: 31; + uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -/** Type of rf_pwc register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** xpd_force_rftx : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t xpd_force_rftx:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_rftx_i2c:1; - /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_i2c:1; - /** xpd_rfpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_rfpll:1; - /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t xpd_force_rfpll:1; + uint32_t reserved0 : 27; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_rftx_i2c : 1; + uint32_t xpd_rfrx_i2c : 1; + uint32_t xpd_rfpll : 1; + uint32_t xpd_force_rfpll: 1; }; uint32_t val; } pmu_rf_pwc_reg_t; -/** Type of vddbat_cfg register - * need_des - */ typedef union { struct { - /** vddbat_mode : RO; bitpos: [1:0]; default: 0; - * need_des - */ - uint32_t vddbat_mode:2; - uint32_t reserved_2:29; - /** vddbat_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vddbat_sw_update:1; + uint32_t ana_vddbat_mode : 2; + uint32_t reserved2 : 29; + uint32_t vddbat_sw_update : 1; }; uint32_t val; } pmu_vddbat_cfg_reg_t; -/** Type of backup_cfg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -/** Type of int_raw register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; + uint32_t reserved0 : 27; + uint32_t lp_exception: 1; + uint32_t sdio_idle: 1; + uint32_t sw : 1; + uint32_t reject : 1; + uint32_t wakeup : 1; }; uint32_t val; -} pmu_int_raw_reg_t; +} pmu_hp_intr_reg_t; + +typedef struct pmu_hp_ext_hw_regmap_t{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_vddbat_cfg_reg_t vddbat_cfg; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; -/** Type of hp_int_st register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; + uint32_t reserved0 : 20; + uint32_t lp_wakeup : 1; + uint32_t modem_switch_active_end : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t sleep_switch_modem_end : 1; + uint32_t modem_switch_sleep_end : 1; + uint32_t active_switch_sleep_end : 1; + uint32_t modem_switch_active_start: 1; + uint32_t sleep_switch_active_start: 1; + uint32_t sleep_switch_modem_start : 1; + uint32_t modem_switch_sleep_start : 1; + uint32_t active_switch_sleep_start: 1; + uint32_t hp_sw_trigger : 1; }; uint32_t val; -} pmu_hp_int_st_reg_t; +} pmu_lp_intr_reg_t; -/** Type of hp_int_ena register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_raw:1; - /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_raw:1; - /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_st:1; - /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_st:1; - /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; - }; - uint32_t val; -} pmu_lp_int_st_reg_t; - -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_ena:1; - /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_ena:1; - /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; - -/** Type of lp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_clr:1; - /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_clr:1; - /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; - }; - uint32_t val; -} pmu_lp_int_clr_reg_t; - -/** Type of lp_cpu_pwr0 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; }; uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -/** Type of lp_cpu_pwr1 register - * need_des - */ typedef union { struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:16; - uint32_t reserved_16:15; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; + uint32_t wakeup_en: 16; + uint32_t reserved0: 15; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; - -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; - -/** Type of main_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** main_last_st_state : RO; bitpos: [17:11]; default: 256; - * need_des - */ - uint32_t main_last_st_state:7; - /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t main_tar_st_state:7; - /** main_cur_st_state : RO; bitpos: [31:25]; default: 1; - * need_des - */ - uint32_t main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; - -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t backup_st_state:5; - /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t lp_pwr_st_state:5; - /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; - -/** Type of dcm_ctrl register - * need_des - */ -typedef union { - struct { - /** dsfmos_use_por : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t dsfmos_use_por:1; - uint32_t reserved_1:21; - /** dcdc_dcm_update : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t dcdc_dcm_update:1; - /** dcdc_pcur_limit : R/W; bitpos: [25:23]; default: 1; - * need_des - */ - uint32_t dcdc_pcur_limit:3; - /** dcdc_bias_cal_done : RO; bitpos: [26]; default: 1; - * need_des - */ - uint32_t dcdc_bias_cal_done:1; - /** dcdc_ccm_sw_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_sw_en:1; - /** dcdc_vcm_enb : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t dcdc_vcm_enb:1; - /** dcdc_ccm_rdy : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_rdy:1; - /** dcdc_vcm_rdy : RO; bitpos: [30]; default: 1; - * need_des - */ - uint32_t dcdc_vcm_rdy:1; - /** dcdc_rdy_clr : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dcdc_rdy_clr:1; - }; - uint32_t val; -} pmu_dcm_ctrl_reg_t; - -/** Type of touch_pwr_ctrl register - * need_des - */ -typedef union { - struct { - /** touch_sleep_cycles : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t touch_sleep_cycles:16; - uint32_t reserved_16:5; - /** touch_wait_cycles : R/W; bitpos: [29:21]; default: 0; - * need_des - */ - uint32_t touch_wait_cycles:9; - /** touch_sleep_timer_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t touch_sleep_timer_en:1; - /** touch_force_done : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t touch_force_done:1; - }; - uint32_t val; -} pmu_touch_pwr_ctrl_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 37814400; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; - - -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t stable_xpd_bbpll_state:1; - /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - uint32_t reserved_2:13; - /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t sys_clk_slp_sel_state:1; - /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sys_clk_sel_state:2; - /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t sys_clk_no_div_state:1; - /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 1; - * need_des - */ - uint32_t icg_sys_clk_en_state:1; - /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t icg_modem_switch_state:1; - /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; - * need_des - */ - uint32_t icg_modem_code_state:2; - /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t icg_slp_sel_state:1; - /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t icg_global_xtal_state:1; - /** icg_global_pll_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t icg_global_pll_state:1; - /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_i2c_iso_en_state:1; - /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_i2c_retention_state:1; - /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t ana_xpd_bb_i2c_state:1; - /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_i2c_state:1; - /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_state:1; - /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; - -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; - -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; - +typedef struct pmu_lp_ext_hw_regmap_t{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; +} pmu_lp_ext_hw_regmap_t; typedef struct { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - uint32_t reserved_034[13]; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - uint32_t reserved_0a4; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - uint32_t reserved_0b0; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_wait_timer2_reg_t power_wait_timer2; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; - volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; - volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; - volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; - volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_flash1p8_ldo_reg_t power_flash1p8_ldo; - volatile pmu_power_flash1p2_ldo_reg_t power_flash1p2_ldo; - volatile pmu_power_vdd_flash_reg_t power_vdd_flash; - volatile pmu_power_io_ldo_reg_t power_io_ldo; - volatile pmu_power_vdd_io_reg_t power_vdd_io; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_vddbat_cfg_reg_t vddbat_cfg; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_dcm_ctrl_reg_t dcm_ctrl; - volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; - uint32_t reserved_1c0[143]; - volatile pmu_date_reg_t date; + volatile struct { + } common; +} pmu_hp_lp_hw_regmap_t; + +typedef struct pmu_dev_t{ + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; + + union { + struct { + uint32_t reserved0 : 30; + volatile uint32_t lp_trigger_hp: 1; + volatile uint32_t hp_trigger_lp: 1; + }; + volatile uint32_t val; + } hp_lp_cpu_comm; + + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t dig_regulator_en_cal: 1; + }; + volatile uint32_t val; + } hp_regulator_cfg; + + union { + struct { + uint32_t reserved0 : 11; + volatile uint32_t last_st : 7; + volatile uint32_t target_st : 7; + volatile uint32_t current_st: 7; + }; + volatile uint32_t val; + } main_state; + + union { + struct { + uint32_t reserved0: 13; + volatile uint32_t backup_st: 5; + volatile uint32_t lp_pwr_st: 5; + volatile uint32_t hp_pwr_st: 9; + }; + volatile uint32_t val; + } pwr_state; + + union { + struct { + volatile uint32_t stable_xpd_bbpll : 1; + volatile uint32_t stable_xpd_xtal : 1; + volatile uint32_t reserved0 : 13; + volatile uint32_t sysclk_slp_sel : 1; + volatile uint32_t sysclk_sel : 2; + volatile uint32_t sysclk_nodiv : 1; + volatile uint32_t icg_sysclk_en : 1; + volatile uint32_t icg_modem_switch : 1; + volatile uint32_t icg_modem_code : 2; + volatile uint32_t icg_slp_sel : 1; + volatile uint32_t icg_global_xtal : 1; + volatile uint32_t icg_global_pll : 1; + volatile uint32_t ana_i2c_iso_en : 1; + volatile uint32_t ana_i2c_retention: 1; + volatile uint32_t ana_xpd_bb_i2c : 1; + volatile uint32_t ana_xpd_bbpll_i2c: 1; + volatile uint32_t ana_xpd_bbpll : 1; + volatile uint32_t ana_xpd_xtal : 1; + }; + volatile uint32_t val; + } clk_state0; + + volatile uint32_t clk_state1; + volatile uint32_t clk_state2; + + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t stable_vdd_spi_pwr_drv: 1; + }; + volatile uint32_t val; + } vdd_spi_status; + + uint32_t reserved[149]; + + union { + struct { + volatile uint32_t pmu_date: 31; + volatile uint32_t clk_en : 1; + }; + volatile uint32_t val; + } date; } pmu_dev_t; extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); + +// _Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); + #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/spi1_mem_reg.h b/components/soc/esp32h21/register/soc/spi1_mem_reg.h index b17d087a9a..1f3373b514 100644 --- a/components/soc/esp32h21/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32h21/register/soc/spi1_mem_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SPI_MEM_CMD_REG register * SPI1 memory command register */ -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +#define SPI_MEM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x0) /** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; * The current status of SPI1 master FSM. */ @@ -172,7 +172,7 @@ extern "C" { /** SPI_MEM_ADDR_REG register * SPI1 address register */ -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +#define SPI_MEM_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x4) /** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; * In user mode, it is the memory address. other then the bit0-bit23 is the memory * address, the bit24-bit31 are the byte length of a transfer. @@ -185,7 +185,7 @@ extern "C" { /** SPI_MEM_CTRL_REG register * SPI1 control register. */ -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +#define SPI_MEM_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8) /** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal * level of SPI bus is output by the MSPI controller. @@ -335,7 +335,7 @@ extern "C" { /** SPI_MEM_CTRL1_REG register * SPI1 control1 register. */ -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc) +#define SPI_MEM_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc) /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: @@ -365,7 +365,7 @@ extern "C" { /** SPI_MEM_CTRL2_REG register * SPI1 control2 register. */ -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +#define SPI_MEM_CTRL2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10) /** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; * The FSM will be reset. */ @@ -377,7 +377,7 @@ extern "C" { /** SPI_MEM_CLOCK_REG register * SPI1 clock division control register. */ -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +#define SPI_MEM_CLOCK_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ @@ -411,7 +411,7 @@ extern "C" { /** SPI_MEM_USER_REG register * SPI1 user register. */ -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +#define SPI_MEM_USER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18) /** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ @@ -511,7 +511,7 @@ extern "C" { /** SPI_MEM_USER1_REG register * SPI1 user1 register. */ -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c) +#define SPI_MEM_USER1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1c) /** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). @@ -531,7 +531,7 @@ extern "C" { /** SPI_MEM_USER2_REG register * SPI1 user2 register. */ -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +#define SPI_MEM_USER2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20) /** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. */ @@ -550,7 +550,7 @@ extern "C" { /** SPI_MEM_MOSI_DLEN_REG register * SPI1 send data bit length control register. */ -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +#define SPI_MEM_MOSI_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x24) /** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; * The length in bits of write-data. The register value shall be (bit_num-1). */ @@ -562,7 +562,7 @@ extern "C" { /** SPI_MEM_MISO_DLEN_REG register * SPI1 receive data bit length control register. */ -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +#define SPI_MEM_MISO_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x28) /** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; * The length in bits of read-data. The register value shall be (bit_num-1). */ @@ -574,7 +574,7 @@ extern "C" { /** SPI_MEM_RD_STATUS_REG register * SPI1 status register. */ -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c) +#define SPI_MEM_RD_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c) /** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0; * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ @@ -610,7 +610,7 @@ extern "C" { /** SPI_MEM_MISC_REG register * SPI1 misc register */ -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +#define SPI_MEM_MISC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34) /** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0; * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI * device, such as flash, external RAM and so on. @@ -647,7 +647,7 @@ extern "C" { * This register is only for internal debugging purposes. Do not use it in * applications. */ -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +#define SPI_MEM_TX_CRC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x38) /** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. * This field is only for internal debugging purposes. Do not use it in applications. @@ -662,7 +662,7 @@ extern "C" { * This register is only for internal debugging purposes. Do not use it in * applications. */ -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) +#define SPI_MEM_CACHE_FCTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. @@ -729,7 +729,7 @@ extern "C" { /** SPI_MEM_W0_REG register * SPI1 memory data buffer0 */ -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +#define SPI_MEM_W0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x58) /** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -741,7 +741,7 @@ extern "C" { /** SPI_MEM_W1_REG register * SPI1 memory data buffer1 */ -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c) +#define SPI_MEM_W1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x5c) /** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -753,7 +753,7 @@ extern "C" { /** SPI_MEM_W2_REG register * SPI1 memory data buffer2 */ -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +#define SPI_MEM_W2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x60) /** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -765,7 +765,7 @@ extern "C" { /** SPI_MEM_W3_REG register * SPI1 memory data buffer3 */ -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +#define SPI_MEM_W3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x64) /** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -777,7 +777,7 @@ extern "C" { /** SPI_MEM_W4_REG register * SPI1 memory data buffer4 */ -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +#define SPI_MEM_W4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x68) /** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -789,7 +789,7 @@ extern "C" { /** SPI_MEM_W5_REG register * SPI1 memory data buffer5 */ -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c) +#define SPI_MEM_W5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x6c) /** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -801,7 +801,7 @@ extern "C" { /** SPI_MEM_W6_REG register * SPI1 memory data buffer6 */ -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +#define SPI_MEM_W6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x70) /** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -813,7 +813,7 @@ extern "C" { /** SPI_MEM_W7_REG register * SPI1 memory data buffer7 */ -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +#define SPI_MEM_W7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x74) /** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -825,7 +825,7 @@ extern "C" { /** SPI_MEM_W8_REG register * SPI1 memory data buffer8 */ -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +#define SPI_MEM_W8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x78) /** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -837,7 +837,7 @@ extern "C" { /** SPI_MEM_W9_REG register * SPI1 memory data buffer9 */ -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c) +#define SPI_MEM_W9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x7c) /** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -849,7 +849,7 @@ extern "C" { /** SPI_MEM_W10_REG register * SPI1 memory data buffer10 */ -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +#define SPI_MEM_W10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x80) /** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -861,7 +861,7 @@ extern "C" { /** SPI_MEM_W11_REG register * SPI1 memory data buffer11 */ -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +#define SPI_MEM_W11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x84) /** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -873,7 +873,7 @@ extern "C" { /** SPI_MEM_W12_REG register * SPI1 memory data buffer12 */ -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +#define SPI_MEM_W12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x88) /** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -885,7 +885,7 @@ extern "C" { /** SPI_MEM_W13_REG register * SPI1 memory data buffer13 */ -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c) +#define SPI_MEM_W13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8c) /** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -897,7 +897,7 @@ extern "C" { /** SPI_MEM_W14_REG register * SPI1 memory data buffer14 */ -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +#define SPI_MEM_W14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x90) /** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -909,7 +909,7 @@ extern "C" { /** SPI_MEM_W15_REG register * SPI1 memory data buffer15 */ -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +#define SPI_MEM_W15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x94) /** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -921,7 +921,7 @@ extern "C" { /** SPI_MEM_FLASH_WAITI_CTRL_REG register * SPI1 wait idle control register */ -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x98) /** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1; * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto @@ -980,7 +980,7 @@ extern "C" { /** SPI_MEM_FLASH_SUS_CTRL_REG register * SPI1 flash suspend control register */ -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c) +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x9c) /** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; * program erase resume bit, program erase suspend operation will be triggered when * the bit is set. The bit will be cleared once the operation done.1: enable 0: @@ -1078,7 +1078,7 @@ extern "C" { /** SPI_MEM_FLASH_SUS_CMD_REG register * SPI1 flash suspend command register */ -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0) +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa0) /** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; * Program/Erase suspend command. */ @@ -1098,7 +1098,7 @@ extern "C" { /** SPI_MEM_SUS_STATUS_REG register * SPI1 flash suspend status register */ -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4) +#define SPI_MEM_SUS_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa4) /** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; * The status of flash suspend, only used in SPI1. */ @@ -1187,7 +1187,7 @@ extern "C" { /** SPI_MEM_FLASH_WAITI_CTRL1_REG register * SPI1 wait idle control register */ -#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac) +#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xac) /** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0; * SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE. */ @@ -1206,7 +1206,7 @@ extern "C" { /** SPI_MEM_INT_ENA_REG register * SPI1 interrupt enable register */ -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0) +#define SPI_MEM_INT_ENA_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc0) /** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; * The enable bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1253,7 +1253,7 @@ extern "C" { /** SPI_MEM_INT_CLR_REG register * SPI1 interrupt clear register */ -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4) +#define SPI_MEM_INT_CLR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc4) /** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; * The clear bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1300,7 +1300,7 @@ extern "C" { /** SPI_MEM_INT_RAW_REG register * SPI1 interrupt raw register */ -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8) +#define SPI_MEM_INT_RAW_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc8) /** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume * command (0x7A) is sent and flash is resumed successfully. 0: Others. @@ -1356,7 +1356,7 @@ extern "C" { /** SPI_MEM_INT_ST_REG register * SPI1 interrupt status register */ -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc) +#define SPI_MEM_INT_ST_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xcc) /** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0; * The status bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1403,7 +1403,7 @@ extern "C" { /** SPI_MEM_DDR_REG register * SPI1 DDR control register */ -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) +#define SPI_MEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd4) /** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in ddr mode, 0 in sdr mode */ @@ -1512,7 +1512,7 @@ extern "C" { /** SPI_MEM_TIMING_CALI_REG register * SPI1 timing control register */ -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +#define SPI_MEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x180) /** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; * The bit is used to enable timing auto-calibration for all reading operations. */ @@ -1531,7 +1531,7 @@ extern "C" { /** SPI_MEM_CLOCK_GATE_REG register * SPI1 clk_gate register */ -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +#define SPI_MEM_CLOCK_GATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x200) /** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ @@ -1543,7 +1543,7 @@ extern "C" { /** SPI_MEM_DATE_REG register * Version control register */ -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) +#define SPI_MEM_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3fc) /** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37786176; * Version control register */ diff --git a/components/soc/esp32h21/register/soc/spi_mem_c_reg.h b/components/soc/esp32h21/register/soc/spi_mem_c_reg.h index 2e78ce4206..04d77b6a1a 100644 --- a/components/soc/esp32h21/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32h21/register/soc/spi_mem_c_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SPI_MEM_CMD_REG register * SPI0 FSM status register */ -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +#define SPI_MEM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x0) /** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent @@ -46,7 +46,7 @@ extern "C" { /** SPI_MEM_ADDR_REG register * SPI0 USR_CMD address register */ -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +#define SPI_MEM_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x4) /** SPI_MEM_USR_ADDR_VALUE : HRO; bitpos: [31:0]; default: 0; * In SPI0 USR_CMD mode when SPI_MEM_USR is set, it is the memory address. */ @@ -58,7 +58,7 @@ extern "C" { /** SPI_MEM_CTRL_REG register * SPI0 control register. */ -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +#define SPI_MEM_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8) /** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. @@ -207,7 +207,7 @@ extern "C" { /** SPI_MEM_CTRL1_REG register * SPI0 control1 register. */ -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc) +#define SPI_MEM_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc) /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: @@ -302,7 +302,7 @@ extern "C" { /** SPI_MEM_CTRL2_REG register * SPI0 control2 register. */ -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +#define SPI_MEM_CTRL2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10) /** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with * SPI_MEM_CS_SETUP bit. @@ -372,7 +372,7 @@ extern "C" { /** SPI_MEM_CLOCK_REG register * SPI clock division control register. */ -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +#define SPI_MEM_CLOCK_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ @@ -407,7 +407,7 @@ extern "C" { /** SPI_MEM_USER_REG register * SPI0 user register. */ -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +#define SPI_MEM_USER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18) /** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; * spi cs keep low when spi is in done phase. 1: enable 0: disable. */ @@ -447,7 +447,7 @@ extern "C" { /** SPI_MEM_USER1_REG register * SPI0 user1 register. */ -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c) +#define SPI_MEM_USER1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1c) /** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). @@ -474,7 +474,7 @@ extern "C" { /** SPI_MEM_USER2_REG register * SPI0 user2 register. */ -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +#define SPI_MEM_USER2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20) /** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. */ @@ -493,7 +493,7 @@ extern "C" { /** SPI_MEM_MISC_REG register * SPI0 misc register */ -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +#define SPI_MEM_MISC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34) /** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -526,7 +526,7 @@ extern "C" { /** SPI_MEM_CACHE_FCTRL_REG register * SPI0 bit mode control register. */ -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) +#define SPI_MEM_CACHE_FCTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -546,7 +546,7 @@ extern "C" { /** SPI_MEM_SRAM_CMD_REG register * SPI0 external RAM mode control register */ -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +#define SPI_MEM_SRAM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x44) /** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -583,7 +583,7 @@ extern "C" { /** SPI_MEM_FSM_REG register * SPI0 FSM status register */ -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +#define SPI_MEM_FSM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x54) /** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ @@ -609,7 +609,7 @@ extern "C" { /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register */ -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0) +#define SPI_MEM_INT_ENA_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc0) /** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -677,7 +677,7 @@ extern "C" { /** SPI_MEM_INT_CLR_REG register * SPI0 interrupt clear register */ -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4) +#define SPI_MEM_INT_CLR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc4) /** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -745,7 +745,7 @@ extern "C" { /** SPI_MEM_INT_RAW_REG register * SPI0 interrupt raw register */ -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8) +#define SPI_MEM_INT_RAW_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc8) /** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: @@ -831,7 +831,7 @@ extern "C" { /** SPI_MEM_INT_ST_REG register * SPI0 interrupt status register */ -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc) +#define SPI_MEM_INT_ST_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xcc) /** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -899,7 +899,7 @@ extern "C" { /** SPI_MEM_DDR_REG register * SPI0 flash DDR mode control register */ -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) +#define SPI_MEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd4) /** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ @@ -1024,7 +1024,7 @@ extern "C" { /** SPI_SMEM_DDR_REG register * SPI0 external RAM DDR mode control register */ -#define SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd8) +#define SPI_SMEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd8) /** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ @@ -1150,7 +1150,7 @@ extern "C" { /** SPI_FMEM_PMS0_ATTR_REG register * SPI1 flash PMS section 0 attribute register */ -#define SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +#define SPI_FMEM_PMS0_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x100) /** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ @@ -1178,7 +1178,7 @@ extern "C" { /** SPI_FMEM_PMS1_ATTR_REG register * SPI1 flash PMS section 1 attribute register */ -#define SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +#define SPI_FMEM_PMS1_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x104) /** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. */ @@ -1206,7 +1206,7 @@ extern "C" { /** SPI_FMEM_PMS2_ATTR_REG register * SPI1 flash PMS section 2 attribute register */ -#define SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +#define SPI_FMEM_PMS2_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x108) /** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. */ @@ -1234,7 +1234,7 @@ extern "C" { /** SPI_FMEM_PMS3_ATTR_REG register * SPI1 flash PMS section 3 attribute register */ -#define SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10c) +#define SPI_FMEM_PMS3_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10c) /** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. */ @@ -1262,7 +1262,7 @@ extern "C" { /** SPI_FMEM_PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +#define SPI_FMEM_PMS0_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x110) /** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 0 start address value */ @@ -1274,7 +1274,7 @@ extern "C" { /** SPI_FMEM_PMS1_ADDR_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +#define SPI_FMEM_PMS1_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x114) /** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 1 start address value */ @@ -1286,7 +1286,7 @@ extern "C" { /** SPI_FMEM_PMS2_ADDR_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +#define SPI_FMEM_PMS2_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x118) /** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 2 start address value */ @@ -1298,7 +1298,7 @@ extern "C" { /** SPI_FMEM_PMS3_ADDR_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11c) +#define SPI_FMEM_PMS3_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x11c) /** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 3 start address value */ @@ -1310,7 +1310,7 @@ extern "C" { /** SPI_FMEM_PMS0_SIZE_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +#define SPI_FMEM_PMS0_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x120) /** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) @@ -1323,7 +1323,7 @@ extern "C" { /** SPI_FMEM_PMS1_SIZE_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +#define SPI_FMEM_PMS1_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x124) /** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) @@ -1336,7 +1336,7 @@ extern "C" { /** SPI_FMEM_PMS2_SIZE_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +#define SPI_FMEM_PMS2_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x128) /** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) @@ -1349,7 +1349,7 @@ extern "C" { /** SPI_FMEM_PMS3_SIZE_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12c) +#define SPI_FMEM_PMS3_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x12c) /** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) @@ -1362,7 +1362,7 @@ extern "C" { /** SPI_SMEM_PMS0_ATTR_REG register * SPI1 external RAM PMS section 0 attribute register */ -#define SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +#define SPI_SMEM_PMS0_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x130) /** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. */ @@ -1390,7 +1390,7 @@ extern "C" { /** SPI_SMEM_PMS1_ATTR_REG register * SPI1 external RAM PMS section 1 attribute register */ -#define SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +#define SPI_SMEM_PMS1_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x134) /** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. */ @@ -1418,7 +1418,7 @@ extern "C" { /** SPI_SMEM_PMS2_ATTR_REG register * SPI1 external RAM PMS section 2 attribute register */ -#define SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +#define SPI_SMEM_PMS2_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x138) /** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. */ @@ -1446,7 +1446,7 @@ extern "C" { /** SPI_SMEM_PMS3_ATTR_REG register * SPI1 external RAM PMS section 3 attribute register */ -#define SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13c) +#define SPI_SMEM_PMS3_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x13c) /** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. */ @@ -1474,7 +1474,7 @@ extern "C" { /** SPI_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +#define SPI_SMEM_PMS0_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x140) /** SPI_SMEM_PMS0_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 0 start address value */ @@ -1486,7 +1486,7 @@ extern "C" { /** SPI_SMEM_PMS1_ADDR_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +#define SPI_SMEM_PMS1_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x144) /** SPI_SMEM_PMS1_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 1 start address value */ @@ -1498,7 +1498,7 @@ extern "C" { /** SPI_SMEM_PMS2_ADDR_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +#define SPI_SMEM_PMS2_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x148) /** SPI_SMEM_PMS2_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 2 start address value */ @@ -1510,7 +1510,7 @@ extern "C" { /** SPI_SMEM_PMS3_ADDR_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14c) +#define SPI_SMEM_PMS3_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14c) /** SPI_SMEM_PMS3_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 3 start address value */ @@ -1522,7 +1522,7 @@ extern "C" { /** SPI_SMEM_PMS0_SIZE_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +#define SPI_SMEM_PMS0_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x150) /** SPI_SMEM_PMS0_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) @@ -1535,7 +1535,7 @@ extern "C" { /** SPI_SMEM_PMS1_SIZE_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +#define SPI_SMEM_PMS1_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x154) /** SPI_SMEM_PMS1_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) @@ -1548,7 +1548,7 @@ extern "C" { /** SPI_SMEM_PMS2_SIZE_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +#define SPI_SMEM_PMS2_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x158) /** SPI_SMEM_PMS2_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) @@ -1561,7 +1561,7 @@ extern "C" { /** SPI_SMEM_PMS3_SIZE_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15c) +#define SPI_SMEM_PMS3_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x15c) /** SPI_SMEM_PMS3_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) @@ -1574,7 +1574,7 @@ extern "C" { /** SPI_MEM_PMS_REJECT_REG register * SPI1 access reject register */ -#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x160) +#define SPI_MEM_PMS_REJECT_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x160) /** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ @@ -1618,7 +1618,7 @@ extern "C" { /** SPI_MEM_PMS_REJECT_ADDR_REG register * SPI1 access reject addr register */ -#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x164) /** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when * SPI_MEM_PMS_REJECT_INT_CLR bit is set. @@ -1631,7 +1631,7 @@ extern "C" { /** SPI_MEM_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +#define SPI_MEM_ECC_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x168) /** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. @@ -1699,7 +1699,7 @@ extern "C" { /** SPI_MEM_ECC_ERR_ADDR_REG register * MSPI ECC error address register */ -#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16c) +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x16c) /** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. @@ -1712,7 +1712,7 @@ extern "C" { /** SPI_MEM_AXI_ERR_ADDR_REG register * SPI0 AXI request error address. */ -#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x170) /** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, @@ -1726,7 +1726,7 @@ extern "C" { /** SPI_SMEM_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +#define SPI_SMEM_ECC_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x174) /** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. @@ -1756,7 +1756,7 @@ extern "C" { /** SPI_SMEM_AXI_ADDR_CTRL_REG register * SPI0 AXI address control register */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x178) +#define SPI_SMEM_AXI_ADDR_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x178) /** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers * and SPI0 transfers are done. 0: Others. @@ -1805,7 +1805,7 @@ extern "C" { /** SPI_MEM_AXI_ERR_RESP_EN_REG register * SPI0 AXI error response enable register */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x17c) +#define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x17c) /** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ @@ -1895,7 +1895,7 @@ extern "C" { /** SPI_MEM_TIMING_CALI_REG register * SPI0 flash timing calibration register */ -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +#define SPI_MEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x180) /** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * The bit is used to enable timing adjust clock for all reading operations. */ @@ -1936,7 +1936,7 @@ extern "C" { /** SPI_MEM_DIN_MODE_REG register * MSPI flash input timing delay mode control register */ -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +#define SPI_MEM_DIN_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x184) /** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input @@ -2026,7 +2026,7 @@ extern "C" { /** SPI_MEM_DIN_NUM_REG register * MSPI flash input timing delay number control register */ -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +#define SPI_MEM_DIN_NUM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x188) /** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... @@ -2103,7 +2103,7 @@ extern "C" { /** SPI_MEM_DOUT_MODE_REG register * MSPI flash output timing adjustment control register */ -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18c) +#define SPI_MEM_DOUT_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18c) /** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: @@ -2193,7 +2193,7 @@ extern "C" { /** SPI_SMEM_TIMING_CALI_REG register * MSPI external RAM timing calibration register */ -#define SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +#define SPI_SMEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x190) /** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ @@ -2244,7 +2244,7 @@ extern "C" { /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register */ -#define SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +#define SPI_SMEM_DIN_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x194) /** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input @@ -2339,7 +2339,7 @@ extern "C" { /** SPI_SMEM_DIN_NUM_REG register * MSPI external RAM input timing delay number control register */ -#define SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +#define SPI_SMEM_DIN_NUM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x198) /** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... @@ -2416,7 +2416,7 @@ extern "C" { /** SPI_SMEM_DOUT_MODE_REG register * MSPI external RAM output timing adjustment control register */ -#define SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19c) +#define SPI_SMEM_DOUT_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x19c) /** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: @@ -2511,7 +2511,7 @@ extern "C" { /** SPI_SMEM_AC_REG register * MSPI external RAM ECC and SPI CS timing control register */ -#define SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1a0) +#define SPI_SMEM_AC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1a0) /** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. @@ -2589,7 +2589,7 @@ extern "C" { /** SPI_MEM_CLOCK_GATE_REG register * SPI0 clock gate register */ -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +#define SPI_MEM_CLOCK_GATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x200) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ @@ -2608,7 +2608,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_EN_REG register * NAND FLASH control register */ -#define SPI_MEM_NAND_FLASH_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x204) +#define SPI_MEM_NAND_FLASH_EN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x204) /** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: * Disable NAND FLASH, Enable NOR FLASH. @@ -2652,7 +2652,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG(i) (REG_SPI_MEM_BASE(i) + 0x208) +#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x208) /** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; * configure state register address for SPI SEQ need. If OIP is in address C0H , user * could configure C0H into this register @@ -2689,7 +2689,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SR_DIN0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SR_DIN0_REG(i) (REG_SPI_MEM_BASE(i) + 0x20c) +#define SPI_MEM_NAND_FLASH_SR_DIN0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20c) /** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; * spi read state register data to this register for SPI SEQ need. * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. @@ -2726,7 +2726,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG(i) (REG_SPI_MEM_BASE(i) + 0x210) +#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x210) /** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2747,7 +2747,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG(i) (REG_SPI_MEM_BASE(i) + 0x214) +#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x214) /** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2768,7 +2768,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG(i) (REG_SPI_MEM_BASE(i) + 0x218) +#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x218) /** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2789,7 +2789,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG(i) (REG_SPI_MEM_BASE(i) + 0x240) +#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x240) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 0. */ @@ -2841,7 +2841,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT1_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT1_REG(i) (REG_SPI_MEM_BASE(i) + 0x244) +#define SPI_MEM_NAND_FLASH_CMD_LUT1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x244) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE1 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 1. */ @@ -2893,7 +2893,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT2_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT2_REG(i) (REG_SPI_MEM_BASE(i) + 0x248) +#define SPI_MEM_NAND_FLASH_CMD_LUT2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x248) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE2 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 2. */ @@ -2945,7 +2945,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT3_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT3_REG(i) (REG_SPI_MEM_BASE(i) + 0x24c) +#define SPI_MEM_NAND_FLASH_CMD_LUT3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x24c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE3 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 3. */ @@ -2997,7 +2997,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT4_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT4_REG(i) (REG_SPI_MEM_BASE(i) + 0x250) +#define SPI_MEM_NAND_FLASH_CMD_LUT4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x250) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE4 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 4. */ @@ -3049,7 +3049,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT5_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT5_REG(i) (REG_SPI_MEM_BASE(i) + 0x254) +#define SPI_MEM_NAND_FLASH_CMD_LUT5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x254) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE5 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 5. */ @@ -3101,7 +3101,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT6_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT6_REG(i) (REG_SPI_MEM_BASE(i) + 0x258) +#define SPI_MEM_NAND_FLASH_CMD_LUT6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x258) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE6 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 6. */ @@ -3153,7 +3153,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT7_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT7_REG(i) (REG_SPI_MEM_BASE(i) + 0x25c) +#define SPI_MEM_NAND_FLASH_CMD_LUT7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x25c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE7 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 7. */ @@ -3205,7 +3205,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT8_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT8_REG(i) (REG_SPI_MEM_BASE(i) + 0x260) +#define SPI_MEM_NAND_FLASH_CMD_LUT8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x260) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE8 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 8. */ @@ -3257,7 +3257,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT9_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT9_REG(i) (REG_SPI_MEM_BASE(i) + 0x264) +#define SPI_MEM_NAND_FLASH_CMD_LUT9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x264) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE9 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 9. */ @@ -3309,7 +3309,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT10_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT10_REG(i) (REG_SPI_MEM_BASE(i) + 0x268) +#define SPI_MEM_NAND_FLASH_CMD_LUT10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x268) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE10 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 10. */ @@ -3361,7 +3361,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT11_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT11_REG(i) (REG_SPI_MEM_BASE(i) + 0x26c) +#define SPI_MEM_NAND_FLASH_CMD_LUT11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x26c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE11 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 11. */ @@ -3413,7 +3413,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT12_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT12_REG(i) (REG_SPI_MEM_BASE(i) + 0x270) +#define SPI_MEM_NAND_FLASH_CMD_LUT12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x270) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE12 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 12. */ @@ -3465,7 +3465,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT13_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT13_REG(i) (REG_SPI_MEM_BASE(i) + 0x274) +#define SPI_MEM_NAND_FLASH_CMD_LUT13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x274) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE13 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 13. */ @@ -3517,7 +3517,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT14_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT14_REG(i) (REG_SPI_MEM_BASE(i) + 0x278) +#define SPI_MEM_NAND_FLASH_CMD_LUT14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x278) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE14 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 14. */ @@ -3569,7 +3569,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT15_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT15_REG(i) (REG_SPI_MEM_BASE(i) + 0x27c) +#define SPI_MEM_NAND_FLASH_CMD_LUT15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x27c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE15 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 15. */ @@ -3621,7 +3621,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG(i) (REG_SPI_MEM_BASE(i) + 0x280) +#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x280) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for * sequence. 0: Not the last index. @@ -3675,7 +3675,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ1_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ1_REG(i) (REG_SPI_MEM_BASE(i) + 0x284) +#define SPI_MEM_NAND_FLASH_SPI_SEQ1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x284) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG1 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 1.1: The last index for * sequence. 0: Not the last index. @@ -3729,7 +3729,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ2_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ2_REG(i) (REG_SPI_MEM_BASE(i) + 0x288) +#define SPI_MEM_NAND_FLASH_SPI_SEQ2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x288) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG2 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 2.1: The last index for * sequence. 0: Not the last index. @@ -3783,7 +3783,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ3_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ3_REG(i) (REG_SPI_MEM_BASE(i) + 0x28c) +#define SPI_MEM_NAND_FLASH_SPI_SEQ3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x28c) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG3 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 3.1: The last index for * sequence. 0: Not the last index. @@ -3837,7 +3837,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ4_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ4_REG(i) (REG_SPI_MEM_BASE(i) + 0x290) +#define SPI_MEM_NAND_FLASH_SPI_SEQ4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x290) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG4 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 4.1: The last index for * sequence. 0: Not the last index. @@ -3891,7 +3891,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ5_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ5_REG(i) (REG_SPI_MEM_BASE(i) + 0x294) +#define SPI_MEM_NAND_FLASH_SPI_SEQ5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x294) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG5 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 5.1: The last index for * sequence. 0: Not the last index. @@ -3945,7 +3945,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ6_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ6_REG(i) (REG_SPI_MEM_BASE(i) + 0x298) +#define SPI_MEM_NAND_FLASH_SPI_SEQ6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x298) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG6 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 6.1: The last index for * sequence. 0: Not the last index. @@ -3999,7 +3999,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ7_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ7_REG(i) (REG_SPI_MEM_BASE(i) + 0x29c) +#define SPI_MEM_NAND_FLASH_SPI_SEQ7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x29c) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG7 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 7.1: The last index for * sequence. 0: Not the last index. @@ -4053,7 +4053,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ8_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ8_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG8 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 8.1: The last index for * sequence. 0: Not the last index. @@ -4107,7 +4107,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ9_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ9_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG9 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 9.1: The last index for * sequence. 0: Not the last index. @@ -4161,7 +4161,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ10_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ10_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG10 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 10.1: The last index for * sequence. 0: Not the last index. @@ -4215,7 +4215,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ11_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ11_REG(i) (REG_SPI_MEM_BASE(i) + 0x2ac) +#define SPI_MEM_NAND_FLASH_SPI_SEQ11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2ac) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG11 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 11.1: The last index for * sequence. 0: Not the last index. @@ -4269,7 +4269,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ12_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ12_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG12 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 12.1: The last index for * sequence. 0: Not the last index. @@ -4323,7 +4323,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ13_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ13_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG13 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 13.1: The last index for * sequence. 0: Not the last index. @@ -4377,7 +4377,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ14_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ14_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG14 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 14.1: The last index for * sequence. 0: Not the last index. @@ -4431,7 +4431,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ15_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ15_REG(i) (REG_SPI_MEM_BASE(i) + 0x2bc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2bc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG15 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 15.1: The last index for * sequence. 0: Not the last index. @@ -4485,7 +4485,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ16_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ16_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ16_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG16 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 16.1: The last index for * sequence. 0: Not the last index. @@ -4539,7 +4539,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ17_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ17_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ17_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG17 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 17.1: The last index for * sequence. 0: Not the last index. @@ -4593,7 +4593,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ18_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ18_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ18_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG18 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 18.1: The last index for * sequence. 0: Not the last index. @@ -4647,7 +4647,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ19_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ19_REG(i) (REG_SPI_MEM_BASE(i) + 0x2cc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ19_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2cc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG19 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 19.1: The last index for * sequence. 0: Not the last index. @@ -4701,7 +4701,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ20_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ20_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ20_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG20 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 20.1: The last index for * sequence. 0: Not the last index. @@ -4755,7 +4755,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ21_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ21_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ21_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG21 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 21.1: The last index for * sequence. 0: Not the last index. @@ -4809,7 +4809,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ22_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ22_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ22_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG22 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 22.1: The last index for * sequence. 0: Not the last index. @@ -4863,7 +4863,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ23_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ23_REG(i) (REG_SPI_MEM_BASE(i) + 0x2dc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ23_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2dc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG23 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 23.1: The last index for * sequence. 0: Not the last index. @@ -4917,7 +4917,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ24_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ24_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ24_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG24 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 24.1: The last index for * sequence. 0: Not the last index. @@ -4971,7 +4971,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ25_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ25_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ25_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG25 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 25.1: The last index for * sequence. 0: Not the last index. @@ -5025,7 +5025,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ26_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ26_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ26_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG26 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 26.1: The last index for * sequence. 0: Not the last index. @@ -5079,7 +5079,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ27_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ27_REG(i) (REG_SPI_MEM_BASE(i) + 0x2ec) +#define SPI_MEM_NAND_FLASH_SPI_SEQ27_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2ec) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG27 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 27.1: The last index for * sequence. 0: Not the last index. @@ -5133,7 +5133,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ28_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ28_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ28_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG28 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 28.1: The last index for * sequence. 0: Not the last index. @@ -5187,7 +5187,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ29_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ29_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ29_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG29 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 29.1: The last index for * sequence. 0: Not the last index. @@ -5241,7 +5241,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ30_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ30_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ30_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG30 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 30.1: The last index for * sequence. 0: Not the last index. @@ -5295,7 +5295,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ31_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ31_REG(i) (REG_SPI_MEM_BASE(i) + 0x2fc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ31_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2fc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG31 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 31.1: The last index for * sequence. 0: Not the last index. @@ -5349,7 +5349,7 @@ extern "C" { /** SPI_MEM_XTS_PLAIN_BASE_REG register * The base address of the memory that stores plaintext in Manual Encryption */ -#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x300) /** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; * This field is only used to generate include file in c case. This field is useless. * Please do not use this field. @@ -5362,7 +5362,7 @@ extern "C" { /** SPI_MEM_XTS_LINESIZE_REG register * Manual Encryption Line-Size register */ -#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +#define SPI_MEM_XTS_LINESIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x340) /** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; * This bits stores the line-size parameter which will be used in manual encryption * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: @@ -5376,7 +5376,7 @@ extern "C" { /** SPI_MEM_XTS_DESTINATION_REG register * Manual Encryption destination register */ -#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +#define SPI_MEM_XTS_DESTINATION_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x344) /** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; * This bit stores the destination parameter which will be used in manual encryption * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. @@ -5389,7 +5389,7 @@ extern "C" { /** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x348) /** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by @@ -5403,7 +5403,7 @@ extern "C" { /** SPI_MEM_XTS_TRIGGER_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34c) +#define SPI_MEM_XTS_TRIGGER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34c) /** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; * Set this bit to trigger the process of manual encryption calculation. This action * should only be asserted when manual encryption status is 0. After this action, @@ -5418,7 +5418,7 @@ extern "C" { /** SPI_MEM_XTS_RELEASE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +#define SPI_MEM_XTS_RELEASE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x350) /** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; * Set this bit to release encrypted result to mspi. This action should only be * asserted when manual encryption status is 2. After this action, manual encryption @@ -5432,7 +5432,7 @@ extern "C" { /** SPI_MEM_XTS_DESTROY_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +#define SPI_MEM_XTS_DESTROY_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x354) /** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; * Set this bit to destroy encrypted result. This action should be asserted only when * manual encryption status is 3. After this action, manual encryption status will @@ -5446,7 +5446,7 @@ extern "C" { /** SPI_MEM_XTS_STATE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +#define SPI_MEM_XTS_STATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x358) /** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption * calculation, 2: encryption calculation is done but the encrypted result is @@ -5460,7 +5460,7 @@ extern "C" { /** SPI_MEM_XTS_DATE_REG register * Manual Encryption version register */ -#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35c) +#define SPI_MEM_XTS_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x35c) /** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ @@ -5472,7 +5472,7 @@ extern "C" { /** SPI_MEM_MMU_ITEM_CONTENT_REG register * MSPI-MMU item content register */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37c) +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x37c) /** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; * MSPI-MMU item content */ @@ -5484,7 +5484,7 @@ extern "C" { /** SPI_MEM_MMU_ITEM_INDEX_REG register * MSPI-MMU item index register */ -#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x380) /** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; * MSPI-MMU item index */ @@ -5496,7 +5496,7 @@ extern "C" { /** SPI_MEM_MMU_POWER_CTRL_REG register * MSPI MMU power control register */ -#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x384) /** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; * Set this bit to enable mmu-memory clock force on */ @@ -5537,7 +5537,7 @@ extern "C" { /** SPI_MEM_DPA_CTRL_REG register * SPI memory cryption DPA register */ -#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +#define SPI_MEM_DPA_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x388) /** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the @@ -5568,7 +5568,7 @@ extern "C" { /** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register * SPI memory cryption PSEUDO register */ -#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x38c) +#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x38c) /** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. @@ -5604,7 +5604,7 @@ extern "C" { /** SPI_MEM_DATE_REG register * SPI0 version control register */ -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) +#define SPI_MEM_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3fc) /** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37814608; * SPI0 register version. */ diff --git a/components/soc/esp32h21/register/soc/spi_struct.h b/components/soc/esp32h21/register/soc/spi_struct.h index a47c7b374e..46ed7a70d0 100644 --- a/components/soc/esp32h21/register/soc/spi_struct.h +++ b/components/soc/esp32h21/register/soc/spi_struct.h @@ -1550,214 +1550,18 @@ typedef union { /** Group: CPU-controlled data buffer */ -/** Type of w0 register - * SPI CPU-controlled buffer0 +/** Type of wn register + * SPI CPU-controlled buffer */ typedef union { struct { /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; * 32-bit data buffer $n. */ - uint32_t buf0:32; + uint32_t buf:32; }; uint32_t val; -} spi_w0_reg_t; - -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - +} spi_wn_reg_t; /** Group: Version register */ /** Type of date register @@ -1795,22 +1599,7 @@ typedef struct { volatile spi_dma_int_st_reg_t dma_int_st; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; - volatile spi_w0_reg_t w0; - volatile spi_w1_reg_t w1; - volatile spi_w2_reg_t w2; - volatile spi_w3_reg_t w3; - volatile spi_w4_reg_t w4; - volatile spi_w5_reg_t w5; - volatile spi_w6_reg_t w6; - volatile spi_w7_reg_t w7; - volatile spi_w8_reg_t w8; - volatile spi_w9_reg_t w9; - volatile spi_w10_reg_t w10; - volatile spi_w11_reg_t w11; - volatile spi_w12_reg_t w12; - volatile spi_w13_reg_t w13; - volatile spi_w14_reg_t w14; - volatile spi_w15_reg_t w15; + volatile spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile spi_slave_reg_t slave; volatile spi_slave1_reg_t slave1; diff --git a/components/soc/esp32h21/register/soc/system_reg.h b/components/soc/esp32h21/register/soc/system_reg.h new file mode 100644 index 0000000000..86453435e0 --- /dev/null +++ b/components/soc/esp32h21/register/soc/system_reg.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/hp_system_reg.h" +#include "intpri_reg.h" + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG +#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32h21/register/soc/systimer_struct.h b/components/soc/esp32h21/register/soc/systimer_struct.h index f69a7f69c9..d136c6bcce 100644 --- a/components/soc/esp32h21/register/soc/systimer_struct.h +++ b/components/soc/esp32h21/register/soc/systimer_struct.h @@ -68,24 +68,24 @@ typedef union { /** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */ -/** Type of unit0_op register - * system timer unit0 value update register +/** Type of unit_op register + * system timer unit value update register */ typedef union { struct { uint32_t reserved_0:29; - /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; * timer value is sync and valid */ - uint32_t timer_unit0_value_valid:1; - /** timer_unit0_update : WT; bitpos: [30]; default: 0; + uint32_t timer_unit_value_valid:1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; * update timer_unit0 */ - uint32_t timer_unit0_update:1; + uint32_t timer_unit_update:1; uint32_t reserved_31:1; }; uint32_t val; -} systimer_unit0_op_reg_t; +} systimer_unit_op_reg_t; /** Type of unit0_load_hi register * system timer unit0 value high load register @@ -95,7 +95,7 @@ typedef union { /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; * timer unit0 load high 20 bits */ - uint32_t timer_unit0_load_hi:20; + uint32_t timer_unit_load_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -106,10 +106,10 @@ typedef union { */ typedef union { struct { - /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; - * timer unit0 load low 32 bits + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bits */ - uint32_t timer_unit0_load_lo:32; + uint32_t timer_unit_load_lo:32; }; uint32_t val; } systimer_unit0_load_lo_reg_t; @@ -119,10 +119,10 @@ typedef union { */ typedef union { struct { - /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; * timer read value high 20bits */ - uint32_t timer_unit0_value_hi:20; + uint32_t timer_unit_value_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -133,48 +133,27 @@ typedef union { */ typedef union { struct { - /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; * timer read value low 32bits */ - uint32_t timer_unit0_value_lo:32; + uint32_t timer_unit_value_lo:32; }; uint32_t val; } systimer_unit0_value_lo_reg_t; -/** Type of unit0_load register - * system timer unit0 conf sync register +/** Type of unit_load register + * system timer unit conf sync register */ typedef union { struct { - /** timer_unit0_load : WT; bitpos: [0]; default: 0; - * timer unit0 sync enable signal + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit sync enable signal */ uint32_t timer_unit0_load:1; uint32_t reserved_1:31; }; uint32_t val; -} systimer_unit0_load_reg_t; - - -/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ -/** Type of unit1_op register - * system timer unit1 value update register - */ -typedef union { - struct { - uint32_t reserved_0:29; - /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0; - * timer value is sync and valid - */ - uint32_t timer_unit1_value_valid:1; - /** timer_unit1_update : WT; bitpos: [30]; default: 0; - * update timer unit1 - */ - uint32_t timer_unit1_update:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} systimer_unit1_op_reg_t; +} systimer_unit_load_reg_t; /** Type of unit1_load_hi register * system timer unit1 value high load register @@ -230,31 +209,16 @@ typedef union { uint32_t val; } systimer_unit1_value_lo_reg_t; -/** Type of unit1_load register - * system timer unit1 conf sync register - */ -typedef union { - struct { - /** timer_unit1_load : WT; bitpos: [0]; default: 0; - * timer unit1 sync enable signal - */ - uint32_t timer_unit1_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_unit1_load_reg_t; - - /** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */ /** Type of target0_hi register * system timer comp0 value high register */ typedef union { struct { - /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; * timer taget0 high 20 bits */ - uint32_t timer_target0_hi:20; + uint32_t timer_target_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -265,49 +229,49 @@ typedef union { */ typedef union { struct { - /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; - * timer taget0 low 32 bits + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bits */ - uint32_t timer_target0_lo:32; + uint32_t timer_target_lo:32; }; uint32_t val; } systimer_target0_lo_reg_t; -/** Type of target0_conf register +/** Type of target_conf register * system timer comp0 target mode register */ typedef union { struct { - /** target0_period : R/W; bitpos: [25:0]; default: 0; - * target0 period + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period */ - uint32_t target0_period:26; + uint32_t target_period:26; uint32_t reserved_26:4; - /** target0_period_mode : R/W; bitpos: [30]; default: 0; - * Set target0 to period mode + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode */ - uint32_t target0_period_mode:1; + uint32_t target_period_mode:1; /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; * select which unit to compare */ - uint32_t target0_timer_unit_sel:1; + uint32_t target_timer_unit_sel:1; }; uint32_t val; -} systimer_target0_conf_reg_t; +} systimer_target_conf_reg_t; -/** Type of comp0_load register - * system timer comp0 conf sync register +/** Type of comp_load register + * system timer comp conf sync register */ typedef union { struct { - /** timer_comp0_load : WT; bitpos: [0]; default: 0; - * timer comp0 sync enable signal + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp sync enable signal */ uint32_t timer_comp0_load:1; uint32_t reserved_1:31; }; uint32_t val; -} systimer_comp0_load_reg_t; +} systimer_comp_load_reg_t; /** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ @@ -360,21 +324,6 @@ typedef union { uint32_t val; } systimer_target1_conf_reg_t; -/** Type of comp1_load register - * system timer comp1 conf sync register - */ -typedef union { - struct { - /** timer_comp1_load : WT; bitpos: [0]; default: 0; - * timer comp1 sync enable signal - */ - uint32_t timer_comp1_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_comp1_load_reg_t; - - /** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */ /** Type of target2_hi register * system timer comp2 value high register @@ -403,43 +352,6 @@ typedef union { uint32_t val; } systimer_target2_lo_reg_t; -/** Type of target2_conf register - * system timer comp2 target mode register - */ -typedef union { - struct { - /** target2_period : R/W; bitpos: [25:0]; default: 0; - * target2 period - */ - uint32_t target2_period:26; - uint32_t reserved_26:4; - /** target2_period_mode : R/W; bitpos: [30]; default: 0; - * Set target2 to period mode - */ - uint32_t target2_period_mode:1; - /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - uint32_t target2_timer_unit_sel:1; - }; - uint32_t val; -} systimer_target2_conf_reg_t; - -/** Type of comp2_load register - * system timer comp2 conf sync register - */ -typedef union { - struct { - /** timer_comp2_load : WT; bitpos: [0]; default: 0; - * timer comp2 sync enable signal - */ - uint32_t timer_comp2_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_comp2_load_reg_t; - - /** Group: SYSTEM TIMER INTERRUPT REGISTER */ /** Type of int_ena register * systimer interrupt enable register @@ -631,43 +543,44 @@ typedef union { uint32_t val; } systimer_date_reg_t; +typedef struct systimer_unit_load_val_reg +{ + systimer_unit0_load_hi_reg_t hi; + systimer_unit0_load_lo_reg_t lo; +} systimer_unit_load_val_reg_t; -typedef struct { +typedef struct systimer_target_val_reg +{ + systimer_target0_hi_reg_t hi; + systimer_target0_lo_reg_t lo; +} systimer_target_val_reg_t; + +typedef struct systimer_unit_value_reg +{ + systimer_unit0_value_hi_reg_t hi; + systimer_unit0_value_lo_reg_t lo; +} systimer_unit_value_reg_t; + +typedef struct systimer_real_target_reg +{ + systimer_real_target0_lo_reg_t lo; + systimer_real_target0_hi_reg_t hi; +} systimer_real_target_reg_t; + +typedef struct systimer_dev_t{ volatile systimer_conf_reg_t conf; - volatile systimer_unit0_op_reg_t unit0_op; - volatile systimer_unit1_op_reg_t unit1_op; - volatile systimer_unit0_load_hi_reg_t unit0_load_hi; - volatile systimer_unit0_load_lo_reg_t unit0_load_lo; - volatile systimer_unit1_load_hi_reg_t unit1_load_hi; - volatile systimer_unit1_load_lo_reg_t unit1_load_lo; - volatile systimer_target0_hi_reg_t target0_hi; - volatile systimer_target0_lo_reg_t target0_lo; - volatile systimer_target1_hi_reg_t target1_hi; - volatile systimer_target1_lo_reg_t target1_lo; - volatile systimer_target2_hi_reg_t target2_hi; - volatile systimer_target2_lo_reg_t target2_lo; - volatile systimer_target0_conf_reg_t target0_conf; - volatile systimer_target1_conf_reg_t target1_conf; - volatile systimer_target2_conf_reg_t target2_conf; - volatile systimer_unit0_value_hi_reg_t unit0_value_hi; - volatile systimer_unit0_value_lo_reg_t unit0_value_lo; - volatile systimer_unit1_value_hi_reg_t unit1_value_hi; - volatile systimer_unit1_value_lo_reg_t unit1_value_lo; - volatile systimer_comp0_load_reg_t comp0_load; - volatile systimer_comp1_load_reg_t comp1_load; - volatile systimer_comp2_load_reg_t comp2_load; - volatile systimer_unit0_load_reg_t unit0_load; - volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; volatile systimer_int_ena_reg_t int_ena; volatile systimer_int_raw_reg_t int_raw; volatile systimer_int_clr_reg_t int_clr; volatile systimer_int_st_reg_t int_st; - volatile systimer_real_target0_lo_reg_t real_target0_lo; - volatile systimer_real_target0_hi_reg_t real_target0_hi; - volatile systimer_real_target1_lo_reg_t real_target1_lo; - volatile systimer_real_target1_hi_reg_t real_target1_hi; - volatile systimer_real_target2_lo_reg_t real_target2_lo; - volatile systimer_real_target2_hi_reg_t real_target2_hi; + volatile systimer_real_target_reg_t real_target[3]; uint32_t reserved_08c[28]; volatile systimer_date_reg_t date; } systimer_dev_t; diff --git a/components/soc/esp32h21/register/soc/timer_group_struct.h b/components/soc/esp32h21/register/soc/timer_group_struct.h index 81eefe5cb5..c5360f1c0b 100644 --- a/components/soc/esp32h21/register/soc/timer_group_struct.h +++ b/components/soc/esp32h21/register/soc/timer_group_struct.h @@ -519,17 +519,20 @@ typedef union { uint32_t val; } timg_regclk_reg_t; +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; typedef struct { - volatile timg_txconfig_reg_t t0config; - volatile timg_txlo_reg_t t0lo; - volatile timg_txhi_reg_t t0hi; - volatile timg_txupdate_reg_t t0update; - volatile timg_txalarmlo_reg_t t0alarmlo; - volatile timg_txalarmhi_reg_t t0alarmhi; - volatile timg_txloadlo_reg_t t0loadlo; - volatile timg_txloadhi_reg_t t0loadhi; - volatile timg_txload_reg_t t0load; + volatile timg_hwtimer_reg_t hw_timer[1]; uint32_t reserved_024[9]; volatile timg_wdtconfig0_reg_t wdtconfig0; volatile timg_wdtconfig1_reg_t wdtconfig1; diff --git a/components/soc/esp32h21/register/soc/uart_reg.h b/components/soc/esp32h21/register/soc/uart_reg.h index 1a614cf327..149160e004 100644 --- a/components/soc/esp32h21/register/soc/uart_reg.h +++ b/components/soc/esp32h21/register/soc/uart_reg.h @@ -14,7 +14,7 @@ extern "C" { /** UART_FIFO_REG register * FIFO data register */ -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0) /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ @@ -26,7 +26,7 @@ extern "C" { /** UART_INT_RAW_REG register * Raw interrupt status */ -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4) /** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * This interrupt raw bit turns to high level when receiver receives more data than * what rxfifo_full_thrhd specifies. @@ -191,7 +191,7 @@ extern "C" { /** UART_INT_ST_REG register * Masked interrupt status */ -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8) /** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. */ @@ -341,7 +341,7 @@ extern "C" { /** UART_INT_ENA_REG register * Interrupt enable bits */ -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc) /** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; * This is the enable bit for rxfifo_full_int_st register. */ @@ -486,7 +486,7 @@ extern "C" { /** UART_INT_CLR_REG register * Interrupt clear bits */ -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10) /** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the rxfifo_full_int_raw interrupt. */ @@ -631,7 +631,7 @@ extern "C" { /** UART_CLKDIV_SYNC_REG register * Clock divider configuration */ -#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14) /** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; * The integral part of the frequency divider factor. */ @@ -650,7 +650,7 @@ extern "C" { /** UART_RX_FILT_REG register * Rx Filter configuration */ -#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18) /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; * when input pulse width is lower than this value the pulse is ignored. */ @@ -669,7 +669,7 @@ extern "C" { /** UART_STATUS_REG register * UART status register */ -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c) /** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; * Stores the byte number of valid data in Rx-FIFO. */ @@ -730,7 +730,7 @@ extern "C" { /** UART_CONF0_SYNC_REG register * a */ -#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20) /** UART_PARITY : R/W; bitpos: [0]; default: 0; * This register is used to configure the parity check mode. */ @@ -893,7 +893,7 @@ extern "C" { /** UART_CONF1_REG register * Configuration register 1 */ -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24) /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; * It will produce rxfifo_full_int interrupt when receiver receives more data than * this register value. @@ -958,7 +958,7 @@ extern "C" { /** UART_HWFC_CONF_SYNC_REG register * Hardware flow-control configuration */ -#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c) /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; * This register is used to configure the maximum amount of data that can be received * when hardware flow control works. @@ -978,7 +978,7 @@ extern "C" { /** UART_SLEEP_CONF0_REG register * UART sleep configure register 0 */ -#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30) /** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified wake up char1 to wake up */ @@ -1011,7 +1011,7 @@ extern "C" { /** UART_SLEEP_CONF1_REG register * UART sleep configure register 1 */ -#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34) /** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified char0 to wake up */ @@ -1023,7 +1023,7 @@ extern "C" { /** UART_SLEEP_CONF2_REG register * UART sleep configure register 2 */ -#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38) /** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; * The uart is activated from light sleeping mode when the input rxd edge changes more * times than this register value. @@ -1066,7 +1066,7 @@ extern "C" { /** UART_SWFC_CONF0_SYNC_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c) /** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; * This register stores the Xon flow control char. */ @@ -1138,7 +1138,7 @@ extern "C" { /** UART_SWFC_CONF1_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40) /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; * When the data amount in Rx-FIFO is less than this register value with * uart_sw_flow_con_en set to 1 it will send a Xon char. @@ -1159,7 +1159,7 @@ extern "C" { /** UART_TXBRK_CONF_SYNC_REG register * Tx Break character configuration */ -#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44) /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * This register is used to configure the number of 0 to be sent after the process of * sending data is done. It is active when txd_brk is set to 1. @@ -1172,7 +1172,7 @@ extern "C" { /** UART_IDLE_CONF_SYNC_REG register * Frame-end idle configuration */ -#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48) /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; * It will produce frame end signal when receiver takes more time to receive one byte * data than this register value. @@ -1192,7 +1192,7 @@ extern "C" { /** UART_RS485_CONF_SYNC_REG register * RS485 mode configuration */ -#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c) /** UART_RS485_EN : R/W; bitpos: [0]; default: 0; * Set this bit to choose the rs485 mode. */ @@ -1247,7 +1247,7 @@ extern "C" { /** UART_AT_CMD_PRECNT_SYNC_REG register * Pre-sequence timing configuration */ -#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50) /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the idle duration time before the first at_cmd * is received by receiver. @@ -1260,7 +1260,7 @@ extern "C" { /** UART_AT_CMD_POSTCNT_SYNC_REG register * Post-sequence timing configuration */ -#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54) /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the duration time between the last at_cmd and * the next data. @@ -1273,7 +1273,7 @@ extern "C" { /** UART_AT_CMD_GAPTOUT_SYNC_REG register * Timeout configuration */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58) /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; * This register is used to configure the duration time between the at_cmd chars. */ @@ -1285,7 +1285,7 @@ extern "C" { /** UART_AT_CMD_CHAR_SYNC_REG register * AT escape sequence detection configuration */ -#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c) /** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; * This register is used to configure the content of at_cmd char. */ @@ -1305,7 +1305,7 @@ extern "C" { /** UART_MEM_CONF_REG register * UART memory power configuration */ -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60) /** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; * Set this bit to force power down UART memory. */ @@ -1324,7 +1324,7 @@ extern "C" { /** UART_TOUT_CONF_SYNC_REG register * UART threshold and allocation configuration */ -#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; * This is the enable bit for uart receiver's timeout function. */ @@ -1352,7 +1352,7 @@ extern "C" { /** UART_MEM_TX_STATUS_REG register * Tx-SRAM write and read offset address. */ -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68) /** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; * This register stores the offset write address in Tx-SRAM. */ @@ -1371,7 +1371,7 @@ extern "C" { /** UART_MEM_RX_STATUS_REG register * Rx-SRAM write and read offset address. */ -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c) /** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; * This register stores the offset read address in RX-SRAM. */ @@ -1390,7 +1390,7 @@ extern "C" { /** UART_FSM_STATUS_REG register * UART transmit and receive status. */ -#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70) /** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; * This is the status register of receiver. */ @@ -1409,7 +1409,7 @@ extern "C" { /** UART_POSPULSE_REG register * Autobaud high pulse register */ -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74) /** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two positive edges. It * is used in boudrate-detect process. @@ -1422,7 +1422,7 @@ extern "C" { /** UART_NEGPULSE_REG register * Autobaud low pulse register */ -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78) /** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two negative edges. It * is used in boudrate-detect process. @@ -1435,7 +1435,7 @@ extern "C" { /** UART_LOWPULSE_REG register * Autobaud minimum low pulse duration register */ -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c) /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the minimum duration time of the low level pulse. * It is used in baud rate-detect process. @@ -1448,7 +1448,7 @@ extern "C" { /** UART_HIGHPULSE_REG register * Autobaud minimum high pulse duration register */ -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. @@ -1461,7 +1461,7 @@ extern "C" { /** UART_RXD_CNT_REG register * Autobaud edge change count register */ -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84) /** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; * This register stores the count of rxd edge change. It is used in baud rate-detect * process. @@ -1474,7 +1474,7 @@ extern "C" { /** UART_CLK_CONF_REG register * UART core clock configuration */ -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88) /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1507,7 +1507,7 @@ extern "C" { /** UART_DATE_REG register * UART Version register */ -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c) /** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; * This is the version register. */ @@ -1519,7 +1519,7 @@ extern "C" { /** UART_AFIFO_STATUS_REG register * UART AFIFO Status */ -#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90) /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; * Full signal of APB TX AFIFO. */ @@ -1552,7 +1552,7 @@ extern "C" { /** UART_REG_UPDATE_REG register * UART Registers Configuration Update register */ -#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98) /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; * Software write 1 would synchronize registers into UART Core clock domain and would * be cleared by hardware after synchronization is done. @@ -1565,7 +1565,7 @@ extern "C" { /** UART_ID_REG register * UART ID register */ -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c) /** UART_ID : R/W; bitpos: [31:0]; default: 1280; * This register is used to configure the uart_id. */ diff --git a/components/soc/esp32h21/register/soc/xts_aes_reg.h b/components/soc/esp32h21/register/soc/xts_aes_reg.h new file mode 100644 index 0000000000..599aaf3486 --- /dev/null +++ b/components/soc/esp32h21/register/soc/xts_aes_reg.h @@ -0,0 +1,129 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define XTS_AES_PLAIN 0xFFFFFFFF +#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S)) +#define XTS_AES_PLAIN_V 0xFFFFFFFF +#define XTS_AES_PLAIN_S 0 + +#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define XTS_AES_LINESIZE 0x00000003 +#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S)) +#define XTS_AES_LINESIZE_V 0x3 +#define XTS_AES_LINESIZE_S 0 + +#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryption +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define XTS_AES_DESTINATION (BIT(0)) +#define XTS_AES_DESTINATION_M (BIT(0)) +#define XTS_AES_DESTINATION_V 0x1 +#define XTS_AES_DESTINATION_S 0 + +#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S)) +#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_S 0 + +#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryption +n status becomes 2..*/ +#define XTS_AES_TRIGGER (BIT(0)) +#define XTS_AES_TRIGGER_M (BIT(0)) +#define XTS_AES_TRIGGER_V 0x1 +#define XTS_AES_TRIGGER_S 0 + +#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define XTS_AES_RELEASE (BIT(0)) +#define XTS_AES_RELEASE_M (BIT(0)) +#define XTS_AES_RELEASE_V 0x1 +#define XTS_AES_RELEASE_S 0 + +#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define XTS_AES_DESTROY (BIT(0)) +#define XTS_AES_DESTROY_M (BIT(0)) +#define XTS_AES_DESTROY_V 0x1 +#define XTS_AES_DESTROY_S 0 + +#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define XTS_AES_STATE 0x00000003 +#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S)) +#define XTS_AES_STATE_V 0x3 +#define XTS_AES_STATE_S 0 + +#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define XTS_AES_DATE 0x3FFFFFFF +#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S)) +#define XTS_AES_DATE_V 0x3FFFFFFF +#define XTS_AES_DATE_S 0 + +#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4 +/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 +#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 +/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 +#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S)) +#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7 +#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0 + +#ifdef __cplusplus +} +#endif