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Merge branch 'bugfix/enable_additional_lp_io_wakeup_v5.3' into 'release/v5.3'

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fix(lp_io): enable setting edge type wakeup sources for targets that support this (v5.3)

See merge request espressif/esp-idf!36012
This commit is contained in:
morris
2025-04-15 10:30:26 +08:00
parent 1eb1fad16d 8d6d6957ce
commit 086e129cd3
5 changed files with 12 additions and 0 deletions
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2
components/esp_driver_gpio/src/rtc_io.c
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@@ -254,9 +254,11 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{ {
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error"); ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
#if !SOC_RTCIO_EDGE_WAKE_SUPPORTED
if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) { if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) {
return ESP_ERR_INVALID_ARG; // Dont support this mode. return ESP_ERR_INVALID_ARG; // Dont support this mode.
} }
#endif //!SOC_RTCIO_EDGE_WAKE_SUPPORTED
RTCIO_ENTER_CRITICAL(); RTCIO_ENTER_CRITICAL();
rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type); rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type);
RTCIO_EXIT_CRITICAL(); RTCIO_EXIT_CRITICAL();

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@@ -555,6 +555,10 @@ config SOC_RTCIO_VALID_RTCIO_MASK
hex hex
default 0xFF default 0xFF
config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int int
default 8 default 8

1
components/soc/esp32c6/include/soc/soc_caps.h
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@@ -230,6 +230,7 @@
#define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_VALID_RTCIO_MASK (0xFF) #define SOC_RTCIO_VALID_RTCIO_MASK (0xFF)
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -679,6 +679,10 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool bool
default y default y
config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int int
default 8 default 8

1
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -270,6 +270,7 @@
*/ */
#define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */