diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index 6d83b506f1..ad81bc5443 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -259,7 +259,11 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
 #if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS
     mode = ESP_IMAGE_LOAD_NO_VALIDATE;
 #elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON
-    if (rtc_get_reset_reason(0) == POWERON_RESET) {
+    if (rtc_get_reset_reason(0) == POWERON_RESET
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+        || rtc_get_reset_reason(0) == EFUSE_RESET
+#endif
+        ) {
         mode = ESP_IMAGE_LOAD_NO_VALIDATE;
     }
 #endif // CONFIG_BOOTLOADER_SKIP_...
diff --git a/components/esp_rom/include/esp32s2/rom/rtc.h b/components/esp_rom/include/esp32s2/rom/rtc.h
index 535dc64a9a..dcbce7f7a0 100644
--- a/components/esp_rom/include/esp32s2/rom/rtc.h
+++ b/components/esp_rom/include/esp32s2/rom/rtc.h
@@ -94,6 +94,7 @@ typedef enum {
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
     GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
 } RESET_REASON;
 
 typedef enum {
diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c
index d3b63ef5e7..2cad1cc9fc 100644
--- a/components/esp_system/port/soc/esp32c3/clk.c
+++ b/components/esp_system/port/soc/esp32c3/clk.c
@@ -77,7 +77,11 @@ static const char *TAG = "clk";
     rtc_config_t cfg = RTC_CONFIG_DEFAULT();
     RESET_REASON rst_reas;
     rst_reas = rtc_get_reset_reason(0);
-    if (rst_reas == POWERON_RESET) {
+    if (rst_reas == POWERON_RESET
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+        || rst_reas == EFUSE_RESET
+#endif
+        ) {
         cfg.cali_ocode = 1;
     }
     rtc_init(cfg);
diff --git a/components/esp_system/port/soc/esp32c3/reset_reason.c b/components/esp_system/port/soc/esp32c3/reset_reason.c
index 98e93d5934..e962ed38b2 100644
--- a/components/esp_system/port/soc/esp32c3/reset_reason.c
+++ b/components/esp_system/port/soc/esp32c3/reset_reason.c
@@ -25,6 +25,9 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
 {
     switch (rtc_reset_reason) {
     case POWERON_RESET:
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+    case EFUSE_RESET:
+#endif
         return ESP_RST_POWERON;
 
     case RTC_SW_CPU_RESET:
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 5189f7b341..5dd7719896 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -18,7 +18,7 @@
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_SUPPORTS_SECURE_DL_MODE         1
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
-
+#define SOC_EFUSE_HAS_EFUSE_RST_BUG         1
 
 /*-------------------------- AES CAPS -----------------------------------------*/
 #define SOC_AES_SUPPORT_DMA     (1)