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change(rom): update the frozen rom for esp32c5mp

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This commit is contained in:
laokaiyao
2024-04-01 20:53:49 +08:00
parent d954057ed8
commit 0cb1057915
13 changed files with 1072 additions and 1063 deletions
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30
components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld
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@@ -7,20 +7,20 @@
* Make sure the bootloader can load into main memory without overwriting itself. * Make sure the bootloader can load into main memory without overwriting itself.
* *
* ESP32-C5 ROM static data usage is as follows: * ESP32-C5 ROM static data usage is as follows:
* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only * - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup * - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable) * - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
* *
* The 2nd stage bootloader can take space up to the end of ROM shared * The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4087c610). * buffers area (0x4085c9a0).
*/ */
/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, /* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards. * and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/ */
/* These lengths can be adjusted, if necessary: */ /* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4085c8d0; bootloader_usable_dram_end = 0x4085c9a0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000; bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000; bootloader_iram_loader_seg_len = 0x7000;
@@ -43,9 +43,9 @@ MEMORY
* If you have changed something above and this assert fails: * If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is. * 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert. * 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c6/memory.ld.in to the same value. * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
*/ */
ASSERT(bootloader_iram_loader_seg_start == 0x4084E8D0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */ /* Default entry point: */
ENTRY(call_start_cpu0); ENTRY(call_start_cpu0);
@@ -222,34 +222,34 @@ SECTIONS
/** /**
* Appendix: Memory Usage of ROM bootloader * Appendix: Memory Usage of ROM bootloader
* *
* 0x4086ad08 ------------------> _dram0_0_start * 0x4084e9a0 ------------------> _dram0_0_start
* | | * | |
* | | * | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | | * | |
* | | * | |
* 0x4087c610 ------------------> __stack_sentry * 0x4085c9a0 ------------------> __stack_sentry
* | | * | |
* | | 2. Startup pro cpu stack (freed when IDF app is running) * | | 2. Startup pro cpu stack (freed when IDF app is running)
* | | * | |
* 0x4087e610 ------------------> __stack (pro cpu) * 0x4085e9a0 ------------------> __stack (pro cpu)
* | | * | |
* | | * | |
* | | 3. Shared memory only used in startup code or nonos/early boot* * | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs) * | | (can be freed when IDF runs)
* | | * | |
* | | * | |
* 0x4087f564 ------------------> _dram0_rtos_reserved_start * 0x4085f500 ------------------> _dram0_rtos_reserved_start
* | | * | |
* | | * | |
* | | 4. Shared memory used in startup code and when IDF runs * | | 4. Shared memory used in startup code and when IDF runs
* | | * | |
* | | * | |
* 0x4087fab0 ------------------> _dram0_rtos_reserved_end * 0x4085fc5c ------------------> _dram0_rtos_reserved_end
* | | * | |
* 0x4087fce8 ------------------> _data_start_interface * 0x4085fc70 ------------------> _data_start_interface
* | | * | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | | * | |
* 0x40880000 ------------------> _data_end_interface * 0x40860000 ------------------> _data_end_interface
*/ */

58
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.coexist.ld
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@@ -1,12 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32c6.rom.coexist.ld for esp32c6 /* ROM function interface esp32c5.rom.coexist.ld for esp32c5
* *
* *
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,30 +18,30 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
esp_coex_rom_version_get = 0x40000afc; esp_coex_rom_version_get = 0x40000ac8;
coex_bt_release = 0x40000b00; coex_bt_release = 0x40000acc;
coex_bt_request = 0x40000b04; coex_bt_request = 0x40000ad0;
coex_core_ble_conn_dyn_prio_get = 0x40000b08; coex_core_ble_conn_dyn_prio_get = 0x40000ad4;
coex_core_event_duration_get = 0x40000b0c; coex_core_event_duration_get = 0x40000ad8;
coex_core_pti_get = 0x40000b10; coex_core_pti_get = 0x40000adc;
coex_core_release = 0x40000b14; coex_core_release = 0x40000ae0;
coex_core_request = 0x40000b18; coex_core_request = 0x40000ae4;
coex_core_status_get = 0x40000b1c; coex_core_status_get = 0x40000ae8;
coex_core_timer_idx_get = 0x40000b20; coex_core_timer_idx_get = 0x40000aec;
coex_event_duration_get = 0x40000b24; coex_event_duration_get = 0x40000af0;
coex_hw_timer_disable = 0x40000b28; coex_hw_timer_disable = 0x40000af4;
coex_hw_timer_enable = 0x40000b2c; coex_hw_timer_enable = 0x40000af8;
coex_hw_timer_set = 0x40000b30; coex_hw_timer_set = 0x40000afc;
coex_schm_interval_set = 0x40000b34; coex_schm_interval_set = 0x40000b00;
coex_schm_lock = 0x40000b38; coex_schm_lock = 0x40000b04;
coex_schm_unlock = 0x40000b3c; coex_schm_unlock = 0x40000b08;
coex_status_get = 0x40000b40; coex_status_get = 0x40000b0c;
coex_wifi_release = 0x40000b44; coex_wifi_release = 0x40000b10;
esp_coex_ble_conn_dynamic_prio_get = 0x40000b48; esp_coex_ble_conn_dynamic_prio_get = 0x40000b14;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
coex_env_ptr = 0x4087ffc4; coex_env_ptr = 0x4085ffc4;
coex_pti_tab_ptr = 0x4087ffc0; coex_pti_tab_ptr = 0x4085ffc0;
coex_schm_env_ptr = 0x4087ffbc; coex_schm_env_ptr = 0x4085ffbc;
coexist_funcs = 0x4087ffb8; coexist_funcs = 0x4085ffb8;
g_coa_funcs_p = 0x4087ffb4; g_coa_funcs_p = 0x4085ffb4;
g_coex_param_ptr = 0x4087ffb0; g_coex_param_ptr = 0x4085ffb0;

2
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.heap.ld
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@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.heap.ld for esp32c5 /* ROM function interface esp32c5.rom.heap.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 6ed52af1f620a978e86457a92f3d325a * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *

255
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.ld for esp32c5 /* ROM function interface esp32c5.rom.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -228,7 +228,12 @@ Cache_MSPI_MMU_Set_Secure = 0x400006d8;
Cache_Count_Flash_Pages = 0x400006dc; Cache_Count_Flash_Pages = 0x400006dc;
Cache_Travel_Tag_Memory = 0x400006e0; Cache_Travel_Tag_Memory = 0x400006e0;
Cache_Get_Virtual_Addr = 0x400006e4; Cache_Get_Virtual_Addr = 0x400006e4;
Cache_Flash_To_SPIRAM_Copy = 0x400006e8; flash2spiram_instruction_offset = 0x400006e8;
flash2spiram_rodata_offset = 0x400006ec;
flash_instr_rodata_start_page = 0x400006f0;
flash_instr_rodata_end_page = 0x400006f4;
Cache_Set_IDROM_MMU_Info = 0x400006f8;
Cache_Flash_To_SPIRAM_Copy = 0x400006fc;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
rom_cache_op_cb = 0x4085ffcc; rom_cache_op_cb = 0x4085ffcc;
rom_cache_internal_table_ptr = 0x4085ffc8; rom_cache_internal_table_ptr = 0x4085ffc8;
@@ -239,8 +244,8 @@ rom_cache_internal_table_ptr = 0x4085ffc8;
***************************************/ ***************************************/
/* Functions */ /* Functions */
ets_clk_get_xtal_freq = 0x400006ec; ets_clk_get_xtal_freq = 0x40000700;
ets_clk_get_cpu_freq = 0x400006f0; ets_clk_get_cpu_freq = 0x40000704;
/*************************************** /***************************************
@@ -248,21 +253,21 @@ ets_clk_get_cpu_freq = 0x400006f0;
***************************************/ ***************************************/
/* Functions */ /* Functions */
gpio_set_output_level = 0x400006f4; gpio_set_output_level = 0x40000708;
gpio_get_input_level = 0x400006f8; gpio_get_input_level = 0x4000070c;
gpio_matrix_in = 0x400006fc; gpio_matrix_in = 0x40000710;
gpio_matrix_out = 0x40000700; gpio_matrix_out = 0x40000714;
gpio_bypass_matrix_in = 0x40000704; gpio_bypass_matrix_in = 0x40000718;
gpio_output_disable = 0x40000708; gpio_output_disable = 0x4000071c;
gpio_output_enable = 0x4000070c; gpio_output_enable = 0x40000720;
gpio_pad_input_disable = 0x40000710; gpio_pad_input_disable = 0x40000724;
gpio_pad_input_enable = 0x40000714; gpio_pad_input_enable = 0x40000728;
gpio_pad_pulldown = 0x40000718; gpio_pad_pulldown = 0x4000072c;
gpio_pad_pullup = 0x4000071c; gpio_pad_pullup = 0x40000730;
gpio_pad_select_gpio = 0x40000720; gpio_pad_select_gpio = 0x40000734;
gpio_pad_set_drv = 0x40000724; gpio_pad_set_drv = 0x40000738;
gpio_pad_unhold = 0x40000728; gpio_pad_unhold = 0x4000073c;
gpio_pad_hold = 0x4000072c; gpio_pad_hold = 0x40000740;
/*************************************** /***************************************
@@ -270,72 +275,33 @@ gpio_pad_hold = 0x4000072c;
***************************************/ ***************************************/
/* Functions */ /* Functions */
esprv_intc_int_set_priority = 0x40000730; esprv_intc_int_set_priority = 0x40000744;
esprv_intc_int_set_threshold = 0x40000734; esprv_intc_int_set_threshold = 0x40000748;
esprv_intc_int_enable = 0x40000738; esprv_intc_int_enable = 0x4000074c;
esprv_intc_int_disable = 0x4000073c; esprv_intc_int_disable = 0x40000750;
esprv_intc_int_set_type = 0x40000740; esprv_intc_int_set_type = 0x40000754;
PROVIDE( intr_handler_set = 0x40000744 ); PROVIDE( intr_handler_set = 0x40000758 );
intr_matrix_set = 0x40000748; intr_matrix_set = 0x4000075c;
ets_intr_register_ctx = 0x4000074c; ets_intr_register_ctx = 0x40000760;
ets_intr_lock = 0x40000750; ets_intr_lock = 0x40000764;
ets_intr_unlock = 0x40000754; ets_intr_unlock = 0x40000768;
ets_isr_attach = 0x40000758; ets_isr_attach = 0x4000076c;
ets_isr_mask = 0x4000075c; ets_isr_mask = 0x40000770;
ets_isr_unmask = 0x40000760; ets_isr_unmask = 0x40000774;
/*************************************** /***************************************
Group crypto Group crc
***************************************/ ***************************************/
/* Functions */ /* Functions */
md5_vector = 0x40000764; crc32_le = 0x40000778;
MD5Init = 0x40000768; crc16_le = 0x4000077c;
MD5Update = 0x4000076c; crc8_le = 0x40000780;
MD5Final = 0x40000770; crc32_be = 0x40000784;
crc32_le = 0x40000774; crc16_be = 0x40000788;
crc16_le = 0x40000778; crc8_be = 0x4000078c;
crc8_le = 0x4000077c; esp_crc8 = 0x40000790;
crc32_be = 0x40000780;
crc16_be = 0x40000784;
crc8_be = 0x40000788;
esp_crc8 = 0x4000078c;
ets_sha_enable = 0x40000790;
ets_sha_disable = 0x40000794;
ets_sha_get_state = 0x40000798;
ets_sha_init = 0x4000079c;
ets_sha_process = 0x400007a0;
ets_sha_starts = 0x400007a4;
ets_sha_update = 0x400007a8;
ets_sha_finish = 0x400007ac;
ets_sha_clone = 0x400007b0;
ets_hmac_enable = 0x400007b4;
ets_hmac_disable = 0x400007b8;
ets_hmac_calculate_message = 0x400007bc;
ets_hmac_calculate_downstream = 0x400007c0;
ets_hmac_invalidate_downstream = 0x400007c4;
ets_jtag_enable_temporarily = 0x400007c8;
ets_aes_enable = 0x400007cc;
ets_aes_disable = 0x400007d0;
ets_aes_setkey = 0x400007d4;
ets_aes_block = 0x400007d8;
ets_aes_setkey_dec = 0x400007dc;
ets_aes_setkey_enc = 0x400007e0;
ets_bigint_enable = 0x400007e4;
ets_bigint_disable = 0x400007e8;
ets_bigint_multiply = 0x400007ec;
ets_bigint_modmult = 0x400007f0;
ets_bigint_modexp = 0x400007f4;
ets_bigint_wait_finish = 0x400007f8;
ets_bigint_getz = 0x400007fc;
ets_ds_enable = 0x40000800;
ets_ds_disable = 0x40000804;
ets_ds_start_sign = 0x40000808;
ets_ds_is_busy = 0x4000080c;
ets_ds_finish_sign = 0x40000810;
ets_ds_encrypt_params = 0x40000814;
ets_mgf1_sha256 = 0x40000818;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
crc32_le_table_ptr = 0x4004fff8; crc32_le_table_ptr = 0x4004fff8;
crc16_le_table_ptr = 0x4004fff4; crc16_le_table_ptr = 0x4004fff4;
@@ -345,36 +311,88 @@ crc16_be_table_ptr = 0x4004ffe8;
crc8_be_table_ptr = 0x4004ffe4; crc8_be_table_ptr = 0x4004ffe4;
/***************************************
Group md5
***************************************/
/* Functions */
md5_vector = 0x40000794;
MD5Init = 0x40000798;
MD5Update = 0x4000079c;
MD5Final = 0x400007a0;
/***************************************
Group hwcrypto
***************************************/
/* Functions */
ets_sha_enable = 0x400007a4;
ets_sha_disable = 0x400007a8;
ets_sha_get_state = 0x400007ac;
ets_sha_init = 0x400007b0;
ets_sha_process = 0x400007b4;
ets_sha_starts = 0x400007b8;
ets_sha_update = 0x400007bc;
ets_sha_finish = 0x400007c0;
ets_sha_clone = 0x400007c4;
ets_hmac_enable = 0x400007c8;
ets_hmac_disable = 0x400007cc;
ets_hmac_calculate_message = 0x400007d0;
ets_hmac_calculate_downstream = 0x400007d4;
ets_hmac_invalidate_downstream = 0x400007d8;
ets_aes_enable = 0x400007dc;
ets_aes_disable = 0x400007e0;
ets_aes_setkey = 0x400007e4;
ets_aes_block = 0x400007e8;
ets_aes_setkey_dec = 0x400007ec;
ets_aes_setkey_enc = 0x400007f0;
ets_bigint_enable = 0x400007f4;
ets_bigint_disable = 0x400007f8;
ets_bigint_multiply = 0x400007fc;
ets_bigint_modmult = 0x40000800;
ets_bigint_modexp = 0x40000804;
ets_bigint_wait_finish = 0x40000808;
ets_bigint_getz = 0x4000080c;
ets_ds_enable = 0x40000810;
ets_ds_disable = 0x40000814;
ets_ds_start_sign = 0x40000818;
ets_ds_is_busy = 0x4000081c;
ets_ds_finish_sign = 0x40000820;
ets_ds_encrypt_params = 0x40000824;
/*************************************** /***************************************
Group efuse Group efuse
***************************************/ ***************************************/
/* Functions */ /* Functions */
ets_efuse_read = 0x4000081c; ets_efuse_read = 0x40000828;
ets_efuse_program = 0x40000820; ets_efuse_program = 0x4000082c;
ets_efuse_clear_program_registers = 0x40000824; ets_efuse_clear_program_registers = 0x40000830;
ets_efuse_write_key = 0x40000828; ets_efuse_write_key = 0x40000834;
ets_efuse_get_read_register_address = 0x4000082c; ets_efuse_get_read_register_address = 0x40000838;
ets_efuse_get_key_purpose = 0x40000830; ets_efuse_get_key_purpose = 0x4000083c;
ets_efuse_key_block_unused = 0x40000834; ets_efuse_key_block_unused = 0x40000840;
ets_efuse_find_unused_key_block = 0x40000838; ets_efuse_find_unused_key_block = 0x40000844;
ets_efuse_rs_calculate = 0x4000083c; ets_efuse_rs_calculate = 0x40000848;
ets_efuse_count_unused_key_blocks = 0x40000840; ets_efuse_count_unused_key_blocks = 0x4000084c;
ets_efuse_secure_boot_enabled = 0x40000844; ets_efuse_secure_boot_enabled = 0x40000850;
ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000848; ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000854;
ets_efuse_cache_encryption_enabled = 0x4000084c; ets_efuse_cache_encryption_enabled = 0x40000858;
ets_efuse_download_modes_disabled = 0x40000850; ets_efuse_download_modes_disabled = 0x4000085c;
ets_efuse_find_purpose = 0x40000854; ets_efuse_find_purpose = 0x40000860;
ets_efuse_force_send_resume = 0x40000858; ets_efuse_force_send_resume = 0x40000864;
ets_efuse_get_flash_delay_us = 0x4000085c; ets_efuse_get_flash_delay_us = 0x40000868;
ets_efuse_get_uart_print_control = 0x40000860; ets_efuse_get_uart_print_control = 0x4000086c;
ets_efuse_direct_boot_mode_disabled = 0x40000864; ets_efuse_direct_boot_mode_disabled = 0x40000870;
ets_efuse_security_download_modes_enabled = 0x40000868; ets_efuse_security_download_modes_enabled = 0x40000874;
ets_efuse_jtag_disabled = 0x4000086c; ets_efuse_jtag_disabled = 0x40000878;
ets_efuse_usb_print_is_disabled = 0x40000870; ets_efuse_usb_print_is_disabled = 0x4000087c;
ets_efuse_usb_download_mode_disabled = 0x40000874; ets_efuse_usb_download_mode_disabled = 0x40000880;
ets_efuse_usb_device_disabled = 0x40000878; ets_efuse_usb_device_disabled = 0x40000884;
ets_efuse_secure_boot_fast_wake_enabled = 0x4000087c; ets_efuse_secure_boot_fast_wake_enabled = 0x40000888;
ets_jtag_enable_temporarily = 0x4000088c;
/*************************************** /***************************************
@@ -382,9 +400,9 @@ ets_efuse_secure_boot_fast_wake_enabled = 0x4000087c;
***************************************/ ***************************************/
/* Functions */ /* Functions */
esp_rom_check_recover_key = 0x40000880; esp_rom_check_recover_key = 0x40000890;
esp_rom_km_huk_conf = 0x40000884; esp_rom_km_huk_conf = 0x40000894;
esp_rom_km_huk_risk = 0x40000888; esp_rom_km_huk_risk = 0x40000898;
/*************************************** /***************************************
@@ -392,13 +410,14 @@ esp_rom_km_huk_risk = 0x40000888;
***************************************/ ***************************************/
/* Functions */ /* Functions */
ets_emsa_pss_verify = 0x4000088c; ets_emsa_pss_verify = 0x4000089c;
ets_rsa_pss_verify = 0x40000890; ets_rsa_pss_verify = 0x400008a0;
ets_ecdsa_verify = 0x40000894; ets_ecdsa_verify = 0x400008a4;
ets_secure_boot_verify_bootloader_with_keys = 0x40000898; ets_secure_boot_verify_bootloader_with_keys = 0x400008a8;
ets_secure_boot_verify_signature = 0x4000089c; ets_secure_boot_verify_signature = 0x400008ac;
ets_secure_boot_read_key_digests = 0x400008a0; ets_secure_boot_read_key_digests = 0x400008b0;
ets_secure_boot_revoke_public_key_digest = 0x400008a4; ets_mgf1_sha256 = 0x400008b4;
ets_secure_boot_revoke_public_key_digest = 0x400008b8;
/*************************************** /***************************************
@@ -406,7 +425,7 @@ ets_secure_boot_revoke_public_key_digest = 0x400008a4;
***************************************/ ***************************************/
/* Functions */ /* Functions */
usb_serial_device_rx_one_char = 0x40000aa4; usb_serial_device_rx_one_char = 0x40000ab8;
usb_serial_device_rx_one_char_block = 0x40000aa8; usb_serial_device_rx_one_char_block = 0x40000abc;
usb_serial_device_tx_flush = 0x40000aac; usb_serial_device_tx_flush = 0x40000ac0;
usb_serial_device_tx_one_char = 0x40000ab0; usb_serial_device_tx_one_char = 0x40000ac4;

186
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.libgcc.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.libgcc.ld for esp32c5 /* ROM function interface esp32c5.rom.libgcc.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,23 +18,23 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
__addsf3 = 0x400008a8; __addsf3 = 0x400008bc;
__divsf3 = 0x400008ac; __divsf3 = 0x400008c0;
__eqsf2 = 0x400008b0; __eqsf2 = 0x400008c4;
__fixsfsi = 0x400008b4; __fixsfsi = 0x400008c8;
__floatsisf = 0x400008b8; __floatsisf = 0x400008cc;
__floatunsisf = 0x400008bc; __floatunsisf = 0x400008d0;
__gesf2 = 0x400008c0; __gesf2 = 0x400008d4;
__gtsf2 = 0x400008c4; __gtsf2 = 0x400008d8;
__lesf2 = 0x400008c8; __lesf2 = 0x400008dc;
__ltsf2 = 0x400008cc; __ltsf2 = 0x400008e0;
__mulsf3 = 0x400008d0; __mulsf3 = 0x400008e4;
__negsf2 = 0x400008d4; __negsf2 = 0x400008e8;
__nesf2 = 0x400008d8; __nesf2 = 0x400008ec;
__powisf2 = 0x400008dc; __powisf2 = 0x400008f0;
__subsf3 = 0x400008e0; __subsf3 = 0x400008f4;
__truncdfsf2 = 0x400008e4; __truncdfsf2 = 0x400008f8;
__unordsf2 = 0x400008e8; __unordsf2 = 0x400008fc;
/*************************************** /***************************************
@@ -42,78 +42,78 @@ __unordsf2 = 0x400008e8;
***************************************/ ***************************************/
/* Functions */ /* Functions */
__absvdi2 = 0x400008ec; __absvdi2 = 0x40000900;
__absvsi2 = 0x400008f0; __absvsi2 = 0x40000904;
__adddf3 = 0x400008f4; __adddf3 = 0x40000908;
__addvdi3 = 0x400008f8; __addvdi3 = 0x4000090c;
__addvsi3 = 0x400008fc; __addvsi3 = 0x40000910;
__ashldi3 = 0x40000900; __ashldi3 = 0x40000914;
__ashrdi3 = 0x40000904; __ashrdi3 = 0x40000918;
__bswapdi2 = 0x40000908; __bswapdi2 = 0x4000091c;
__bswapsi2 = 0x4000090c; __bswapsi2 = 0x40000920;
__clear_cache = 0x40000910; __clear_cache = 0x40000924;
__clrsbdi2 = 0x40000914; __clrsbdi2 = 0x40000928;
__clrsbsi2 = 0x40000918; __clrsbsi2 = 0x4000092c;
__clzdi2 = 0x4000091c; __clzdi2 = 0x40000930;
__clzsi2 = 0x40000920; __clzsi2 = 0x40000934;
__cmpdi2 = 0x40000924; __cmpdi2 = 0x40000938;
__ctzdi2 = 0x40000928; __ctzdi2 = 0x4000093c;
__ctzsi2 = 0x4000092c; __ctzsi2 = 0x40000940;
__divdc3 = 0x40000930; __divdc3 = 0x40000944;
__divdf3 = 0x40000934; __divdf3 = 0x40000948;
__divdi3 = 0x40000938; __divdi3 = 0x4000094c;
__divsc3 = 0x4000093c; __divsc3 = 0x40000950;
__divsi3 = 0x40000940; __divsi3 = 0x40000954;
__eqdf2 = 0x40000944; __eqdf2 = 0x40000958;
__extendsfdf2 = 0x40000948; __extendsfdf2 = 0x4000095c;
__ffsdi2 = 0x4000094c; __ffsdi2 = 0x40000960;
__ffssi2 = 0x40000950; __ffssi2 = 0x40000964;
__fixdfdi = 0x40000954; __fixdfdi = 0x40000968;
__fixdfsi = 0x40000958; __fixdfsi = 0x4000096c;
__fixsfdi = 0x4000095c; __fixsfdi = 0x40000970;
__fixunsdfsi = 0x40000960; __fixunsdfsi = 0x40000974;
__fixunssfdi = 0x40000964; __fixunssfdi = 0x40000978;
__fixunssfsi = 0x40000968; __fixunssfsi = 0x4000097c;
__floatdidf = 0x4000096c; __floatdidf = 0x40000980;
__floatdisf = 0x40000970; __floatdisf = 0x40000984;
__floatsidf = 0x40000974; __floatsidf = 0x40000988;
__floatundidf = 0x40000978; __floatundidf = 0x4000098c;
__floatundisf = 0x4000097c; __floatundisf = 0x40000990;
__floatunsidf = 0x40000980; __floatunsidf = 0x40000994;
__gcc_bcmp = 0x40000984; __gcc_bcmp = 0x40000998;
__gedf2 = 0x40000988; __gedf2 = 0x4000099c;
__gtdf2 = 0x4000098c; __gtdf2 = 0x400009a0;
__ledf2 = 0x40000990; __ledf2 = 0x400009a4;
__lshrdi3 = 0x40000994; __lshrdi3 = 0x400009a8;
__ltdf2 = 0x40000998; __ltdf2 = 0x400009ac;
__moddi3 = 0x4000099c; __moddi3 = 0x400009b0;
__modsi3 = 0x400009a0; __modsi3 = 0x400009b4;
__muldc3 = 0x400009a4; __muldc3 = 0x400009b8;
__muldf3 = 0x400009a8; __muldf3 = 0x400009bc;
__muldi3 = 0x400009ac; __muldi3 = 0x400009c0;
__mulsc3 = 0x400009b0; __mulsc3 = 0x400009c4;
__mulsi3 = 0x400009b4; __mulsi3 = 0x400009c8;
__mulvdi3 = 0x400009b8; __mulvdi3 = 0x400009cc;
__mulvsi3 = 0x400009bc; __mulvsi3 = 0x400009d0;
__nedf2 = 0x400009c0; __nedf2 = 0x400009d4;
__negdf2 = 0x400009c4; __negdf2 = 0x400009d8;
__negdi2 = 0x400009c8; __negdi2 = 0x400009dc;
__negvdi2 = 0x400009cc; __negvdi2 = 0x400009e0;
__negvsi2 = 0x400009d0; __negvsi2 = 0x400009e4;
__paritysi2 = 0x400009d4; __paritysi2 = 0x400009e8;
__popcountdi2 = 0x400009d8; __popcountdi2 = 0x400009ec;
__popcountsi2 = 0x400009dc; __popcountsi2 = 0x400009f0;
__powidf2 = 0x400009e0; __powidf2 = 0x400009f4;
__subdf3 = 0x400009e4; __subdf3 = 0x400009f8;
__subvdi3 = 0x400009e8; __subvdi3 = 0x400009fc;
__subvsi3 = 0x400009ec; __subvsi3 = 0x40000a00;
__ucmpdi2 = 0x400009f0; __ucmpdi2 = 0x40000a04;
__udivdi3 = 0x400009f4; __udivdi3 = 0x40000a08;
__udivmoddi4 = 0x400009f8; __udivmoddi4 = 0x40000a0c;
__udivsi3 = 0x400009fc; __udivsi3 = 0x40000a10;
__udiv_w_sdiv = 0x40000a00; __udiv_w_sdiv = 0x40000a14;
__umoddi3 = 0x40000a04; __umoddi3 = 0x40000a18;
__umodsi3 = 0x40000a08; __umodsi3 = 0x40000a1c;
__unorddf2 = 0x40000a0c; __unorddf2 = 0x40000a20;
__extenddftf2 = 0x40000a10; __extenddftf2 = 0x40000a24;
__trunctfdf2 = 0x40000a14; __trunctfdf2 = 0x40000a28;

119
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.net80211.ld
View File

@@ -1,12 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32c6.rom.net80211.ld for esp32c6 /* ROM function interface esp32c5.rom.net80211.ld for esp32c5
* *
* *
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,50 +18,71 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
esp_net80211_rom_version_get = 0x40000b4c; esp_net80211_rom_version_get = 0x40000b18;
ampdu_dispatch = 0x40000b50; esp_wifi_internal_tx = 0x40000b1c;
ampdu_dispatch_all = 0x40000b54; ampdu_dispatch = 0x40000b20;
ampdu_dispatch_as_many_as_possible = 0x40000b58; ampdu_dispatch_all = 0x40000b24;
ampdu_dispatch_movement = 0x40000b5c; ampdu_dispatch_as_many_as_possible = 0x40000b28;
ampdu_dispatch_upto = 0x40000b60; ampdu_dispatch_movement = 0x40000b2c;
chm_is_at_home_channel = 0x40000b64; ampdu_dispatch_upto = 0x40000b30;
cnx_node_is_existing = 0x40000b68; chm_is_at_home_channel = 0x40000b34;
cnx_node_search = 0x40000b6c; cnx_node_is_existing = 0x40000b38;
ic_ebuf_recycle_rx = 0x40000b70; cnx_node_search = 0x40000b3c;
ic_ebuf_recycle_tx = 0x40000b74; ic_ebuf_recycle_rx = 0x40000b40;
ic_reset_rx_ba = 0x40000b78; ic_ebuf_recycle_tx = 0x40000b44;
ieee80211_align_eb = 0x40000b7c; ic_reset_rx_ba = 0x40000b48;
/*ieee80211_ampdu_reorder = 0x40000b80;*/ ic_ebuf_alloc = 0x40000b4c;
ieee80211_ampdu_start_age_timer = 0x40000b84; ic_reset_extra_softap_rx_ba = 0x40000b50;
ieee80211_encap_esfbuf = 0x40000b88; ieee80211_align_eb = 0x40000b54;
ieee80211_is_tx_allowed = 0x40000b8c; ieee80211_ampdu_reorder = 0x40000b58;
ieee80211_output_pending_eb = 0x40000b90; ieee80211_ampdu_start_age_timer = 0x40000b5c;
/*ieee80211_output_process = 0x40000b94;*/ ieee80211_encap_esfbuf = 0x40000b60;
ieee80211_set_tx_desc = 0x40000b98; ieee80211_is_tx_allowed = 0x40000b64;
//sta_input = 0x40000b9c; ieee80211_output_pending_eb = 0x40000b68;
wifi_get_macaddr = 0x40000ba0; ieee80211_output_process = 0x40000b6c;
wifi_rf_phy_disable = 0x40000ba4; ieee80211_set_tx_desc = 0x40000b70;
wifi_rf_phy_enable = 0x40000ba8; ieee80211_classify = 0x40000b74;
ic_ebuf_alloc = 0x40000bac; ieee80211_copy_eb_header = 0x40000b78;
ieee80211_classify = 0x40000bb0; ieee80211_recycle_cache_eb = 0x40000b7c;
ieee80211_copy_eb_header = 0x40000bb4; ieee80211_search_node = 0x40000b80;
ieee80211_recycle_cache_eb = 0x40000bb8; ieee80211_crypto_encap = 0x40000b84;
ieee80211_search_node = 0x40000bbc; ieee80211_crypto_decap = 0x40000b88;
ieee80211_crypto_encap = 0x40000bc0; ieee80211_decap = 0x40000b8c;
/* ieee80211_crypto_decap = 0x40000bc4; */ ieee80211_set_tx_pti = 0x40000b90;
ieee80211_decap = 0x40000bc8; ieee80211_gettid = 0x40000b94;
wifi_is_started = 0x40000bcc; ieee80211_post_hmac_tx = 0x40000b98;
ieee80211_gettid = 0x40000bd0; ieee80211_alloc_tx_buf = 0x40000b9c;
ieee80211_encap_esfbuf_htc = 0x40000bd4; ieee80211_output_do = 0x40000ba0;
ieee80211_find_elem_match = 0x40000ba4;
ieee80211_find_ie_match = 0x40000ba8;
ieee80211_find_elem = 0x40000bac;
ieee80211_find_ext_elem = 0x40000bb0;
ieee80211_find_ie = 0x40000bb4;
ieee80211_find_ext_ie = 0x40000bb8;
ieee80211_merge_mbssid_profile = 0x40000bbc;
ieee80211_encap_esfbuf_htc = 0x40000bc0;
wifi_get_macaddr = 0x40000bc4;
wifi_rf_phy_disable = 0x40000bc8;
wifi_rf_phy_enable = 0x40000bcc;
wifi_is_started = 0x40000bd0;
sta_input = 0x40000bd4;
sta_rx_eapol = 0x40000bd8;
sta_reset_beacon_timeout = 0x40000bdc;
sta_get_beacon_timeout = 0x40000be0;
ampdu_process_multicast_address_qos_frame = 0x40000be4;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
net80211_funcs = 0x4087ffac; net80211_funcs = 0x4085ffac;
g_scan = 0x4087ffa8; g_scan = 0x4085ffa8;
g_chm = 0x4087ffa4; g_chm = 0x4085ffa4;
g_ic_ptr = 0x4087ffa0; g_ic_ptr = 0x4085ffa0;
g_hmac_cnt_ptr = 0x4087ff9c; g_hmac_cnt_ptr = 0x4085ff9c;
g_tx_cacheq_ptr = 0x4087ff98; g_tx_cacheq_ptr = 0x4085ff98;
s_netstack_free = 0x4087ff94; s_netstack_free = 0x4085ff94;
mesh_rxcb = 0x4087ff90; s_encap_amsdu_func = 0x4085ff90;
sta_rxcb = 0x4087ff8c; mesh_rxcb = 0x4085ff8c;
g_itwt_fid = 0x4087ff88; sta_rxcb = 0x4085ff88;
esp_test_tx_addba_request = 0x4087ff84; s_netstack_ref = 0x4085ff84;
g_sta_connected_flag = 0x4085ff81;
g_itwt_fid = 0x4085ff80;
g_misc_nvs = 0x4085ff7c;
esp_test_dump_htc = 0x4085ff78;

2
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.newlib-normal.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5 /* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *

2
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.newlib.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.newlib.ld for esp32c5 /* ROM function interface esp32c5.rom.newlib.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *

497
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.phy.ld
View File

@@ -1,12 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32c6.rom.phy.ld for esp32c6 /* ROM function interface esp32c5.rom.phy.ld for esp32c5
* *
* *
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,228 +18,271 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
phy_param_addr = 0x40001104; phy_param_addr = 0x400010dc;
phy_get_romfuncs = 0x40001108; chip752_phyrom_version = 0x400010e0;
chip761_phyrom_version = 0x4000110c; chip752_phyrom_version_num = 0x400010e4;
chip761_phyrom_version_num = 0x40001110; phy_rate_to_index = 0x400010e8;
get_rc_dout = 0x40001114; phy_get_target_pwr = 0x400010ec;
rc_cal = 0x40001118; phy_get_max_pwr = 0x400010f0;
rom_enter_critical_phy = 0x4000111c; phy_get_pwr_index = 0x400010f4;
rom_exit_critical_phy = 0x40001120; phy_get_rc_dout = 0x400010f8;
rom_set_chan_cal_interp = 0x40001124; phy_rc_cal = 0x400010fc;
rom_loopback_mode_en = 0x40001128; phy_abs_temp = 0x40001100;
rom_bb_bss_cbw40 = 0x4000112c; phy_set_chan_interp = 0x40001104;
abs_temp = 0x40001130; phy_loop_clk_en = 0x40001108;
get_data_sat = 0x40001134; phy_get_data_sat = 0x4000110c;
phy_byte_to_word = 0x40001138; phy_byte_to_word = 0x40001110;
set_chan_reg = 0x4000113c; phy_get_rx_freq = 0x40001114;
i2c_master_reset = 0x40001140; phy_bb_bss_cbw40 = 0x40001118;
rom_set_chan_freq_sw_start = 0x40001144; phy_set_chan_reg = 0x4000111c;
freq_module_resetn = 0x40001148; phy_i2c_master_reset = 0x40001120;
freq_chan_en_sw = 0x4000114c; phy_chan14_mic_enable = 0x40001124;
write_chan_freq = 0x40001150; phy_chan14_mic_cfg = 0x40001128;
get_freq_mem_param = 0x40001154; phy_set_most_tpw = 0x4000112c;
get_freq_mem_addr = 0x40001158; phy_get_most_tpw = 0x40001130;
bt_txpwr_freq = 0x4000115c; phy_tx_state_out = 0x40001134;
wr_rf_freq_mem = 0x40001160; phy_ant_dft_cfg = 0x40001138;
read_rf_freq_mem = 0x40001164; phy_ant_wifitx_cfg = 0x4000113c;
freq_i2c_mem_write = 0x40001168; phy_ant_wifirx_cfg = 0x40001140;
freq_num_get_data = 0x4000116c; phy_ant_bttx_cfg = 0x40001144;
freq_i2c_num_addr = 0x40001170; phy_ant_btrx_cfg = 0x40001148;
freq_i2c_write_set = 0x40001174; phy_chan_dump_cfg = 0x4000114c;
pll_dac_mem_update = 0x40001178; phy_chan_dump_cfg_752 = 0x40001150;
pll_cap_mem_update = 0x4000117c; phy_enable_low_rate = 0x40001154;
get_rf_freq_cap = 0x40001180; phy_disable_low_rate = 0x40001158;
get_rf_freq_init = 0x40001184; phy_is_low_rate_enabled = 0x4000115c;
phy_en_hw_set_freq = 0x40001188; phy_dig_reg_backup = 0x40001160;
phy_dis_hw_set_freq = 0x4000118c; phy_chan_filt_set = 0x40001164;
rom_pwdet_sar2_init = 0x40001190; phy_rx11blr_cfg = 0x40001168;
rom_en_pwdet = 0x40001194; phy_set_cca = 0x4000116c;
rom_get_sar_sig_ref = 0x40001198; phy_set_rx_sense = 0x40001170;
rom_pwdet_tone_start = 0x4000119c; phy_freq_module_resetn = 0x40001174;
rom_pwdet_wait_idle = 0x400011a0; phy_freq_chan_en_sw = 0x40001178;
rom_read_sar_dout = 0x400011a4; phy_write_chan_freq = 0x4000117c;
get_tone_sar_dout = 0x400011a8; phy_get_freq_mem_param = 0x40001180;
get_fm_sar_dout = 0x400011ac; phy_get_freq_mem_addr = 0x40001184;
txtone_linear_pwr = 0x400011b0; phy_wr_freq_mem = 0x40001188;
linear_to_db = 0x400011b4; phy_read_rf_freq_mem = 0x4000118c;
get_power_db = 0x400011b8; phy_freq_i2c_mem_write = 0x40001190;
meas_tone_pwr_db = 0x400011bc; phy_freq_num_get_data = 0x40001194;
pkdet_vol_start = 0x400011c0; phy_freq_i2c_num_addr = 0x40001198;
read_sar2_code = 0x400011c4; phy_freq_i2c_write_set = 0x4000119c;
get_sar2_vol = 0x400011c8; phy_pll_cap_mem_update = 0x400011a0;
get_pll_vol = 0x400011cc; phy_en_hw_set_freq = 0x400011a4;
tx_pwctrl_bg_init = 0x400011d0; phy_dis_hw_set_freq = 0x400011a8;
phy_pwdet_always_en = 0x400011d4; phy_wait_freq_set_busy = 0x400011ac;
phy_pwdet_onetime_en = 0x400011d8; phy_i2c_enter_critical_ = 0x400011b0;
esp_tx_state_out_rom = 0x400011dc; phy_i2c_exit_critical_ = 0x400011b4;
ant_dft_cfg_rom = 0x400011e0; phy_i2c_clk_sel = 0x400011b8;
ant_wifitx_cfg_rom = 0x400011e4; phy_get_i2c_read_mask_ = 0x400011bc;
ant_wifirx_cfg_rom = 0x400011e8; phy_get_i2c_mst0_mask = 0x400011c0;
ant_bttx_cfg_rom = 0x400011ec; phy_get_i2c_hostid_ = 0x400011c4;
ant_btrx_cfg_rom = 0x400011f0; phy_chip_i2c_readReg_org = 0x400011c8;
phy_chan_dump_cfg_rom = 0x400011f4; phy_chip_i2c_readReg = 0x400011cc;
phy_enable_low_rate = 0x400011f8; phy_i2c_paral_set_mst0 = 0x400011d0;
phy_disable_low_rate = 0x400011fc; phy_i2c_paral_set_read = 0x400011d4;
phy_is_low_rate_enabled = 0x40001200; phy_i2c_paral_read = 0x400011d8;
phy_dig_reg_backup_rom = 0x40001204; phy_i2c_paral_write = 0x400011dc;
phy_chan_filt_set_rom = 0x40001208; phy_i2c_paral_write_num = 0x400011e0;
phy_rx11blr_cfg = 0x4000120c; phy_i2c_paral_write_mask = 0x400011e4;
set_cca_rom = 0x40001210; phy_i2c_readReg = 0x400011e8;
set_rx_sense_rom = 0x40001214; phy_chip_i2c_writeReg = 0x400011ec;
rx_gain_force_rom = 0x40001218; phy_i2c_writeReg = 0x400011f0;
rom_rfpll_set_freq = 0x4000121c; phy_i2c_readReg_Mask = 0x400011f4;
mhz2ieee = 0x40001220; phy_set_txcap_reg = 0x400011f8;
chan_to_freq = 0x40001224; phy_i2c_sar2_init_code = 0x400011fc;
restart_cal = 0x40001228; phy_i2c_pkdet_set = 0x40001200;
write_rfpll_sdm = 0x4000122c; phy_filter_dcap_set = 0x40001204;
wait_rfpll_cal_end = 0x40001230; phy_i2c_rc_cal_set = 0x40001208;
set_rf_freq_offset = 0x40001234; phy_ckgen_5g_cal = 0x4000120c;
set_rfpll_freq = 0x40001238; phy_ckgen_2g_cal = 0x40001210;
set_channel_rfpll_freq = 0x4000123c; phy_adc_rate_set = 0x40001214;
rfpll_cap_correct = 0x40001240; phy_dac_rate_set = 0x40001218;
rfpll_cap_init_cal = 0x40001244; phy_encode_i2c_master = 0x4000121c;
write_pll_cap = 0x40001248; phy_i2c_master_fill = 0x40001220;
read_pll_cap = 0x4000124c; phy_band_reg = 0x40001224;
chip_v7_set_chan_ana = 0x40001250; phy_open_fe_bb_clk = 0x40001228;
freq_set_reg = 0x40001254; phy_get_mac_addr = 0x4000122c;
gen_rx_gain_table = 0x40001258; phy_set_mac_data = 0x40001230;
bt_txdc_cal = 0x4000125c; phy_rfcal_data_sub = 0x40001234;
bt_txiq_cal = 0x40001260; phy_rf_cal_data_recovery = 0x40001238;
txiq_cal_init = 0x40001264; phy_rf_cal_data_backup = 0x4000123c;
txdc_cal_init = 0x40001268; phy_rfcal_data_check = 0x40001240;
txdc_cal = 0x4000126c; phy_pbus_force_mode = 0x40001244;
txiq_get_mis_pwr = 0x40001270; phy_pbus_rd_addr_ = 0x40001248;
txiq_cover = 0x40001274; phy_pbus_force_test = 0x4000124c;
rfcal_txiq = 0x40001278; phy_pbus_rd = 0x40001250;
get_power_atten = 0x4000127c; phy_pbus_debugmode = 0x40001254;
pwdet_ref_code = 0x40001280; phy_pbus_workmode = 0x40001258;
pwdet_code_cal = 0x40001284; phy_pbus_clear_reg = 0x4000125c;
rfcal_txcap = 0x40001288; phy_pbus_set_rxgain = 0x40001260;
tx_cap_init = 0x4000128c; phy_pbus_set_dco = 0x40001264;
rfcal_pwrctrl = 0x40001290; phy_set_loopback_gain = 0x40001268;
tx_pwctrl_init_cal = 0x40001294; phy_txcal_debuge_mode_ = 0x4000126c;
tx_pwctrl_init = 0x40001298; phy_txcal_work_mode = 0x40001270;
bt_tx_pwctrl_init = 0x4000129c; phy_write_pbus_mem = 0x40001274;
rom_i2c_enter_critical = 0x400012a0; phy_set_pbus_mem_2g = 0x40001278;
rom_i2c_exit_critical = 0x400012a4; phy_set_pbus_mem_5g = 0x4000127c;
rom_get_i2c_read_mask = 0x400012a8; phy_pbus_reg_store = 0x40001280;
rom_get_i2c_mst0_mask = 0x400012ac; phy_set_pbus_mem = 0x40001284;
rom_get_i2c_hostid = 0x400012b0; phy_get_rx_pbus_freq = 0x40001288;
rom_chip_i2c_readReg_org = 0x400012b4; phy_set_rx_pbus_freq = 0x4000128c;
rom_chip_i2c_readReg = 0x400012b8; phy_pbus_xpd_iq_path = 0x40001290;
rom_chip_i2c_writeReg = 0x400012c0; phy_pbus_set_rftx1_5g = 0x40001294;
rom_set_txcap_reg = 0x400012d0; phy_pwdet_reg_init = 0x40001298;
i2c_paral_set_mst0 = 0x400012d4; phy_pwdet_sar2_init = 0x4000129c;
i2c_paral_set_read = 0x400012d8; phy_en_pwdet = 0x400012a0;
i2c_paral_read = 0x400012dc; phy_get_sar_sig_ref = 0x400012a4;
i2c_paral_write = 0x400012e0; phy_pwdet_tone_start = 0x400012a8;
i2c_paral_write_num = 0x400012e4; phy_get_tone_sar_dout = 0x400012ac;
i2c_paral_write_mask = 0x400012e8; phy_get_fm_sar_dout = 0x400012b0;
i2c_sar2_init_code = 0x400012ec; phy_txtone_linear_pwr = 0x400012b4;
rom_pbus_force_mode = 0x400012f0; phy_linear_to_db = 0x400012b8;
rom_pbus_rd_addr = 0x400012f4; phy_get_power_db = 0x400012bc;
rom_pbus_rd_shift = 0x400012f8; phy_meas_tone_pwr_db = 0x400012c0;
rom_pbus_force_test = 0x400012fc; phy_pwdet_wait_idle = 0x400012c4;
rom_pbus_rd = 0x40001300; phy_pkdet_vol_start = 0x400012c8;
rom_pbus_set_rxgain = 0x40001304; phy_read_sar_dout = 0x400012cc;
rom_pbus_xpd_rx_off = 0x40001308; phy_read_sar2_code = 0x400012d0;
rom_pbus_xpd_rx_on = 0x4000130c; phy_get_sar2_vol = 0x400012d4;
rom_pbus_xpd_tx_off = 0x40001310; phy_get_pkdet_data = 0x400012d8;
rom_pbus_xpd_tx_on = 0x40001314; phy_rx_pkdet_dc_cal = 0x400012dc;
rom_set_loopback_gain = 0x40001318; phy_disable_agc = 0x400012e0;
rom_txcal_debuge_mode = 0x4000131c; phy_enable_agc = 0x400012e4;
pbus_debugmode = 0x40001320; phy_disable_cca = 0x400012e8;
pbus_workmode = 0x40001324; phy_enable_cca = 0x400012ec;
pbus_set_dco = 0x40001328; phy_write_gain_mem = 0x400012f0;
txcal_work_mode = 0x4000132c; phy_bb_bss_cbw40_dig = 0x400012f4;
rom_start_tx_tone_step = 0x40001330; phy_tx_paon_set = 0x400012f8;
rom_stop_tx_tone = 0x40001334; phy_i2cmst_reg_init = 0x400012fc;
disable_agc = 0x40001338; phy_bt_gain_offset = 0x40001300;
enable_agc = 0x4000133c; phy_fe_reg_init = 0x40001304;
phy_disable_cca = 0x40001340; phy_mac_enable_bb = 0x40001308;
phy_enable_cca = 0x40001344; phy_bb_wdg_cfg = 0x4000130c;
write_gain_mem = 0x40001348; phy_fe_txrx_reset = 0x40001310;
bb_bss_cbw40_dig = 0x4000134c; phy_set_rx_comp_ = 0x40001314;
cbw2040_cfg = 0x40001350; phy_agc_max_gain_set = 0x40001318;
mac_tx_chan_offset = 0x40001354; phy_agc_reg_init = 0x4000131c;
tx_paon_set = 0x40001358; phy_bb_reg_init = 0x40001320;
pwdet_reg_init = 0x4000135c; phy_open_i2c_xpd = 0x40001324;
i2cmst_reg_init = 0x40001360; phy_force_txrx_off = 0x40001328;
bt_gain_offset = 0x40001364; phy_txiq_set_reg = 0x4000132c;
fe_reg_init = 0x40001368; phy_rxiq_set_reg = 0x40001330;
mac_enable_bb = 0x4000136c; phy_rx_gain_force = 0x40001334;
bb_wdg_cfg = 0x40001370; phy_set_txclk_en = 0x40001338;
fe_txrx_reset = 0x40001374; phy_set_rxclk_en = 0x4000133c;
set_rx_comp = 0x40001378; phy_start_tx_tone_step = 0x40001340;
agc_reg_init = 0x4000137c; phy_stop_tx_tone = 0x40001344;
bb_reg_init = 0x40001380; phy_bb_wdg_test_en = 0x40001348;
open_i2c_xpd = 0x40001384; phy_noise_floor_auto_set = 0x4000134c;
txiq_set_reg = 0x40001388; phy_read_hw_noisefloor = 0x40001350;
rxiq_set_reg = 0x4000138c; phy_iq_corr_enable = 0x40001354;
set_txclk_en = 0x40001390; phy_wifi_agc_sat_gain = 0x40001358;
set_rxclk_en = 0x40001394; phy_bbpll_cal = 0x4000135c;
bb_wdg_test_en = 0x40001398; phy_ant_init = 0x40001360;
noise_floor_auto_set = 0x4000139c; phy_wifi_fbw_sel = 0x40001364;
read_hw_noisefloor = 0x400013a0; phy_bt_filter_reg = 0x40001368;
iq_corr_enable = 0x400013a4; phy_rx_sense_set = 0x4000136c;
wifi_agc_sat_gain = 0x400013a8; phy_tx_state_set = 0x40001370;
phy_bbpll_cal = 0x400013ac; phy_close_pa = 0x40001374;
phy_ant_init = 0x400013b0; phy_freq_correct = 0x40001378;
phy_set_bbfreq_init = 0x400013b4; phy_set_pbus_reg = 0x4000137c;
wifi_fbw_sel = 0x400013b8; phy_wifi_rifs_mode_en = 0x40001380;
bt_filter_reg = 0x400013bc; phy_rfagc_disable = 0x40001384;
phy_rx_sense_set = 0x400013c0; phy_pkdadc_set = 0x40001388;
tx_state_set = 0x400013c4; phy_nrx_freq_set = 0x4000138c;
phy_close_pa = 0x400013c8; phy_fe_adc_on = 0x40001390;
phy_freq_correct = 0x400013cc; phy_force_pwr_index = 0x40001394;
set_pbus_reg = 0x400013d0; phy_fft_scale_force = 0x40001398;
wifi_rifs_mode_en = 0x400013d4; phy_force_rx_gain = 0x4000139c;
nrx_freq_set = 0x400013d8; phy_wifi_enable_set = 0x400013a0;
fe_adc_on = 0x400013dc; phy_bb_cbw_chan_cfg = 0x400013a4;
phy_force_pwr_index = 0x400013e0; phy_vht_support = 0x400013a8;
rom_iq_est_enable = 0x400013e4; phy_csidump_force_lltf_cfg = 0x400013ac;
rom_iq_est_disable = 0x400013e8; phy_hemu_ru26_good_res = 0x400013b0;
rom_bb_gain_index = 0x400013ec; phy_bb_cfo_cfg = 0x400013b4;
rom_rfrx_gain_index = 0x400013f0; phy_freq_band_reg_set = 0x400013b8;
dc_iq_est = 0x400013f4; phy_set_bb_wdg = 0x400013bc;
set_cal_rxdc = 0x400013f8; phy_sifs_reg_init = 0x400013c0;
rxiq_get_mis = 0x400013fc; phy_bbtx_outfilter = 0x400013c4;
rxiq_cover_mg_mp = 0x40001400; phy_bb_wdt_rst_enable = 0x400013c8;
rfcal_rxiq = 0x40001404; phy_bb_wdt_int_enable = 0x400013cc;
get_rfcal_rxiq_data = 0x40001408; phy_bb_wdt_timeout_clear = 0x400013d0;
get_dco_comp = 0x4000140c; phy_bb_wdt_get_status = 0x400013d4;
pbus_rx_dco_cal = 0x40001410; phy_freq_to_chan = 0x400013d8;
rxdc_est_min = 0x40001414; phy_chan_to_freq = 0x400013dc;
pbus_rx_dco_cal_1step = 0x40001418; phy_freq_to_index = 0x400013e0;
set_lb_txiq = 0x4000141c; phy_iq_est_enable = 0x400013e4;
set_rx_gain_cal_iq = 0x40001420; phy_iq_est_disable = 0x400013e8;
set_rx_gain_cal_dc = 0x40001424; phy_dc_iq_est = 0x400013ec;
spur_reg_write_one_tone = 0x40001428; phy_set_cal_rxdc = 0x400013f0;
spur_cal = 0x4000142c; phy_rxiq_get_mis = 0x400013f4;
spur_coef_cfg = 0x40001430; phy_rxiq_cover_mg_mp = 0x400013f8;
tsens_power_up = 0x40001434; phy_rfcal_rxiq = 0x400013fc;
tsens_read_init = 0x40001438; phy_get_rfcal_rxiq_data = 0x40001400;
code_to_temp = 0x4000143c; phy_get_dco_comp = 0x40001404;
tsens_index_to_dac = 0x40001440; phy_pbus_rx_dco_cal = 0x40001408;
tsens_index_to_offset = 0x40001444; phy_rxdc_est_min = 0x4000140c;
tsens_dac_cal = 0x40001448; phy_rx_dco_cal_1step = 0x40001410;
tsens_code_read = 0x4000144c; phy_set_lb_txiq = 0x40001414;
tsens_temp_read = 0x40001450; phy_rxiq_opt = 0x40001418;
temp_to_power = 0x40001454; phy_set_rx_gain_cal_iq = 0x4000141c;
get_temp_init = 0x40001458; phy_set_rx_gain_cal_dc = 0x40001420;
txbbgain_to_index = 0x4000145c; phy_spur_reg_write = 0x40001424;
index_to_txbbgain = 0x40001460; phy_spur_cal = 0x40001428;
bt_index_to_bb = 0x40001464; phy_spur_coef_cfg = 0x4000142c;
bt_bb_to_index = 0x40001468; phy_bb_gain_index = 0x40001430;
bt_get_tx_gain = 0x4000146c; phy_rfrx_gain_index = 0x40001434;
dig_gain_check = 0x40001470; phy_gen_rx_gain_table = 0x40001438;
wifi_get_tx_gain = 0x40001474; phy_get_rxbb_dc = 0x4000143c;
wifi_11g_rate_chg = 0x40001478; phy_wr_rx_gain_mem = 0x40001440;
bt_chan_pwr_interp = 0x4000147c; phy_set_tsens_power_ = 0x40001444;
get_rate_fcc_index = 0x40001480; phy_get_tsens_value_ = 0x40001448;
get_chan_target_power = 0x40001484; phy_tsens_read_init = 0x4000144c;
get_tx_gain_value = 0x40001488; phy_code_to_temp = 0x40001450;
wifi_get_target_power = 0x4000148c; phy_tsens_dac_to_index = 0x40001454;
phy_tsens_dac_cal = 0x40001458;
phy_tsens_code_read = 0x4000145c;
phy_tsens_temp_read = 0x40001460;
phy_tsens_temp_read_local = 0x40001464;
phy_temp_to_power_ = 0x40001468;
phy_bt_txdc_cal = 0x4000146c;
phy_bt_txiq_cal = 0x40001470;
phy_txdc_cal = 0x40001474;
phy_txdc_cal_pwdet = 0x40001478;
phy_txiq_get_mis_pwr = 0x4000147c;
phy_txiq_cover = 0x40001480;
phy_rfcal_txiq = 0x40001484;
phy_get_power_atten = 0x40001488;
phy_pwdet_ref_code = 0x4000148c;
phy_pwdet_code_cal = 0x40001490;
phy_rfcal_txcap = 0x40001494;
phy_txcap_setting = 0x40001498;
phy_get_cal_chan = 0x4000149c;
phy_get_chan_cal_index = 0x400014a0;
phy_get_chan_cap = 0x400014a4;
phy_freq_to_mbgain = 0x400014a8;
phy_rfcal_pwrctrl = 0x400014ac;
phy_get_pwdet_offset_ = 0x400014b0;
phy_tx_pwctrl_init_cal = 0x400014b4;
phy_tx_pwctrl_init = 0x400014b8;
phy_bt_tx_pwctrl_init = 0x400014bc;
phy_txbbgain_to_index = 0x400014c0;
phy_index_to_txbbgain = 0x400014c4;
phy_bt_get_tx_gain = 0x400014c8;
phy_dig_gain_check = 0x400014cc;
phy_wifi_get_tx_gain = 0x400014d0;
phy_wifi_11g_rate_chg = 0x400014d4;
phy_bt_chan_pwr_interp = 0x400014d8;
phy_set_tx_gain_mem = 0x400014dc;
phy_get_rate_fcc_index = 0x400014e0;
phy_get_chan_target_power = 0x400014e4;
phy_get_tx_gain_value = 0x400014e8;
phy_wifi_get_target_power = 0x400014ec;
phy_wifi_get_tx_tab_ = 0x400014f0;
phy_wifi_set_tx_gain = 0x400014f4;
phy_bt_get_tx_tab_ = 0x400014f8;
phy_bt_set_tx_gain = 0x400014fc;
phy_bt_tx_gain_init = 0x40001500;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
phy_param_rom = 0x4087fce8; phy_param_rom = 0x4085fc70;

845
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld
View File

@@ -1,12 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32c6.rom.pp.ld for esp32c6 /* ROM function interface esp32c5.rom.pp.ld for esp32c5
* *
* *
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,433 +18,419 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
esp_pp_rom_version_get = 0x40000bd8; esp_pp_rom_version_get = 0x40000be8;
ppCalTxopRTSThreshold = 0x40000bdc; RC_GetBlockAckTime = 0x40000bec;
RC_GetBlockAckTime = 0x40000be0; ebuf_list_remove = 0x40000bf0;
ebuf_list_remove = 0x40000be4; esf_buf_alloc = 0x40000bf4;
//esf_buf_alloc = 0x40000be8; esf_buf_alloc_dynamic = 0x40000bf8;
//esf_buf_alloc_dynamic = 0x40000bec; esf_buf_recycle = 0x40000bfc;
//esf_buf_recycle = 0x40000bf0; GetAccess = 0x40000c00;
GetAccess = 0x40000bf4; hal_mac_is_low_rate_enabled = 0x40000c04;
hal_mac_is_low_rate_enabled = 0x40000bf8; hal_mac_tx_get_blockack = 0x40000c08;
hal_mac_tx_get_blockack = 0x40000bfc; hal_mac_tx_set_ppdu = 0x40000c0c;
//hal_mac_tx_set_ppdu = 0x40000c00; hal_mac_tx_clr_mplen = 0x40000c10;
ic_get_trc = 0x40000c04; hal_mac_get_txq_state = 0x40000c14;
//ic_mac_deinit = 0x40000c08; hal_mac_clr_txq_state = 0x40000c18;
ic_mac_init = 0x40000c0c; hal_mac_get_txq_complete = 0x40000c1c;
ic_interface_enabled = 0x40000c10; hal_mac_deinit_twt_tx = 0x40000c20;
is_lmac_idle = 0x40000c14; hal_mac_is_dma_enable = 0x40000c24;
/*lmacAdjustTimestamp = 0x40000c18;*/ hal_he_get_bss_color = 0x40000c28;
lmacDiscardAgedMSDU = 0x40000c1c; hal_he_set_ersu = 0x40000c2c;
/*lmacDiscardMSDU = 0x40000c20;*/ hal_he_get_mplen_addr_start = 0x40000c30;
lmacEndFrameExchangeSequence = 0x40000c24; hal_he_get_mplen_addr_end = 0x40000c34;
lmacIsIdle = 0x40000c28; hal_he_set_bf_report_rate = 0x40000c38;
lmacIsLongFrame = 0x40000c2c; hal_he_set_ersu_ack_rate = 0x40000c3c;
/*lmacMSDUAged = 0x40000c30;*/ hal_he_get_aid = 0x40000c40;
lmacPostTxComplete = 0x40000c34; hal_random = 0x40000c44;
lmacProcessAllTxTimeout = 0x40000c38; hal_enable_tx_statistics = 0x40000c48;
lmacProcessCollisions = 0x40000c3c; hal_enable_rx_statistics = 0x40000c4c;
//lmacProcessRxSucData = 0x40000c40; hal_enable_tsf_timer = 0x40000c50;
lmacReachLongLimit = 0x40000c44; hal_wdev_timer_target_enable = 0x40000c54;
lmacReachShortLimit = 0x40000c48; hal_wdev_timer_set_target = 0x40000c58;
lmacRecycleMPDU = 0x40000c4c; hal_tsf_timer_set_target = 0x40000c5c;
lmacRxDone = 0x40000c50; hal_tsf_clear_soc_wakeup_request = 0x40000c60;
//lmacSetTxFrame = 0x40000c54; hal_get_tsf_time = 0x40000c64;
//lmacTxDone = 0x40000c58; hal_get_sta_tsf = 0x40000c68;
lmacTxFrame = 0x40000c5c; dbg_hal_check_clr_mplen_bitmap = 0x40000c6c;
mac_tx_set_duration = 0x40000c60; dbg_hal_check_set_mplen_bitmap = 0x40000c70;
//mac_tx_set_plcp0 = 0x40000c64; ic_get_trc = 0x40000c74;
//mac_tx_set_plcp1 = 0x40000c68; ic_mac_deinit = 0x40000c78;
mac_tx_set_plcp2 = 0x40000c6c; ic_mac_init = 0x40000c7c;
/* pm_check_state = 0x40000c70; */ ic_interface_enabled = 0x40000c80;
/* pm_disable_dream_timer = 0x40000c74; */ is_lmac_idle = 0x40000c84;
pm_disable_sleep_delay_timer = 0x40000c78; ic_get_he_rts_threshold_bytes = 0x40000c88;
pm_dream = 0x40000c7c; lmacAdjustTimestamp = 0x40000c8c;
pm_mac_wakeup = 0x40000c80; lmacDiscardAgedMSDU = 0x40000c90;
pm_mac_sleep = 0x40000c84; lmacDiscardMSDU = 0x40000c94;
//pm_enable_active_timer = 0x40000c88; lmacEndFrameExchangeSequence = 0x40000c98;
pm_enable_sleep_delay_timer = 0x40000c8c; lmacIsIdle = 0x40000c9c;
pm_local_tsf_process = 0x40000c90; lmacIsLongFrame = 0x40000ca0;
//pm_set_beacon_filter = 0x40000c94; lmacMSDUAged = 0x40000ca4;
pm_is_in_wifi_slice_threshold = 0x40000c98; lmacPostTxComplete = 0x40000ca8;
pm_is_waked = 0x40000c9c; lmacProcessAllTxTimeout = 0x40000cac;
//pm_keep_alive = 0x40000ca0; lmacProcessCollisions = 0x40000cb0;
/* pm_on_beacon_rx = 0x40000ca4; */ lmacProcessRxSucData = 0x40000cb4;
pm_on_data_rx = 0x40000ca8; lmacReachLongLimit = 0x40000cb8;
//pm_on_tbtt = 0x40000cac; lmacReachShortLimit = 0x40000cbc;
/* pm_parse_beacon = 0x40000cb0; */ lmacRecycleMPDU = 0x40000cc0;
//pm_process_tim = 0x40000cb4; lmacRxDone = 0x40000cc4;
//pm_rx_beacon_process = 0x40000cb8; lmacSetTxFrame = 0x40000cc8;
/* pm_rx_data_process = 0x40000cbc; */ lmacTxDone = 0x40000ccc;
//pm_sleep = 0x40000cc0; lmacTxFrame = 0x40000cd0;
pm_sleep_for = 0x40000cc4; lmacDisableTransmit = 0x40000cd4;
//pm_tbtt_process = 0x40000cc8; lmacDiscardFrameExchangeSequence = 0x40000cd8;
ppAMPDU2Normal = 0x40000ccc; lmacProcessCollision = 0x40000cdc;
ppAssembleAMPDU = 0x40000cd0; lmacProcessAckTimeout = 0x40000ce0;
ppCalFrameTimes = 0x40000cd4; lmacProcessShortRetryFail = 0x40000ce4;
ppCalSubFrameLength = 0x40000cd8; lmacProcessCollisions_task = 0x40000ce8;
//ppCalTxAMPDULength = 0x40000cdc; lmacProcessTxRtsError = 0x40000cec;
ppCheckTxAMPDUlength = 0x40000ce0; lmacProcessTxError = 0x40000cf0;
ppDequeueRxq_Locked = 0x40000ce4; lmacProcessCtsTimeout = 0x40000cf4;
ppDequeueTxQ = 0x40000ce8; lmacProcessLongRetryFail = 0x40000cf8;
ppEmptyDelimiterLength = 0x40000cec; lmacRetryTxFrame = 0x40000cfc;
ppEnqueueRxq = 0x40000cf0; lmacEndRetryAMPDUFail = 0x40000d00;
ppEnqueueTxDone = 0x40000cf4; lmacProcessTxSuccess = 0x40000d04;
ppGetTxframe = 0x40000cf8; lmacProcessTxComplete = 0x40000d08;
//ppMapTxQueue = 0x40000cfc; lmacProcessLongFrameSuccess = 0x40000d0c;
//ppProcTxSecFrame = 0x40000d00; lmacProcessShortFrameSuccess = 0x40000d10;
ppProcessRxPktHdr = 0x40000d04; lmacProcessModemStateRxBeacon = 0x40000d14;
//ppProcessTxQ = 0x40000d08; mac_tx_set_duration = 0x40000d18;
ppRecordBarRRC = 0x40000d0c; mac_tx_set_plcp0 = 0x40000d1c;
ppRecycleAmpdu = 0x40000d10; mac_tx_set_plcp1 = 0x40000d20;
ppRecycleRxPkt = 0x40000d14; mac_tx_set_plcp2 = 0x40000d24;
//ppResortTxAMPDU = 0x40000d18; mac_tx_set_len = 0x40000d28;
ppResumeTxAMPDU = 0x40000d1c; mac_tx_set_htsig = 0x40000d2c;
/*ppRxFragmentProc = 0x40000d20;*/ mac_tx_set_vhtsig = 0x40000d30;
//ppRxPkt = 0x40000d24; mac_tx_set_hesig = 0x40000d34;
ppRxProtoProc = 0x40000d28; mac_tx_set_tb = 0x40000d38;
ppSearchTxQueue = 0x40000d2c; mac_tx_set_mplen = 0x40000d3c;
ppSearchTxframe = 0x40000d30; mac_tx_set_txop_q = 0x40000d40;
ppSelectNextQueue = 0x40000d34; mac_tx_set_pti = 0x40000d44;
ppSubFromAMPDU = 0x40000d38; pm_check_state = 0x40000d48;
//ppTask = 0x40000d3c; pm_disable_dream_timer = 0x40000d4c;
//ppTxPkt = 0x40000d40; pm_disable_sleep_delay_timer = 0x40000d50;
ppTxProtoProc = 0x40000d44; pm_dream = 0x40000d54;
ppTxqUpdateBitmap = 0x40000d48; pm_mac_wakeup = 0x40000d58;
pp_coex_tx_request = 0x40000d4c; pm_mac_sleep = 0x40000d5c;
pp_hdrsize = 0x40000d50; pm_enable_active_timer = 0x40000d60;
pp_post = 0x40000d54; pm_enable_sleep_delay_timer = 0x40000d64;
pp_process_hmac_waiting_txq = 0x40000d58; pm_local_tsf_process = 0x40000d68;
rcGetAmpduSched = 0x40000d5c; pm_set_beacon_filter = 0x40000d6c;
rcUpdateRxDone = 0x40000d60; pm_is_in_wifi_slice_threshold = 0x40000d70;
rc_get_trc = 0x40000d64; pm_is_waked = 0x40000d74;
rc_get_trc_by_index = 0x40000d68; pm_keep_alive = 0x40000d78;
rcAmpduLowerRate = 0x40000d6c; pm_on_beacon_rx = 0x40000d7c;
rcampduuprate = 0x40000d70; pm_on_data_rx = 0x40000d80;
rcClearCurAMPDUSched = 0x40000d74; pm_on_data_tx = 0x40000d84;
rcClearCurSched = 0x40000d78; pm_on_tbtt = 0x40000d88;
rcClearCurStat = 0x40000d7c; pm_on_isr_sleep = 0x40000d8c;
/*rcGetSched = 0x40000d80;*/ pm_on_isr = 0x40000d90;
rcLowerSched = 0x40000d84; pm_on_isr_set_twt_target = 0x40000d94;
rcSetTxAmpduLimit = 0x40000d88; pm_on_isr_twt_wake = 0x40000d98;
rcTxUpdatePer = 0x40000d8c; pm_on_tsf_timer = 0x40000d9c;
rcUpdateAckSnr = 0x40000d90; pm_on_twt_force_tx = 0x40000da0;
/*rcUpdateRate = 0x40000d94;*/ pm_parse_beacon = 0x40000da4;
rcUpdateTxDone = 0x40000d98; pm_process_tim = 0x40000da8;
rcUpdateTxDoneAmpdu2 = 0x40000d9c; pm_rx_beacon_process = 0x40000dac;
rcUpSched = 0x40000da0; pm_rx_data_process = 0x40000db0;
rssi_margin = 0x40000da4; pm_sleep = 0x40000db4;
rx11NRate2AMPDULimit = 0x40000da8; pm_sleep_for = 0x40000db8;
TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000dac; pm_tbtt_process = 0x40000dbc;
TRC_AMPDU_PER_UP_THRESHOLD = 0x40000db0; pm_tx_data_done_process = 0x40000dc0;
trc_calc_duration = 0x40000db4; pm_allow_tx = 0x40000dc4;
trc_isTxAmpduOperational = 0x40000db8; pm_extend_tbtt_adaptive_servo = 0x40000dc8;
trc_onAmpduOp = 0x40000dbc; pm_scale_listen_interval = 0x40000dcc;
TRC_PER_IS_GOOD = 0x40000dc0; pm_parse_mbssid_element = 0x40000dd0;
trc_SetTxAmpduState = 0x40000dc4; pm_disconnected_wake = 0x40000dd4;
trc_tid_isTxAmpduOperational = 0x40000dc8; pm_tx_data_process = 0x40000dd8;
trcAmpduSetState = 0x40000dcc; pm_is_twt_awake = 0x40000ddc;
//wDevCheckBlockError = 0x40000dd0; pm_enable_twt_keep_alive = 0x40000de0;
wDev_AppendRxBlocks = 0x40000dd4; pm_twt_on_tsf_timer = 0x40000de4;
wDev_DiscardFrame = 0x40000dd8; pm_twt_process = 0x40000de8;
wDev_GetNoiseFloor = 0x40000ddc; pm_is_twt_start = 0x40000dec;
wDev_IndicateAmpdu = 0x40000de0; pm_twt_set_target_wdev_time = 0x40000df0;
//wDev_IndicateFrame = 0x40000de4; pm_twt_set_target_tsf = 0x40000df4;
wdev_mac_reg_load = 0x40000de8; pm_enable_twt_keep_alive_timer = 0x40000df8;
wdev_mac_reg_store = 0x40000dec; pm_mac_try_enable_modem_state = 0x40000dfc;
wdev_mac_special_reg_load = 0x40000df0; pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
wdev_mac_special_reg_store = 0x40000df4; pm_update_next_tbtt = 0x40000e04;
wdev_mac_wakeup = 0x40000df8; pm_twt_disallow_tx = 0x40000e08;
wdev_mac_sleep = 0x40000dfc; pm_clear_wakeup_signal = 0x40000e0c;
hal_mac_is_dma_enable = 0x40000e00; pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000e10;
//wDev_ProcessFiq = 0x40000e04; pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000e14;
//wDev_ProcessRxSucData = 0x40000e08; pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000e18;
//wdevProcessRxSucDataAll = 0x40000e0c; pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000e1c;
wdev_csi_len_align = 0x40000e10; pm_mac_modem_params_rt_update = 0x40000e20;
ppDequeueTxDone_Locked = 0x40000e14; pm_update_at_next_beacon = 0x40000e24;
//ppProcTxDone = 0x40000e18; tbtt_adaptive_setup = 0x40000e28;
//pm_tx_data_done_process = 0x40000e1c; tbtt_adaptive_servo = 0x40000e2c;
config_is_cache_tx_buf_enabled = 0x40000e20; ppAMPDU2Normal = 0x40000e30;
//ppMapWaitTxq = 0x40000e24; ppHEAMPDU2Normal = 0x40000e34;
ppProcessWaitingQueue = 0x40000e28; ppAssembleAMPDU = 0x40000e38;
ppDisableQueue = 0x40000e2c; ppCalFrameTimes = 0x40000e3c;
pm_allow_tx = 0x40000e30; ppCalSubFrameLength = 0x40000e40;
//wdev_is_data_in_rxlist = 0x40000e34; ppCalTxAMPDULength = 0x40000e44;
ppProcTxCallback = 0x40000e38; ppCheckTxAMPDUlength = 0x40000e48;
//mac_tx_set_hesig = 0x40000e3c; ppDequeueRxq_Locked = 0x40000e4c;
ppCalPreFecPaddingFactor = 0x40000e40; ppDequeueTxQ = 0x40000e50;
mac_tx_set_tb = 0x40000e44; ppEmptyDelimiterLength = 0x40000e54;
mac_tx_set_mplen = 0x40000e48; ppEnqueueRxq = 0x40000e58;
hal_get_tsf_timer = 0x40000e4c; ppEnqueueTxDone = 0x40000e5c;
ppTxPktForceWaked = 0x40000e50; ppGetTxframe = 0x40000e60;
lmacProcessLongFrameSuccess = 0x40000e54; ppMapTxQueue = 0x40000e64;
lmacProcessShortFrameSuccess = 0x40000e58; ppProcTxSecFrame = 0x40000e68;
//lmacDiscardFrameExchangeSequence = 0x40000e5c; ppProcessRxPktHdr = 0x40000e6c;
lmacProcessTBSuccess = 0x40000e60; ppProcessTxQ = 0x40000e70;
/*lmacProcessTxSuccess = 0x40000e64;*/ ppRecordBarRRC = 0x40000e74;
lmacProcessAckTimeout = 0x40000e68; ppRecycleAmpdu = 0x40000e78;
//lmacProcessTxComplete = 0x40000e6c; ppRecycleRxPkt = 0x40000e7c;
//ppRemoveHTC = 0x40000e70; ppResortTxAMPDU = 0x40000e80;
get_estimated_batime = 0x40000e74; ppResumeTxAMPDU = 0x40000e84;
is_use_muedca = 0x40000e78; ppRxFragmentProc = 0x40000e88;
hal_mac_tx_clr_mplen = 0x40000e7c; ppRxPkt = 0x40000e8c;
hal_mac_get_txq_state = 0x40000e80; ppRxProtoProc = 0x40000e90;
hal_mac_clr_txq_state = 0x40000e84; ppSearchTxQueue = 0x40000e94;
hal_mac_get_txq_complete = 0x40000e88; ppSearchTxframe = 0x40000e98;
ht_get_min_subframe_len = 0x40000e8c; ppSelectNextQueue = 0x40000e9c;
rx11ACRate2AMPDULimit = 0x40000e90; ppSubFromAMPDU = 0x40000ea0;
pwr_hal_clear_intr_status = 0x40000e94; ppTask = 0x40000ea4;
pwr_hal_clear_mac_modem_beacon_miss_intr_filter = 0x40000e98; ppTxPkt = 0x40000ea8;
pwr_hal_clear_mac_modem_rx_beacon_info = 0x40000e9c; ppTxProtoProc = 0x40000eac;
pwr_hal_clear_mac_modem_rx_beacon_miss_counter = 0x40000ea0; ppTxqUpdateBitmap = 0x40000eb0;
pwr_hal_clear_mac_modem_rx_beacon_sleep_counter = 0x40000ea4; pp_coex_tx_request = 0x40000eb4;
pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x40000ea8; pp_hdrsize = 0x40000eb8;
pwr_hal_get_intr_raw_signal = 0x40000eac; pp_post = 0x40000ebc;
pwr_hal_get_intr_status = 0x40000eb0; pp_process_hmac_waiting_txq = 0x40000ec0;
pwr_hal_get_mac_modem_beacon_miss_limit_exceeded_status = 0x40000eb4; ppDequeueTxDone_Locked = 0x40000ec4;
pwr_hal_get_mac_modem_rx_beacon_location_state = 0x40000eb8; ppProcTxDone = 0x40000ec8;
pwr_hal_get_mac_modem_rx_beacon_valid_state = 0x40000ebc; ppMapWaitTxq = 0x40000ecc;
pwr_hal_get_mac_modem_state_sleep_limit_exceeded_status = 0x40000ec0; ppProcessWaitingQueue = 0x40000ed0;
pwr_hal_set_beacon_filter_abort_disable = 0x40000ec4; ppDisableQueue = 0x40000ed4;
pwr_hal_set_beacon_filter_abort_enable = 0x40000ec8; ppCalVHTDeliNum = 0x40000ed8;
pwr_hal_set_beacon_filter_abort_length = 0x40000ecc; ppCalTxVHTSMPDULength = 0x40000edc;
//pwr_hal_set_beacon_filter_broadcast_wakeup_disable = 0x40000ed0; ppCheckTxRTS = 0x40000ee0;
//pwr_hal_set_beacon_filter_broadcast_wakeup_enable = 0x40000ed4; ppProcessLifeTime = 0x40000ee4;
pwr_hal_set_beacon_filter_disable = 0x40000ed8; ppProcTxCallback = 0x40000ee8;
pwr_hal_set_beacon_filter_enable = 0x40000edc; ppCalPreFecPaddingFactor = 0x40000eec;
pwr_hal_set_beacon_filter_force_dump_disable = 0x40000ee0; ppCalDeliNum = 0x40000ef0;
pwr_hal_set_beacon_filter_force_dump_enable = 0x40000ee4; ppRemoveHTC = 0x40000ef4;
pwr_hal_set_beacon_filter_force_dump_limit = 0x40000ee8; ppCheckTxHEAMPDUlength = 0x40000ef8;
pwr_hal_set_beacon_filter_force_sync_disable = 0x40000eec; ppCertSetRate = 0x40000efc;
pwr_hal_set_beacon_filter_force_sync_enable = 0x40000ef0; ppSelectTxFormat = 0x40000f00;
pwr_hal_set_beacon_filter_force_sync_limit = 0x40000ef4; ppCalTxHEAMPDULength = 0x40000f04;
pwr_hal_set_beacon_filter_frame_crc_state = 0x40000ef8; pp_coex_tx_release = 0x40000f08;
pwr_hal_set_beacon_filter_soc_wakeup_and_intr_disable = 0x40000efc; ppAdd2AMPDUTail = 0x40000f0c;
pwr_hal_set_beacon_filter_soc_wakeup_and_intr_enable = 0x40000f00; ppDirectRecycleAmpdu = 0x40000f10;
pwr_hal_set_beacon_filter_unicast_wakeup_disable = 0x40000f04; ppRegressAmpdu = 0x40000f14;
pwr_hal_set_beacon_filter_unicast_wakeup_enable = 0x40000f08; pp_timer_do_process = 0x40000f18;
pwr_hal_set_lpclk_cycle_time = 0x40000f0c; rcGetAmpduSched = 0x40000f1c;
pwr_hal_set_lpclk_sync_disable = 0x40000f10; rcUpdateRxDone = 0x40000f20;
pwr_hal_set_lpclk_sync_enable = 0x40000f14; rc_get_trc = 0x40000f24;
pwr_hal_set_mac_modem_beacon_miss_intr_disable = 0x40000f18; rc_get_trc_by_index = 0x40000f28;
pwr_hal_set_mac_modem_beacon_miss_intr_enable = 0x40000f1c; rcAmpduLowerRate = 0x40000f2c;
pwr_hal_set_mac_modem_beacon_miss_limit = 0x40000f20; rcampduuprate = 0x40000f30;
pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_disable = 0x40000f24; rcClearCurAMPDUSched = 0x40000f34;
pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_enable = 0x40000f28; rcClearCurSched = 0x40000f38;
pwr_hal_set_mac_modem_beacon_miss_timeout = 0x40000f2c; rcClearCurStat = 0x40000f3c;
pwr_hal_set_mac_modem_state_sleep_limit = 0x40000f30; rcGetSched = 0x40000f40;
pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_disable = 0x40000f34; rcLowerSched = 0x40000f44;
pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_enable = 0x40000f38; rcSetTxAmpduLimit = 0x40000f48;
pwr_hal_set_mac_modem_state_wakeup_protect_disable = 0x40000f3c; rcTxUpdatePer = 0x40000f4c;
pwr_hal_set_mac_modem_state_wakeup_protect_early_time = 0x40000f40; rcUpdateAckSnr = 0x40000f50;
pwr_hal_set_mac_modem_state_wakeup_protect_enable = 0x40000f44; rcUpdateRate = 0x40000f54;
pwr_hal_set_mac_modem_tbtt_auto_period_disable = 0x40000f48; rcUpdateTxDone = 0x40000f58;
pwr_hal_set_mac_modem_tbtt_auto_period_enable = 0x40000f4c; rcUpdateTxDoneAmpdu2 = 0x40000f5c;
pwr_hal_set_mac_modem_tbtt_auto_period_interval = 0x40000f50; rcUpSched = 0x40000f60;
pwr_hal_set_modem_state_interface = 0x40000f54; rcReachRetryLimit = 0x40000f64;
hal_tsf_clear_soc_wakeup_request = 0x40000f58; rcGetDCMMaxRate = 0x40000f68;
tsf_hal_clear_mac_modem_rf_power_state = 0x40000f5c; rcGetSMPDURate = 0x40000f6c;
tsf_hal_clear_soc_wakeup_request = 0x40000f60; rcGetRate = 0x40000f70;
tsf_hal_get_counter_value = 0x40000f64; rx11AXRate2AMPDULimit = 0x40000f74;
tsf_hal_get_mac_modem_rf_power_state = 0x40000f68; rx11NRate2AMPDULimit = 0x40000f78;
tsf_hal_get_tbtt_interval = 0x40000f6c; rssi_margin = 0x40000f7c;
tsf_hal_get_time = 0x40000f70; TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000f80;
tsf_hal_get_timer_target = 0x40000f74; TRC_AMPDU_PER_UP_THRESHOLD = 0x40000f84;
tsf_hal_is_tsf_enabled = 0x40000f78; TRC_PER_IS_GOOD = 0x40000f88;
tsf_hal_map_tbtt_target_to_rx_frame = 0x40000f7c; trc_calc_duration = 0x40000f8c;
tsf_hal_map_tsf_to_bssid = 0x40000f80; trc_isTxAmpduOperational = 0x40000f90;
tsf_hal_set_counter_value = 0x40000f84; trc_onAmpduOp = 0x40000f94;
tsf_hal_set_modem_wakeup_early_time = 0x40000f88; trc_SetTxAmpduState = 0x40000f98;
tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_disable = 0x40000f8c; trc_tid_isTxAmpduOperational = 0x40000f9c;
tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_enable = 0x40000f90; trcAmpduSetState = 0x40000fa0;
tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_disable = 0x40000f94; trc_set_bf_report_rate = 0x40000fa4;
tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_enable = 0x40000f98; trc_onPPTxDone = 0x40000fa8;
tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_disable = 0x40000f9c; wDevCheckBlockError = 0x40000fac;
tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_enable = 0x40000fa0; wDev_AppendRxBlocks = 0x40000fb0;
tsf_hal_set_tbtt_disable = 0x40000fa4; wDev_DiscardFrame = 0x40000fb4;
tsf_hal_set_tbtt_early_time = 0x40000fa8; wDev_GetNoiseFloor = 0x40000fb8;
tsf_hal_set_tbtt_enable = 0x40000fac; wDev_IndicateAmpdu = 0x40000fbc;
tsf_hal_set_tbtt_interval = 0x40000fb0; wDev_IndicateFrame = 0x40000fc0;
tsf_hal_set_tbtt_intr_disable = 0x40000fb4; wdev_mac_reg_load = 0x40000fc4;
tsf_hal_set_tbtt_intr_enable = 0x40000fb8; wdev_mac_reg_store = 0x40000fc8;
tsf_hal_set_tbtt_modem_wakeup_disable = 0x40000fbc; wdev_mac_special_reg_load = 0x40000fcc;
tsf_hal_set_tbtt_modem_wakeup_enable = 0x40000fc0; wdev_mac_special_reg_store = 0x40000fd0;
tsf_hal_set_tbtt_rf_ctrl_disable = 0x40000fc4; wdev_mac_wakeup = 0x40000fd4;
tsf_hal_set_tbtt_rf_ctrl_enable = 0x40000fc8; wdev_mac_sleep = 0x40000fd8;
tsf_hal_set_tbtt_rf_ctrl_wait_cycles = 0x40000fcc; wDev_ProcessFiq = 0x40000fdc;
tsf_hal_set_tbtt_soc_wakeup_disable = 0x40000fd0; wDev_ProcessRxSucData = 0x40000fe0;
tsf_hal_set_tbtt_soc_wakeup_enable = 0x40000fd4; wdevProcessRxSucDataAll = 0x40000fe4;
tsf_hal_set_tbtt_start_time = 0x40000fd8; wdev_csi_len_align = 0x40000fe8;
tsf_hal_set_time = 0x40000fdc; wDev_IndicateBeaconMemoryFrame = 0x40000fec;
tsf_hal_set_timer_disable = 0x40000fe0; wDev_ProcessBeaconMemoryRxSuc = 0x40000ff0;
tsf_hal_set_timer_enable = 0x40000fe4; wdevProcessModemStateRxBeacon = 0x40000ff4;
tsf_hal_set_timer_intr_disable = 0x40000fe8; wdev_is_data_in_rxlist = 0x40000ff8;
tsf_hal_set_timer_intr_enable = 0x40000fec; wdev_process_tbtt = 0x40000ffc;
tsf_hal_set_timer_modem_wakeup_disable = 0x40000ff0; wdev_process_tsf_timer = 0x40001000;
tsf_hal_set_timer_modem_wakeup_enable = 0x40000ff4; wdev_process_beacon_filter = 0x40001004;
tsf_hal_set_timer_rf_ctrl_disable = 0x40000ff8; wdev_process_mac_modem_beacon_miss = 0x40001008;
tsf_hal_set_timer_rf_ctrl_enable = 0x40000ffc; config_is_cache_tx_buf_enabled = 0x4000100c;
tsf_hal_set_timer_rf_ctrl_wait_cycles = 0x40001000; config_get_wifi_feature_capabilities = 0x40001010;
tsf_hal_set_timer_soc_wakeup_disable = 0x40001004; config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40001014;
tsf_hal_set_timer_soc_wakeup_enable = 0x40001008; esp_test_disable_tx_statistics = 0x40001018;
tsf_hal_set_timer_target = 0x4000100c; esp_test_enable_tx_statistics = 0x4000101c;
tsf_hal_set_tsf_disable = 0x40001010; esp_test_clr_tx_statistics = 0x40001020;
tsf_hal_set_tsf_enable = 0x40001014; esp_test_get_tx_statistics = 0x40001024;
tsf_hal_set_tsf_time_deviation = 0x40001018; esp_test_clr_tx_tb_statistics = 0x40001028;
tsf_hal_set_tsf_time_deviation_sync_disable = 0x4000101c; esp_test_get_tx_tb_statistics = 0x4000102c;
tsf_hal_set_tsf_time_deviation_sync_enable = 0x40001020; esp_test_tx_process_complete = 0x40001030;
tsf_hal_unmap_tbtt_target_to_rx_frame = 0x40001024; esp_test_tx_process_txq_state = 0x40001034;
//ppSelectTxFormat = 0x40001028; esp_test_tx_enab_statistics = 0x40001038;
//ppCertSetRate = 0x4000102c; esp_test_tx_tb_complete = 0x4000103c;
//ppHEAMPDU2Normal = 0x40001030; esp_test_tx_count_retry = 0x40001040;
//ppCalTxHEAMPDULength = 0x40001034; esp_test_tx_count_collision = 0x40001044;
//ppCalTxHESMPDULength = 0x40001038; esp_test_tx_count_timeout = 0x40001048;
rcGetRate = 0x4000103c; esp_test_rx_process_complete = 0x4000104c;
rcGetDCMMaxRate = 0x40001040; esp_test_clr_rx_statistics = 0x40001050;
//rcGetSMPDURate = 0x40001044; esp_test_get_rx_statistics = 0x40001054;
ppDirectRecycleAmpdu = 0x40001048; esp_test_set_rx_error_occurs = 0x40001058;
//ppCheckTxHEAMPDUlength = 0x4000104c; esp_test_get_rx_error_occurs = 0x4000105c;
//rx11AXRate2AMPDULimit = 0x40001050; esp_test_clr_rx_error_occurs = 0x40001060;
//ppRegressAmpdu = 0x40001054; esp_test_disable_rx_statistics = 0x40001064;
//ppCalDeliNum = 0x40001058; esp_test_enable_rx_statistics = 0x40001068;
ppAdd2AMPDUTail = 0x4000105c; esp_test_rx_parse_mu = 0x4000106c;
esp_test_disable_tx_statistics = 0x40001060; esp_test_get_rx_mu_statistics = 0x40001070;
esp_test_enable_tx_statistics = 0x40001064; esp_test_clr_rx_mu_statistics = 0x40001074;
esp_test_clr_tx_statistics = 0x40001068; esp_test_enable_rx_mu_statistics = 0x40001078;
esp_test_get_tx_statistics = 0x4000106c; esp_test_disable_rx_mu_statistics = 0x4000107c;
esp_test_clr_tx_tb_statistics = 0x40001070; test_tx_fail_statistics = 0x40001080;
esp_test_get_tx_tb_statistics = 0x40001074; test_tx_succ_statistics = 0x40001084;
test_tx_fail_statistics = 0x40001078; test_rx_process_complete_noeb = 0x40001088;
//test_tx_succ_statistics = 0x4000107c; test_rx_process_complete_retry = 0x4000108c;
//esp_test_tx_process_complete = 0x40001080; test_mumimo_get_heltf_num = 0x40001090;
//esp_test_tx_process_txq_state = 0x40001084; test_mimo_update_user_info = 0x40001094;
esp_test_tx_enab_statistics = 0x40001088; test_parse_rx_mu_mimo = 0x40001098;
esp_test_tx_tb_complete = 0x4000108c; test_nonmimo_update_user_info = 0x4000109c;
esp_test_tx_count_retry = 0x40001090; test_rx_parse_mumimo_complete_sigb = 0x400010a0;
esp_test_tx_count_collision = 0x40001094; test_get_nonmumimo_common = 0x400010a4;
esp_test_tx_count_timeout = 0x40001098; test_rx_parse_nonmumimo_complete_sigb = 0x400010a8;
hal_enable_tx_statistics = 0x4000109c; test_rx_parse_nonmumimo = 0x400010ac;
test_rx_process_complete_noeb = 0x400010a0; wifi_he_get_hetb_tid_bitmap = 0x400010b0;
test_rx_process_complete_retry = 0x400010a4; wifi_he_get_hetb_tid_bawin = 0x400010b4;
esp_test_rx_process_complete = 0x400010a8; ht_get_min_subframe_len = 0x400010b8;
esp_test_clr_rx_statistics = 0x400010ac; vht_get_min_subframe_len = 0x400010bc;
esp_test_get_rx_statistics = 0x400010b0; he_get_min_subframe_len = 0x400010c0;
test_free_rx_statistics = 0x400010b4; he_get_min_subframe_len_dcm = 0x400010c4;
esp_test_set_rx_error_occurs = 0x400010b8; is_ndpa_to_dut = 0x400010c8;
esp_test_get_rx_error_occurs = 0x400010bc; is_use_muedca = 0x400010cc;
esp_test_clr_rx_error_occurs = 0x400010c0; pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x400010d0;
esp_test_disable_rx_statistics = 0x400010c4; get_estimated_batime = 0x400010d4;
esp_test_enable_rx_statistics = 0x400010c8; get_sublen_offset = 0x400010d8;
hal_enable_rx_statistics = 0x400010cc;
get_user_num = 0x400010d0;
mumimo_spatial_cfg_get_nsts = 0x400010d4;
mumimo_spatial_cfg_get_nsts_tot = 0x400010d8;
test_mumimo_get_heltf_num = 0x400010dc;
test_mimo_update_user_info = 0x400010e0;
test_parse_rx_mu_mimo = 0x400010e4;
test_nonmimo_update_user_info = 0x400010e8;
test_parse_rx_mu_nonmimo = 0x400010ec;
esp_test_rx_parse_mu = 0x400010f0;
esp_test_get_rx_mu_statistics = 0x400010f4;
esp_test_clr_rx_mu_statistics = 0x400010f8;
esp_test_enable_rx_mu_statistics = 0x400010fc;
esp_test_disable_rx_mu_statistics = 0x40001100;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
our_instances_ptr = 0x4004ffe0; our_instances_ptr = 0x4004ffe0;
pTxRx = 0x4087ff80; pTxRx = 0x4085ff74;
lmacConfMib_ptr = 0x4087ff7c; lmacConfMib_ptr = 0x4085ff70;
our_wait_eb = 0x4087ff78; our_wait_eb = 0x4085ff6c;
our_tx_eb = 0x4087ff74; our_tx_eb = 0x4085ff68;
pp_wdev_funcs = 0x4087ff70; pp_wdev_funcs = 0x4085ff64;
g_osi_funcs_p = 0x4087ff6c; g_osi_funcs_p = 0x4085ff60;
wDevCtrl_ptr = 0x4087ff68; wDevCtrl_ptr = 0x4085ff5c;
g_wdev_last_desc_reset_ptr = 0x4004ffdc; g_wdev_last_desc_reset_ptr = 0x4004ffdc;
wDevMacSleep_ptr = 0x4087ff64; wDevMacSleep_ptr = 0x4085ff58;
g_lmac_cnt_ptr = 0x4087ff60; g_lmac_cnt_ptr = 0x4085ff54;
our_controls_ptr = 0x4004ffd8; our_controls_ptr = 0x4004ffd8;
pp_sig_cnt_ptr = 0x4087ff5c; pp_sig_cnt_ptr = 0x4085ff50;
g_eb_list_desc_ptr = 0x4087ff58; g_eb_list_desc_ptr = 0x4085ff4c;
s_fragment_ptr = 0x4087ff54; s_fragment_ptr = 0x4085ff48;
if_ctrl_ptr = 0x4087ff50; if_ctrl_ptr = 0x4085ff44;
g_intr_lock_mux = 0x4087ff4c; g_intr_lock_mux = 0x4085ff40;
g_wifi_global_lock = 0x4087ff48; g_wifi_global_lock = 0x4085ff3c;
s_wifi_queue = 0x4087ff44; s_wifi_queue = 0x4085ff38;
pp_task_hdl = 0x4087ff40; pp_task_hdl = 0x4085ff34;
s_pp_task_create_sem = 0x4087ff3c; s_pp_task_create_sem = 0x4085ff30;
s_pp_task_del_sem = 0x4087ff38; s_pp_task_del_sem = 0x4085ff2c;
g_wifi_menuconfig_ptr = 0x4087ff34; xphyQueue = 0x4085ff28;
xphyQueue = 0x4087ff30; ap_no_lr_ptr = 0x4085ff24;
ap_no_lr_ptr = 0x4087ff2c; rc11ASchedTbl_ptr = 0x4085ff20;
rc11BSchedTbl_ptr = 0x4087ff28; rc11BSchedTbl_ptr = 0x4085ff1c;
rc11NSchedTbl_ptr = 0x4087ff24; rc11NSchedTbl_ptr = 0x4085ff18;
rcLoRaSchedTbl_ptr = 0x4087ff20; rcLoRaSchedTbl_ptr = 0x4085ff14;
BasicOFDMSched_ptr = 0x4087ff1c; BasicOFDMSched_ptr = 0x4085ff10;
trc_ctl_ptr = 0x4087ff18; trc_ctl_ptr = 0x4085ff0c;
g_pm_cnt_ptr = 0x4087ff14; g_wifi_menuconfig_ptr = 0x4085ff08;
g_pm_ptr = 0x4087ff10; g_pm_cnt_ptr = 0x4085ff04;
g_pm_cfg_ptr = 0x4087ff0c; g_pm_ptr = 0x4085ff00;
g_esp_mesh_quick_funcs_ptr = 0x4087ff08; g_pm_cfg_ptr = 0x4085fefc;
g_txop_queue_status_ptr = 0x4087ff04; g_pm_twt_ptr = 0x4085fef8;
g_mac_sleep_en_ptr = 0x4087ff00; g_esp_mesh_quick_funcs_ptr = 0x4085fef4;
g_mesh_is_root_ptr = 0x4087fefc; g_txop_queue_status_ptr = 0x4085fef0;
g_mesh_topology_ptr = 0x4087fef8; g_mac_sleep_en_ptr = 0x4085feec;
g_mesh_init_ps_type_ptr = 0x4087fef4; g_mesh_is_root_ptr = 0x4085fee8;
g_mesh_is_started_ptr = 0x4087fef0; g_mesh_topology_ptr = 0x4085fee4;
g_config_func = 0x4087feec; g_mesh_init_ps_type_ptr = 0x4085fee0;
g_net80211_tx_func = 0x4087fee8; g_mesh_is_started_ptr = 0x4085fedc;
g_timer_func = 0x4087fee4; g_config_func = 0x4085fed8;
s_michael_mic_failure_cb = 0x4087fee0; g_net80211_tx_func = 0x4085fed4;
wifi_sta_rx_probe_req = 0x4087fedc; g_timer_func = 0x4085fed0;
g_tx_done_cb_func = 0x4087fed8; g_dbg_interp_tsf = 0x4085fecc;
g_per_conn_trc = 0x4087fe8c; g_dbg_interp_tsf_end = 0x4085fec8;
s_encap_amsdu_func = 0x4087fe88; g_dbg_closrf_tsf = 0x4085fec4;
rx_beacon_count = 0x4087fe84; g_dbg_closrf_idx = 0x4085fec0;
rx_beacon_sw_parse = 0x4087fe80; g_dbg_closrf_blk = 0x4085febc;
rx_beacon_hw_parse = 0x4087fe7c; s_michael_mic_failure_cb = 0x4085feb8;
rx_beacon_tim_count = 0x4087fe78; wifi_sta_rx_probe_req = 0x4085feb4;
rx_beacon_tim_udata = 0x4087fe74; g_tx_done_cb_func = 0x4085feb0;
rx_beacon_tim_udata_bitmap = 0x4087fe70; g_per_conn_trc = 0x4085fe58;
rx_beacon_tim_bdata = 0x4087fe6c; rx_beacon_count = 0x4085fe54;
rx_beacon_tim_bdata_bitmapctl = 0x4087fe68; rx_beacon_tim_count = 0x4085fe50;
rx_beacon_tim_bdata_bitmap_trans = 0x4087fe64; rx_beacon_tim_udata = 0x4085fe4c;
rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4087fe60; rx_beacon_tim_udata_bitmap = 0x4085fe48;
rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4087fe5c; rx_beacon_tim_bdata = 0x4085fe44;
rx_beacon_dtim_tim = 0x4087fe58; rx_beacon_tim_bdata_bitmapctl = 0x4085fe40;
rx_beacon_dtim_tim_mcast = 0x4087fe54; rx_beacon_tim_bdata_bitmap_trans = 0x4085fe3c;
amdpu_delay_time_ms = 0x4087fd08; rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4085fe38;
ampdu_delay_packet = 0x4087fd04; rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4085fe34;
ampdu_delay = 0x4087fe51; rx_beacon_dtim_tim = 0x4085fe30;
first_ampdu = 0x4087fe50; rx_beacon_dtim_tim_mcast = 0x4085fe2c;
s_ht_ampdu_density_us = 0x4087fd02; ampdu_delay = 0x4085fe28;
s_ht_ampdu_density = 0x4087fd01; s_ht_ampdu_density_us = 0x4085fc8a;
s_running_phy_type = 0x4087fd00; s_ht_ampdu_density = 0x4085fc89;
complete_ena_tb_seqno = 0x4087fe4c; s_running_phy_type = 0x4085fc88;
complete_ena_tb_final = 0x4087fe48; complete_ena_tb_seqno = 0x4085fe24;
complete_ena_tb_count = 0x4087fe44; complete_ena_tb_final = 0x4085fe20;
s_itwt_state = 0x4087fe40; complete_ena_tb_count = 0x4085fe1c;
g_dbg_interp_tsf = 0x4087fe3c; s_he_min_len_bytes = 0x4085fde0;
g_dbg_interp_tsf_end = 0x4087fe38; s_he_dcm_min_len_bytes = 0x4085fdc0;
g_dbg_closrf_tsf = 0x4087fe34; g_wdev_dbg_rx_ptr = 0x4085fdbc;
g_dbg_closrf_idx = 0x4087fe30; s_mplen_txq_bitmap = 0x4085fdac;
g_dbg_closrf_blk = 0x4087fe2c; s_mplen_be_high_bitmap = 0x4085fda8;
s_he_min_len_bytes = 0x4087fdf0; s_phy_get_max_pwr = 0x4085fd50;
s_he_dcm_min_len_bytes = 0x4087fdd0; esp_wifi_cert_tx_mcs = 0x4085fc84;
s_mplen_low_bitmap = 0x4087fdc0; esp_wifi_cert_tx_bcc = 0x4085fc80;
s_mplen_high_bitmap = 0x4087fdb0; esp_wifi_cert_tx_ltf = 0x4085fc7c;
s_mplen_vi_bitmap = 0x4087fdac; esp_wifi_cert_tx_gi = 0x4085fc78;
s_mplen_bk_bitmap = 0x4087fda8; esp_wifi_cert_tx_nss = 0x4085fc74;
esp_wifi_cert_tx_mcs = 0x4087fcfc; esp_wifi_cert_tx_ersu = 0x4085fd4c;
esp_wifi_cert_tx_bcc = 0x4087fcf8; g_mac_deinit_count = 0x4085fd48;
//esp_wifi_cert_tx_ltf = 0x4087fcf4; g_mac_deinit_rxing = 0x4085fd45;
//esp_wifi_cert_tx_gi = 0x4087fcf0; g_mac_deinit_txing = 0x4085fd44;
esp_wifi_cert_tx_nss = 0x4087fcec; s_bars = 0x4085fd34;
esp_test_tx_statistics_aci_bitmap = 0x4087fda4; esp_test_rx_statistics = 0x4085fd2c;
esp_test_tx_statistics = 0x4087fd94; esp_test_rx_mu_statistics = 0x4085fd28;
esp_test_tx_tb_statistics = 0x4087fd84; esp_test_tx_statistics_aci_bitmap = 0x4085fd24;
esp_test_tx_fail_statistics = 0x4087fd24; esp_test_tx_statistics = 0x4085fd14;
esp_test_rx_statistics = 0x4087fd1c; esp_test_tx_tb_statistics = 0x4085fd04;
esp_test_rx_mu_statistics = 0x4087fd18; esp_test_tx_fail_statistics = 0x4085fca4;
esp_test_mu_print_ru_allocation = 0x4087fd14; esp_test_mu_print_ru_allocation = 0x4085fca0;
sigb_ru_allocation_user_num = 0x4004ffc8; sigb_ru_allocation_user_num = 0x4004ffc8;
sigb_common_ru_allocation = 0x4004ff38; sigb_common_ru_allocation = 0x4004ff38;
mu_mimo_special_cfg_user_num_2 = 0x4004fee8; mu_mimo_special_cfg_user_num_2 = 0x4004fee8;
@@ -454,6 +440,9 @@ mu_mimo_special_cfg_user_num_5 = 0x4004fdf0;
mu_mimo_special_cfg_user_num_6 = 0x4004fdd0; mu_mimo_special_cfg_user_num_6 = 0x4004fdd0;
mu_mimo_special_cfg_user_num_7 = 0x4004fdc0; mu_mimo_special_cfg_user_num_7 = 0x4004fdc0;
mu_mimo_special_cfg_user_num_8 = 0x4004fdb8; mu_mimo_special_cfg_user_num_8 = 0x4004fdb8;
esp_test_rx_error_occurs = 0x4087fd10; esp_test_rx_error_occurs = 0x4085fc9c;
g_pp_tx_pkt_num = 0x4087fd0c; g_pp_tx_pkt_num = 0x4085fc98;
he_max_apep_length = 0x4004fd40; he_max_apep_length = 0x4004fd40;
g_pp_timer_info_ptr = 0x4085fc94;
g_rts_threshold_bytes_ptr = 0x4085fc90;
g_he_max_apep_length_tab_ptr = 0x4085fc8c;

135
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.rvfp.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.rvfp.ld for esp32c5 /* ROM function interface esp32c5.rom.rvfp.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -18,23 +18,23 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
__addsf3 = 0x40000a18; _rvfp__addsf3 = 0x40000a2c;
__eqsf2 = 0x40000a1c; _rvfp__eqsf2 = 0x40000a30;
__extendsfdf2 = 0x40000a20; _rvfp__extendsfdf2 = 0x40000a34;
__fixsfsi = 0x40000a24; _rvfp__fixsfsi = 0x40000a38;
__fixunssfsi = 0x40000a28; _rvfp__fixunssfsi = 0x40000a3c;
__floatdisf = 0x40000a2c; _rvfp__floatdisf = 0x40000a40;
__floatsisf = 0x40000a30; _rvfp__floatsisf = 0x40000a44;
__floatundisf = 0x40000a34; _rvfp__floatundisf = 0x40000a48;
__floatunsisf = 0x40000a38; _rvfp__floatunsisf = 0x40000a4c;
__gesf2 = 0x40000a3c; _rvfp__gesf2 = 0x40000a50;
__gtsf2 = 0x40000a40; _rvfp__gtsf2 = 0x40000a54;
__lesf2 = 0x40000a44; _rvfp__lesf2 = 0x40000a58;
__ltsf2 = 0x40000a48; _rvfp__ltsf2 = 0x40000a5c;
__mulsf3 = 0x40000a4c; _rvfp__mulsf3 = 0x40000a60;
__nesf2 = 0x40000a50; _rvfp__nesf2 = 0x40000a64;
__subsf3 = 0x40000a54; _rvfp__subsf3 = 0x40000a68;
__truncdfsf2 = 0x40000a58; _rvfp__truncdfsf2 = 0x40000a6c;
/*************************************** /***************************************
@@ -42,84 +42,21 @@ __truncdfsf2 = 0x40000a58;
***************************************/ ***************************************/
/* Functions */ /* Functions */
__adddf3 = 0x40000a5c; _rvfp__adddf3 = 0x40000a70;
__eqdf2 = 0x40000a60; _rvfp__eqdf2 = 0x40000a74;
__fixdfdi = 0x40000a64; _rvfp__fixdfdi = 0x40000a78;
__fixdfsi = 0x40000a68; _rvfp__fixdfsi = 0x40000a7c;
__fixsfdi = 0x40000a6c; _rvfp__fixsfdi = 0x40000a80;
__fixunsdfsi = 0x40000a70; _rvfp__fixunsdfsi = 0x40000a84;
__fixunssfdi = 0x40000a74; _rvfp__fixunssfdi = 0x40000a88;
__floatdidf = 0x40000a78; _rvfp__floatdidf = 0x40000a8c;
__floatsidf = 0x40000a7c; _rvfp__floatsidf = 0x40000a90;
__floatundidf = 0x40000a80; _rvfp__floatundidf = 0x40000a94;
__floatunsidf = 0x40000a84; _rvfp__floatunsidf = 0x40000a98;
__gedf2 = 0x40000a88; _rvfp__gedf2 = 0x40000a9c;
__gtdf2 = 0x40000a8c; _rvfp__gtdf2 = 0x40000aa0;
__ledf2 = 0x40000a90; _rvfp__ledf2 = 0x40000aa4;
__ltdf2 = 0x40000a94; _rvfp__ltdf2 = 0x40000aa8;
__muldf3 = 0x40000a98; _rvfp__muldf3 = 0x40000aac;
__nedf2 = 0x40000a9c; _rvfp__nedf2 = 0x40000ab0;
__subdf3 = 0x40000aa0; _rvfp__subdf3 = 0x40000ab4;
/***************************************
Group libgcc
***************************************/
/* Functions */
__divsf3 = 0x400008ac;
__negsf2 = 0x400008d4;
__powisf2 = 0x400008dc;
__unordsf2 = 0x400008e8;
__absvdi2 = 0x400008ec;
__absvsi2 = 0x400008f0;
__addvdi3 = 0x400008f8;
__addvsi3 = 0x400008fc;
__ashldi3 = 0x40000900;
__ashrdi3 = 0x40000904;
__bswapdi2 = 0x40000908;
__bswapsi2 = 0x4000090c;
__clear_cache = 0x40000910;
__clrsbdi2 = 0x40000914;
__clrsbsi2 = 0x40000918;
__clzdi2 = 0x4000091c;
__clzsi2 = 0x40000920;
__cmpdi2 = 0x40000924;
__ctzdi2 = 0x40000928;
__ctzsi2 = 0x4000092c;
__divdc3 = 0x40000930;
__divdf3 = 0x40000934;
__divdi3 = 0x40000938;
__divsc3 = 0x4000093c;
__divsi3 = 0x40000940;
__ffsdi2 = 0x4000094c;
__ffssi2 = 0x40000950;
__gcc_bcmp = 0x40000984;
__lshrdi3 = 0x40000994;
__moddi3 = 0x4000099c;
__modsi3 = 0x400009a0;
__muldc3 = 0x400009a4;
__muldi3 = 0x400009ac;
__mulsc3 = 0x400009b0;
__mulsi3 = 0x400009b4;
__mulvdi3 = 0x400009b8;
__mulvsi3 = 0x400009bc;
__negdf2 = 0x400009c4;
__negdi2 = 0x400009c8;
__negvdi2 = 0x400009cc;
__negvsi2 = 0x400009d0;
__paritysi2 = 0x400009d4;
__popcountdi2 = 0x400009d8;
__popcountsi2 = 0x400009dc;
__powidf2 = 0x400009e0;
__subvdi3 = 0x400009e8;
__subvsi3 = 0x400009ec;
__ucmpdi2 = 0x400009f0;
__udivdi3 = 0x400009f4;
__udivmoddi4 = 0x400009f8;
__udivsi3 = 0x400009fc;
__udiv_w_sdiv = 0x40000a00;
__umoddi3 = 0x40000a04;
__umodsi3 = 0x40000a08;
__unorddf2 = 0x40000a0c;
__extenddftf2 = 0x40000a10;
__trunctfdf2 = 0x40000a14;

2
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.spiflash.ld
View File

@@ -6,7 +6,7 @@
/* ROM function interface esp32c5.rom.spiflash.ld for esp32c5 /* ROM function interface esp32c5.rom.spiflash.ld for esp32c5
* *
* *
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2f8bd1d8c95e398fe4f1ea496130ceb5 * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *

2
components/esp_system/ld/esp32c5/mp/memory.ld.in
View File

@@ -16,7 +16,7 @@
#include "ld.common" #include "ld.common"
#define SRAM_SEG_START 0x40800000 #define SRAM_SEG_START 0x40800000
#define SRAM_SEG_END 0x4086E610 /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_SEG_END 0x4084E9A0 /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_SEG_SIZE SRAM_SEG_END - SRAM_SEG_START #define SRAM_SEG_SIZE SRAM_SEG_END - SRAM_SEG_START
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS