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fix(ledc): overflowed integer argument in ledc_hal_clear_left_off_fade_param

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This commit is contained in:
Song Ruo Jing
2025-02-14 16:42:36 +08:00
parent 346d084a5d
commit 0ced5fbd21
4 changed files with 8 additions and 3 deletions
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4
components/hal/esp32c6/include/hal/ledc_ll.h
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@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h" #include "soc/clk_tree_defs.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround #include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -442,6 +443,7 @@ static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t sp
*/ */
static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
{ {
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
// To workaround sync issue // To workaround sync issue
// This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr
ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range);
@@ -539,7 +541,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{ {
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue // On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range); ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5); esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);

4
components/hal/esp32h2/include/hal/ledc_ll.h
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@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h" #include "soc/clk_tree_defs.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround #include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -440,6 +441,7 @@ static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t sp
*/ */
static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
{ {
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
// To workaround sync issue // To workaround sync issue
// This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr
ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range);
@@ -537,7 +539,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{ {
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue // On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range); ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5); esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);

2
components/hal/esp32p4/include/hal/ledc_ll.h
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@@ -15,6 +15,7 @@
#include "soc/ledc_reg.h" #include "soc/ledc_reg.h"
#include "soc/clk_tree_defs.h" #include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h" #include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -372,6 +373,7 @@ static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc
*/ */
static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
{ {
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
ledc_channel_gamma_fade_param_t range_param = { ledc_channel_gamma_fade_param_t range_param = {
.duty_inc = dir, .duty_inc = dir,
.duty_cycle = cycle, .duty_cycle = cycle,

1
components/hal/ledc_hal_iram.c
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@@ -39,7 +39,6 @@ void ledc_hal_get_duty(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint
void ledc_hal_set_fade_param(const ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) void ledc_hal_set_fade_param(const ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
{ {
#if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED #if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
ledc_ll_set_fade_param_range(hal->dev, hal->speed_mode, channel_num, range, dir, cycle, scale, step); ledc_ll_set_fade_param_range(hal->dev, hal->speed_mode, channel_num, range, dir, cycle, scale, step);
#else // !SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED #else // !SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
HAL_ASSERT(range == 0); HAL_ASSERT(range == 0);