From 97acf998674a8297ffee40cd6d0bf99f69677df0 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Wed, 5 Jun 2024 17:01:12 +0800 Subject: [PATCH 1/4] feat(isp_hist): Add ISP histogram support for esp32p4 (part1) --- components/esp_driver_isp/CMakeLists.txt | 3 +- .../esp_driver_isp/include/driver/isp.h | 1 + .../esp_driver_isp/include/driver/isp_hist.h | 194 ++++++++++++ .../esp_driver_isp/include/driver/isp_types.h | 5 + .../include/esp_private/isp_private.h | 1 + components/esp_driver_isp/src/isp_hist.c | 282 ++++++++++++++++++ components/hal/esp32p4/include/hal/isp_ll.h | 195 ++++++++++++ components/hal/include/hal/isp_types.h | 52 ++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 + .../soc/esp32p4/include/soc/isp_struct.h | 239 +-------------- components/soc/esp32p4/include/soc/soc_caps.h | 3 + docs/en/api-reference/peripherals/isp.rst | 64 +++- 12 files changed, 815 insertions(+), 236 deletions(-) create mode 100644 components/esp_driver_isp/include/driver/isp_hist.h create mode 100644 components/esp_driver_isp/src/isp_hist.c diff --git a/components/esp_driver_isp/CMakeLists.txt b/components/esp_driver_isp/CMakeLists.txt index 9ae964dd23..ac61811fe7 100644 --- a/components/esp_driver_isp/CMakeLists.txt +++ b/components/esp_driver_isp/CMakeLists.txt @@ -14,7 +14,8 @@ if(CONFIG_SOC_ISP_SUPPORTED) "src/isp_ccm.c" "src/isp_awb.c" "src/isp_ae.c" - "src/isp_gamma.c") + "src/isp_gamma.c" + "src/isp_hist.c") endif() if(CONFIG_SOC_ISP_BF_SUPPORTED) diff --git a/components/esp_driver_isp/include/driver/isp.h b/components/esp_driver_isp/include/driver/isp.h index ffd4547995..9511c278fe 100644 --- a/components/esp_driver_isp/include/driver/isp.h +++ b/components/esp_driver_isp/include/driver/isp.h @@ -18,3 +18,4 @@ #include "driver/isp_bf.h" #include "driver/isp_ccm.h" #include "driver/isp_sharpen.h" +#include "driver/isp_hist.h" diff --git a/components/esp_driver_isp/include/driver/isp_hist.h b/components/esp_driver_isp/include/driver/isp_hist.h new file mode 100644 index 0000000000..79698b0dde --- /dev/null +++ b/components/esp_driver_isp/include/driver/isp_hist.h @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_err.h" +#include "driver/isp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t first_window_x_offs; /*!< x offset for the first window */ + uint32_t window_x_size; /*!< x size for the window */ + uint32_t first_window_y_offs; /*!< y offset for the first window */ + uint32_t window_y_size; /*!< y size for the window */ + isp_hist_mode_enum_t hist_mode; /*!< ISP histogram mode */ + uint32_t hist_windows_weight[ISP_HIST_WINDOW_NUM]; /*!< Weight for histogram statistic windows */ + uint32_t hist_segment_threshold[ISP_HIST_INTERVAL_NUMS - 1]; /*!< threshold for histogram */ + isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficient for isp histogram */ + int intr_priority; /*!< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with + * a relative low priority (1,2,3) */ +} esp_isp_hist_config_t; + +/** + * @brief New an ISP hist controller + * + * @param[in] isp_proc ISP Processor handle + * @param[in] hist_cfg Pointer to hist config. Refer to ``esp_isp_hist_config_t``. + * @param[out] ret_hdl hist controller handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid + * - ESP_ERR_INVALID_STATE Invalid state + * - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags + * - ESP_ERR_NO_MEM If out of memory + */ +esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl); + +/** + * @brief Delete an ISP hist controller + * + * @param[in] hist_ctlr hist controller handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr); + +/** + * @brief Reconfigure the ISP histogram controller + * @note This function is allowed to be called no matter the awb controller is enabled or not. + * + * @param[in] hist_ctlr hist controller handle + * @param[in] hist_cfg Pointer to histogram config. Refer to ``esp_isp_hist_config_t`` + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid + */ +esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg); + +/** + * @brief Enable an ISP hist controller + * + * @param[in] hist_ctlr hist controller handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr); + +/** + * @brief Disable an ISP hist controller + * + * @param[in] hist_ctlr hist controller handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr); + +/** + * @brief Trigger hist reference statistics for one time and get the result + * @note This function is a synchronous and block function, + * it only returns when hist reference statistics is done or timeout. + * It's a simple method to get the result directly for one time. + * + * @param[in] hist_ctlr hist controller handle + * @param[in] timeout_ms Timeout in millisecond + * - timeout_ms < 0: Won't return until finished + * - timeout_ms = 0: No timeout, trigger one time statistics and return immediately, + * in this case, the result won't be assigned in this function, + * but you can get the result in the callback `esp_isp_hist_cbs_t::on_statistics_done` + * - timeout_ms > 0: Wait for specified milliseconds, if not finished, then return timeout error + * @param[out] out_res hist reference statistics result + * + * @return + * - ESP_OK On success + * - ESP_ERR_TIMEOUT Wait for the result timeout + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res); + +/** + * @brief Start hist continuous statistics of the reference in the window + * @note This function is an asynchronous and non-block function, + * it will start the continuous statistics and return immediately. + * You have to register the hist callback and get the result from the callback event data. + * + * @param[in] hist_ctlr hist controller handle + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG Null pointer + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr); + +/** + * @brief Stop hist continuous statistics of the reference in the window + * + * @param[in] hist_ctlr hist controller handle + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG Null pointer + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr); + +/** + * @brief Event data of callbacks + */ +typedef struct { + isp_hist_result_t hist_result; /*!< The histogram reference statistics result */ +} esp_isp_hist_evt_data_t; + +/** + * @brief Prototype of ISP hist event callback + * + * @param[in] handle ISP hist controller handle + * @param[in] edata ISP hist event data + * @param[in] user_data User registered context, registered when in `esp_isp_hist_env_detector_register_event_callbacks()` + * + * @return Whether a high priority task is woken up by this function + */ +typedef bool (*esp_isp_hist_callback_t)(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data); + +/** + * @brief Group of ISP hist callbacks + * + * @note These callbacks are all running in an ISR environment. + * @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM. + * Involved variables should be in internal RAM as well. + */ +typedef struct { + esp_isp_hist_callback_t on_statistics_done; ///< Event callback, invoked when histogram statistic done. +} esp_isp_hist_cbs_t; + +/** + * @brief Register hist event callbacks + * + * @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in + * the `cbs` structure to NULL. + * @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM. + * Involved variables (including `user_data`) should be in internal RAM as well. + * + * @param[in] hist_ctlr hist controller handle + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be delivered to the callback functions directly + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_isp/include/driver/isp_types.h b/components/esp_driver_isp/include/driver/isp_types.h index 142922b54d..a1ff944014 100644 --- a/components/esp_driver_isp/include/driver/isp_types.h +++ b/components/esp_driver_isp/include/driver/isp_types.h @@ -76,6 +76,11 @@ typedef struct isp_awb_controller_t *isp_awb_ctlr_t; */ typedef struct isp_ae_controller_t *isp_ae_ctlr_t; +/** + * @brief Type of ISP HIST controller handle + */ +typedef struct isp_hist_controller_t *isp_hist_ctlr_t; + /*--------------------------------------------- Event Callbacks ----------------------------------------------*/ diff --git a/components/esp_driver_isp/include/esp_private/isp_private.h b/components/esp_driver_isp/include/esp_private/isp_private.h index 90bc4cf079..8ed746f652 100644 --- a/components/esp_driver_isp/include/esp_private/isp_private.h +++ b/components/esp_driver_isp/include/esp_private/isp_private.h @@ -68,6 +68,7 @@ typedef struct isp_processor_t { isp_af_ctlr_t af_ctlr[SOC_ISP_AF_CTLR_NUMS]; isp_awb_ctlr_t awb_ctlr; isp_ae_ctlr_t ae_ctlr; + isp_hist_ctlr_t hist_ctlr; isp_fsm_t bf_fsm; isp_fsm_t sharpen_fsm; esp_isp_evt_cbs_t cbs; diff --git a/components/esp_driver_isp/src/isp_hist.c b/components/esp_driver_isp/src/isp_hist.c new file mode 100644 index 0000000000..3fc1c66272 --- /dev/null +++ b/components/esp_driver_isp/src/isp_hist.c @@ -0,0 +1,282 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "freertos/FreeRTOS.h" +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_heap_caps.h" +#include "driver/isp_hist.h" +#include "esp_private/isp_private.h" + +typedef struct isp_hist_controller_t { + isp_fsm_t fsm; + portMUX_TYPE spinlock; + intr_handle_t intr_handle; + int intr_priority; + isp_proc_handle_t isp_proc; + QueueHandle_t evt_que; + esp_isp_hist_cbs_t cbs; + void *user_data; +} isp_hist_controller_t; + +static const char *TAG = "ISP_hist"; + +static void s_isp_hist_default_isr(void *arg); + +/*--------------------------------------------- + hist +----------------------------------------------*/ +static esp_err_t s_isp_claim_hist_controller(isp_proc_handle_t isp_proc, isp_hist_ctlr_t hist_ctlr) +{ + assert(isp_proc && hist_ctlr); + + bool found = false; + portENTER_CRITICAL(&isp_proc->spinlock); + if (!isp_proc->hist_ctlr) { + isp_proc->hist_ctlr = hist_ctlr; + found = true; + } + portEXIT_CRITICAL(&isp_proc->spinlock); + + if (!found) { + return ESP_ERR_NOT_FOUND; + } + return ESP_OK; +} + +static void s_isp_declaim_hist_controller(isp_hist_ctlr_t hist_ctlr) +{ + if (hist_ctlr && hist_ctlr->isp_proc) { + portENTER_CRITICAL(&hist_ctlr->isp_proc->spinlock); + hist_ctlr->isp_proc->hist_ctlr = NULL; + portEXIT_CRITICAL(&hist_ctlr->isp_proc->spinlock); + } +} + +static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr) +{ + if (hist_ctlr) { + if (hist_ctlr->intr_handle) { + esp_intr_free(hist_ctlr->intr_handle); + } + if (hist_ctlr->evt_que) { + vQueueDelete(hist_ctlr->evt_que); + } + free(hist_ctlr); + } +} + +esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl) +{ + esp_err_t ret = ESP_FAIL; + ESP_RETURN_ON_FALSE(isp_proc && hist_cfg && ret_hdl, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + isp_hist_ctlr_t hist_ctlr = heap_caps_calloc(1, sizeof(isp_hist_controller_t), ISP_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller"); + hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue"); + hist_ctlr->fsm = ISP_FSM_INIT; + hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + hist_ctlr->isp_proc = isp_proc; + + // Claim an hist controller + ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller"); + // Register the hist ISR + uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(isp_proc->hal.hw); + int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 7 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; + ESP_GOTO_ON_ERROR(esp_intr_alloc_intrstatus(isp_hw_info.instances[isp_proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | intr_priority, intr_st_reg_addr, ISP_LL_EVENT_HIST_MASK, + s_isp_hist_default_isr, hist_ctlr, &hist_ctlr->intr_handle), err2, TAG, "allocate interrupt failed"); + + // Configure the hardware + isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode); + isp_ll_hist_set_x_offset(isp_proc->hal.hw, hist_cfg->first_window_x_offs); + isp_ll_hist_set_y_offset(isp_proc->hal.hw, hist_cfg->first_window_y_offs); + isp_ll_hist_set_window_x_size(isp_proc->hal.hw, hist_cfg->window_x_size); + isp_ll_hist_set_window_y_size(isp_proc->hal.hw, hist_cfg->window_y_size); + isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->hist_windows_weight); + isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->hist_segment_threshold); + if (hist_cfg->hist_mode == ISP_HIST_RGB) { + isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient); + } + + *ret_hdl = hist_ctlr; + + return ESP_OK; + +err2: + s_isp_declaim_hist_controller(hist_ctlr); +err1: + s_isp_hist_free_controller(hist_ctlr); + + return ret; +} + +esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr) +{ + ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use"); + ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state"); + s_isp_declaim_hist_controller(hist_ctlr); + + s_isp_hist_free_controller(hist_ctlr); + + return ESP_OK; +} + +esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr) +{ + ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state"); + esp_err_t ret = ESP_OK; + + ESP_GOTO_ON_ERROR(esp_intr_enable(hist_ctlr->intr_handle), err, TAG, "failed to enable the HIST interrupt"); + isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true); + isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true); + hist_ctlr->fsm = ISP_FSM_ENABLE; + +err: + hist_ctlr->fsm = ISP_FSM_INIT; + return ret; +} + +esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr) +{ + ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); + + isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false); + isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false); + esp_intr_disable(hist_ctlr->intr_handle); + hist_ctlr->fsm = ISP_FSM_INIT; + + return ESP_OK; +} + +esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg) +{ + ESP_RETURN_ON_FALSE(hist_ctlr && hist_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 3 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; + ESP_RETURN_ON_FALSE(intr_priority == hist_ctlr->intr_priority, ESP_ERR_INVALID_ARG, TAG, "can't change interrupt priority after initialized"); + + // Configure the hardware + isp_ll_hist_set_mode(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_mode); + isp_ll_hist_set_x_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_x_offs); + isp_ll_hist_set_y_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_y_offs); + isp_ll_hist_set_window_x_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_x_size); + isp_ll_hist_set_window_y_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_y_size); + isp_ll_hist_set_subwindow_weight(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_windows_weight); + isp_ll_hist_set_segment_threshold(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_segment_threshold); + if (hist_cfg->hist_mode == ISP_HIST_RGB) { + isp_ll_hist_set_rgb_coefficient(hist_ctlr->isp_proc->hal.hw, &hist_cfg->rgb_coefficient); + } + + return ESP_OK; +} + +esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res) +{ + ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); + + esp_err_t ret = ESP_OK; + TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms); + // Reset the queue in case receiving the legacy data in the queue + xQueueReset(hist_ctlr->evt_que); + // Start the histogram reference statistics and waiting it done + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); + // Wait the statistics to finish and receive the result from the queue + if ((ticks > 0) && xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) { + ret = ESP_ERR_TIMEOUT; + } + // Stop the histogram reference statistics + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); + + return ret; +} + +esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr) +{ + ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); + + hist_ctlr->fsm = ISP_FSM_START; + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); + + return ESP_OK; +} + +esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr) +{ + ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_START, ESP_ERR_INVALID_STATE, TAG, "controller isn't in continuous state"); + + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); + hist_ctlr->fsm = ISP_FSM_ENABLE; + + return ESP_OK; +} + +/*--------------------------------------------------------------- + INTR +---------------------------------------------------------------*/ +static void IRAM_ATTR s_isp_hist_default_isr(void *arg) +{ + isp_hist_ctlr_t hist_ctlr = (isp_hist_ctlr_t)arg; + isp_proc_handle_t proc = hist_ctlr->isp_proc; + + uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK); + + bool need_yield = false; + + if (hist_events & ISP_LL_EVENT_HIST_MASK) { + isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr; + uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; + isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value); + // Get the statistics result + esp_isp_hist_evt_data_t edata = {}; + for (int i = 0; i < ISP_HIST_SEGMENT_NUMS; i++) { + edata.hist_result.hist_value[i] = hist_value[i]; + } + // Invoke the callback if the callback is registered + if (hist_ctlr->cbs.on_statistics_done) { + need_yield |= hist_ctlr->cbs.on_statistics_done(hist_ctlr, &edata, hist_ctlr->user_data); + } + BaseType_t high_task_awake = false; + // Send the event data to the queue, overwrite the legacy one if exist + xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake); + need_yield |= high_task_awake == pdTRUE; + /* If started continuous sampling, then trigger the next hist sample */ + if (hist_ctlr->fsm == ISP_FSM_START) { + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); + isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); + } + } + + if (need_yield) { + portYIELD_FROM_ISR(); + } +} + +esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data) +{ + ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "detector isn't in the init state"); +#if CONFIG_ISP_ISR_IRAM_SAFE + if (cbs->on_statistics_done) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_env_change callback not in IRAM"); + } + if (user_data) { + ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM"); + } +#endif + hist_ctlr->cbs.on_statistics_done = cbs->on_statistics_done; + hist_ctlr->user_data = user_data; + + return ESP_OK; +} diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index 79284ae4cb..963d31d865 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -68,6 +68,7 @@ extern "C" { #define ISP_LL_EVENT_AE_MASK (ISP_LL_EVENT_AE_FDONE | ISP_LL_EVENT_AE_ENV) #define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE) #define ISP_LL_EVENT_SHARP_MASK (ISP_LL_EVENT_SHARP_FRAME) +#define ISP_LL_EVENT_HIST_MASK (ISP_LL_EVENT_HIST_FDONE) /*--------------------------------------------------------------- AF @@ -1614,6 +1615,200 @@ static inline void isp_ll_gamma_set_correction_curve(isp_dev_t *hw, color_compon while (hw->gamma_ctrl.gamma_update); } +/*--------------------------------------------------------------- + HIST +---------------------------------------------------------------*/ +/** + * @brief enable histogram clock + * + * @param[in] hw Hardware instance address + * @param[in] enable true: enable the clock. false: disable the clock +*/ +static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable) +{ + hw->clk_en.clk_hist_force_on = enable; +} + +/** + * @brief Set histogram subwindow weight + * + * @param[in] hw Hardware instance address + * @param[in] window_weight array for window weight +*/ +static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_WINDOW_NUMS]) +{ + int idx = 0; + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_00, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_01, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_02, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_03, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_04, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_10, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_11, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_12, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_13, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_14, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_20, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_21, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_22, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_23, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_24, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_30, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_31, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_32, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_33, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_34, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_40, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_41, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_42, window_weight[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_43, window_weight[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight6, hist_weight_44, window_weight[idx++]); + + HAL_ASSERT(idx == 25); +} + +/** + * @brief Set histogram segment threshold + * + * @param[in] hw Hardware instance address + * @param[in] segment_threshold array for segment threshold +*/ +static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS - 1]) +{ + int idx = 0; + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_0_1, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_1_2, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_2_3, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_3_4, segment_threshold[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_4_5, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_5_6, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_6_7, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_7_8, segment_threshold[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_8_9, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_9_10, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_10_11, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_11_12, segment_threshold[idx++]); + + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_12_13, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_13_14, segment_threshold[idx++]); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_14_15, segment_threshold[idx++]); + + HAL_ASSERT(idx == 15); +} + +/** + * @brief Set histogram x offset + * + * @param[in] hw Hardware instance address + * @param[in] x_offset value for x offset +*/ +static inline void isp_ll_hist_set_x_offset(isp_dev_t *hw, uint32_t x_offset) +{ + hw->hist_offs.hist_x_offs = x_offset; +} + +/** + * @brief Set histogram y offset + * + * @param[in] hw Hardware instance address + * @param[in] y_offset value for y offset +*/ +static inline void isp_ll_hist_set_y_offset(isp_dev_t *hw, uint32_t y_offset) +{ + hw->hist_offs.hist_y_offs = y_offset; +} + +/** + * @brief Set histogram x size + * + * @param[in] hw Hardware instance address + * @param[in] x_size value for x size +*/ +static inline void isp_ll_hist_set_window_x_size(isp_dev_t *hw, uint32_t x_size) +{ + hw->hist_size.hist_x_size = x_size; +} + +/** + * @brief Set histogram y size + * + * @param[in] hw Hardware instance address + * @param[in] y_size value for y size +*/ +static inline void isp_ll_hist_set_window_y_size(isp_dev_t *hw, uint32_t y_size) +{ + hw->hist_size.hist_y_size = y_size; +} + +/** + * @brief Start histogram statistic + * + * @param[in] hw Hardware instance address + * @param[in] enable enable/disable +*/ +static inline void isp_ll_hist_enable(isp_dev_t *hw, bool enable) +{ + hw->cntl.hist_en = enable; +} + +/** + * @brief Stop histogram statistic + * + * @param[in] hw Hardware instance address +*/ +static inline void isp_ll_hist_stop(isp_dev_t *hw) +{ + hw->cntl.hist_en = 1; +} + +/** + * @brief Get histogram value + * + * @param[in] hw Hardware instance address + * @param[out] histogram_value pointer to histogram result +*/ +__attribute__((always_inline)) +static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *histogram_value) +{ + for (int i = 0; i < SOC_ISP_HIST_SEGMENT_NUMS; i++) { + histogram_value[i] = hw->hist_binn[i].hist_bin_n; + } +} + +/** + * @brief Get histogram value + * + * @param[in] hw Hardware instance address + * @param[out] histogram_value pointer to histogram result +*/ +static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_mode_enum_t hist_mode) +{ + hw->hist_mode.hist_mode = hist_mode; +} + +/** + * @brief Get histogram value + * + * @param[in] hw Hardware instance address + * @param[out] histogram_value pointer to histogram result +*/ +static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient *rgb_coeff) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/isp_types.h b/components/hal/include/hal/isp_types.h index e9bbaa18ec..19a2a1bad2 100644 --- a/components/hal/include/hal/isp_types.h +++ b/components/hal/include/hal/isp_types.h @@ -235,6 +235,58 @@ typedef struct { } pt[ISP_GAMMA_CURVE_POINTS_NUM]; ///< Point (x, y) } isp_gamma_curve_points_t; +/*--------------------------------------------------------------- + HIST +---------------------------------------------------------------*/ +#if SOC_ISP_HIST_WINDOW_NUMS +#define ISP_HIST_WINDOW_NUM SOC_ISP_HIST_WINDOW_NUMS // The HIST window number for sampling +#else +#define ISP_HIST_WINDOW_NUM 0 +#endif + +#if SOC_ISP_HIST_SEGMENT_NUMS +#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram +#else +#define ISP_HIST_SEGMENT_NUMS 0 +#endif + +#if SOC_ISP_HIST_INTERVAL_NUMS +#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The segment of histogram +#else +#define ISP_HIST_INTERVAL_NUMS 0 +#endif + +/** + * @brief ISP histogram mode. +*/ +typedef enum { + ISP_HIST_RGB_B, ///< histogram mode for B component for RGB + ISP_HIST_RGB_GB, ///< histogram mode for GB component for RGB + ISP_HIST_RGB_GR, ///< histogram mode for GR component for RGB + ISP_HIST_RGB_R, ///< histogram mode for R component for RGB + ISP_HIST_RGB, ///< histogram mode for RGB + ISP_HIST_YUV_Y, ///< histogram mode for Y component for YUV + ISP_HIST_YUV_U, ///< histogram mode for U component for YUV + ISP_HIST_YUV_V, ///< histogram mode for V component for YUV +} isp_hist_mode_enum_t; + +/** + * @brief ISP histogram r,g,b coefficient +*/ +typedef struct { + uint8_t coeff_r; ///< R coefficient + uint8_t coeff_g; ///< G coefficient + uint8_t coeff_b; ///< B coefficient +} isp_hist_rgb_coefficient; + +/** + * @brief ISP histogram result. +*/ +typedef struct { + uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< histogram value. +} isp_hist_result_t; + + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index b85306c91f..c441679b7d 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -923,6 +923,18 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS int default 24 +config SOC_ISP_HIST_WINDOW_NUMS + int + default 25 + +config SOC_ISP_HIST_SEGMENT_NUMS + int + default 16 + +config SOC_ISP_HIST_INTERVAL_NUMS + int + default 15 + config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK bool default y diff --git a/components/soc/esp32p4/include/soc/isp_struct.h b/components/soc/esp32p4/include/soc/isp_struct.h index ff57fb6bcf..7104e5202b 100644 --- a/components/soc/esp32p4/include/soc/isp_struct.h +++ b/components/soc/esp32p4/include/soc/isp_struct.h @@ -2584,229 +2584,19 @@ typedef union { uint32_t val; } isp_blc_mean_reg_t; -/** Type of hist_bin0 register - * result of histogram bin 0 +/** Type of hist_bin register + * result of histogram bin n */ typedef union { struct { - /** hist_bin_0 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 0 + /** hist_bin_n : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin n */ - uint32_t hist_bin_0:17; + uint32_t hist_bin_n:17; uint32_t reserved_17:15; }; uint32_t val; -} isp_hist_bin0_reg_t; - -/** Type of hist_bin1 register - * result of histogram bin 1 - */ -typedef union { - struct { - /** hist_bin_1 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 1 - */ - uint32_t hist_bin_1:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin1_reg_t; - -/** Type of hist_bin2 register - * result of histogram bin 2 - */ -typedef union { - struct { - /** hist_bin_2 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 2 - */ - uint32_t hist_bin_2:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin2_reg_t; - -/** Type of hist_bin3 register - * result of histogram bin 3 - */ -typedef union { - struct { - /** hist_bin_3 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 3 - */ - uint32_t hist_bin_3:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin3_reg_t; - -/** Type of hist_bin4 register - * result of histogram bin 4 - */ -typedef union { - struct { - /** hist_bin_4 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 4 - */ - uint32_t hist_bin_4:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin4_reg_t; - -/** Type of hist_bin5 register - * result of histogram bin 5 - */ -typedef union { - struct { - /** hist_bin_5 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 5 - */ - uint32_t hist_bin_5:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin5_reg_t; - -/** Type of hist_bin6 register - * result of histogram bin 6 - */ -typedef union { - struct { - /** hist_bin_6 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 6 - */ - uint32_t hist_bin_6:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin6_reg_t; - -/** Type of hist_bin7 register - * result of histogram bin 7 - */ -typedef union { - struct { - /** hist_bin_7 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 7 - */ - uint32_t hist_bin_7:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin7_reg_t; - -/** Type of hist_bin8 register - * result of histogram bin 8 - */ -typedef union { - struct { - /** hist_bin_8 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 8 - */ - uint32_t hist_bin_8:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin8_reg_t; - -/** Type of hist_bin9 register - * result of histogram bin 9 - */ -typedef union { - struct { - /** hist_bin_9 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 9 - */ - uint32_t hist_bin_9:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin9_reg_t; - -/** Type of hist_bin10 register - * result of histogram bin 10 - */ -typedef union { - struct { - /** hist_bin_10 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 10 - */ - uint32_t hist_bin_10:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin10_reg_t; - -/** Type of hist_bin11 register - * result of histogram bin 11 - */ -typedef union { - struct { - /** hist_bin_11 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 11 - */ - uint32_t hist_bin_11:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin11_reg_t; - -/** Type of hist_bin12 register - * result of histogram bin 12 - */ -typedef union { - struct { - /** hist_bin_12 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 12 - */ - uint32_t hist_bin_12:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin12_reg_t; - -/** Type of hist_bin13 register - * result of histogram bin 13 - */ -typedef union { - struct { - /** hist_bin_13 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 13 - */ - uint32_t hist_bin_13:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin13_reg_t; - -/** Type of hist_bin14 register - * result of histogram bin 14 - */ -typedef union { - struct { - /** hist_bin_14 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 14 - */ - uint32_t hist_bin_14:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin14_reg_t; - -/** Type of hist_bin15 register - * result of histogram bin 15 - */ -typedef union { - struct { - /** hist_bin_15 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 15 - */ - uint32_t hist_bin_15:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin15_reg_t; +} isp_hist_binn_reg_t; /** Type of rdn_eco_cs register * rdn eco cs register @@ -3448,22 +3238,7 @@ typedef struct { volatile isp_hist_weight4_reg_t hist_weight4; volatile isp_hist_weight5_reg_t hist_weight5; volatile isp_hist_weight6_reg_t hist_weight6; - volatile isp_hist_bin0_reg_t hist_bin0; - volatile isp_hist_bin1_reg_t hist_bin1; - volatile isp_hist_bin2_reg_t hist_bin2; - volatile isp_hist_bin3_reg_t hist_bin3; - volatile isp_hist_bin4_reg_t hist_bin4; - volatile isp_hist_bin5_reg_t hist_bin5; - volatile isp_hist_bin6_reg_t hist_bin6; - volatile isp_hist_bin7_reg_t hist_bin7; - volatile isp_hist_bin8_reg_t hist_bin8; - volatile isp_hist_bin9_reg_t hist_bin9; - volatile isp_hist_bin10_reg_t hist_bin10; - volatile isp_hist_bin11_reg_t hist_bin11; - volatile isp_hist_bin12_reg_t hist_bin12; - volatile isp_hist_bin13_reg_t hist_bin13; - volatile isp_hist_bin14_reg_t hist_bin14; - volatile isp_hist_bin15_reg_t hist_bin15; + volatile isp_hist_binn_reg_t hist_binn[16]; volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 683ae77543..efa9e9c0ce 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -355,6 +355,9 @@ #define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3 #define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5 #define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24 +#define SOC_ISP_HIST_WINDOW_NUMS 25 +#define SOC_ISP_HIST_SEGMENT_NUMS 16 +#define SOC_ISP_HIST_INTERVAL_NUMS 15 /*-------------------------- LEDC CAPS ---------------------------------------*/ #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst index 00db391776..d44ccc3c2b 100644 --- a/docs/en/api-reference/peripherals/isp.rst +++ b/docs/en/api-reference/peripherals/isp.rst @@ -62,8 +62,9 @@ The ISP driver offers following services: - `Get AF statistics in one shot or continuous way <#isp-af-statistics>`__ - covers how to get AF statistics one-shot or continuously. - `Get AE statistics in one shot or continuous way <#isp-ae-statistics>`__ - covers how to get AE statistics one-shot or continuously. - `Get AWB statistics in one shot or continuous way <#isp-awb-statistics>`__ - covers how to get AWB white patches statistics one-shot or continuously. -- `Enable BF function <#isp-bf>`__ - covers how to enable and configure BF function. -- `Configure CCM <#isp-ccm-config>`__ - covers how to config the Color Correction Matrix. +- `Get histogram statistics in one shot or continuous way <#isp-hist-statistics>`__ - covers how to get histogram statistics one-shot or continuously. +- `Enable BF function <#isp_bf>`__ - covers how to enable and configure BF function. +- `Configure CCM <#isp-ccm-config>`__ - covers how to configure the Color Correction Matrix. - `Enable Gamma Correction <#isp-gamma-correction>`__ - covers how to enable and configure gamma correction. - `Configure Sharpen <#isp-sharpen>`__ - covers how to config the Sharpen function. - `Register callback <#isp-callback>`__ - covers how to hook user specific code to ISP driver event callback function. @@ -394,7 +395,64 @@ Note that if you want to use the continuous statistics, you need to register the /* Delete the awb controller and free the resources */ ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr)); -.. _isp-bf: +.. _isp-hist: + +ISP histogram Processor +----------------------- + +Before doing ISP histogram statistics, you need to enable the ISP histogram processor first, by calling :cpp:func:`esp_isp_hist_controller_enable`. This function: + +* Switches the driver state from **init** to **enable**. + +Calling :cpp:func:`esp_isp_hist_controller_disable` does the opposite, that is, put the driver back to the **init** state. + +.. _isp-hist-statistics: + +Histogram One-shot and Continuous Statistics +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Calling :cpp:func:`esp_isp_hist_controller_get_oneshot_statistics` to get oneshot histogram statistics result. You can take following code as reference. + +Aside from the above oneshot API, the ISP histogram driver also provides a way to start histogram statistics continuously. Calling :cpp:func:`esp_isp_hist_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_hist_controller_stop_continuous_statistics` stops it. + +Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__ + +.. code:: c + + static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data) + { + for(int i = 0; i < 16; i++) { + esp_rom_printf(DRAM_STR("val %d is %x\n"), i, edata->hist_result.hist_value[i]); // get the histogram statistic value + } + return true; + } + + isp_hist_ctlr_t hist_ctrlr = NULL; + esp_isp_hist_config_t hist_cfg = { + .first_window_x_offs = 0, + .first_window_y_offs = 0, + .window_x_size = 800 / 25, + .window_y_size = 640 / 25, + .rgb_coefficient = { + .coeff_b = 85, + .coeff_g = 85, + .coeff_r = 85, + }, + .hist_windows_weight = {[0 ... ISP_HIST_WINDOW_NUM - 1] = 10}, + .hist_segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .hist_mode = ISP_HIST_RGB, + }; + + esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctrlr); + esp_isp_hist_cbs_t hist_cbs = { + .on_statistics_done = s_hist_scheme_on_statistics_done_callback, + }; + + esp_isp_hist_register_event_callbacks(hist_ctrlr, &hist_cbs, hist_ctrlr); + esp_isp_hist_controller_enable(hist_ctrlr); + + +.. _isp_bf: ISP BF Processor ~~~~~~~~~~~~~~~~ From fb5df708a186c4eef660c30e3abd5deaf8e9d2f7 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Mon, 5 Aug 2024 09:15:34 +0800 Subject: [PATCH 2/4] feat(isp_hist): Add ISP histogram support and add test for esp32p4(part 2) --- .../esp_driver_isp/include/driver/isp_core.h | 2 +- .../esp_driver_isp/include/driver/isp_hist.h | 35 +--- .../include/esp_private/isp_private.h | 3 + components/esp_driver_isp/src/isp_core.c | 18 ++- components/esp_driver_isp/src/isp_hist.c | 137 ++++++++-------- .../test_apps/isp/main/test_isp_driver.c | 99 ++++++++++++ components/hal/esp32p4/include/hal/isp_ll.h | 149 ++++-------------- components/hal/include/hal/isp_hal.h | 11 ++ components/hal/include/hal/isp_types.h | 41 +++-- components/hal/isp_hal.c | 29 +++- .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 +- .../soc/esp32p4/include/soc/isp_struct.h | 46 ++++-- components/soc/esp32p4/include/soc/soc_caps.h | 8 +- docs/en/api-reference/peripherals/isp.rst | 55 +++++-- 14 files changed, 366 insertions(+), 279 deletions(-) diff --git a/components/esp_driver_isp/include/driver/isp_core.h b/components/esp_driver_isp/include/driver/isp_core.h index a028b31989..ef8307645c 100644 --- a/components/esp_driver_isp/include/driver/isp_core.h +++ b/components/esp_driver_isp/include/driver/isp_core.h @@ -30,7 +30,7 @@ typedef struct { bool has_line_end_packet; ///< Enable line end packet uint32_t h_res; ///< Input horizontal resolution, i.e. the number of pixels in a line uint32_t v_res; ///< Input vertical resolution, i.e. the number of lines in a frame - int intr_priority; ///< The interrupt priority, range 0~3 + int intr_priority; ///< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) } esp_isp_processor_cfg_t; /** diff --git a/components/esp_driver_isp/include/driver/isp_hist.h b/components/esp_driver_isp/include/driver/isp_hist.h index 79698b0dde..e7568e64d7 100644 --- a/components/esp_driver_isp/include/driver/isp_hist.h +++ b/components/esp_driver_isp/include/driver/isp_hist.h @@ -16,16 +16,13 @@ extern "C" { #endif typedef struct { - uint32_t first_window_x_offs; /*!< x offset for the first window */ - uint32_t window_x_size; /*!< x size for the window */ - uint32_t first_window_y_offs; /*!< y offset for the first window */ - uint32_t window_y_size; /*!< y size for the window */ - isp_hist_mode_enum_t hist_mode; /*!< ISP histogram mode */ - uint32_t hist_windows_weight[ISP_HIST_WINDOW_NUM]; /*!< Weight for histogram statistic windows */ - uint32_t hist_segment_threshold[ISP_HIST_INTERVAL_NUMS - 1]; /*!< threshold for histogram */ - isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficient for isp histogram */ - int intr_priority; /*!< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with - * a relative low priority (1,2,3) */ + isp_window_t window; /*!< The sampling window of histogram, see `isp_window_t`*/ + isp_hist_sampling_mode_t hist_mode; /*!< ISP histogram sampling mode */ + isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficients, adjust the sensitivity to red, geen, and blue colors in the image, + only effect when hist_mode is ISP_HIST_SAMPLING_RGB, the sum of all coefficients should be 100**/ + uint32_t windows_weight[ISP_HIST_BLOCK_X_NUM][ISP_HIST_BLOCK_Y_NUM]; /*!< Weights of histogram's each subwindows, the sum of all subwindows's weight should be 100*/ + uint32_t segment_threshold[ISP_HIST_INTERVAL_NUMS]; /*!< Threshold to segment the histogram into intervals, range 0~256 */ + } esp_isp_hist_config_t; /** @@ -56,19 +53,6 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_ */ esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr); -/** - * @brief Reconfigure the ISP histogram controller - * @note This function is allowed to be called no matter the awb controller is enabled or not. - * - * @param[in] hist_ctlr hist controller handle - * @param[in] hist_cfg Pointer to histogram config. Refer to ``esp_isp_hist_config_t`` - * - * @return - * - ESP_OK On success - * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid - */ -esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg); - /** * @brief Enable an ISP hist controller * @@ -95,9 +79,6 @@ esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr); /** * @brief Trigger hist reference statistics for one time and get the result - * @note This function is a synchronous and block function, - * it only returns when hist reference statistics is done or timeout. - * It's a simple method to get the result directly for one time. * * @param[in] hist_ctlr hist controller handle * @param[in] timeout_ms Timeout in millisecond @@ -153,7 +134,7 @@ typedef struct { * * @param[in] handle ISP hist controller handle * @param[in] edata ISP hist event data - * @param[in] user_data User registered context, registered when in `esp_isp_hist_env_detector_register_event_callbacks()` + * @param[in] user_data User registered context, registered when in `esp_isp_hist_register_event_callbacks()` * * @return Whether a high priority task is woken up by this function */ diff --git a/components/esp_driver_isp/include/esp_private/isp_private.h b/components/esp_driver_isp/include/esp_private/isp_private.h index 8ed746f652..5af0fdfc93 100644 --- a/components/esp_driver_isp/include/esp_private/isp_private.h +++ b/components/esp_driver_isp/include/esp_private/isp_private.h @@ -83,6 +83,7 @@ typedef struct isp_processor_t { uint32_t ae_isr_added: 1; uint32_t awb_isr_added: 1; uint32_t sharp_isr_added: 1; + uint32_t hist_isr_added: 1; } isr_users; } isp_processor_t; @@ -93,6 +94,7 @@ typedef enum { ISP_SUBMODULE_AE, ISP_SUBMODULE_AWB, ISP_SUBMODULE_SHARPEN, + ISP_SUBMODULE_HIST, } isp_submodule_t; /*--------------------------------------------------------------- @@ -104,6 +106,7 @@ bool esp_isp_af_isr(isp_proc_handle_t proc, uint32_t af_events); bool esp_isp_ae_isr(isp_proc_handle_t proc, uint32_t ae_events); bool esp_isp_awb_isr(isp_proc_handle_t proc, uint32_t awb_events); bool esp_isp_sharpen_isr(isp_proc_handle_t proc, uint32_t sharp_events); +bool esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events); #ifdef __cplusplus } diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c index 64b54520ea..1f1e002d2f 100644 --- a/components/esp_driver_isp/src/isp_core.c +++ b/components/esp_driver_isp/src/isp_core.c @@ -231,6 +231,7 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg) uint32_t awb_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AWB_MASK); uint32_t ae_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AE_MASK); uint32_t sharp_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_SHARP_MASK); + uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK); bool do_dispatch = false; //Deal with hw events @@ -274,7 +275,16 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg) } do_dispatch = false; } + if (hist_events) { + portENTER_CRITICAL_ISR(&proc->spinlock); + do_dispatch = proc->isr_users.hist_isr_added; + portEXIT_CRITICAL_ISR(&proc->spinlock); + if (do_dispatch) { + need_yield |= esp_isp_hist_isr(proc, hist_events); + } + do_dispatch = false; + } if (need_yield) { portYIELD_FROM_ISR(); } @@ -306,6 +316,9 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule case ISP_SUBMODULE_SHARPEN: proc->isr_users.sharp_isr_added = true; break; + case ISP_SUBMODULE_HIST: + proc->isr_users.hist_isr_added = true; + break; default: assert(false); } @@ -314,7 +327,7 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule if (do_alloc) { uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(proc->hal.hw); - uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK; + uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK | ISP_LL_EVENT_HIST_MASK; ret = esp_intr_alloc_intrstatus(isp_hw_info.instances[proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | proc->intr_priority, intr_st_reg_addr, intr_st_mask, s_isp_isr_dispatcher, (void *)proc, &proc->intr_hdl); if (ret != ESP_OK) { @@ -354,6 +367,9 @@ esp_err_t esp_isp_deregister_isr(isp_proc_handle_t proc, isp_submodule_t submodu case ISP_SUBMODULE_SHARPEN: proc->isr_users.sharp_isr_added = false; break; + case ISP_SUBMODULE_HIST: + proc->isr_users.hist_isr_added = false; + break; default: assert(false); } diff --git a/components/esp_driver_isp/src/isp_hist.c b/components/esp_driver_isp/src/isp_hist.c index 3fc1c66272..225b0d46ed 100644 --- a/components/esp_driver_isp/src/isp_hist.c +++ b/components/esp_driver_isp/src/isp_hist.c @@ -6,6 +6,7 @@ #include #include +#include #include "freertos/FreeRTOS.h" #include "sdkconfig.h" #include "esp_log.h" @@ -15,10 +16,9 @@ #include "esp_private/isp_private.h" typedef struct isp_hist_controller_t { - isp_fsm_t fsm; + _Atomic isp_fsm_t fsm; portMUX_TYPE spinlock; intr_handle_t intr_handle; - int intr_priority; isp_proc_handle_t isp_proc; QueueHandle_t evt_que; esp_isp_hist_cbs_t cbs; @@ -27,8 +27,6 @@ typedef struct isp_hist_controller_t { static const char *TAG = "ISP_hist"; -static void s_isp_hist_default_isr(void *arg); - /*--------------------------------------------- hist ----------------------------------------------*/ @@ -66,7 +64,7 @@ static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr) esp_intr_free(hist_ctlr->intr_handle); } if (hist_ctlr->evt_que) { - vQueueDelete(hist_ctlr->evt_que); + vQueueDeleteWithCaps(hist_ctlr->evt_que); } free(hist_ctlr); } @@ -81,27 +79,43 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_ ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller"); hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue"); + + atomic_init(&hist_ctlr->fsm, ISP_FSM_INIT); hist_ctlr->fsm = ISP_FSM_INIT; hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; hist_ctlr->isp_proc = isp_proc; + for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) { + ESP_GOTO_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, err1, TAG, "invalid segment threshold"); + } + + int weight_sum = 0; + for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) { + for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) { + weight_sum = weight_sum + hist_cfg->windows_weight[i][j]; + } + } + ESP_GOTO_ON_FALSE(weight_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of all subwindow's weight is not 100"); + + if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { + int rgb_coefficient_sum = hist_cfg->rgb_coefficient.coeff_r + hist_cfg->rgb_coefficient.coeff_g + hist_cfg->rgb_coefficient.coeff_b; + ESP_GOTO_ON_FALSE(rgb_coefficient_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of rgb_coefficient is not 100"); + } + // Claim an hist controller ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller"); - // Register the hist ISR - uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(isp_proc->hal.hw); - int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 7 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; - ESP_GOTO_ON_ERROR(esp_intr_alloc_intrstatus(isp_hw_info.instances[isp_proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | intr_priority, intr_st_reg_addr, ISP_LL_EVENT_HIST_MASK, - s_isp_hist_default_isr, hist_ctlr, &hist_ctlr->intr_handle), err2, TAG, "allocate interrupt failed"); + + // Register the HIGT ISR + ESP_GOTO_ON_ERROR(esp_isp_register_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST), err2, TAG, "fail to register ISR"); // Configure the hardware isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode); - isp_ll_hist_set_x_offset(isp_proc->hal.hw, hist_cfg->first_window_x_offs); - isp_ll_hist_set_y_offset(isp_proc->hal.hw, hist_cfg->first_window_y_offs); - isp_ll_hist_set_window_x_size(isp_proc->hal.hw, hist_cfg->window_x_size); - isp_ll_hist_set_window_y_size(isp_proc->hal.hw, hist_cfg->window_y_size); - isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->hist_windows_weight); - isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->hist_segment_threshold); - if (hist_cfg->hist_mode == ISP_HIST_RGB) { + isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window); + + isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->windows_weight); + + isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold); + if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient); } @@ -121,9 +135,13 @@ esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr) { ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use"); - ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state"); - s_isp_declaim_hist_controller(hist_ctlr); + ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); + + // Deregister the HIST ISR + ESP_RETURN_ON_FALSE(esp_isp_deregister_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST) == ESP_OK, ESP_FAIL, TAG, "fail to deregister ISR"); + + s_isp_declaim_hist_controller(hist_ctlr); s_isp_hist_free_controller(hist_ctlr); return ESP_OK; @@ -132,49 +150,28 @@ esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr) esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr) { ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state"); - esp_err_t ret = ESP_OK; - ESP_GOTO_ON_ERROR(esp_intr_enable(hist_ctlr->intr_handle), err, TAG, "failed to enable the HIST interrupt"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE), + ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); + isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true); isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true); - hist_ctlr->fsm = ISP_FSM_ENABLE; -err: - hist_ctlr->fsm = ISP_FSM_INIT; - return ret; + return ESP_OK; } esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr) { ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); + + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_INIT), + ESP_ERR_INVALID_STATE, TAG, "controller not in enable state"); isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false); isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false); esp_intr_disable(hist_ctlr->intr_handle); - hist_ctlr->fsm = ISP_FSM_INIT; - - return ESP_OK; -} - -esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg) -{ - ESP_RETURN_ON_FALSE(hist_ctlr && hist_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 3 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; - ESP_RETURN_ON_FALSE(intr_priority == hist_ctlr->intr_priority, ESP_ERR_INVALID_ARG, TAG, "can't change interrupt priority after initialized"); - - // Configure the hardware - isp_ll_hist_set_mode(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_mode); - isp_ll_hist_set_x_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_x_offs); - isp_ll_hist_set_y_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_y_offs); - isp_ll_hist_set_window_x_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_x_size); - isp_ll_hist_set_window_y_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_y_size); - isp_ll_hist_set_subwindow_weight(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_windows_weight); - isp_ll_hist_set_segment_threshold(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_segment_threshold); - if (hist_cfg->hist_mode == ISP_HIST_RGB) { - isp_ll_hist_set_rgb_coefficient(hist_ctlr->isp_proc->hal.hw, &hist_cfg->rgb_coefficient); - } return ESP_OK; } @@ -182,10 +179,13 @@ esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_ esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res) { ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); esp_err_t ret = ESP_OK; TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms); + + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ONESHOT), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet"); + // Reset the queue in case receiving the legacy data in the queue xQueueReset(hist_ctlr->evt_que); // Start the histogram reference statistics and waiting it done @@ -197,15 +197,16 @@ esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ct // Stop the histogram reference statistics isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); + atomic_store(&hist_ctlr->fsm, ISP_FSM_ENABLE); return ret; } esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr) { ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state"); - hist_ctlr->fsm = ISP_FSM_START; + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_CONTINUOUS), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet"); isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); return ESP_OK; @@ -214,10 +215,11 @@ esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hi esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr) { ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_START, ESP_ERR_INVALID_STATE, TAG, "controller isn't in continuous state"); + isp_fsm_t expected_fsm = ISP_FSM_CONTINUOUS; + ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE), + ESP_ERR_INVALID_STATE, TAG, "controller is not running"); isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); - hist_ctlr->fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -225,18 +227,14 @@ esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t his /*--------------------------------------------------------------- INTR ---------------------------------------------------------------*/ -static void IRAM_ATTR s_isp_hist_default_isr(void *arg) + +bool IRAM_ATTR esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events) { - isp_hist_ctlr_t hist_ctlr = (isp_hist_ctlr_t)arg; - isp_proc_handle_t proc = hist_ctlr->isp_proc; - - uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK); - bool need_yield = false; - if (hist_events & ISP_LL_EVENT_HIST_MASK) { + if (hist_events & ISP_LL_EVENT_HIST_FDONE) { isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr; - uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; + uint32_t hist_value[ISP_HIST_SEGMENT_NUMS] = {}; isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value); // Get the statistics result esp_isp_hist_evt_data_t edata = {}; @@ -251,25 +249,20 @@ static void IRAM_ATTR s_isp_hist_default_isr(void *arg) // Send the event data to the queue, overwrite the legacy one if exist xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake); need_yield |= high_task_awake == pdTRUE; - /* If started continuous sampling, then trigger the next hist sample */ - if (hist_ctlr->fsm == ISP_FSM_START) { - isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false); - isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); - } + } - if (need_yield) { - portYIELD_FROM_ISR(); - } + return need_yield; } esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data) { ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "detector isn't in the init state"); + + ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); #if CONFIG_ISP_ISR_IRAM_SAFE if (cbs->on_statistics_done) { - ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_env_change callback not in IRAM"); + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_statistics_done callback not in IRAM"); } if (user_data) { ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM"); diff --git a/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c b/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c index ffcaeba7f9..0895852749 100644 --- a/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c +++ b/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c @@ -327,3 +327,102 @@ TEST_CASE("ISP AE controller exhausted allocation", "[isp]") } TEST_ESP_OK(esp_isp_del_processor(isp_proc)); } + +static bool test_isp_hist_default_on_statistics_done_cb(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data) +{ + (void) hist_ctlr; + (void) edata; + (void) user_data; + // Do nothing + return false; +} + +/*--------------------------------------------------------------- + HIST +---------------------------------------------------------------*/ +TEST_CASE("ISP HIST driver basic function", "[isp]") +{ + esp_isp_processor_cfg_t isp_config = { + .clk_hz = 80 * 1000 * 1000, + .input_data_source = ISP_INPUT_DATA_SOURCE_CSI, + .input_data_color_type = ISP_COLOR_RAW8, + .output_data_color_type = ISP_COLOR_RGB565, + }; + isp_proc_handle_t isp_proc = NULL; + TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc)); + TEST_ESP_OK(esp_isp_enable(isp_proc)); + + isp_hist_ctlr_t hist_ctlr = NULL; + isp_hist_result_t hist_res = {}; + + /* Test when sum of weight is not 256 */ + esp_isp_hist_config_t hist_config_error = { + .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .windows_weight = {{5, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + }; + TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_isp_new_hist_controller(isp_proc, &hist_config_error, &hist_ctlr)); + + esp_isp_hist_config_t hist_config = { + .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .hist_mode = ISP_HIST_SAMPLING_RGB, + .rgb_coefficient.coeff_r = 33, + .rgb_coefficient.coeff_g = 33, + .rgb_coefficient.coeff_b = 34, + .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + }; + TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr)); + + /* Register HIST callback */ + esp_isp_hist_cbs_t hist_cb = { + .on_statistics_done = test_isp_hist_default_on_statistics_done_cb, + }; + TEST_ESP_OK(esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cb, NULL)); + /* Enabled the hist controller */ + TEST_ESP_OK(esp_isp_hist_controller_enable(hist_ctlr)); + /* Start continuous HIST statistics */ + TEST_ESP_OK(esp_isp_hist_controller_start_continuous_statistics(hist_ctlr)); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 0, &hist_res)); + /* Stop continuous HIST statistics */ + TEST_ESP_OK(esp_isp_hist_controller_stop_continuous_statistics(hist_ctlr)); + TEST_ESP_ERR(ESP_ERR_TIMEOUT, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 1, &hist_res)); + /* Disable the hist controller */ + TEST_ESP_OK(esp_isp_hist_controller_disable(hist_ctlr)); + /* Delete the hist controller and free the resources */ + TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr)); + + TEST_ESP_OK(esp_isp_disable(isp_proc)); + TEST_ESP_OK(esp_isp_del_processor(isp_proc)); +} + +TEST_CASE("ISP HIST controller exhausted allocation", "[isp]") +{ + esp_isp_processor_cfg_t isp_config = { + .clk_hz = 80 * 1000 * 1000, + .input_data_source = ISP_INPUT_DATA_SOURCE_CSI, + .input_data_color_type = ISP_COLOR_RAW8, + .output_data_color_type = ISP_COLOR_RGB565, + }; + isp_proc_handle_t isp_proc = NULL; + TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc)); + + esp_isp_hist_config_t hist_config = { + .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .hist_mode = ISP_HIST_SAMPLING_RGB, + .rgb_coefficient.coeff_r = 33, + .rgb_coefficient.coeff_g = 33, + .rgb_coefficient.coeff_b = 34, + .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + }; + + isp_hist_ctlr_t hist_ctlr[SOC_ISP_HIST_CTLR_NUMS + 1] = {}; + for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) { + TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[i])); + } + + TEST_ASSERT(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[SOC_ISP_HIST_CTLR_NUMS]) == ESP_ERR_NOT_FOUND); + + for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) { + TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr[i])); + } + TEST_ESP_OK(esp_isp_del_processor(isp_proc)); +} diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index 963d31d865..6be3b69c9b 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -1635,43 +1635,13 @@ static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable) * @param[in] hw Hardware instance address * @param[in] window_weight array for window weight */ -static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_WINDOW_NUMS]) +static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_BLOCK_X_NUMS][SOC_ISP_HIST_BLOCK_Y_NUMS]) { - int idx = 0; - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_00, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_01, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_02, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_03, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_04, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_10, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_11, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_12, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_13, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_14, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_20, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_21, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_22, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_23, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_24, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_30, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_31, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_32, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_33, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_34, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_40, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_41, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_42, window_weight[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_43, window_weight[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight6, hist_weight_44, window_weight[idx++]); - - HAL_ASSERT(idx == 25); + for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) { + for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) { + hw->hist_weight[i / 4].hist_weight_b[3 - (i % 4)] = (window_weight[i][j] * 256) / 100; + } + } } /** @@ -1680,78 +1650,33 @@ static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_ * @param[in] hw Hardware instance address * @param[in] segment_threshold array for segment threshold */ -static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS - 1]) +static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS]) { - int idx = 0; - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_0_1, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_1_2, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_2_3, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_3_4, segment_threshold[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_4_5, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_5_6, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_6_7, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_7_8, segment_threshold[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_8_9, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_9_10, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_10_11, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_11_12, segment_threshold[idx++]); - - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_12_13, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_13_14, segment_threshold[idx++]); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_14_15, segment_threshold[idx++]); - - HAL_ASSERT(idx == 15); + for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) + { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg[i / 4], hist_seg_b[3 - (i % 4)], segment_threshold[i]) + } } /** - * @brief Set histogram x offset + * @brief Set histogram window range * - * @param[in] hw Hardware instance address - * @param[in] x_offset value for x offset -*/ -static inline void isp_ll_hist_set_x_offset(isp_dev_t *hw, uint32_t x_offset) + * @param[in] hw Hardware instance address + * @param[in] x_start Top left pixel x axis value + * @param[in] x_bsize Block size on x axis + * @param[in] y_start Top left pixel y axis value + * @param[in] y_bsize Block size on y axis + */ +static inline void isp_ll_hist_set_window_range(isp_dev_t *hw, int x_start, int x_bsize, int y_start, int y_bsize) { - hw->hist_offs.hist_x_offs = x_offset; + hw->hist_offs.hist_x_offs = x_start; + hw->hist_offs.hist_y_offs = y_start; + hw->hist_size.hist_x_size = x_bsize; + hw->hist_size.hist_y_size = y_bsize; } /** - * @brief Set histogram y offset - * - * @param[in] hw Hardware instance address - * @param[in] y_offset value for y offset -*/ -static inline void isp_ll_hist_set_y_offset(isp_dev_t *hw, uint32_t y_offset) -{ - hw->hist_offs.hist_y_offs = y_offset; -} - -/** - * @brief Set histogram x size - * - * @param[in] hw Hardware instance address - * @param[in] x_size value for x size -*/ -static inline void isp_ll_hist_set_window_x_size(isp_dev_t *hw, uint32_t x_size) -{ - hw->hist_size.hist_x_size = x_size; -} - -/** - * @brief Set histogram y size - * - * @param[in] hw Hardware instance address - * @param[in] y_size value for y size -*/ -static inline void isp_ll_hist_set_window_y_size(isp_dev_t *hw, uint32_t y_size) -{ - hw->hist_size.hist_y_size = y_size; -} - -/** - * @brief Start histogram statistic + * @brief Enable / Disable histogram statistic * * @param[in] hw Hardware instance address * @param[in] enable enable/disable @@ -1761,16 +1686,6 @@ static inline void isp_ll_hist_enable(isp_dev_t *hw, bool enable) hw->cntl.hist_en = enable; } -/** - * @brief Stop histogram statistic - * - * @param[in] hw Hardware instance address -*/ -static inline void isp_ll_hist_stop(isp_dev_t *hw) -{ - hw->cntl.hist_en = 1; -} - /** * @brief Get histogram value * @@ -1786,27 +1701,27 @@ static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *hist } /** - * @brief Get histogram value + * @brief Set histogram sampling mode * * @param[in] hw Hardware instance address - * @param[out] histogram_value pointer to histogram result + * @param[in] hist_mode histogram mode */ -static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_mode_enum_t hist_mode) +static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_sampling_mode_t hist_mode) { hw->hist_mode.hist_mode = hist_mode; } /** - * @brief Get histogram value + * @brief Set histogram RGB coefficients, only effect when hist_mode is ISP_HIST_SAMPLING_RGB * * @param[in] hw Hardware instance address - * @param[out] histogram_value pointer to histogram result + * @param[in] rgb_coeff RGB coefficients */ static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient *rgb_coeff) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, (rgb_coeff->coeff_r * 256) / 100); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, (rgb_coeff->coeff_g * 256) / 100); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, (rgb_coeff->coeff_b * 256) / 100); } #ifdef __cplusplus diff --git a/components/hal/include/hal/isp_hal.h b/components/hal/include/hal/isp_hal.h index 0b7f7cb889..b4e38ffd4d 100644 --- a/components/hal/include/hal/isp_hal.h +++ b/components/hal/include/hal/isp_hal.h @@ -188,6 +188,17 @@ uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t m */ void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *config); +/*--------------------------------------------------------------- + Histogram +---------------------------------------------------------------*/ +/** + * @brief Configure Histogram window + * + * @param[in] hal Context of the HAL layer + * @param[in] window Window info, see `isp_window_t` + */ +void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window); + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/isp_types.h b/components/hal/include/hal/isp_types.h index 19a2a1bad2..47fda745f5 100644 --- a/components/hal/include/hal/isp_types.h +++ b/components/hal/include/hal/isp_types.h @@ -33,8 +33,7 @@ typedef struct { } isp_coordinate_t; /** - * @brief ISP window type - * + * @brief The top left and bottom right coordinates of ISP full window */ typedef struct { isp_coordinate_t top_left; ///< The top left point coordinate @@ -238,37 +237,35 @@ typedef struct { /*--------------------------------------------------------------- HIST ---------------------------------------------------------------*/ -#if SOC_ISP_HIST_WINDOW_NUMS -#define ISP_HIST_WINDOW_NUM SOC_ISP_HIST_WINDOW_NUMS // The HIST window number for sampling +#if (SOC_ISP_HIST_BLOCK_X_NUMS && SOC_ISP_HIST_BLOCK_Y_NUMS) +#define ISP_HIST_BLOCK_X_NUM SOC_ISP_HIST_BLOCK_X_NUMS // The AF window number for sampling +#define ISP_HIST_BLOCK_Y_NUM SOC_ISP_HIST_BLOCK_Y_NUMS // The AF window number for sampling #else -#define ISP_HIST_WINDOW_NUM 0 +#define ISP_HIST_BLOCK_X_NUM 0 +#define ISP_HIST_BLOCK_Y_NUM 0 #endif -#if SOC_ISP_HIST_SEGMENT_NUMS +#if (SOC_ISP_HIST_SEGMENT_NUMS && SOC_ISP_HIST_INTERVAL_NUMS) #define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram +#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The interval of histogram #else #define ISP_HIST_SEGMENT_NUMS 0 -#endif - -#if SOC_ISP_HIST_INTERVAL_NUMS -#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The segment of histogram -#else -#define ISP_HIST_INTERVAL_NUMS 0 +#define ISP_HIST_INTERVAL_NUMS 0 #endif /** * @brief ISP histogram mode. */ typedef enum { - ISP_HIST_RGB_B, ///< histogram mode for B component for RGB - ISP_HIST_RGB_GB, ///< histogram mode for GB component for RGB - ISP_HIST_RGB_GR, ///< histogram mode for GR component for RGB - ISP_HIST_RGB_R, ///< histogram mode for R component for RGB - ISP_HIST_RGB, ///< histogram mode for RGB - ISP_HIST_YUV_Y, ///< histogram mode for Y component for YUV - ISP_HIST_YUV_U, ///< histogram mode for U component for YUV - ISP_HIST_YUV_V, ///< histogram mode for V component for YUV -} isp_hist_mode_enum_t; + ISP_HIST_SAMPLING_RAW_RGB_B, ///< histogram mode for B component of raw image + ISP_HIST_SAMPLING_RAW_RGB_GB, ///< histogram mode for GB component of raw image + ISP_HIST_SAMPLING_RAW_RGB_GR, ///< histogram mode for GR component of raw image + ISP_HIST_SAMPLING_RAW_RGB_R, ///< histogram mode for R component of raw image + ISP_HIST_SAMPLING_RGB, ///< histogram mode for RGB + ISP_HIST_SAMPLING_YUV_Y, ///< histogram mode for Y component for YUV + ISP_HIST_SAMPLING_YUV_U, ///< histogram mode for U component for YUV + ISP_HIST_SAMPLING_YUV_V, ///< histogram mode for V component for YUV +} isp_hist_sampling_mode_t; /** * @brief ISP histogram r,g,b coefficient @@ -283,7 +280,7 @@ typedef struct { * @brief ISP histogram result. */ typedef struct { - uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< histogram value. + uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< Histogram value, represents the number of pixels that the histogram window's brightness results fall into the segment X. } isp_hist_result_t; diff --git a/components/hal/isp_hal.c b/components/hal/isp_hal.c index 2c8ad430a7..864e4026c1 100644 --- a/components/hal/isp_hal.c +++ b/components/hal/isp_hal.c @@ -169,17 +169,18 @@ bool isp_hal_ccm_set_matrix(const isp_hal_context_t *hal, bool saturation, const } /*--------------------------------------------------------------- - INTR, put in iram + Histogram ---------------------------------------------------------------*/ -uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask) +void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window) { - uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask; + uint32_t hist_x_start = window->top_left.x; + uint32_t hist_x_bsize = (window->btm_right.x - window-> top_left.x) / SOC_ISP_HIST_BLOCK_X_NUMS; - if (triggered_events) { - isp_ll_clear_intr(hal->hw, triggered_events); - } + uint32_t hist_y_start = window->top_left.y; + uint32_t hist_y_bsize = (window->btm_right.y - window->top_left.y) / SOC_ISP_HIST_BLOCK_Y_NUMS; + + isp_ll_hist_set_window_range(hal->hw, hist_x_start, hist_x_bsize, hist_y_start, hist_y_bsize); - return triggered_events; } /*--------------------------------------------------------------- @@ -213,3 +214,17 @@ void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *confi isp_ll_sharp_set_template(hal->hw, default_template); } } + +/*--------------------------------------------------------------- + INTR, put in iram +---------------------------------------------------------------*/ +uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask) +{ + uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask; + + if (triggered_events) { + isp_ll_clear_intr(hal->hw, triggered_events); + } + + return triggered_events; +} diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index c441679b7d..3910124057 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -923,9 +923,17 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS int default 24 -config SOC_ISP_HIST_WINDOW_NUMS +config SOC_ISP_HIST_CTLR_NUMS int - default 25 + default 1 + +config SOC_ISP_HIST_BLOCK_X_NUMS + int + default 5 + +config SOC_ISP_HIST_BLOCK_Y_NUMS + int + default 5 config SOC_ISP_HIST_SEGMENT_NUMS int diff --git a/components/soc/esp32p4/include/soc/isp_struct.h b/components/soc/esp32p4/include/soc/isp_struct.h index 7104e5202b..c5edfc6a19 100644 --- a/components/soc/esp32p4/include/soc/isp_struct.h +++ b/components/soc/esp32p4/include/soc/isp_struct.h @@ -1821,6 +1821,25 @@ typedef union { uint32_t val; } isp_hist_size_reg_t; +/** Type of hist_seg register + * histogram bin control register + */ +typedef union { + struct { + /** hist_seg: R/W; + * default: + * 16, 32, 48, 64, + * 80, 96, 112, 128, + * 144, 160, 176, 192, + * 208, 224, 240 + * this field configures threshold of histogram + */ + uint8_t hist_seg_b[4]; + }; + uint32_t val; +} isp_hist_seg_reg_t; + + /** Type of hist_seg0 register * histogram bin control register 0 */ @@ -1918,6 +1937,20 @@ typedef union { uint32_t val; } isp_hist_seg3_reg_t; +/** Type of hist_weight register + * histogram sub-window weight register 0 + */ +typedef union { + struct { + /** histogram weight : RO; bitpos: [31:0]; + * weight[12] default 232, others default 1 + * this field represents the weight of histogram subwindow, sum of all weight should be 256 + */ + uint8_t hist_weight_b[4]; + }; + uint32_t val; +} isp_hist_weight_reg_t; + /** Type of hist_weight0 register * histogram sub-window weight register 0 */ @@ -3227,17 +3260,8 @@ typedef struct { volatile isp_hist_coeff_reg_t hist_coeff; volatile isp_hist_offs_reg_t hist_offs; volatile isp_hist_size_reg_t hist_size; - volatile isp_hist_seg0_reg_t hist_seg0; - volatile isp_hist_seg1_reg_t hist_seg1; - volatile isp_hist_seg2_reg_t hist_seg2; - volatile isp_hist_seg3_reg_t hist_seg3; - volatile isp_hist_weight0_reg_t hist_weight0; - volatile isp_hist_weight1_reg_t hist_weight1; - volatile isp_hist_weight2_reg_t hist_weight2; - volatile isp_hist_weight3_reg_t hist_weight3; - volatile isp_hist_weight4_reg_t hist_weight4; - volatile isp_hist_weight5_reg_t hist_weight5; - volatile isp_hist_weight6_reg_t hist_weight6; + volatile isp_hist_seg_reg_t hist_seg[4]; + volatile isp_hist_weight_reg_t hist_weight[7]; volatile isp_hist_binn_reg_t hist_binn[16]; volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index efa9e9c0ce..0b09a6ee89 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -355,9 +355,11 @@ #define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3 #define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5 #define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24 -#define SOC_ISP_HIST_WINDOW_NUMS 25 -#define SOC_ISP_HIST_SEGMENT_NUMS 16 -#define SOC_ISP_HIST_INTERVAL_NUMS 15 +#define SOC_ISP_HIST_CTLR_NUMS 1U +#define SOC_ISP_HIST_BLOCK_X_NUMS 5 +#define SOC_ISP_HIST_BLOCK_Y_NUMS 5 +#define SOC_ISP_HIST_SEGMENT_NUMS 16 +#define SOC_ISP_HIST_INTERVAL_NUMS 15 /*-------------------------- LEDC CAPS ---------------------------------------*/ #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst index d44ccc3c2b..b2c9bd39b0 100644 --- a/docs/en/api-reference/peripherals/isp.rst +++ b/docs/en/api-reference/peripherals/isp.rst @@ -153,6 +153,28 @@ If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, users can You can use the created handle to do driver enable / disable the ISP AE driver and ISP AE environment detector setup. +Install ISP histogram (HIST) Driver +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +ISP histogram (HIST) driver requires the configuration that specified by :cpp:type:`esp_isp_hist_config_t`. + +If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP HISTG processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference. + +.. code:: c + + esp_isp_hist_config_t hist_cfg = { + .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .rgb_coefficient.coeff_r = 33, + .rgb_coefficient.coeff_g = 33, + .rgb_coefficient.coeff_b = 34, + .hist_mode = ISP_HIST_SAMPLING_RGB, + .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + }; + isp_hist_ctlr_t hist_ctlr_ctlr = NULL; + ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr)); + +You can use the created handle to do driver enable / disable the ISP HIST driver setup. + Uninstall ISP Driver ~~~~~~~~~~~~~~~~~~~~ @@ -173,6 +195,11 @@ UnInstall ISP AE Driver If a previously installed ISP AE processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_ae_controller`, it will also release the underlying hardware. +UnInstall ISP HIST Driver +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If a previously installed ISP HIST processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_hist_controller`, it will also release the underlying hardware. + .. _isp-enable-disable: @@ -417,6 +444,8 @@ Aside from the above oneshot API, the ISP histogram driver also provides a way t Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__ +Note that the sum of all subwindows's weight should be 100, the sum of all RGB coefficients should be 100, and segment_threshold must be 0 ~ 256. + .. code:: c static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data) @@ -427,29 +456,23 @@ Note that if you want to use the continuous statistics, you need to register the return true; } - isp_hist_ctlr_t hist_ctrlr = NULL; + isp_hist_ctlr_t hist_ctlr = NULL; esp_isp_hist_config_t hist_cfg = { - .first_window_x_offs = 0, - .first_window_y_offs = 0, - .window_x_size = 800 / 25, - .window_y_size = 640 / 25, - .rgb_coefficient = { - .coeff_b = 85, - .coeff_g = 85, - .coeff_r = 85, - }, - .hist_windows_weight = {[0 ... ISP_HIST_WINDOW_NUM - 1] = 10}, - .hist_segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, - .hist_mode = ISP_HIST_RGB, + .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, + .rgb_coefficient.coeff_r = 33, + .rgb_coefficient.coeff_g = 33, + .rgb_coefficient.coeff_b = 34, + .hist_mode = ISP_HIST_SAMPLING_RGB, + .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, }; - esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctrlr); + esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctlr); esp_isp_hist_cbs_t hist_cbs = { .on_statistics_done = s_hist_scheme_on_statistics_done_callback, }; - esp_isp_hist_register_event_callbacks(hist_ctrlr, &hist_cbs, hist_ctrlr); - esp_isp_hist_controller_enable(hist_ctrlr); + esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cbs, hist_ctlr); + esp_isp_hist_controller_enable(hist_ctlr); .. _isp_bf: From 8c31479fe5648c75bbec15e5733c16cf4486e062 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Sat, 17 Aug 2024 19:02:09 +0800 Subject: [PATCH 3/4] docs(isp): Add ISP histogram in the programming guide --- docs/en/api-reference/peripherals/isp.rst | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst index b2c9bd39b0..40a1bf0cca 100644 --- a/docs/en/api-reference/peripherals/isp.rst +++ b/docs/en/api-reference/peripherals/isp.rst @@ -618,6 +618,8 @@ Calling :cpp:func:`esp_isp_sharpen_disable` does the opposite, that is, put the Register Event Callbacks ^^^^^^^^^^^^^^^^^^^^^^^^ +After an ISP module starts up, it can generate a specific event dynamically. +You can save your own context to callback function as well, via the parameter ``user_data``. The user data will be directly passed to the callback function. .. note:: @@ -630,8 +632,6 @@ After the ISP processor is enabled, it can generate multiple events of multiple - :cpp:member:`esp_isp_evt_cbs_t::on_sharpen_frame_done`. sets a callback function for sharpen frame done. It will be called after the ISP sharpen submodule finishes its operation for one frame. The function prototype is declared in :cpp:type:`esp_isp_sharpen_callback_t`. -You can save your own context to :cpp:func:`esp_isp_register_event_callbacks` as well, via the parameter ``user_data``. The user data will be directly passed to the callback function. - Register ISP AF Environment Detector Event Callbacks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -640,8 +640,6 @@ After the ISP AF environment detector starts up, it can generate a specific even - :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. The function prototype is declared in :cpp:type:`esp_isp_af_env_detector_callback_t`. - :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. The function prototype is declared in :cpp:type:`esp_isp_af_env_detector_callback_t`. -You can save your own context to :cpp:func:`esp_isp_af_env_detector_register_event_callbacks` as well, via the parameter ``user_data``. The user data will be directly passed to the callback function. - Register ISP AWB Statistics Done Event Callbacks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -649,7 +647,22 @@ After the ISP AWB controller finished statistics of white patches, it can genera - :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` sets a callback function when finished statistics of the white patches. The function prototype is declared in :cpp:type:`esp_isp_awb_callback_t`. -You can save your own context via the parameter ``user_data`` of :cpp:func:`esp_isp_awb_register_event_callbacks`. The user data will be directly passed to the callback function. + +Register ISP AE Environment Detector Event Callbacks +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After the ISP AE environment detector starts up, it can generate a specific event dynamically. If you have some functions that should be called when the event happens, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_ae_env_detector_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_ae_env_detector_evt_cbs_t`: + +- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`. +- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`. + + +Register ISP HIST Statistics Done Event Callbacks +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After the ISP HIST controller finished statistics of brightness, it can generate a specific event dynamically. If you want to be informed when the statistics done event takes place, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_hist_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_hist_cbs_t`: + +- :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` sets a callback function when finished statistics of the brightness. . The function prototype is declared in :cpp:type:`esp_isp_hist_callback_t`. .. _isp-thread-safety: From c3155c39d1f8274a546e4288f67984f5a208394d Mon Sep 17 00:00:00 2001 From: gaoxu Date: Thu, 22 Aug 2024 11:19:07 +0800 Subject: [PATCH 4/4] feat(isp_hist): change coeff and weight of HIST to integer/decimal struct --- .../esp_driver_isp/include/driver/isp_hist.h | 25 ++++-- components/esp_driver_isp/src/isp_hist.c | 59 +++++++------ .../test_apps/isp/main/test_isp_driver.c | 40 +++++++-- components/hal/esp32p4/include/hal/isp_ll.h | 22 +++-- components/hal/include/hal/isp_types.h | 85 ++++++++++++++----- docs/doxygen/Doxyfile_esp32p4 | 1 + docs/en/api-reference/peripherals/isp.rst | 45 ++++++---- 7 files changed, 182 insertions(+), 95 deletions(-) diff --git a/components/esp_driver_isp/include/driver/isp_hist.h b/components/esp_driver_isp/include/driver/isp_hist.h index e7568e64d7..331b0207d9 100644 --- a/components/esp_driver_isp/include/driver/isp_hist.h +++ b/components/esp_driver_isp/include/driver/isp_hist.h @@ -15,14 +15,25 @@ extern "C" { #endif -typedef struct { - isp_window_t window; /*!< The sampling window of histogram, see `isp_window_t`*/ - isp_hist_sampling_mode_t hist_mode; /*!< ISP histogram sampling mode */ - isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficients, adjust the sensitivity to red, geen, and blue colors in the image, - only effect when hist_mode is ISP_HIST_SAMPLING_RGB, the sum of all coefficients should be 100**/ - uint32_t windows_weight[ISP_HIST_BLOCK_X_NUM][ISP_HIST_BLOCK_Y_NUM]; /*!< Weights of histogram's each subwindows, the sum of all subwindows's weight should be 100*/ - uint32_t segment_threshold[ISP_HIST_INTERVAL_NUMS]; /*!< Threshold to segment the histogram into intervals, range 0~256 */ +/* + * ISP Histogram Struct + * |<----------------------------- INTERVAL_NUMS = 16 ------------------------------>| + * | | | | | + * | Segment 0 | Segment 1 | ............ | Segment 15 | + * 0 threshold 0 threshold 1 ... threshold 14 255 + * |<------------------------------------------------------------------------------->| + */ +/** + * @brief Hist controller config + */ +typedef struct { + isp_window_t window; /*!< The sampling window of histogram, see `isp_window_t`*/ + isp_hist_sampling_mode_t hist_mode; /*!< ISP histogram sampling mode */ + isp_hist_rgb_coefficient_t rgb_coefficient; /*!< RGB coefficients, adjust the sensitivity to red, geen, and blue colors in the image, + only effect when hist_mode is ISP_HIST_SAMPLING_RGB, the sum of all coefficients decimal should be 256**/ + isp_hist_weight_t window_weight[ISP_HIST_BLOCK_X_NUM * ISP_HIST_BLOCK_Y_NUM]; /*!< Weights of histogram's each subwindows, the sum of all subwindows's weight decimal should be 256*/ + uint32_t segment_threshold[ISP_HIST_INTERVAL_NUMS]; /*!< Threshold to segment the histogram into intervals, range 0~255 */ } esp_isp_hist_config_t; /** diff --git a/components/esp_driver_isp/src/isp_hist.c b/components/esp_driver_isp/src/isp_hist.c index 225b0d46ed..739a8a2ac7 100644 --- a/components/esp_driver_isp/src/isp_hist.c +++ b/components/esp_driver_isp/src/isp_hist.c @@ -70,6 +70,34 @@ static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr) } } +static esp_err_t s_esp_isp_hist_config_hardware(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg) +{ + for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) { + ESP_RETURN_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, TAG, "invalid segment threshold"); + } + ESP_RETURN_ON_FALSE(hist_cfg->rgb_coefficient.coeff_r.integer == 0 && hist_cfg->rgb_coefficient.coeff_g.integer == 0 && hist_cfg->rgb_coefficient.coeff_b.integer == 0, \ + ESP_ERR_INVALID_ARG, TAG, "The rgb_coefficient's integer value is bigger than 0"); + + int weight_sum = 0; + for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS; i++) { + ESP_RETURN_ON_FALSE(hist_cfg->window_weight[i].integer == 0, ESP_ERR_INVALID_ARG, TAG, "The subwindow weight's integer value is bigger than -"); + weight_sum = weight_sum + hist_cfg->window_weight[i].decimal; + } + ESP_RETURN_ON_FALSE(weight_sum == 256, ESP_ERR_INVALID_ARG, TAG, "The sum of all subwindow weight's decimal value is not 256"); + + isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode); + isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window); + + isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->window_weight); + + isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold); + if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { + isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient); + } + + return ESP_OK; +} + esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl) { esp_err_t ret = ESP_FAIL; @@ -85,22 +113,8 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_ hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; hist_ctlr->isp_proc = isp_proc; - for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) { - ESP_GOTO_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, err1, TAG, "invalid segment threshold"); - } - - int weight_sum = 0; - for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) { - for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) { - weight_sum = weight_sum + hist_cfg->windows_weight[i][j]; - } - } - ESP_GOTO_ON_FALSE(weight_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of all subwindow's weight is not 100"); - - if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { - int rgb_coefficient_sum = hist_cfg->rgb_coefficient.coeff_r + hist_cfg->rgb_coefficient.coeff_g + hist_cfg->rgb_coefficient.coeff_b; - ESP_GOTO_ON_FALSE(rgb_coefficient_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of rgb_coefficient is not 100"); - } + // Configure the hardware + ESP_GOTO_ON_ERROR(s_esp_isp_hist_config_hardware(isp_proc, hist_cfg), err1, TAG, "configure HIST hardware failed"); // Claim an hist controller ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller"); @@ -108,17 +122,6 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_ // Register the HIGT ISR ESP_GOTO_ON_ERROR(esp_isp_register_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST), err2, TAG, "fail to register ISR"); - // Configure the hardware - isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode); - isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window); - - isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->windows_weight); - - isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold); - if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { - isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient); - } - *ret_hdl = hist_ctlr; return ESP_OK; @@ -191,7 +194,7 @@ esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ct // Start the histogram reference statistics and waiting it done isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true); // Wait the statistics to finish and receive the result from the queue - if ((ticks > 0) && xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) { + if (xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) { ret = ESP_ERR_TIMEOUT; } // Stop the histogram reference statistics diff --git a/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c b/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c index 0895852749..d14f6033a2 100644 --- a/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c +++ b/components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c @@ -358,17 +358,33 @@ TEST_CASE("ISP HIST driver basic function", "[isp]") /* Test when sum of weight is not 256 */ esp_isp_hist_config_t hist_config_error = { .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, - .windows_weight = {{5, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + .hist_mode = ISP_HIST_SAMPLING_RGB, + .rgb_coefficient.coeff_r = {{86, 0}}, + .rgb_coefficient.coeff_g = {{85, 0}}, + .rgb_coefficient.coeff_b = {{85, 0}}, + .window_weight = { + {{15, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + }, }; TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_isp_new_hist_controller(isp_proc, &hist_config_error, &hist_ctlr)); esp_isp_hist_config_t hist_config = { .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, .hist_mode = ISP_HIST_SAMPLING_RGB, - .rgb_coefficient.coeff_r = 33, - .rgb_coefficient.coeff_g = 33, - .rgb_coefficient.coeff_b = 34, - .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + .rgb_coefficient.coeff_r = {{86, 0}}, + .rgb_coefficient.coeff_g = {{85, 0}}, + .rgb_coefficient.coeff_b = {{85, 0}}, + .window_weight = { + {{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + }, }; TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr)); @@ -408,10 +424,16 @@ TEST_CASE("ISP HIST controller exhausted allocation", "[isp]") esp_isp_hist_config_t hist_config = { .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, .hist_mode = ISP_HIST_SAMPLING_RGB, - .rgb_coefficient.coeff_r = 33, - .rgb_coefficient.coeff_g = 33, - .rgb_coefficient.coeff_b = 34, - .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + .rgb_coefficient.coeff_r = {{86, 0}}, + .rgb_coefficient.coeff_g = {{85, 0}}, + .rgb_coefficient.coeff_b = {{85, 0}}, + .window_weight = { + {{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + }, }; isp_hist_ctlr_t hist_ctlr[SOC_ISP_HIST_CTLR_NUMS + 1] = {}; diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index 6be3b69c9b..90d268256a 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -1635,12 +1635,11 @@ static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable) * @param[in] hw Hardware instance address * @param[in] window_weight array for window weight */ -static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_BLOCK_X_NUMS][SOC_ISP_HIST_BLOCK_Y_NUMS]) +static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const isp_hist_weight_t hist_window_weight[SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS]) { - for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) { - for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) { - hw->hist_weight[i / 4].hist_weight_b[3 - (i % 4)] = (window_weight[i][j] * 256) / 100; - } + for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS; i++) { + // On ESP32P4, hist_weight [7,0] are decimal + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight[i / 4], hist_weight_b[3 - (i % 4)], hist_window_weight[i].decimal); } } @@ -1652,9 +1651,8 @@ static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_ */ static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS]) { - for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) - { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg[i / 4], hist_seg_b[3 - (i % 4)], segment_threshold[i]) + for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg[i / 4], hist_seg_b[3 - (i % 4)], segment_threshold[i]); } } @@ -1717,11 +1715,11 @@ static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_sampling_mode_t * @param[in] hw Hardware instance address * @param[in] rgb_coeff RGB coefficients */ -static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient *rgb_coeff) +static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient_t *rgb_coeff) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, (rgb_coeff->coeff_r * 256) / 100); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, (rgb_coeff->coeff_g * 256) / 100); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, (rgb_coeff->coeff_b * 256) / 100); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r.decimal); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g.decimal); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b.decimal); } #ifdef __cplusplus diff --git a/components/hal/include/hal/isp_types.h b/components/hal/include/hal/isp_types.h index 47fda745f5..81210da06e 100644 --- a/components/hal/include/hal/isp_types.h +++ b/components/hal/include/hal/isp_types.h @@ -23,6 +23,19 @@ typedef soc_periph_isp_clk_src_t isp_clk_src_t; ///< Clock source type of typedef int isp_clk_src_t; ///< Default type #endif +/* + ISP window and subwindow + +----------------------------------------------------------+ + | <-- top left point coordinate | + | | subwindow[0][0] |......| subwindow[0][Y_NUM]| | + | . | + | . | + | . | + | | subwindow[X_NUM][0] |......| subwindow[X_NUM][Y_NUM]| | + | bottom right point coordinate --> | + +----------------------------------------------------------+ +*/ + /** * @brief ISP coordinate type * @@ -180,14 +193,13 @@ typedef enum { #define ISP_SHARPEN_M_FREQ_COEF_RES_BITS 16 #endif - /** * @brief High freq pixel sharpeness coeff */ typedef union { struct { - uint32_t decimal:ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Integer part - uint32_t integer:ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Decimal part + uint32_t decimal:ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Decimal part + uint32_t integer:ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Integer part uint32_t reserved:ISP_SHARPEN_H_FREQ_COEF_RES_BITS; ///< Reserved }; uint32_t val; ///< 32-bit high freq pixel sharpeness coeff register value @@ -198,8 +210,8 @@ typedef union { */ typedef union { struct { - uint32_t decimal:ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Integer part - uint32_t integer:ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Decimal part + uint32_t decimal:ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Decimal part + uint32_t integer:ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Integer part uint32_t reserved:ISP_SHARPEN_M_FREQ_COEF_RES_BITS; ///< Reserved }; uint32_t val; ///< 32-bit medium freq pixel sharpeness coeff register value @@ -238,43 +250,74 @@ typedef struct { HIST ---------------------------------------------------------------*/ #if (SOC_ISP_HIST_BLOCK_X_NUMS && SOC_ISP_HIST_BLOCK_Y_NUMS) -#define ISP_HIST_BLOCK_X_NUM SOC_ISP_HIST_BLOCK_X_NUMS // The AF window number for sampling -#define ISP_HIST_BLOCK_Y_NUM SOC_ISP_HIST_BLOCK_Y_NUMS // The AF window number for sampling +#define ISP_HIST_BLOCK_X_NUM SOC_ISP_HIST_BLOCK_X_NUMS // The AF window number for sampling +#define ISP_HIST_BLOCK_Y_NUM SOC_ISP_HIST_BLOCK_Y_NUMS // The AF window number for sampling #else -#define ISP_HIST_BLOCK_X_NUM 0 -#define ISP_HIST_BLOCK_Y_NUM 0 +#define ISP_HIST_BLOCK_X_NUM 0 +#define ISP_HIST_BLOCK_Y_NUM 0 #endif #if (SOC_ISP_HIST_SEGMENT_NUMS && SOC_ISP_HIST_INTERVAL_NUMS) -#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram -#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The interval of histogram +#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram +#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The interval of histogram #else -#define ISP_HIST_SEGMENT_NUMS 0 -#define ISP_HIST_INTERVAL_NUMS 0 +#define ISP_HIST_SEGMENT_NUMS 0 +#define ISP_HIST_INTERVAL_NUMS 0 #endif +#define ISP_HIST_WEIGHT_INT_BITS 8 +#define ISP_HIST_WEIGHT_DEC_BITS 7 +#define ISP_HIST_WEIGHT_RES_BITS 17 +#define ISP_HIST_COEFF_INT_BITS 8 +#define ISP_HIST_COEFF_DEC_BITS 7 +#define ISP_HIST_COEFF_RES_BITS 17 + /** * @brief ISP histogram mode. */ typedef enum { - ISP_HIST_SAMPLING_RAW_RGB_B, ///< histogram mode for B component of raw image - ISP_HIST_SAMPLING_RAW_RGB_GB, ///< histogram mode for GB component of raw image - ISP_HIST_SAMPLING_RAW_RGB_GR, ///< histogram mode for GR component of raw image - ISP_HIST_SAMPLING_RAW_RGB_R, ///< histogram mode for R component of raw image + ISP_HIST_SAMPLING_RAW_B, ///< histogram mode for B component of raw image + ISP_HIST_SAMPLING_RAW_GB, ///< histogram mode for GB component of raw image + ISP_HIST_SAMPLING_RAW_GR, ///< histogram mode for GR component of raw image + ISP_HIST_SAMPLING_RAW_R, ///< histogram mode for R component of raw image ISP_HIST_SAMPLING_RGB, ///< histogram mode for RGB ISP_HIST_SAMPLING_YUV_Y, ///< histogram mode for Y component for YUV ISP_HIST_SAMPLING_YUV_U, ///< histogram mode for U component for YUV ISP_HIST_SAMPLING_YUV_V, ///< histogram mode for V component for YUV } isp_hist_sampling_mode_t; +/** + * @brief ISP histogram weight value +*/ +typedef union { + struct { + uint32_t decimal:ISP_HIST_WEIGHT_DEC_BITS; ///< Decimal part + uint32_t integer:ISP_HIST_WEIGHT_INT_BITS; ///< Integer part + uint32_t reserved:ISP_HIST_WEIGHT_RES_BITS; ///< Reserved + }; + uint32_t val; ///< 32-bit histogram weight value +} isp_hist_weight_t; + +/** + * @brief ISP histogram coefficient value +*/ +typedef union { + struct { + uint32_t decimal:ISP_HIST_COEFF_DEC_BITS; ///< Decimal part + uint32_t integer:ISP_HIST_COEFF_INT_BITS; ///< Integer part + uint32_t reserved:ISP_HIST_COEFF_RES_BITS; ///< Reserved + }; + uint32_t val; ///< 32-bit histogram coefficient value +} isp_hist_coeff_t; + /** * @brief ISP histogram r,g,b coefficient */ typedef struct { - uint8_t coeff_r; ///< R coefficient - uint8_t coeff_g; ///< G coefficient - uint8_t coeff_b; ///< B coefficient -} isp_hist_rgb_coefficient; + isp_hist_coeff_t coeff_r; ///< R coefficient + isp_hist_coeff_t coeff_g; ///< G coefficient + isp_hist_coeff_t coeff_b; ///< B coefficient +} isp_hist_rgb_coefficient_t; /** * @brief ISP histogram result. diff --git a/docs/doxygen/Doxyfile_esp32p4 b/docs/doxygen/Doxyfile_esp32p4 index f408182d6a..0883585060 100644 --- a/docs/doxygen/Doxyfile_esp32p4 +++ b/docs/doxygen/Doxyfile_esp32p4 @@ -36,6 +36,7 @@ INPUT += \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_sharpen.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_core.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_gamma.h \ + $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_hist.h \ $(PROJECT_PATH)/components/esp_driver_jpeg/include/driver/jpeg_decode.h \ $(PROJECT_PATH)/components/esp_driver_jpeg/include/driver/jpeg_encode.h \ $(PROJECT_PATH)/components/esp_driver_ppa/include/driver/ppa.h \ diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst index 40a1bf0cca..1e08164848 100644 --- a/docs/en/api-reference/peripherals/isp.rst +++ b/docs/en/api-reference/peripherals/isp.rst @@ -158,17 +158,38 @@ Install ISP histogram (HIST) Driver ISP histogram (HIST) driver requires the configuration that specified by :cpp:type:`esp_isp_hist_config_t`. -If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP HISTG processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference. +If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP Histogram processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference. + +.. list:: + + - The sum of all subwindows weight's decimal value should be 256 or the statistics will be small, and integer value should be 0. + - The sum of all RGB coefficients' decimal value should be 256 or the statistics will be small, and integer value should be 0. + - The segment_threshold must be 0 ~ 255 and in order .. code:: c esp_isp_hist_config_t hist_cfg = { .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, - .rgb_coefficient.coeff_r = 33, - .rgb_coefficient.coeff_g = 33, - .rgb_coefficient.coeff_b = 34, .hist_mode = ISP_HIST_SAMPLING_RGB, - .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, + .rgb_coefficient.coeff_r = { + .integer = 0, + .decimal = 86, + }, + .rgb_coefficient.coeff_g = { + .integer = 0, + .decimal = 85, + }, + .rgb_coefficient.coeff_b = { + .integer = 0, + .decimal = 85, + }, + .window_weight = { + {{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, + }, }; isp_hist_ctlr_t hist_ctlr_ctlr = NULL; ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr)); @@ -444,8 +465,6 @@ Aside from the above oneshot API, the ISP histogram driver also provides a way t Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__ -Note that the sum of all subwindows's weight should be 100, the sum of all RGB coefficients should be 100, and segment_threshold must be 0 ~ 256. - .. code:: c static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data) @@ -456,17 +475,6 @@ Note that the sum of all subwindows's weight should be 100, the sum of all RGB c return true; } - isp_hist_ctlr_t hist_ctlr = NULL; - esp_isp_hist_config_t hist_cfg = { - .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240}, - .rgb_coefficient.coeff_r = 33, - .rgb_coefficient.coeff_g = 33, - .rgb_coefficient.coeff_b = 34, - .hist_mode = ISP_HIST_SAMPLING_RGB, - .windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}}, - }; - - esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctlr); esp_isp_hist_cbs_t hist_cbs = { .on_statistics_done = s_hist_scheme_on_statistics_done_callback, }; @@ -715,3 +723,4 @@ API Reference .. include-build-file:: inc/isp_ccm.inc .. include-build-file:: inc/isp_sharpen.inc .. include-build-file:: inc/isp_gamma.inc +.. include-build-file:: inc/isp_hist.inc