feat(hal/aes): Add LL layer support for ESP32-P4 AES-GCM

components/hal/esp32p4/include/hal/aes_ll.h

@@ -249,6 +249,92 @@ static inline void aes_ll_interrupt_clear(void)
     REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
+/**
+ * @brief Continue a previous started transform
+ *
+ * @note Only used when doing GCM
+ */
+static inline void aes_ll_cont_transform(void)
+{
+    REG_WRITE(AES_CONTINUE_REG, 1);
+}
+
+/**
+ * @brief Reads the AES-GCM hash sub-key H
+ *
+ * @param gcm_hash hash value
+ */
+static inline void aes_ll_gcm_read_hash(uint8_t *gcm_hash)
+{
+    const size_t REG_WIDTH = sizeof(uint32_t);
+    uint32_t hash_word;
+
+    for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
+        hash_word = REG_READ(AES_H_MEM + (i * REG_WIDTH));
+        /* Memcpy to avoid potential unaligned access */
+        memcpy(gcm_hash + i * 4, &hash_word, sizeof(hash_word));
+    }
+}
+
+/**
+ * @brief Sets the number of Additional Authenticated Data (AAD) blocks
+ *
+ * @note Only affects AES-GCM
+
+ * @param aad_num_blocks the number of Additional Authenticated Data (AAD) blocks
+ */
+static inline void aes_ll_gcm_set_aad_num_blocks(size_t aad_num_blocks)
+{
+    REG_WRITE(AES_AAD_BLOCK_NUM_REG, aad_num_blocks);
+}
+
+/**
+ * @brief Sets the J0 value, for more information see the GCM subchapter in the TRM
+ *
+ * @note Only affects AES-GCM
+ *
+ * @param j0 J0 value
+ */
+static inline void aes_ll_gcm_set_j0(const uint8_t *j0)
+{
+    uint32_t *reg_addr_buf = (uint32_t *)(AES_J0_MEM);
+    uint32_t j0_word;
+
+    for (int i = 0; i < AES_BLOCK_WORDS; i++) {
+        /* Memcpy to avoid potential unaligned access */
+        memcpy(&j0_word, j0 + 4 * i, sizeof(j0_word));
+        REG_WRITE(&reg_addr_buf[i], j0_word);
+    }
+}
+
+/**
+ * @brief Sets the number of effective bits of incomplete blocks in plaintext/cipertext.
+ *
+ * @note Only affects AES-GCM
+ *
+ * @param num_valid_bits the number of effective bits of incomplete blocks in plaintext/cipertext.
+ */
+static inline void aes_ll_gcm_set_num_valid_bit(size_t num_valid_bits)
+{
+    REG_WRITE(AES_REMAINDER_BIT_NUM_REG, num_valid_bits);
+}
+
+/**
+ * @brief Read the tag after a AES-GCM transform
+ *
+ * @param tag Pointer to where to store the result with length TAG_WORDS
+ */
+static inline void aes_ll_gcm_read_tag(uint8_t *tag)
+{
+    uint32_t tag_word;
+    const size_t REG_WIDTH = sizeof(uint32_t);
+
+    for (size_t i = 0; i < TAG_WORDS; i++) {
+        tag_word = REG_READ(AES_T0_MEM + (i * REG_WIDTH));
+        /* Memcpy to avoid potential unaligned access */
+        memcpy(tag + i * 4, &tag_word, sizeof(tag_word));
+    }
+}
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -243,6 +243,10 @@ config SOC_AES_SUPPORT_DMA
     bool
     default y
 
+config SOC_AES_SUPPORT_GCM
+    bool
+    default y
+
 config SOC_AES_GDMA
     bool
     default y

components/soc/esp32p4/include/soc/aes_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -216,6 +216,19 @@ extern "C" {
 #define AES_MODE_V  0x00000007U
 #define AES_MODE_S  0
 
+/** AES_ENDIAN_REG register
+ *  AES Endian configure register
+ */
+#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
+/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
+ *  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out
+ *  endian or out_stream endian
+ */
+#define AES_ENDIAN    0x0000003FU
+#define AES_ENDIAN_M  (AES_ENDIAN_V << AES_ENDIAN_S)
+#define AES_ENDIAN_V  0x0000003FU
+#define AES_ENDIAN_S  0
+
 /** AES_TRIGGER_REG register
  *  AES trigger register
  */
@@ -314,6 +327,42 @@ extern "C" {
 #define AES_INC_SEL_V  0x00000001U
 #define AES_INC_SEL_S  0
 
+/** AES_AAD_BLOCK_NUM_REG register
+ *  Additional Authential Data block number register
+ */
+#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
+/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the number of AAD block.
+ */
+#define AES_AAD_BLOCK_NUM    0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_M  (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
+#define AES_AAD_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_S  0
+
+/** AES_REMAINDER_BIT_NUM_REG register
+ *  AES remainder bit number register
+ */
+#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
+/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
+ *  Those bits stores the number of remainder bit.
+ */
+#define AES_REMAINDER_BIT_NUM    0x0000007FU
+#define AES_REMAINDER_BIT_NUM_M  (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
+#define AES_REMAINDER_BIT_NUM_V  0x0000007FU
+#define AES_REMAINDER_BIT_NUM_S  0
+
+/** AES_CONTINUE_REG register
+ *  AES continue register
+ */
+#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
+/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to continue GCM operation.
+ */
+#define AES_CONTINUE    (BIT(0))
+#define AES_CONTINUE_M  (AES_CONTINUE_V << AES_CONTINUE_S)
+#define AES_CONTINUE_V  0x00000001U
+#define AES_CONTINUE_S  0
+
 /** AES_INT_CLEAR_REG register
  *  AES Interrupt clear register
  */

components/soc/esp32p4/include/soc/aes_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -240,6 +240,21 @@ typedef union {
     uint32_t val;
 } aes_mode_reg_t;
 
+/** Type of endian register
+ *  AES Endian configure register
+ */
+typedef union {
+    struct {
+        /** endian : R/W; bitpos: [5:0]; default: 0;
+         *  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out
+         *  endian or out_stream endian
+         */
+        uint32_t endian:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} aes_endian_reg_t;
+
 /** Type of block_mode register
  *  AES cipher block mode register
  */
@@ -282,6 +297,33 @@ typedef union {
     uint32_t val;
 } aes_inc_sel_reg_t;
 
+/** Type of aad_block_num register
+ *  Additional Authential Data block number register
+ */
+typedef union {
+    struct {
+        /** aad_block_num : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits stores the number of AAD block.
+         */
+        uint32_t aad_block_num:32;
+    };
+    uint32_t val;
+} aes_aad_block_num_reg_t;
+
+/** Type of remainder_bit_num register
+ *  AES remainder bit number register
+ */
+typedef union {
+    struct {
+        /** remainder_bit_num : R/W; bitpos: [6:0]; default: 0;
+         *  Those bits stores the number of remainder bit.
+         */
+        uint32_t remainder_bit_num:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} aes_remainder_bit_num_reg_t;
+
 
 /** Group: Control/Status register */
 /** Type of trigger register
@@ -327,6 +369,20 @@ typedef union {
     uint32_t val;
 } aes_dma_enable_reg_t;
 
+/** Type of continue register
+ *  AES continue register
+ */
+typedef union {
+    struct {
+        /** continue : WT; bitpos: [0]; default: 0;
+         *  Set this bit to continue GCM operation.
+         */
+        uint32_t continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_continue_reg_t;
+
 /** Type of dma_exit register
  *  AES-DMA exit config
  */
@@ -409,7 +465,7 @@ typedef struct {
     volatile aes_text_out_2_reg_t text_out_2;
     volatile aes_text_out_3_reg_t text_out_3;
     volatile aes_mode_reg_t mode;
-    uint32_t reserved_044;
+    volatile aes_endian_reg_t endian;
     volatile aes_trigger_reg_t trigger;
     volatile aes_state_reg_t state;
     volatile uint32_t iv[4];
@@ -420,7 +476,9 @@ typedef struct {
     volatile aes_block_mode_reg_t block_mode;
     volatile aes_block_num_reg_t block_num;
     volatile aes_inc_sel_reg_t inc_sel;
-    uint32_t reserved_0a0[3];
+    volatile aes_aad_block_num_reg_t aad_block_num;
+    volatile aes_remainder_bit_num_reg_t remainder_bit_num;
+    volatile aes_continue_reg_t continue;
     volatile aes_int_clear_reg_t int_clear;
     volatile aes_int_ena_reg_t int_ena;
     volatile aes_date_reg_t date;

components/soc/esp32p4/include/soc/soc_caps.h

@@ -95,6 +95,7 @@
 
 /*-------------------------- AES CAPS -----------------------------------------*/
 #define SOC_AES_SUPPORT_DMA     (1)
+#define SOC_AES_SUPPORT_GCM     (1)
 
 /* Has a centralized DMA, which is shared with all peripherals */
 #define SOC_AES_GDMA            (1)