diff --git a/components/hal/esp32c5/include/hal/assist_debug_ll.h b/components/hal/esp32c5/include/hal/assist_debug_ll.h index aa6d7eedb0..646a1ccbe8 100644 --- a/components/hal/esp32c5/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c5/include/hal/assist_debug_ll.h @@ -9,8 +9,11 @@ #pragma once #include "soc/assist_debug_reg.h" -#define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) -#define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_MONTR_ENA_REG +#define BUS_MONITOR_SP_SPILL_BITS (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA | BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA) +#define BUS_MONITOR_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONTR_ENA_REG +// Compatible alias +#define ASSIST_DEBUG_SP_SPILL_BITS BUS_MONITOR_SP_SPILL_BITS +#define ASSIST_DEBUG_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONITOR_REG #ifndef __ASSEMBLER__ @@ -60,57 +63,57 @@ extern "C" { FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { - REG_SET_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); + REG_SET_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { - REG_CLR_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); + REG_CLR_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { - REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); + REG_SET_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { - REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); + REG_CLR_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { - return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; + return REG_READ(BUS_MONITOR_CORE_0_INTR_RAW_REG) & BUS_MONITOR_SP_SPILL_BITS; } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { - REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); + REG_WRITE(BUS_MONITOR_CORE_0_INTR_CLR_REG, BUS_MONITOR_SP_SPILL_BITS); } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { - REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); + REG_WRITE(BUS_MONITOR_CORE_0_SP_MIN_REG, min); } FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { - return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); + return REG_READ(BUS_MONITOR_CORE_0_SP_MIN_REG); } FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { - REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); + REG_WRITE(BUS_MONITOR_CORE_0_SP_MAX_REG, max); } FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { - return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); + return REG_READ(BUS_MONITOR_CORE_0_SP_MAX_REG); } FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { - return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); + return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG); } FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable) diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index 60fdd0ab32..0101350403 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -561,7 +561,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { - buf[i] = hw->fifo.rxfifo_rd_byte; + buf[i] = hw->fifo.val; } } diff --git a/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h index 7608b92f9d..6cff591138 100644 --- a/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h @@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = USB_SERIAL_JTAG.ep1.val; } return i; } @@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + USB_SERIAL_JTAG.ep1.val = buf[i]; } return i; } diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..68d4ec7982 --- /dev/null +++ b/components/soc/esp32c5/include/soc/assist_debug_reg.h @@ -0,0 +1,21 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/bus_monitor_reg.h" + +// Compatible alias +#define DR_REG_ASSIST_DEBUG_BASE DR_REG_BUS_MONITOR_BASE + +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG BUS_MONITOR_CORE_0_DEBUG_MODE_REG +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE + +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG BUS_MONITOR_CORE_0_SP_MIN_REG +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG BUS_MONITOR_CORE_0_SP_MAX_REG + +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG BUS_MONITOR_CORE_0_RCD_EN_REG +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN BUS_MONITOR_CORE_0_RCD_PDEBUGEN +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN BUS_MONITOR_CORE_0_RCD_RECORDEN diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/include/soc/gpio_sig_map.h index 813f0a0515..2b595f9ac5 100644 --- a/components/soc/esp32c5/include/soc/gpio_sig_map.h +++ b/components/soc/esp32c5/include/soc/gpio_sig_map.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,6 +152,7 @@ #define PWM0_F2_IN_IDX 85 #define PWM0_OUT2B_IDX 85 #define PWM0_CAP0_IN_IDX 86 +#define PARL_TX_CS_O_IDX 86 #define PWM0_CAP1_IN_IDX 87 #define PWM0_CAP2_IN_IDX 88 #define GPIO_EVENT_MATRIX_IN0_IDX 89 @@ -165,6 +166,7 @@ #define CLK_OUT_OUT1_IDX 93 #define CLK_OUT_OUT2_IDX 94 #define CLK_OUT_OUT3_IDX 95 +#define SDIO_TOHOST_INT_OUT_IDX 96 #define SIG_IN_FUNC_97_IDX 97 #define SIG_IN_FUNC97_IDX 97 #define SIG_IN_FUNC_98_IDX 98 @@ -242,5 +244,5 @@ #define ANT_SEL13_IDX 151 #define ANT_SEL14_IDX 152 #define ANT_SEL15_IDX 153 -#define SIG_GPIO_OUT_IDX 256 // version date 2311280 +#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h index f98ff1c6cd..5581950d7c 100644 --- a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h +++ b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h @@ -1,67 +1,67 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define PMU_ICG_APB_ENA_CAN0 18 -#define PMU_ICG_APB_ENA_CAN1 19 -#define PMU_ICG_APB_ENA_GDMA 1 -#define PMU_ICG_APB_ENA_I2C 13 -#define PMU_ICG_APB_ENA_I2S 4 -#define PMU_ICG_APB_ENA_INTMTX 3 -#define PMU_ICG_APB_ENA_IOMUX 26 -#define PMU_ICG_APB_ENA_LEDC 14 -#define PMU_ICG_APB_ENA_MEM_MONITOR 25 -#define PMU_ICG_APB_ENA_MSPI 5 -#define PMU_ICG_APB_ENA_PARL 23 -#define PMU_ICG_APB_ENA_PCNT 20 -#define PMU_ICG_APB_ENA_PVT_MONITOR 27 -#define PMU_ICG_APB_ENA_PWM 21 -#define PMU_ICG_APB_ENA_REGDMA 24 -#define PMU_ICG_APB_ENA_RMT 15 -#define PMU_ICG_APB_ENA_SARADC 9 -#define PMU_ICG_APB_ENA_SEC 0 -#define PMU_ICG_APB_ENA_SOC_ETM 22 -#define PMU_ICG_APB_ENA_SPI2 2 -#define PMU_ICG_APB_ENA_SYSTIMER 16 -#define PMU_ICG_APB_ENA_TG0 11 -#define PMU_ICG_APB_ENA_TG1 12 -#define PMU_ICG_APB_ENA_UART0 6 -#define PMU_ICG_APB_ENA_UART1 7 -#define PMU_ICG_APB_ENA_UHCI 8 -#define PMU_ICG_APB_ENA_USB_DEVICE 17 -#define PMU_ICG_FUNC_ENA_CAN0 31 -#define PMU_ICG_FUNC_ENA_CAN1 30 -#define PMU_ICG_FUNC_ENA_I2C 29 -#define PMU_ICG_FUNC_ENA_I2S_RX 2 -#define PMU_ICG_FUNC_ENA_I2S_TX 7 -#define PMU_ICG_FUNC_ENA_IOMUX 28 -#define PMU_ICG_FUNC_ENA_LEDC 27 -#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 -#define PMU_ICG_FUNC_ENA_MSPI 26 -#define PMU_ICG_FUNC_ENA_PARL_RX 25 -#define PMU_ICG_FUNC_ENA_PARL_TX 24 -#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 -#define PMU_ICG_FUNC_ENA_PWM 22 -#define PMU_ICG_FUNC_ENA_RMT 21 -#define PMU_ICG_FUNC_ENA_SARADC 20 -#define PMU_ICG_FUNC_ENA_SEC 19 -#define PMU_ICG_FUNC_ENA_SPI2 1 -#define PMU_ICG_FUNC_ENA_SYSTIMER 18 -#define PMU_ICG_FUNC_ENA_TG0 14 -#define PMU_ICG_FUNC_ENA_TG1 13 -#define PMU_ICG_FUNC_ENA_TSENS 12 -#define PMU_ICG_FUNC_ENA_UART0 3 -#define PMU_ICG_FUNC_ENA_UART1 4 -#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 -#define PMU_ICG_FUNC_ENA_GDMA 0 -#define PMU_ICG_FUNC_ENA_SOC_ETM 16 -#define PMU_ICG_FUNC_ENA_REGDMA 8 -#define PMU_ICG_FUNC_ENA_RETENTION 9 -#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 -#define PMU_ICG_FUNC_ENA_UHCI 5 -#define PMU_ICG_FUNC_ENA_HPCORE 17 -#define PMU_ICG_FUNC_ENA_HPBUS 15 +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_APB_ENA_TWAI0 18 +#define PMU_ICG_APB_ENA_TWAI1 19 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_TWAI1 30 +#define PMU_ICG_FUNC_ENA_TWAI0 31 diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld index e1f8c4a005..220551516d 100644 --- a/components/soc/esp32c5/ld/esp32c5.peripherals.ld +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,6 +27,9 @@ PROVIDE ( PCNT = 0x60012000 ); PROVIDE ( SOC_ETM = 0x60013000 ); PROVIDE ( MCPWM0 = 0x60014000 ); PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( HINF = 0x60016000 ); +PROVIDE ( SLC = 0x60017000 ); +PROVIDE ( HOST = 0x60018000 ); PROVIDE ( PVT_MONITOR = 0x60019000 ); PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); PROVIDE ( AHB_DMA = 0x60080000 ); @@ -53,6 +56,7 @@ PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); PROVIDE ( LP_APM0 = 0x60099800 ); +PROVIDE ( CPU_APM = 0x6009A000 ); PROVIDE ( MISC = 0x6009F000 ); PROVIDE ( IEEE802154 = 0x600A3000 ); /* TODO: [ESP32C5] IDF-9140 Check the address */ @@ -82,6 +86,6 @@ PROVIDE ( LP_GPIO = 0x600B4400 ); PROVIDE ( EFUSE = 0x600B4800 ); PROVIDE ( OTP_DEBUG = 0x600B4D00 ); PROVIDE ( TRACE = 0x600C0000 ); -PROVIDE ( ASSIST_DEBUG = 0x600C2000 ); +PROVIDE ( BUS_MONITOR = 0x600C2000 ); PROVIDE ( INTPRI = 0x600C5000 ); PROVIDE ( CACHE = 0x600C8000 ); diff --git a/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h b/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h new file mode 100644 index 0000000000..3a48a96c91 --- /dev/null +++ b/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h @@ -0,0 +1,3977 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AHB_DMA_IN_INT_RAW_CH0_REG register + * Raw interrupt status of RX channel 0 + */ +#define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) +/** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT + */ +#define AHB_DMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define AHB_DMA_IN_DONE_CH0_INT_RAW_M (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S) +#define AHB_DMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DONE_CH0_INT_RAW_S 0 +/** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + */ +#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S) +#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + */ +#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S) +#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S 7 + +/** AHB_DMA_IN_INT_ST_CH0_REG register + * Masked interrupt status of RX channel 0 + */ +#define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) +/** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT + */ +#define AHB_DMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define AHB_DMA_IN_DONE_CH0_INT_ST_M (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S) +#define AHB_DMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DONE_CH0_INT_ST_S 0 +/** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + */ +#define AHB_DMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S) +#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + */ +#define AHB_DMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S) +#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S 7 + +/** AHB_DMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of RX channel 0 + */ +#define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) +/** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT + */ +#define AHB_DMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define AHB_DMA_IN_DONE_CH0_INT_ENA_M (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S) +#define AHB_DMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DONE_CH0_INT_ENA_S 0 +/** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT + */ +#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S) +#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT + */ +#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S) +#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S 7 + +/** AHB_DMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of RX channel 0 + */ +#define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) +/** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT + */ +#define AHB_DMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define AHB_DMA_IN_DONE_CH0_INT_CLR_M (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S) +#define AHB_DMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DONE_CH0_INT_CLR_S 0 +/** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT + */ +#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S) +#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT + */ +#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S) +#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S 7 + +/** AHB_DMA_IN_INT_RAW_CH1_REG register + * Raw interrupt status of RX channel 1 + */ +#define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) +/** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT + */ +#define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) +#define AHB_DMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 +/** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + */ +#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S) +#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + */ +#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S) +#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S 7 + +/** AHB_DMA_IN_INT_ST_CH1_REG register + * Masked interrupt status of RX channel 1 + */ +#define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) +/** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT + */ +#define AHB_DMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define AHB_DMA_IN_DONE_CH1_INT_ST_M (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S) +#define AHB_DMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DONE_CH1_INT_ST_S 0 +/** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + */ +#define AHB_DMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S) +#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + */ +#define AHB_DMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S) +#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S 7 + +/** AHB_DMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of RX channel 1 + */ +#define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) +/** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT + */ +#define AHB_DMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define AHB_DMA_IN_DONE_CH1_INT_ENA_M (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S) +#define AHB_DMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DONE_CH1_INT_ENA_S 0 +/** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT + */ +#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S) +#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT + */ +#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S) +#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S 7 + +/** AHB_DMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of RX channel 1 + */ +#define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) +/** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT + */ +#define AHB_DMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define AHB_DMA_IN_DONE_CH1_INT_CLR_M (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S) +#define AHB_DMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DONE_CH1_INT_CLR_S 0 +/** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT + */ +#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S) +#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT + */ +#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S) +#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S 7 + +/** AHB_DMA_IN_INT_RAW_CH2_REG register + * Raw interrupt status of RX channel 2 + */ +#define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20) +/** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT + */ +#define AHB_DMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define AHB_DMA_IN_DONE_CH2_INT_RAW_M (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S) +#define AHB_DMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DONE_CH2_INT_RAW_S 0 +/** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT + */ +#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S) +#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT + */ +#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S) +#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S 7 + +/** AHB_DMA_IN_INT_ST_CH2_REG register + * Masked interrupt status of RX channel 2 + */ +#define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24) +/** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT + */ +#define AHB_DMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define AHB_DMA_IN_DONE_CH2_INT_ST_M (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S) +#define AHB_DMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DONE_CH2_INT_ST_S 0 +/** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT + */ +#define AHB_DMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S) +#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT + */ +#define AHB_DMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S) +#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S 7 + +/** AHB_DMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of RX channel 2 + */ +#define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28) +/** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT + */ +#define AHB_DMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define AHB_DMA_IN_DONE_CH2_INT_ENA_M (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S) +#define AHB_DMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DONE_CH2_INT_ENA_S 0 +/** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT + */ +#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S) +#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT + */ +#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S) +#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S 7 + +/** AHB_DMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of RX channel 2 + */ +#define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c) +/** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT + */ +#define AHB_DMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define AHB_DMA_IN_DONE_CH2_INT_CLR_M (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S) +#define AHB_DMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DONE_CH2_INT_CLR_S 0 +/** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT + */ +#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT + */ +#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT + */ +#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S) +#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT + */ +#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S) +#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S 7 + +/** AHB_DMA_OUT_INT_RAW_CH0_REG register + * //Raw interrupt status of TX channel 0 + */ +#define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) +/** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT + */ +#define AHB_DMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define AHB_DMA_OUT_DONE_CH0_INT_RAW_M (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S) +#define AHB_DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH0_INT_RAW_S 0 +/** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT + */ +#define AHB_DMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define AHB_DMA_OUT_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S) +#define AHB_DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH0_INT_RAW_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S 6 + +/** AHB_DMA_OUT_INT_ST_CH0_REG register + * Masked interrupt status of TX channel 0 + */ +#define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) +/** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT + */ +#define AHB_DMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define AHB_DMA_OUT_DONE_CH0_INT_ST_M (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S) +#define AHB_DMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH0_INT_ST_S 0 +/** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT + */ +#define AHB_DMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define AHB_DMA_OUT_EOF_CH0_INT_ST_M (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S) +#define AHB_DMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH0_INT_ST_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S 6 + +/** AHB_DMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of TX channel 0 + */ +#define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) +/** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT + */ +#define AHB_DMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define AHB_DMA_OUT_DONE_CH0_INT_ENA_M (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S) +#define AHB_DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH0_INT_ENA_S 0 +/** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT + */ +#define AHB_DMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define AHB_DMA_OUT_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S) +#define AHB_DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH0_INT_ENA_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S 6 + +/** AHB_DMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of TX channel 0 + */ +#define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) +/** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT + */ +#define AHB_DMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define AHB_DMA_OUT_DONE_CH0_INT_CLR_M (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S) +#define AHB_DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH0_INT_CLR_S 0 +/** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT + */ +#define AHB_DMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define AHB_DMA_OUT_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S) +#define AHB_DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH0_INT_CLR_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S 6 + +/** AHB_DMA_OUT_INT_RAW_CH1_REG register + * //Raw interrupt status of TX channel 1 + */ +#define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) +/** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT + */ +#define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) +#define AHB_DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 +/** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT + */ +#define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) +#define AHB_DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH1_INT_RAW_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S 6 + +/** AHB_DMA_OUT_INT_ST_CH1_REG register + * Masked interrupt status of TX channel 1 + */ +#define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) +/** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT + */ +#define AHB_DMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define AHB_DMA_OUT_DONE_CH1_INT_ST_M (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S) +#define AHB_DMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH1_INT_ST_S 0 +/** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT + */ +#define AHB_DMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define AHB_DMA_OUT_EOF_CH1_INT_ST_M (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S) +#define AHB_DMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH1_INT_ST_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S 6 + +/** AHB_DMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of TX channel 1 + */ +#define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) +/** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT + */ +#define AHB_DMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define AHB_DMA_OUT_DONE_CH1_INT_ENA_M (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S) +#define AHB_DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH1_INT_ENA_S 0 +/** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT + */ +#define AHB_DMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define AHB_DMA_OUT_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S) +#define AHB_DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH1_INT_ENA_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S 6 + +/** AHB_DMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of TX channel 1 + */ +#define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) +/** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT + */ +#define AHB_DMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define AHB_DMA_OUT_DONE_CH1_INT_CLR_M (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S) +#define AHB_DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH1_INT_CLR_S 0 +/** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT + */ +#define AHB_DMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define AHB_DMA_OUT_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S) +#define AHB_DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH1_INT_CLR_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S 6 + +/** AHB_DMA_OUT_INT_RAW_CH2_REG register + * //Raw interrupt status of TX channel 2 + */ +#define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50) +/** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT + */ +#define AHB_DMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define AHB_DMA_OUT_DONE_CH2_INT_RAW_M (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S) +#define AHB_DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH2_INT_RAW_S 0 +/** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT + */ +#define AHB_DMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define AHB_DMA_OUT_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S) +#define AHB_DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH2_INT_RAW_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S 6 + +/** AHB_DMA_OUT_INT_ST_CH2_REG register + * Masked interrupt status of TX channel 2 + */ +#define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54) +/** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT + */ +#define AHB_DMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define AHB_DMA_OUT_DONE_CH2_INT_ST_M (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S) +#define AHB_DMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH2_INT_ST_S 0 +/** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT + */ +#define AHB_DMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define AHB_DMA_OUT_EOF_CH2_INT_ST_M (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S) +#define AHB_DMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH2_INT_ST_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S 6 + +/** AHB_DMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of TX channel 2 + */ +#define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58) +/** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT + */ +#define AHB_DMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define AHB_DMA_OUT_DONE_CH2_INT_ENA_M (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S) +#define AHB_DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH2_INT_ENA_S 0 +/** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT + */ +#define AHB_DMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define AHB_DMA_OUT_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S) +#define AHB_DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH2_INT_ENA_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S 6 + +/** AHB_DMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of TX channel 2 + */ +#define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c) +/** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT + */ +#define AHB_DMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define AHB_DMA_OUT_DONE_CH2_INT_CLR_M (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S) +#define AHB_DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DONE_CH2_INT_CLR_S 0 +/** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT + */ +#define AHB_DMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define AHB_DMA_OUT_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S) +#define AHB_DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_EOF_CH2_INT_CLR_S 1 +/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT + */ +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S 6 + +/** AHB_DMA_AHB_TEST_REG register + * only for test + */ +#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) +/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define AHB_DMA_AHB_TESTMODE 0x00000007U +#define AHB_DMA_AHB_TESTMODE_M (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S) +#define AHB_DMA_AHB_TESTMODE_V 0x00000007U +#define AHB_DMA_AHB_TESTMODE_S 0 +/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define AHB_DMA_AHB_TESTADDR 0x00000003U +#define AHB_DMA_AHB_TESTADDR_M (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S) +#define AHB_DMA_AHB_TESTADDR_V 0x00000003U +#define AHB_DMA_AHB_TESTADDR_S 4 + +/** AHB_DMA_MISC_CONF_REG register + * reserved + */ +#define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64) +/** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset the internal AHB FSM + */ +#define AHB_DMA_AHBM_RST_INTER (BIT(0)) +#define AHB_DMA_AHBM_RST_INTER_M (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S) +#define AHB_DMA_AHBM_RST_INTER_V 0x00000001U +#define AHB_DMA_AHBM_RST_INTER_S 0 +/** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Configures whether to disable the fixed-priority channel arbitration. + * 0: Enable + * 1: Disable + */ +#define AHB_DMA_ARB_PRI_DIS (BIT(2)) +#define AHB_DMA_ARB_PRI_DIS_M (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S) +#define AHB_DMA_ARB_PRI_DIS_V 0x00000001U +#define AHB_DMA_ARB_PRI_DIS_S 2 +/** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. + */ +#define AHB_DMA_CLK_EN (BIT(3)) +#define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) +#define AHB_DMA_CLK_EN_V 0x00000001U +#define AHB_DMA_CLK_EN_S 3 + +/** AHB_DMA_DATE_REG register + * Version control register + */ +#define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68) +/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2410220; + * Version control register + */ +#define AHB_DMA_DATE 0xFFFFFFFFU +#define AHB_DMA_DATE_M (AHB_DMA_DATE_V << AHB_DMA_DATE_S) +#define AHB_DMA_DATE_V 0xFFFFFFFFU +#define AHB_DMA_DATE_S 0 + +/** AHB_DMA_IN_CONF0_CH0_REG register + * Configuration register 0 of RX channel 0 + */ +#define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70) +/** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + */ +#define AHB_DMA_IN_RST_CH0 (BIT(0)) +#define AHB_DMA_IN_RST_CH0_M (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S) +#define AHB_DMA_IN_RST_CH0_V 0x00000001U +#define AHB_DMA_IN_RST_CH0_S 0 +/** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) +#define AHB_DMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define AHB_DMA_IN_LOOP_TEST_CH0_S 1 +/** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 0 to read + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define AHB_DMA_INDSCR_BURST_EN_CH0_M (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S) +#define AHB_DMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define AHB_DMA_INDSCR_BURST_EN_CH0_S 2 +/** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define AHB_DMA_MEM_TRANS_EN_CH0_M (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S) +#define AHB_DMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define AHB_DMA_MEM_TRANS_EN_CH0_S 4 +/** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel0. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_ETM_EN_CH0 (BIT(5)) +#define AHB_DMA_IN_ETM_EN_CH0_M (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S) +#define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U +#define AHB_DMA_IN_ETM_EN_CH0_S 5 +/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S 6 + +/** AHB_DMA_IN_CONF1_CH0_REG register + * Configuration register 1 of RX channel 0 + */ +#define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74) +/** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 0. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define AHB_DMA_IN_CHECK_OWNER_CH0_M (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S) +#define AHB_DMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define AHB_DMA_IN_CHECK_OWNER_CH0_S 12 + +/** AHB_DMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of RX channel 0 + */ +#define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) +/** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_INFIFO_FULL_CH0 (BIT(0)) +#define AHB_DMA_INFIFO_FULL_CH0_M (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S) +#define AHB_DMA_INFIFO_FULL_CH0_V 0x00000001U +#define AHB_DMA_INFIFO_FULL_CH0_S 0 +/** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define AHB_DMA_INFIFO_EMPTY_CH0_M (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S) +#define AHB_DMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define AHB_DMA_INFIFO_EMPTY_CH0_S 1 +/** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 0 + */ +#define AHB_DMA_INFIFO_CNT_CH0 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH0_M (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S) +#define AHB_DMA_INFIFO_CNT_CH0_V 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH0_S 8 +/** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define AHB_DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define AHB_DMA_IN_BUF_HUNGRY_CH0_M (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S) +#define AHB_DMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define AHB_DMA_IN_BUF_HUNGRY_CH0_S 27 + +/** AHB_DMA_IN_POP_CH0_REG register + * Receive FIFO status of RX channel 0 + */ +#define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) +/** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ +#define AHB_DMA_INFIFO_RDATA_CH0 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH0_M (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S) +#define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH0_S 0 +/** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ +#define AHB_DMA_INFIFO_POP_CH0 (BIT(12)) +#define AHB_DMA_INFIFO_POP_CH0_M (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S) +#define AHB_DMA_INFIFO_POP_CH0_V 0x00000001U +#define AHB_DMA_INFIFO_POP_CH0_S 12 + +/** AHB_DMA_IN_LINK_CH0_REG register + * Receive FIFO status of RX channel 0 + */ +#define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) +/** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ +#define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) +#define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) +#define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 +/** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_INLINK_STOP_CH0 (BIT(1)) +#define AHB_DMA_INLINK_STOP_CH0_M (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S) +#define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U +#define AHB_DMA_INLINK_STOP_CH0_S 1 +/** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INLINK_START_CH0 (BIT(2)) +#define AHB_DMA_INLINK_START_CH0_M (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S) +#define AHB_DMA_INLINK_START_CH0_V 0x00000001U +#define AHB_DMA_INLINK_START_CH0_S 2 +/** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_INLINK_RESTART_CH0 (BIT(3)) +#define AHB_DMA_INLINK_RESTART_CH0_M (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S) +#define AHB_DMA_INLINK_RESTART_CH0_V 0x00000001U +#define AHB_DMA_INLINK_RESTART_CH0_S 3 +/** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_INLINK_PARK_CH0 (BIT(4)) +#define AHB_DMA_INLINK_PARK_CH0_M (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S) +#define AHB_DMA_INLINK_PARK_CH0_V 0x00000001U +#define AHB_DMA_INLINK_PARK_CH0_S 4 + +/** AHB_DMA_IN_STATE_CH0_REG register + * Receive status of RX channel 0 + */ +#define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) +/** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * reserved + */ +#define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) +#define AHB_DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH0_S 0 +/** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_IN_DSCR_STATE_CH0 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH0_M (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S) +#define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH0_S 18 +/** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ +#define AHB_DMA_IN_STATE_CH0 0x00000007U +#define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) +#define AHB_DMA_IN_STATE_CH0_V 0x00000007U +#define AHB_DMA_IN_STATE_CH0_S 20 + +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x88) +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Receive descriptor address when errors occur of RX channel 0 + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8c) +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** AHB_DMA_IN_DSCR_CH0_REG register + * Current receive descriptor address of RX channel 0 + */ +#define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90) +/** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ +#define AHB_DMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH0_M (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S) +#define AHB_DMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH0_S 0 + +/** AHB_DMA_IN_DSCR_BF0_CH0_REG register + * The last receive descriptor address of RX channel 0 + */ +#define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94) +/** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH0_M (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S) +#define AHB_DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH0_S 0 + +/** AHB_DMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last receive descriptor address of RX channel 0 + */ +#define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98) +/** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH0_M (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S) +#define AHB_DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH0_S 0 + +/** AHB_DMA_IN_PERI_CH0_REG register + * Priority register of RX channel 0 + */ +#define AHB_DMA_IN_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) +/** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 0.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_RX_PRI_CH0 0x0000000FU +#define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) +#define AHB_DMA_RX_PRI_CH0_V 0x0000000FU +#define AHB_DMA_RX_PRI_CH0_S 0 + +/** AHB_DMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection register of RX channel 0 + */ +#define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0) +/** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ +#define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) +#define AHB_DMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH0_S 0 + +/** AHB_DMA_OUT_CONF0_CH0_REG register + * Configuration register 0 of TX channel 0 + */ +#define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) +/** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ +#define AHB_DMA_OUT_RST_CH0 (BIT(0)) +#define AHB_DMA_OUT_RST_CH0_M (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S) +#define AHB_DMA_OUT_RST_CH0_V 0x00000001U +#define AHB_DMA_OUT_RST_CH0_S 0 +/** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) +#define AHB_DMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define AHB_DMA_OUT_LOOP_TEST_CH0_S 1 +/** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define AHB_DMA_OUT_AUTO_WRBACK_CH0_M (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S) +#define AHB_DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define AHB_DMA_OUT_AUTO_WRBACK_CH0_S 2 +/** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ +#define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) +#define AHB_DMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define AHB_DMA_OUT_EOF_MODE_CH0_S 3 +/** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 0 reading + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define AHB_DMA_OUTDSCR_BURST_EN_CH0_M (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S) +#define AHB_DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define AHB_DMA_OUTDSCR_BURST_EN_CH0_S 4 +/** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 0. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_ETM_EN_CH0 (BIT(6)) +#define AHB_DMA_OUT_ETM_EN_CH0_M (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S) +#define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U +#define AHB_DMA_OUT_ETM_EN_CH0_S 6 +/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S 8 + +/** AHB_DMA_OUT_CONF1_CH0_REG register + * Configuration register 1 of TX channel 0 + */ +#define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4) +/** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 0. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define AHB_DMA_OUT_CHECK_OWNER_CH0_M (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S) +#define AHB_DMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 + +/** AHB_DMA_OUTFIFO_STATUS_CH0_REG register + * Receive FIFO status of RX channel 0 + */ +#define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) +/** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define AHB_DMA_OUTFIFO_FULL_CH0_M (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S) +#define AHB_DMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define AHB_DMA_OUTFIFO_FULL_CH0_S 0 +/** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define AHB_DMA_OUTFIFO_EMPTY_CH0_M (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S) +#define AHB_DMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define AHB_DMA_OUTFIFO_EMPTY_CH0_S 1 +/** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 0 + */ +#define AHB_DMA_OUTFIFO_CNT_CH0 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH0_M (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S) +#define AHB_DMA_OUTFIFO_CNT_CH0_V 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH0_S 8 +/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** AHB_DMA_OUT_PUSH_CH0_REG register + * Push control register of TX channel 0 + */ +#define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) +/** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ +#define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) +#define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 +/** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ +#define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) +#define AHB_DMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define AHB_DMA_OUTFIFO_PUSH_CH0_S 9 + +/** AHB_DMA_OUT_LINK_CH0_REG register + * Push control register of TX channel 0 + */ +#define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) +/** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_OUTLINK_STOP_CH0 (BIT(0)) +#define AHB_DMA_OUTLINK_STOP_CH0_M (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S) +#define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U +#define AHB_DMA_OUTLINK_STOP_CH0_S 0 +/** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTLINK_START_CH0 (BIT(1)) +#define AHB_DMA_OUTLINK_START_CH0_M (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S) +#define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U +#define AHB_DMA_OUTLINK_START_CH0_S 1 +/** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_OUTLINK_RESTART_CH0 (BIT(2)) +#define AHB_DMA_OUTLINK_RESTART_CH0_M (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S) +#define AHB_DMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define AHB_DMA_OUTLINK_RESTART_CH0_S 2 +/** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_OUTLINK_PARK_CH0 (BIT(3)) +#define AHB_DMA_OUTLINK_PARK_CH0_M (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S) +#define AHB_DMA_OUTLINK_PARK_CH0_V 0x00000001U +#define AHB_DMA_OUTLINK_PARK_CH0_S 3 + +/** AHB_DMA_OUT_STATE_CH0_REG register + * Transmit status of TX channel 0 + */ +#define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4) +/** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S) +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_DSCR_STATE_CH0 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH0_M (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S) +#define AHB_DMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH0_S 18 +/** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_STATE_CH0 0x00000007U +#define AHB_DMA_OUT_STATE_CH0_M (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S) +#define AHB_DMA_OUT_STATE_CH0_V 0x00000007U +#define AHB_DMA_OUT_STATE_CH0_S 20 + +/** AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe8) +/** AHB_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_M (AHB_DMA_OUT_EOF_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_DES_ADDR_CH0_S) +#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xec) +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** AHB_DMA_OUT_DSCR_CH0_REG register + * Current transmit descriptor address of TX channel 0 + */ +#define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0) +/** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH0_M (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S) +#define AHB_DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH0_S 0 + +/** AHB_DMA_OUT_DSCR_BF0_CH0_REG register + * The last transmit descriptor address of TX channel 0 + */ +#define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4) +/** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S) +#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** AHB_DMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last transmit descriptor address of TX channel 0 + */ +#define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8) +/** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S) +#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** AHB_DMA_OUT_PERI_CH0_REG register + * Priority register of TX channel 0 + */ +#define AHB_DMA_OUT_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) +/** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 0.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_TX_PRI_CH0 0x0000000FU +#define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) +#define AHB_DMA_TX_PRI_CH0_V 0x0000000FU +#define AHB_DMA_TX_PRI_CH0_S 0 + +/** AHB_DMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection register of TX channel 0 + */ +#define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100) +/** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ +#define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) +#define AHB_DMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH0_S 0 + +/** AHB_DMA_IN_CONF0_CH1_REG register + * Configuration register 0 of RX channel 1 + */ +#define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) +/** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. + */ +#define AHB_DMA_IN_RST_CH1 (BIT(0)) +#define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) +#define AHB_DMA_IN_RST_CH1_V 0x00000001U +#define AHB_DMA_IN_RST_CH1_S 0 +/** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) +#define AHB_DMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define AHB_DMA_IN_LOOP_TEST_CH1_S 1 +/** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 1 to read + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define AHB_DMA_INDSCR_BURST_EN_CH1_M (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S) +#define AHB_DMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define AHB_DMA_INDSCR_BURST_EN_CH1_S 2 +/** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define AHB_DMA_MEM_TRANS_EN_CH1_M (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S) +#define AHB_DMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define AHB_DMA_MEM_TRANS_EN_CH1_S 4 +/** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel1. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_ETM_EN_CH1 (BIT(5)) +#define AHB_DMA_IN_ETM_EN_CH1_M (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S) +#define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U +#define AHB_DMA_IN_ETM_EN_CH1_S 5 +/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S 6 + +/** AHB_DMA_IN_CONF1_CH1_REG register + * Configuration register 1 of RX channel 1 + */ +#define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134) +/** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 1. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define AHB_DMA_IN_CHECK_OWNER_CH1_M (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S) +#define AHB_DMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 + +/** AHB_DMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of RX channel 1 + */ +#define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) +/** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_INFIFO_FULL_CH1 (BIT(0)) +#define AHB_DMA_INFIFO_FULL_CH1_M (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S) +#define AHB_DMA_INFIFO_FULL_CH1_V 0x00000001U +#define AHB_DMA_INFIFO_FULL_CH1_S 0 +/** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define AHB_DMA_INFIFO_EMPTY_CH1_M (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S) +#define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define AHB_DMA_INFIFO_EMPTY_CH1_S 1 +/** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 1 + */ +#define AHB_DMA_INFIFO_CNT_CH1 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) +#define AHB_DMA_INFIFO_CNT_CH1_V 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH1_S 8 +/** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define AHB_DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define AHB_DMA_IN_BUF_HUNGRY_CH1_M (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S) +#define AHB_DMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 + +/** AHB_DMA_IN_POP_CH1_REG register + * Receive FIFO status of RX channel 1 + */ +#define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) +/** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ +#define AHB_DMA_INFIFO_RDATA_CH1 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH1_M (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S) +#define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH1_S 0 +/** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ +#define AHB_DMA_INFIFO_POP_CH1 (BIT(12)) +#define AHB_DMA_INFIFO_POP_CH1_M (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S) +#define AHB_DMA_INFIFO_POP_CH1_V 0x00000001U +#define AHB_DMA_INFIFO_POP_CH1_S 12 + +/** AHB_DMA_IN_LINK_CH1_REG register + * Receive FIFO status of RX channel 1 + */ +#define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) +/** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ +#define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) +#define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) +#define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 +/** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_INLINK_STOP_CH1 (BIT(1)) +#define AHB_DMA_INLINK_STOP_CH1_M (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S) +#define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U +#define AHB_DMA_INLINK_STOP_CH1_S 1 +/** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INLINK_START_CH1 (BIT(2)) +#define AHB_DMA_INLINK_START_CH1_M (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S) +#define AHB_DMA_INLINK_START_CH1_V 0x00000001U +#define AHB_DMA_INLINK_START_CH1_S 2 +/** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_INLINK_RESTART_CH1 (BIT(3)) +#define AHB_DMA_INLINK_RESTART_CH1_M (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S) +#define AHB_DMA_INLINK_RESTART_CH1_V 0x00000001U +#define AHB_DMA_INLINK_RESTART_CH1_S 3 +/** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_INLINK_PARK_CH1 (BIT(4)) +#define AHB_DMA_INLINK_PARK_CH1_M (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S) +#define AHB_DMA_INLINK_PARK_CH1_V 0x00000001U +#define AHB_DMA_INLINK_PARK_CH1_S 4 + +/** AHB_DMA_IN_STATE_CH1_REG register + * Receive status of RX channel 1 + */ +#define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) +/** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * reserved + */ +#define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) +#define AHB_DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH1_S 0 +/** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_IN_DSCR_STATE_CH1 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH1_M (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S) +#define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH1_S 18 +/** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ +#define AHB_DMA_IN_STATE_CH1 0x00000007U +#define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) +#define AHB_DMA_IN_STATE_CH1_V 0x00000007U +#define AHB_DMA_IN_STATE_CH1_S 20 + +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Receive descriptor address when EOF occurs on RX channel 1 + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148) +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Receive descriptor address when errors occur of RX channel 1 + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** AHB_DMA_IN_DSCR_CH1_REG register + * Current receive descriptor address of RX channel 1 + */ +#define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) +/** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ +#define AHB_DMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH1_M (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S) +#define AHB_DMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH1_S 0 + +/** AHB_DMA_IN_DSCR_BF0_CH1_REG register + * The last receive descriptor address of RX channel 1 + */ +#define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) +/** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH1_M (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S) +#define AHB_DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 + +/** AHB_DMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last receive descriptor address of RX channel 1 + */ +#define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) +/** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH1_M (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S) +#define AHB_DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 + +/** AHB_DMA_IN_PERI_CH1_REG register + * Priority register of RX channel 1 + */ +#define AHB_DMA_IN_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) +/** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 1.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_RX_PRI_CH1 0x0000000FU +#define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) +#define AHB_DMA_RX_PRI_CH1_V 0x0000000FU +#define AHB_DMA_RX_PRI_CH1_S 0 + +/** AHB_DMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection register of RX channel 1 + */ +#define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160) +/** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ +#define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) +#define AHB_DMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH1_S 0 + +/** AHB_DMA_OUT_CONF0_CH1_REG register + * Configuration register 0 of TX channel 1 + */ +#define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) +/** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ +#define AHB_DMA_OUT_RST_CH1 (BIT(0)) +#define AHB_DMA_OUT_RST_CH1_M (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S) +#define AHB_DMA_OUT_RST_CH1_V 0x00000001U +#define AHB_DMA_OUT_RST_CH1_S 0 +/** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) +#define AHB_DMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define AHB_DMA_OUT_LOOP_TEST_CH1_S 1 +/** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define AHB_DMA_OUT_AUTO_WRBACK_CH1_M (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S) +#define AHB_DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define AHB_DMA_OUT_AUTO_WRBACK_CH1_S 2 +/** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ +#define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) +#define AHB_DMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define AHB_DMA_OUT_EOF_MODE_CH1_S 3 +/** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 1 reading + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define AHB_DMA_OUTDSCR_BURST_EN_CH1_M (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S) +#define AHB_DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define AHB_DMA_OUTDSCR_BURST_EN_CH1_S 4 +/** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 1. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_ETM_EN_CH1 (BIT(6)) +#define AHB_DMA_OUT_ETM_EN_CH1_M (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S) +#define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U +#define AHB_DMA_OUT_ETM_EN_CH1_S 6 +/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S 8 + +/** AHB_DMA_OUT_CONF1_CH1_REG register + * Configuration register 1 of TX channel 1 + */ +#define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194) +/** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 1. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define AHB_DMA_OUT_CHECK_OWNER_CH1_M (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S) +#define AHB_DMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 + +/** AHB_DMA_OUTFIFO_STATUS_CH1_REG register + * Receive FIFO status of RX channel 1 + */ +#define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) +/** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define AHB_DMA_OUTFIFO_FULL_CH1_M (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S) +#define AHB_DMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define AHB_DMA_OUTFIFO_FULL_CH1_S 0 +/** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define AHB_DMA_OUTFIFO_EMPTY_CH1_M (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S) +#define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 +/** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 1 + */ +#define AHB_DMA_OUTFIFO_CNT_CH1 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) +#define AHB_DMA_OUTFIFO_CNT_CH1_V 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH1_S 8 +/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** AHB_DMA_OUT_PUSH_CH1_REG register + * Push control register of TX channel 1 + */ +#define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) +/** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ +#define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) +#define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 +/** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ +#define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) +#define AHB_DMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 + +/** AHB_DMA_OUT_LINK_CH1_REG register + * Push control register of TX channel 1 + */ +#define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) +/** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_OUTLINK_STOP_CH1 (BIT(0)) +#define AHB_DMA_OUTLINK_STOP_CH1_M (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S) +#define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U +#define AHB_DMA_OUTLINK_STOP_CH1_S 0 +/** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTLINK_START_CH1 (BIT(1)) +#define AHB_DMA_OUTLINK_START_CH1_M (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S) +#define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U +#define AHB_DMA_OUTLINK_START_CH1_S 1 +/** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_OUTLINK_RESTART_CH1 (BIT(2)) +#define AHB_DMA_OUTLINK_RESTART_CH1_M (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S) +#define AHB_DMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define AHB_DMA_OUTLINK_RESTART_CH1_S 2 +/** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_OUTLINK_PARK_CH1 (BIT(3)) +#define AHB_DMA_OUTLINK_PARK_CH1_M (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S) +#define AHB_DMA_OUTLINK_PARK_CH1_V 0x00000001U +#define AHB_DMA_OUTLINK_PARK_CH1_S 3 + +/** AHB_DMA_OUT_STATE_CH1_REG register + * Transmit status of TX channel 1 + */ +#define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) +/** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S) +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_DSCR_STATE_CH1 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH1_M (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S) +#define AHB_DMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH1_S 18 +/** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_STATE_CH1 0x00000007U +#define AHB_DMA_OUT_STATE_CH1_M (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S) +#define AHB_DMA_OUT_STATE_CH1_V 0x00000007U +#define AHB_DMA_OUT_STATE_CH1_S 20 + +/** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register + * Transmit descriptor address when EOF occurs on TX channel 1 + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8) +/** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_M (AHB_DMA_OUT_EOF_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_DES_ADDR_CH1_S) +#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last transmit descriptor address when EOF occurs on TX channel 1 + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac) +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** AHB_DMA_OUT_DSCR_CH1_REG register + * Current transmit descriptor address of TX channel 1 + */ +#define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) +/** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH1_M (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S) +#define AHB_DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH1_S 0 + +/** AHB_DMA_OUT_DSCR_BF0_CH1_REG register + * The last transmit descriptor address of TX channel 1 + */ +#define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) +/** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S) +#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** AHB_DMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last transmit descriptor address of TX channel 1 + */ +#define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) +/** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S) +#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** AHB_DMA_OUT_PERI_CH1_REG register + * Priority register of TX channel 1 + */ +#define AHB_DMA_OUT_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) +/** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 1.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_TX_PRI_CH1 0x0000000FU +#define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) +#define AHB_DMA_TX_PRI_CH1_V 0x0000000FU +#define AHB_DMA_TX_PRI_CH1_S 0 + +/** AHB_DMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection register of TX channel 1 + */ +#define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0) +/** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ +#define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) +#define AHB_DMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH1_S 0 + +/** AHB_DMA_IN_CONF0_CH2_REG register + * Configuration register 0 of RX channel 2 + */ +#define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0) +/** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. + */ +#define AHB_DMA_IN_RST_CH2 (BIT(0)) +#define AHB_DMA_IN_RST_CH2_M (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S) +#define AHB_DMA_IN_RST_CH2_V 0x00000001U +#define AHB_DMA_IN_RST_CH2_S 0 +/** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define AHB_DMA_IN_LOOP_TEST_CH2_M (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S) +#define AHB_DMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define AHB_DMA_IN_LOOP_TEST_CH2_S 1 +/** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 2 to read + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define AHB_DMA_INDSCR_BURST_EN_CH2_M (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S) +#define AHB_DMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define AHB_DMA_INDSCR_BURST_EN_CH2_S 2 +/** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define AHB_DMA_MEM_TRANS_EN_CH2_M (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S) +#define AHB_DMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define AHB_DMA_MEM_TRANS_EN_CH2_S 4 +/** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel2. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_ETM_EN_CH2 (BIT(5)) +#define AHB_DMA_IN_ETM_EN_CH2_M (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S) +#define AHB_DMA_IN_ETM_EN_CH2_V 0x00000001U +#define AHB_DMA_IN_ETM_EN_CH2_S 5 +/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S) +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V 0x00000003U +#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S 6 + +/** AHB_DMA_IN_CONF1_CH2_REG register + * Configuration register 1 of RX channel 2 + */ +#define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4) +/** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 2. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define AHB_DMA_IN_CHECK_OWNER_CH2_M (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S) +#define AHB_DMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define AHB_DMA_IN_CHECK_OWNER_CH2_S 12 + +/** AHB_DMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of RX channel 2 + */ +#define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8) +/** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_INFIFO_FULL_CH2 (BIT(0)) +#define AHB_DMA_INFIFO_FULL_CH2_M (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S) +#define AHB_DMA_INFIFO_FULL_CH2_V 0x00000001U +#define AHB_DMA_INFIFO_FULL_CH2_S 0 +/** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define AHB_DMA_INFIFO_EMPTY_CH2_M (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S) +#define AHB_DMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define AHB_DMA_INFIFO_EMPTY_CH2_S 1 +/** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 2 + */ +#define AHB_DMA_INFIFO_CNT_CH2 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH2_M (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S) +#define AHB_DMA_INFIFO_CNT_CH2_V 0x0000007FU +#define AHB_DMA_INFIFO_CNT_CH2_S 8 +/** AHB_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S) +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** AHB_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S) +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** AHB_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S) +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** AHB_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S) +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** AHB_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define AHB_DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define AHB_DMA_IN_BUF_HUNGRY_CH2_M (AHB_DMA_IN_BUF_HUNGRY_CH2_V << AHB_DMA_IN_BUF_HUNGRY_CH2_S) +#define AHB_DMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define AHB_DMA_IN_BUF_HUNGRY_CH2_S 27 + +/** AHB_DMA_IN_POP_CH2_REG register + * Receive FIFO status of RX channel 2 + */ +#define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc) +/** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ +#define AHB_DMA_INFIFO_RDATA_CH2 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH2_M (AHB_DMA_INFIFO_RDATA_CH2_V << AHB_DMA_INFIFO_RDATA_CH2_S) +#define AHB_DMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define AHB_DMA_INFIFO_RDATA_CH2_S 0 +/** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ +#define AHB_DMA_INFIFO_POP_CH2 (BIT(12)) +#define AHB_DMA_INFIFO_POP_CH2_M (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S) +#define AHB_DMA_INFIFO_POP_CH2_V 0x00000001U +#define AHB_DMA_INFIFO_POP_CH2_S 12 + +/** AHB_DMA_IN_LINK_CH2_REG register + * Receive FIFO status of RX channel 2 + */ +#define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200) +/** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ +#define AHB_DMA_INLINK_AUTO_RET_CH2 (BIT(0)) +#define AHB_DMA_INLINK_AUTO_RET_CH2_M (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S) +#define AHB_DMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define AHB_DMA_INLINK_AUTO_RET_CH2_S 0 +/** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_INLINK_STOP_CH2 (BIT(1)) +#define AHB_DMA_INLINK_STOP_CH2_M (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S) +#define AHB_DMA_INLINK_STOP_CH2_V 0x00000001U +#define AHB_DMA_INLINK_STOP_CH2_S 1 +/** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_INLINK_START_CH2 (BIT(2)) +#define AHB_DMA_INLINK_START_CH2_M (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S) +#define AHB_DMA_INLINK_START_CH2_V 0x00000001U +#define AHB_DMA_INLINK_START_CH2_S 2 +/** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_INLINK_RESTART_CH2 (BIT(3)) +#define AHB_DMA_INLINK_RESTART_CH2_M (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S) +#define AHB_DMA_INLINK_RESTART_CH2_V 0x00000001U +#define AHB_DMA_INLINK_RESTART_CH2_S 3 +/** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_INLINK_PARK_CH2 (BIT(4)) +#define AHB_DMA_INLINK_PARK_CH2_M (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S) +#define AHB_DMA_INLINK_PARK_CH2_V 0x00000001U +#define AHB_DMA_INLINK_PARK_CH2_S 4 + +/** AHB_DMA_IN_STATE_CH2_REG register + * Receive status of RX channel 2 + */ +#define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204) +/** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * reserved + */ +#define AHB_DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH2_M (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S) +#define AHB_DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define AHB_DMA_INLINK_DSCR_ADDR_CH2_S 0 +/** AHB_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_IN_DSCR_STATE_CH2 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH2_M (AHB_DMA_IN_DSCR_STATE_CH2_V << AHB_DMA_IN_DSCR_STATE_CH2_S) +#define AHB_DMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define AHB_DMA_IN_DSCR_STATE_CH2_S 18 +/** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ +#define AHB_DMA_IN_STATE_CH2 0x00000007U +#define AHB_DMA_IN_STATE_CH2_M (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S) +#define AHB_DMA_IN_STATE_CH2_V 0x00000007U +#define AHB_DMA_IN_STATE_CH2_S 20 + +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Receive descriptor address when EOF occurs on RX channel 2 + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208) +/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Receive descriptor address when errors occur of RX channel 2 + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c) +/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** AHB_DMA_IN_DSCR_CH2_REG register + * Current receive descriptor address of RX channel 2 + */ +#define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210) +/** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ +#define AHB_DMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH2_M (AHB_DMA_INLINK_DSCR_CH2_V << AHB_DMA_INLINK_DSCR_CH2_S) +#define AHB_DMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_CH2_S 0 + +/** AHB_DMA_IN_DSCR_BF0_CH2_REG register + * The last receive descriptor address of RX channel 2 + */ +#define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214) +/** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH2_M (AHB_DMA_INLINK_DSCR_BF0_CH2_V << AHB_DMA_INLINK_DSCR_BF0_CH2_S) +#define AHB_DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF0_CH2_S 0 + +/** AHB_DMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last receive descriptor address of RX channel 2 + */ +#define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218) +/** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ +#define AHB_DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH2_M (AHB_DMA_INLINK_DSCR_BF1_CH2_V << AHB_DMA_INLINK_DSCR_BF1_CH2_S) +#define AHB_DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_DSCR_BF1_CH2_S 0 + +/** AHB_DMA_IN_PERI_CH2_REG register + * Priority register of RX channel 2 + */ +#define AHB_DMA_IN_PERI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c) +/** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 2.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_RX_PRI_CH2 0x0000000FU +#define AHB_DMA_RX_PRI_CH2_M (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S) +#define AHB_DMA_RX_PRI_CH2_V 0x0000000FU +#define AHB_DMA_RX_PRI_CH2_S 0 + +/** AHB_DMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection register of RX channel 2 + */ +#define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220) +/** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ +#define AHB_DMA_PERI_IN_SEL_CH2 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH2_M (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S) +#define AHB_DMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define AHB_DMA_PERI_IN_SEL_CH2_S 0 + +/** AHB_DMA_OUT_CONF0_CH2_REG register + * Configuration register 0 of TX channel 2 + */ +#define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250) +/** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ +#define AHB_DMA_OUT_RST_CH2 (BIT(0)) +#define AHB_DMA_OUT_RST_CH2_M (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S) +#define AHB_DMA_OUT_RST_CH2_V 0x00000001U +#define AHB_DMA_OUT_RST_CH2_S 0 +/** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define AHB_DMA_OUT_LOOP_TEST_CH2_M (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S) +#define AHB_DMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define AHB_DMA_OUT_LOOP_TEST_CH2_S 1 +/** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define AHB_DMA_OUT_AUTO_WRBACK_CH2_M (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S) +#define AHB_DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define AHB_DMA_OUT_AUTO_WRBACK_CH2_S 2 +/** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ +#define AHB_DMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define AHB_DMA_OUT_EOF_MODE_CH2_M (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S) +#define AHB_DMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define AHB_DMA_OUT_EOF_MODE_CH2_S 3 +/** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 2 reading + * descriptors. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define AHB_DMA_OUTDSCR_BURST_EN_CH2_M (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S) +#define AHB_DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define AHB_DMA_OUTDSCR_BURST_EN_CH2_S 4 +/** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 2. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_ETM_EN_CH2 (BIT(6)) +#define AHB_DMA_OUT_ETM_EN_CH2_M (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S) +#define AHB_DMA_OUT_ETM_EN_CH2_V 0x00000001U +#define AHB_DMA_OUT_ETM_EN_CH2_S 6 +/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S) +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V 0x00000003U +#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S 8 + +/** AHB_DMA_OUT_CONF1_CH2_REG register + * Configuration register 1 of TX channel 2 + */ +#define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254) +/** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 2. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define AHB_DMA_OUT_CHECK_OWNER_CH2_M (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S) +#define AHB_DMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define AHB_DMA_OUT_CHECK_OWNER_CH2_S 12 + +/** AHB_DMA_OUTFIFO_STATUS_CH2_REG register + * Receive FIFO status of RX channel 2 + */ +#define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258) +/** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ +#define AHB_DMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define AHB_DMA_OUTFIFO_FULL_CH2_M (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S) +#define AHB_DMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define AHB_DMA_OUTFIFO_FULL_CH2_S 0 +/** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ +#define AHB_DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define AHB_DMA_OUTFIFO_EMPTY_CH2_M (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S) +#define AHB_DMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define AHB_DMA_OUTFIFO_EMPTY_CH2_S 1 +/** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 2 + */ +#define AHB_DMA_OUTFIFO_CNT_CH2 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH2_M (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S) +#define AHB_DMA_OUTFIFO_CNT_CH2_V 0x0000007FU +#define AHB_DMA_OUTFIFO_CNT_CH2_S 8 +/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** AHB_DMA_OUT_PUSH_CH2_REG register + * Push control register of TX channel 2 + */ +#define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c) +/** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ +#define AHB_DMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH2_M (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S) +#define AHB_DMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define AHB_DMA_OUTFIFO_WDATA_CH2_S 0 +/** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ +#define AHB_DMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define AHB_DMA_OUTFIFO_PUSH_CH2_M (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S) +#define AHB_DMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define AHB_DMA_OUTFIFO_PUSH_CH2_S 9 + +/** AHB_DMA_OUT_LINK_CH2_REG register + * Push control register of TX channel 2 + */ +#define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260) +/** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ +#define AHB_DMA_OUTLINK_STOP_CH2 (BIT(0)) +#define AHB_DMA_OUTLINK_STOP_CH2_M (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S) +#define AHB_DMA_OUTLINK_STOP_CH2_V 0x00000001U +#define AHB_DMA_OUTLINK_STOP_CH2_S 0 +/** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_OUTLINK_START_CH2 (BIT(1)) +#define AHB_DMA_OUTLINK_START_CH2_M (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S) +#define AHB_DMA_OUTLINK_START_CH2_V 0x00000001U +#define AHB_DMA_OUTLINK_START_CH2_S 1 +/** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ +#define AHB_DMA_OUTLINK_RESTART_CH2 (BIT(2)) +#define AHB_DMA_OUTLINK_RESTART_CH2_M (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S) +#define AHB_DMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define AHB_DMA_OUTLINK_RESTART_CH2_S 2 +/** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ +#define AHB_DMA_OUTLINK_PARK_CH2 (BIT(3)) +#define AHB_DMA_OUTLINK_PARK_CH2_M (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S) +#define AHB_DMA_OUTLINK_PARK_CH2_V 0x00000001U +#define AHB_DMA_OUTLINK_PARK_CH2_S 3 + +/** AHB_DMA_OUT_STATE_CH2_REG register + * Transmit status of TX channel 2 + */ +#define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264) +/** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S) +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** AHB_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_DSCR_STATE_CH2 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH2_M (AHB_DMA_OUT_DSCR_STATE_CH2_V << AHB_DMA_OUT_DSCR_STATE_CH2_S) +#define AHB_DMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define AHB_DMA_OUT_DSCR_STATE_CH2_S 18 +/** AHB_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define AHB_DMA_OUT_STATE_CH2 0x00000007U +#define AHB_DMA_OUT_STATE_CH2_M (AHB_DMA_OUT_STATE_CH2_V << AHB_DMA_OUT_STATE_CH2_S) +#define AHB_DMA_OUT_STATE_CH2_V 0x00000007U +#define AHB_DMA_OUT_STATE_CH2_S 20 + +/** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register + * Transmit descriptor address when EOF occurs on TX channel 2 + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268) +/** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ +#define AHB_DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_M (AHB_DMA_OUT_EOF_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_DES_ADDR_CH2_S) +#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last transmit descriptor address when EOF occurs on TX channel 2 + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c) +/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** AHB_DMA_OUT_DSCR_CH2_REG register + * Current transmit descriptor address of TX channel 2 + */ +#define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270) +/** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH2_M (AHB_DMA_OUTLINK_DSCR_CH2_V << AHB_DMA_OUTLINK_DSCR_CH2_S) +#define AHB_DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_CH2_S 0 + +/** AHB_DMA_OUT_DSCR_BF0_CH2_REG register + * The last transmit descriptor address of TX channel 2 + */ +#define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274) +/** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_M (AHB_DMA_OUTLINK_DSCR_BF0_CH2_V << AHB_DMA_OUTLINK_DSCR_BF0_CH2_S) +#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** AHB_DMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last transmit descriptor address of TX channel 2 + */ +#define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278) +/** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ +#define AHB_DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_M (AHB_DMA_OUTLINK_DSCR_BF1_CH2_V << AHB_DMA_OUTLINK_DSCR_BF1_CH2_S) +#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** AHB_DMA_OUT_PERI_CH2_REG register + * Priority register of TX channel 2 + */ +#define AHB_DMA_OUT_PERI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c) +/** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 2.The larger of the value, the higher of the + * priority.. + */ +#define AHB_DMA_TX_PRI_CH2 0x0000000FU +#define AHB_DMA_TX_PRI_CH2_M (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S) +#define AHB_DMA_TX_PRI_CH2_V 0x0000000FU +#define AHB_DMA_TX_PRI_CH2_S 0 + +/** AHB_DMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection register of TX channel 2 + */ +#define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280) +/** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + * \ + */ +#define AHB_DMA_PERI_OUT_SEL_CH2 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH2_M (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S) +#define AHB_DMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define AHB_DMA_PERI_OUT_SEL_CH2_S 0 + +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG register + * TX channel 0 arbitration weight configuration register + */ +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel0 + */ +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S 0 + +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register + * TX channel 0 weight arbitration optimization enable register + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S 0 + +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG register + * TX channel 1 arbitration weight configuration register + */ +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel1 + */ +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S 0 + +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register + * TX channel 1 weight arbitration optimization enable register + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S 0 + +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG register + * TX channel 2 arbitration weight configuration register + */ +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel2 + */ +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S 0 + +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG register + * TX channel 2 weight arbitration optimization enable register + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S 0 + +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG register + * RX channel 0 arbitration weight configuration register + */ +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel0 + */ +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S 0 + +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register + * RX channel 0 weight arbitration optimization enable register + */ +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S 0 + +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG register + * RX channel 1 arbitration weight configuration register + */ +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel1 + */ +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S 0 + +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register + * RX channel 1 weight arbitration optimization enable register + */ +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S 0 + +/** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register + * RX channel 2 arbitration weight configuration register + */ +#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4) +/** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel2 + */ +#define AHB_DMA_RX_CH_ARB_WEIGH_CH2 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_M (AHB_DMA_RX_CH_ARB_WEIGH_CH2_V << AHB_DMA_RX_CH_ARB_WEIGH_CH2_S) +#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S 0 + +/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register + * RX channel 2 weight arbitration optimization enable register + */ +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8) +/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S) +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S 0 + +/** AHB_DMA_IN_LINK_ADDR_CH0_REG register + * Link list descriptor address configuration of RX channel 0 + */ +#define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) +/** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ +#define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) +#define AHB_DMA_INLINK_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH0_S 0 + +/** AHB_DMA_IN_LINK_ADDR_CH1_REG register + * Link list descriptor address configuration of RX channel 1 + */ +#define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) +/** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ +#define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) +#define AHB_DMA_INLINK_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH1_S 0 + +/** AHB_DMA_IN_LINK_ADDR_CH2_REG register + * Link list descriptor address configuration of RX channel 2 + */ +#define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4) +/** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ +#define AHB_DMA_INLINK_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH2_M (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S) +#define AHB_DMA_INLINK_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_INLINK_ADDR_CH2_S 0 + +/** AHB_DMA_OUT_LINK_ADDR_CH0_REG register + * Link list descriptor address configuration of TX channel 0 + */ +#define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8) +/** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define AHB_DMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH0_M (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S) +#define AHB_DMA_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH0_S 0 + +/** AHB_DMA_OUT_LINK_ADDR_CH1_REG register + * Link list descriptor address configuration of TX channel 1 + */ +#define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) +/** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define AHB_DMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH1_M (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S) +#define AHB_DMA_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH1_S 0 + +/** AHB_DMA_OUT_LINK_ADDR_CH2_REG register + * Link list descriptor address configuration of TX channel 2 + */ +#define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0) +/** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define AHB_DMA_OUTLINK_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH2_M (AHB_DMA_OUTLINK_ADDR_CH2_V << AHB_DMA_OUTLINK_ADDR_CH2_S) +#define AHB_DMA_OUTLINK_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUTLINK_ADDR_CH2_S 0 + +/** AHB_DMA_INTR_MEM_START_ADDR_REG register + * Accessible address space start address configuration register + */ +#define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4) +/** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Accessible address space start address configuration register + */ +#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU +#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S) +#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU +#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S 0 + +/** AHB_DMA_INTR_MEM_END_ADDR_REG register + * Accessible address space end address configuration register + */ +#define AHB_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c8) +/** AHB_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of accessible address space. + */ +#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU +#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S) +#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU +#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S 0 + +/** AHB_DMA_ARB_TIMEOUT_TX_REG register + * TX arbitration timeout configuration register + */ +#define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc) +/** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. + */ +#define AHB_DMA_ARB_TIMEOUT_TX 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_TX_M (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S) +#define AHB_DMA_ARB_TIMEOUT_TX_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_TX_S 0 + +/** AHB_DMA_ARB_TIMEOUT_RX_REG register + * RX arbitration timeout configuration register + */ +#define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0) +/** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. + */ +#define AHB_DMA_ARB_TIMEOUT_RX 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_RX_M (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S) +#define AHB_DMA_ARB_TIMEOUT_RX_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_RX_S 0 + +/** AHB_DMA_WEIGHT_EN_TX_REG register + * TX weight arbitration enable register + */ +#define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4) +/** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for TX. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_WEIGHT_EN_TX (BIT(0)) +#define AHB_DMA_WEIGHT_EN_TX_M (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S) +#define AHB_DMA_WEIGHT_EN_TX_V 0x00000001U +#define AHB_DMA_WEIGHT_EN_TX_S 0 + +/** AHB_DMA_WEIGHT_EN_RX_REG register + * RX weight arbitration enable register + */ +#define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8) +/** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for RX. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_WEIGHT_EN_RX (BIT(0)) +#define AHB_DMA_WEIGHT_EN_RX_M (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S) +#define AHB_DMA_WEIGHT_EN_RX_V 0x00000001U +#define AHB_DMA_WEIGHT_EN_RX_S 0 + +/** AHB_DMA_ARB_TIMEOUT_REG register + * TX arbitration timeout configuration register + */ +#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc) +/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. + */ +#define AHB_DMA_ARB_TIMEOUT_NUM 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_M (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S) +#define AHB_DMA_ARB_TIMEOUT_NUM_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_S 0 + +/** AHB_DMA_WEIGHT_EN_REG register + * TX weight arbitration enable register + */ +#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400) +/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_WEIGHT_EN (BIT(0)) +#define AHB_DMA_WEIGHT_EN_M (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S) +#define AHB_DMA_WEIGHT_EN_V 0x00000001U +#define AHB_DMA_WEIGHT_EN_S 0 + +/** AHB_DMA_MODULE_CLK_EN_REG register + * Module clock force on register + */ +#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404) +/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [2:0]; default: 7; + * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock + */ +#define AHB_DMA_AHB_APB_SYNC_CLK_EN 0x00000007U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S) +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V 0x00000007U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S 0 +/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [5:3]; default: 7; + * Configures whether to force on out_dscr 2~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ +#define AHB_DMA_OUT_DSCR_CLK_EN 0x00000007U +#define AHB_DMA_OUT_DSCR_CLK_EN_M (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S) +#define AHB_DMA_OUT_DSCR_CLK_EN_V 0x00000007U +#define AHB_DMA_OUT_DSCR_CLK_EN_S 3 +/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [8:6]; default: 7; + * Configures whether to force on out_ctrl 2~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ +#define AHB_DMA_OUT_CTRL_CLK_EN 0x00000007U +#define AHB_DMA_OUT_CTRL_CLK_EN_M (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S) +#define AHB_DMA_OUT_CTRL_CLK_EN_V 0x00000007U +#define AHB_DMA_OUT_CTRL_CLK_EN_S 6 +/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [11:9]; default: 7; + * Configures whether to force on in_dscr 2~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ +#define AHB_DMA_IN_DSCR_CLK_EN 0x00000007U +#define AHB_DMA_IN_DSCR_CLK_EN_M (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S) +#define AHB_DMA_IN_DSCR_CLK_EN_V 0x00000007U +#define AHB_DMA_IN_DSCR_CLK_EN_S 9 +/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [14:12]; default: 7; + * Configures whether to force on in_ctrl 2~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ +#define AHB_DMA_IN_CTRL_CLK_EN 0x00000007U +#define AHB_DMA_IN_CTRL_CLK_EN_M (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S) +#define AHB_DMA_IN_CTRL_CLK_EN_V 0x00000007U +#define AHB_DMA_IN_CTRL_CLK_EN_S 12 +/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ +#define AHB_DMA_CMD_ARB_CLK_EN (BIT(27)) +#define AHB_DMA_CMD_ARB_CLK_EN_M (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S) +#define AHB_DMA_CMD_ARB_CLK_EN_V 0x00000001U +#define AHB_DMA_CMD_ARB_CLK_EN_S 27 +/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ +#define AHB_DMA_AHBINF_CLK_EN (BIT(28)) +#define AHB_DMA_AHBINF_CLK_EN_M (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S) +#define AHB_DMA_AHBINF_CLK_EN_V 0x00000001U +#define AHB_DMA_AHBINF_CLK_EN_S 28 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register + * AHB response error status 0 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408) +/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ADDR 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S) +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S 0 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register + * AHB response error status 1 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c) +/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ +#define AHB_DMA_AHBINF_RESP_ERR_WR (BIT(0)) +#define AHB_DMA_AHBINF_RESP_ERR_WR_M (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S) +#define AHB_DMA_AHBINF_RESP_ERR_WR_V 0x00000001U +#define AHB_DMA_AHBINF_RESP_ERR_WR_S 0 +/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ID 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_M (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_ID_V 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_S 1 +/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [7:5]; default: 0; + * Represents the AHB response error request channel id.bit[2]=1:TX channel. + * bit[2]=0:RX channel. + */ +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID 0x00000007U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V 0x00000007U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S 5 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register + * RX_done Inlink descriptor address of RX channel 0 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x410) +/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register + * TX done outlink descriptor address of TX channel 0 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x414) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S 0 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register + * RX_done Inlink descriptor address of RX channel 1 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x418) +/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register + * TX done outlink descriptor address of TX channel 1 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x41c) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S 0 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register + * RX_done Inlink descriptor address of RX channel 2 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x420) +/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register + * TX done outlink descriptor address of TX channel 2 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x424) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h b/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h new file mode 100644 index 0000000000..0f168341aa --- /dev/null +++ b/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h @@ -0,0 +1,3574 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_ch0 register + * Raw interrupt status of RX channel 0 + */ +typedef union { + struct { + /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT + */ + uint32_t in_done_ch0_int_raw:1; + /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + */ + uint32_t in_suc_eof_ch0_int_raw:1; + /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + */ + uint32_t in_err_eof_ch0_int_raw:1; + /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + */ + uint32_t in_dscr_err_ch0_int_raw:1; + /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ + uint32_t in_dscr_empty_ch0_int_raw:1; + /** infifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + */ + uint32_t infifo_ovf_ch0_int_raw:1; + /** infifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + */ + uint32_t infifo_udf_ch0_int_raw:1; + /** in_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ + uint32_t in_ahbinf_resp_err_ch0_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_raw_ch0_reg_t; + + +/** Group: Status Registers */ +/** Type of in_int_st_ch0 register + * Masked interrupt status of RX channel 0 + */ +typedef union { + struct { + /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT + */ + uint32_t in_done_ch0_int_st:1; + /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + */ + uint32_t in_suc_eof_ch0_int_st:1; + /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + */ + uint32_t in_err_eof_ch0_int_st:1; + /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + */ + uint32_t in_dscr_err_ch0_int_st:1; + /** in_dscr_empty_ch0_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ + uint32_t in_dscr_empty_ch0_int_st:1; + /** infifo_ovf_ch0_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + */ + uint32_t infifo_ovf_ch0_int_st:1; + /** infifo_udf_ch0_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + */ + uint32_t infifo_udf_ch0_int_st:1; + /** in_ahbinf_resp_err_ch0_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ + uint32_t in_ahbinf_resp_err_ch0_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_st_ch0_reg_t; + +/** Type of in_int_ena_ch0 register + * Interrupt enable bits of RX channel 0 + */ +typedef union { + struct { + /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT + */ + uint32_t in_done_ch0_int_ena:1; + /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT + */ + uint32_t in_suc_eof_ch0_int_ena:1; + /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT + */ + uint32_t in_err_eof_ch0_int_ena:1; + /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT + */ + uint32_t in_dscr_err_ch0_int_ena:1; + /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ + uint32_t in_dscr_empty_ch0_int_ena:1; + /** infifo_ovf_ch0_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT + */ + uint32_t infifo_ovf_ch0_int_ena:1; + /** infifo_udf_ch0_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT + */ + uint32_t infifo_udf_ch0_int_ena:1; + /** in_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT + */ + uint32_t in_ahbinf_resp_err_ch0_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_ena_ch0_reg_t; + +/** Type of in_int_clr_ch0 register + * Interrupt clear bits of RX channel 0 + */ +typedef union { + struct { + /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT + */ + uint32_t in_done_ch0_int_clr:1; + /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT + */ + uint32_t in_suc_eof_ch0_int_clr:1; + /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT + */ + uint32_t in_err_eof_ch0_int_clr:1; + /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT + */ + uint32_t in_dscr_err_ch0_int_clr:1; + /** in_dscr_empty_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT + */ + uint32_t in_dscr_empty_ch0_int_clr:1; + /** infifo_ovf_ch0_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT + */ + uint32_t infifo_ovf_ch0_int_clr:1; + /** infifo_udf_ch0_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT + */ + uint32_t infifo_udf_ch0_int_clr:1; + /** in_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT + */ + uint32_t in_ahbinf_resp_err_ch0_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_clr_ch0_reg_t; + +/** Type of in_int_raw_ch1 register + * Raw interrupt status of RX channel 1 + */ +typedef union { + struct { + /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT + */ + uint32_t in_done_ch1_int_raw:1; + /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + */ + uint32_t in_suc_eof_ch1_int_raw:1; + /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + */ + uint32_t in_err_eof_ch1_int_raw:1; + /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + */ + uint32_t in_dscr_err_ch1_int_raw:1; + /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ + uint32_t in_dscr_empty_ch1_int_raw:1; + /** infifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + */ + uint32_t infifo_ovf_ch1_int_raw:1; + /** infifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + */ + uint32_t infifo_udf_ch1_int_raw:1; + /** in_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ + uint32_t in_ahbinf_resp_err_ch1_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_raw_ch1_reg_t; + +/** Type of in_int_st_ch1 register + * Masked interrupt status of RX channel 1 + */ +typedef union { + struct { + /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT + */ + uint32_t in_done_ch1_int_st:1; + /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + */ + uint32_t in_suc_eof_ch1_int_st:1; + /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + */ + uint32_t in_err_eof_ch1_int_st:1; + /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + */ + uint32_t in_dscr_err_ch1_int_st:1; + /** in_dscr_empty_ch1_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ + uint32_t in_dscr_empty_ch1_int_st:1; + /** infifo_ovf_ch1_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + */ + uint32_t infifo_ovf_ch1_int_st:1; + /** infifo_udf_ch1_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + */ + uint32_t infifo_udf_ch1_int_st:1; + /** in_ahbinf_resp_err_ch1_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ + uint32_t in_ahbinf_resp_err_ch1_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_st_ch1_reg_t; + +/** Type of in_int_ena_ch1 register + * Interrupt enable bits of RX channel 1 + */ +typedef union { + struct { + /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT + */ + uint32_t in_done_ch1_int_ena:1; + /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT + */ + uint32_t in_suc_eof_ch1_int_ena:1; + /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT + */ + uint32_t in_err_eof_ch1_int_ena:1; + /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT + */ + uint32_t in_dscr_err_ch1_int_ena:1; + /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ + uint32_t in_dscr_empty_ch1_int_ena:1; + /** infifo_ovf_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT + */ + uint32_t infifo_ovf_ch1_int_ena:1; + /** infifo_udf_ch1_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT + */ + uint32_t infifo_udf_ch1_int_ena:1; + /** in_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT + */ + uint32_t in_ahbinf_resp_err_ch1_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_ena_ch1_reg_t; + +/** Type of in_int_clr_ch1 register + * Interrupt clear bits of RX channel 1 + */ +typedef union { + struct { + /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT + */ + uint32_t in_done_ch1_int_clr:1; + /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT + */ + uint32_t in_suc_eof_ch1_int_clr:1; + /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT + */ + uint32_t in_err_eof_ch1_int_clr:1; + /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT + */ + uint32_t in_dscr_err_ch1_int_clr:1; + /** in_dscr_empty_ch1_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT + */ + uint32_t in_dscr_empty_ch1_int_clr:1; + /** infifo_ovf_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT + */ + uint32_t infifo_ovf_ch1_int_clr:1; + /** infifo_udf_ch1_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT + */ + uint32_t infifo_udf_ch1_int_clr:1; + /** in_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT + */ + uint32_t in_ahbinf_resp_err_ch1_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_clr_ch1_reg_t; + +/** Type of in_int_raw_ch2 register + * Raw interrupt status of RX channel 2 + */ +typedef union { + struct { + /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT + */ + uint32_t in_done_ch2_int_raw:1; + /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT + */ + uint32_t in_suc_eof_ch2_int_raw:1; + /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT + */ + uint32_t in_err_eof_ch2_int_raw:1; + /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT + */ + uint32_t in_dscr_err_ch2_int_raw:1; + /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ + uint32_t in_dscr_empty_ch2_int_raw:1; + /** infifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT + */ + uint32_t infifo_ovf_ch2_int_raw:1; + /** infifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT + */ + uint32_t infifo_udf_ch2_int_raw:1; + /** in_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ + uint32_t in_ahbinf_resp_err_ch2_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_raw_ch2_reg_t; + +/** Type of in_int_st_ch2 register + * Masked interrupt status of RX channel 2 + */ +typedef union { + struct { + /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT + */ + uint32_t in_done_ch2_int_st:1; + /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT + */ + uint32_t in_suc_eof_ch2_int_st:1; + /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT + */ + uint32_t in_err_eof_ch2_int_st:1; + /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT + */ + uint32_t in_dscr_err_ch2_int_st:1; + /** in_dscr_empty_ch2_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ + uint32_t in_dscr_empty_ch2_int_st:1; + /** infifo_ovf_ch2_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT + */ + uint32_t infifo_ovf_ch2_int_st:1; + /** infifo_udf_ch2_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT + */ + uint32_t infifo_udf_ch2_int_st:1; + /** in_ahbinf_resp_err_ch2_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ + uint32_t in_ahbinf_resp_err_ch2_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_st_ch2_reg_t; + +/** Type of in_int_ena_ch2 register + * Interrupt enable bits of RX channel 2 + */ +typedef union { + struct { + /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT + */ + uint32_t in_done_ch2_int_ena:1; + /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT + */ + uint32_t in_suc_eof_ch2_int_ena:1; + /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT + */ + uint32_t in_err_eof_ch2_int_ena:1; + /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT + */ + uint32_t in_dscr_err_ch2_int_ena:1; + /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ + uint32_t in_dscr_empty_ch2_int_ena:1; + /** infifo_ovf_ch2_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT + */ + uint32_t infifo_ovf_ch2_int_ena:1; + /** infifo_udf_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT + */ + uint32_t infifo_udf_ch2_int_ena:1; + /** in_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT + */ + uint32_t in_ahbinf_resp_err_ch2_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_ena_ch2_reg_t; + +/** Type of in_int_clr_ch2 register + * Interrupt clear bits of RX channel 2 + */ +typedef union { + struct { + /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT + */ + uint32_t in_done_ch2_int_clr:1; + /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT + */ + uint32_t in_suc_eof_ch2_int_clr:1; + /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT + */ + uint32_t in_err_eof_ch2_int_clr:1; + /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT + */ + uint32_t in_dscr_err_ch2_int_clr:1; + /** in_dscr_empty_ch2_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT + */ + uint32_t in_dscr_empty_ch2_int_clr:1; + /** infifo_ovf_ch2_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT + */ + uint32_t infifo_ovf_ch2_int_clr:1; + /** infifo_udf_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT + */ + uint32_t infifo_udf_ch2_int_clr:1; + /** in_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT + */ + uint32_t in_ahbinf_resp_err_ch2_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_int_clr_ch2_reg_t; + +/** Type of out_int_raw_ch0 register + * //Raw interrupt status of TX channel 0 + */ +typedef union { + struct { + /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT + */ + uint32_t out_done_ch0_int_raw:1; + /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT + */ + uint32_t out_eof_ch0_int_raw:1; + /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ + uint32_t out_dscr_err_ch0_int_raw:1; + /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ + uint32_t out_total_eof_ch0_int_raw:1; + /** outfifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + */ + uint32_t outfifo_ovf_ch0_int_raw:1; + /** outfifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + */ + uint32_t outfifo_udf_ch0_int_raw:1; + /** out_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ + uint32_t out_ahbinf_resp_err_ch0_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_raw_ch0_reg_t; + +/** Type of out_int_st_ch0 register + * Masked interrupt status of TX channel 0 + */ +typedef union { + struct { + /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT + */ + uint32_t out_done_ch0_int_st:1; + /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT + */ + uint32_t out_eof_ch0_int_st:1; + /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ + uint32_t out_dscr_err_ch0_int_st:1; + /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ + uint32_t out_total_eof_ch0_int_st:1; + /** outfifo_ovf_ch0_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + */ + uint32_t outfifo_ovf_ch0_int_st:1; + /** outfifo_udf_ch0_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + */ + uint32_t outfifo_udf_ch0_int_st:1; + /** out_ahbinf_resp_err_ch0_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ + uint32_t out_ahbinf_resp_err_ch0_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_st_ch0_reg_t; + +/** Type of out_int_ena_ch0 register + * Interrupt enable bits of TX channel 0 + */ +typedef union { + struct { + /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT + */ + uint32_t out_done_ch0_int_ena:1; + /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT + */ + uint32_t out_eof_ch0_int_ena:1; + /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ + uint32_t out_dscr_err_ch0_int_ena:1; + /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ + uint32_t out_total_eof_ch0_int_ena:1; + /** outfifo_ovf_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT + */ + uint32_t outfifo_ovf_ch0_int_ena:1; + /** outfifo_udf_ch0_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT + */ + uint32_t outfifo_udf_ch0_int_ena:1; + /** out_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT + */ + uint32_t out_ahbinf_resp_err_ch0_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_ena_ch0_reg_t; + +/** Type of out_int_clr_ch0 register + * Interrupt clear bits of TX channel 0 + */ +typedef union { + struct { + /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT + */ + uint32_t out_done_ch0_int_clr:1; + /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT + */ + uint32_t out_eof_ch0_int_clr:1; + /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT + */ + uint32_t out_dscr_err_ch0_int_clr:1; + /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT + */ + uint32_t out_total_eof_ch0_int_clr:1; + /** outfifo_ovf_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT + */ + uint32_t outfifo_ovf_ch0_int_clr:1; + /** outfifo_udf_ch0_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT + */ + uint32_t outfifo_udf_ch0_int_clr:1; + /** out_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT + */ + uint32_t out_ahbinf_resp_err_ch0_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_clr_ch0_reg_t; + +/** Type of out_int_raw_ch1 register + * //Raw interrupt status of TX channel 1 + */ +typedef union { + struct { + /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT + */ + uint32_t out_done_ch1_int_raw:1; + /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT + */ + uint32_t out_eof_ch1_int_raw:1; + /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ + uint32_t out_dscr_err_ch1_int_raw:1; + /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ + uint32_t out_total_eof_ch1_int_raw:1; + /** outfifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + */ + uint32_t outfifo_ovf_ch1_int_raw:1; + /** outfifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + */ + uint32_t outfifo_udf_ch1_int_raw:1; + /** out_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ + uint32_t out_ahbinf_resp_err_ch1_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_raw_ch1_reg_t; + +/** Type of out_int_st_ch1 register + * Masked interrupt status of TX channel 1 + */ +typedef union { + struct { + /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT + */ + uint32_t out_done_ch1_int_st:1; + /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT + */ + uint32_t out_eof_ch1_int_st:1; + /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ + uint32_t out_dscr_err_ch1_int_st:1; + /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ + uint32_t out_total_eof_ch1_int_st:1; + /** outfifo_ovf_ch1_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + */ + uint32_t outfifo_ovf_ch1_int_st:1; + /** outfifo_udf_ch1_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + */ + uint32_t outfifo_udf_ch1_int_st:1; + /** out_ahbinf_resp_err_ch1_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ + uint32_t out_ahbinf_resp_err_ch1_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_st_ch1_reg_t; + +/** Type of out_int_ena_ch1 register + * Interrupt enable bits of TX channel 1 + */ +typedef union { + struct { + /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT + */ + uint32_t out_done_ch1_int_ena:1; + /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT + */ + uint32_t out_eof_ch1_int_ena:1; + /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ + uint32_t out_dscr_err_ch1_int_ena:1; + /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ + uint32_t out_total_eof_ch1_int_ena:1; + /** outfifo_ovf_ch1_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT + */ + uint32_t outfifo_ovf_ch1_int_ena:1; + /** outfifo_udf_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT + */ + uint32_t outfifo_udf_ch1_int_ena:1; + /** out_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT + */ + uint32_t out_ahbinf_resp_err_ch1_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_ena_ch1_reg_t; + +/** Type of out_int_clr_ch1 register + * Interrupt clear bits of TX channel 1 + */ +typedef union { + struct { + /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT + */ + uint32_t out_done_ch1_int_clr:1; + /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT + */ + uint32_t out_eof_ch1_int_clr:1; + /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT + */ + uint32_t out_dscr_err_ch1_int_clr:1; + /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT + */ + uint32_t out_total_eof_ch1_int_clr:1; + /** outfifo_ovf_ch1_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT + */ + uint32_t outfifo_ovf_ch1_int_clr:1; + /** outfifo_udf_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT + */ + uint32_t outfifo_udf_ch1_int_clr:1; + /** out_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT + */ + uint32_t out_ahbinf_resp_err_ch1_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_clr_ch1_reg_t; + +/** Type of out_int_raw_ch2 register + * //Raw interrupt status of TX channel 2 + */ +typedef union { + struct { + /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT + */ + uint32_t out_done_ch2_int_raw:1; + /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT + */ + uint32_t out_eof_ch2_int_raw:1; + /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ + uint32_t out_dscr_err_ch2_int_raw:1; + /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ + uint32_t out_total_eof_ch2_int_raw:1; + /** outfifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT + */ + uint32_t outfifo_ovf_ch2_int_raw:1; + /** outfifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT + */ + uint32_t outfifo_udf_ch2_int_raw:1; + /** out_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ + uint32_t out_ahbinf_resp_err_ch2_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_raw_ch2_reg_t; + +/** Type of out_int_st_ch2 register + * Masked interrupt status of TX channel 2 + */ +typedef union { + struct { + /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT + */ + uint32_t out_done_ch2_int_st:1; + /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT + */ + uint32_t out_eof_ch2_int_st:1; + /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ + uint32_t out_dscr_err_ch2_int_st:1; + /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ + uint32_t out_total_eof_ch2_int_st:1; + /** outfifo_ovf_ch2_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT + */ + uint32_t outfifo_ovf_ch2_int_st:1; + /** outfifo_udf_ch2_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT + */ + uint32_t outfifo_udf_ch2_int_st:1; + /** out_ahbinf_resp_err_ch2_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ + uint32_t out_ahbinf_resp_err_ch2_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_st_ch2_reg_t; + +/** Type of out_int_ena_ch2 register + * Interrupt enable bits of TX channel 2 + */ +typedef union { + struct { + /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT + */ + uint32_t out_done_ch2_int_ena:1; + /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT + */ + uint32_t out_eof_ch2_int_ena:1; + /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ + uint32_t out_dscr_err_ch2_int_ena:1; + /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ + uint32_t out_total_eof_ch2_int_ena:1; + /** outfifo_ovf_ch2_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT + */ + uint32_t outfifo_ovf_ch2_int_ena:1; + /** outfifo_udf_ch2_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT + */ + uint32_t outfifo_udf_ch2_int_ena:1; + /** out_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT + */ + uint32_t out_ahbinf_resp_err_ch2_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_ena_ch2_reg_t; + +/** Type of out_int_clr_ch2 register + * Interrupt clear bits of TX channel 2 + */ +typedef union { + struct { + /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT + */ + uint32_t out_done_ch2_int_clr:1; + /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT + */ + uint32_t out_eof_ch2_int_clr:1; + /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT + */ + uint32_t out_dscr_err_ch2_int_clr:1; + /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT + */ + uint32_t out_total_eof_ch2_int_clr:1; + /** outfifo_ovf_ch2_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT + */ + uint32_t outfifo_ovf_ch2_int_clr:1; + /** outfifo_udf_ch2_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT + */ + uint32_t outfifo_udf_ch2_int_clr:1; + /** out_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT + */ + uint32_t out_ahbinf_resp_err_ch2_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_out_int_clr_ch2_reg_t; + +/** Type of ahb_test register + * only for test + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_ahb_test_reg_t; + +/** Type of misc_conf register + * reserved + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset the internal AHB FSM + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Configures whether to disable the fixed-priority channel arbitration. + * 0: Enable + * 1: Disable + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_misc_conf_reg_t; + +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 2410220; + * Version control register + */ + uint32_t date:32; + }; + uint32_t val; +} ahb_dma_date_reg_t; + +/** Type of in_conf0_ch0 register + * Configuration register 0 of RX channel 0 + */ +typedef union { + struct { + /** in_rst_ch0 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + */ + uint32_t in_rst_ch0:1; + /** in_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_ch0:1; + /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 0 to read + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t indscr_burst_en_ch0:1; + uint32_t reserved_3:1; + /** mem_trans_en_ch0 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t mem_trans_en_ch0:1; + /** in_etm_en_ch0 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel0. + * 0: Disable + * 1: Enable + */ + uint32_t in_etm_en_ch0:1; + /** in_data_burst_mode_sel_ch0 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t in_data_burst_mode_sel_ch0:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_conf0_ch0_reg_t; + +/** Type of in_conf1_ch0 register + * Configuration register 1 of RX channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_ch0 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 0. + * 0: Disable + * 1: Enable + */ + uint32_t in_check_owner_ch0:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_conf1_ch0_reg_t; + +/** Type of infifo_status_ch0 register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** infifo_full_ch0 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t infifo_full_ch0:1; + /** infifo_empty_ch0 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t infifo_empty_ch0:1; + uint32_t reserved_2:6; + /** infifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 0 + */ + uint32_t infifo_cnt_ch0:7; + uint32_t reserved_15:8; + /** in_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_ch0:1; + /** in_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_ch0:1; + /** in_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_ch0:1; + /** in_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_ch0:1; + /** in_buf_hungry_ch0 : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_ch0:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} ahb_dma_infifo_status_ch0_reg_t; + +/** Type of in_pop_ch0 register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** infifo_rdata_ch0 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ + uint32_t infifo_rdata_ch0:12; + /** infifo_pop_ch0 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ + uint32_t infifo_pop_ch0:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_pop_ch0_reg_t; + +/** Type of in_link_ch0 register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** inlink_auto_ret_ch0 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ + uint32_t inlink_auto_ret_ch0:1; + /** inlink_stop_ch0 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t inlink_stop_ch0:1; + /** inlink_start_ch0 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t inlink_start_ch0:1; + /** inlink_restart_ch0 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t inlink_restart_ch0:1; + /** inlink_park_ch0 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t inlink_park_ch0:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} ahb_dma_in_link_ch0_reg_t; + +/** Type of in_state_ch0 register + * Receive status of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; + * reserved + */ + uint32_t inlink_dscr_addr_ch0:18; + /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_ch0:2; + /** in_state_ch0 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ + uint32_t in_state_ch0:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_in_state_ch0_reg_t; + +/** Type of in_suc_eof_des_addr_ch0 register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_suc_eof_des_addr_ch0_reg_t; + +/** Type of in_err_eof_des_addr_ch0 register + * Receive descriptor address when errors occur of RX channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ + uint32_t in_err_eof_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_err_eof_des_addr_ch0_reg_t; + +/** Type of in_dscr_ch0 register + * Current receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ + uint32_t inlink_dscr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_dscr_ch0_reg_t; + +/** Type of in_dscr_bf0_ch0 register + * The last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ + uint32_t inlink_dscr_bf0_ch0:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf0_ch0_reg_t; + +/** Type of in_dscr_bf1_ch0 register + * The second-to-last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ + uint32_t inlink_dscr_bf1_ch0:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf1_ch0_reg_t; + +/** Type of in_peri_ch0 register + * Priority register of RX channel 0 + */ +typedef union { + struct { + /** rx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 0.The larger of the value, the higher of the + * priority.. + */ + uint32_t rx_pri_ch0:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_in_peri_ch0_reg_t; + +/** Type of in_peri_sel_ch0 register + * Peripheral selection register of RX channel 0 + */ +typedef union { + struct { + /** peri_in_sel_ch0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ + uint32_t peri_in_sel_ch0:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_in_peri_sel_ch0_reg_t; + +/** Type of out_conf0_ch0 register + * Configuration register 0 of TX channel 0 + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 0 reading + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t outdscr_burst_en_ch0:1; + uint32_t reserved_5:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 0. + * 0: Disable + * 1: Enable + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t out_data_burst_mode_sel_ch0:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_ch0 register + * Configuration register 1 of TX channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_ch0 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 0. + * 0: Disable + * 1: Enable + */ + uint32_t out_check_owner_ch0:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_out_conf1_ch0_reg_t; + +/** Type of outfifo_status_ch0 register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** outfifo_full_ch0 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t outfifo_full_ch0:1; + /** outfifo_empty_ch0 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t outfifo_empty_ch0:1; + uint32_t reserved_2:6; + /** outfifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 0 + */ + uint32_t outfifo_cnt_ch0:7; + uint32_t reserved_15:8; + /** out_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_ch0:1; + /** out_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_ch0:1; + /** out_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_ch0:1; + /** out_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_ch0:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ahb_dma_outfifo_status_ch0_reg_t; + +/** Type of out_push_ch0 register + * Push control register of TX channel 0 + */ +typedef union { + struct { + /** outfifo_wdata_ch0 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ + uint32_t outfifo_wdata_ch0:9; + /** outfifo_push_ch0 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ + uint32_t outfifo_push_ch0:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_push_ch0_reg_t; + +/** Type of out_link_ch0 register + * Push control register of TX channel 0 + */ +typedef union { + struct { + /** outlink_stop_ch0 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t outlink_stop_ch0:1; + /** outlink_start_ch0 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t outlink_start_ch0:1; + /** outlink_restart_ch0 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t outlink_restart_ch0:1; + /** outlink_park_ch0 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t outlink_park_ch0:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_link_ch0_reg_t; + +/** Type of out_state_ch0 register + * Transmit status of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ + uint32_t outlink_dscr_addr_ch0:18; + /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_ch0:2; + /** out_state_ch0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_ch0:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_out_state_ch0_reg_t; + +/** Type of out_eof_des_addr_ch0 register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_eof_des_addr_ch0_reg_t; + +/** Type of out_eof_bfr_des_addr_ch0 register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_eof_bfr_des_addr_ch0_reg_t; + +/** Type of out_dscr_ch0 register + * Current transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ + uint32_t outlink_dscr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_dscr_ch0_reg_t; + +/** Type of out_dscr_bf0_ch0 register + * The last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ + uint32_t outlink_dscr_bf0_ch0:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf0_ch0_reg_t; + +/** Type of out_dscr_bf1_ch0 register + * The second-to-last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ + uint32_t outlink_dscr_bf1_ch0:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf1_ch0_reg_t; + +/** Type of out_peri_ch0 register + * Priority register of TX channel 0 + */ +typedef union { + struct { + /** tx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 0.The larger of the value, the higher of the + * priority.. + */ + uint32_t tx_pri_ch0:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_peri_ch0_reg_t; + +/** Type of out_peri_sel_ch0 register + * Peripheral selection register of TX channel 0 + */ +typedef union { + struct { + /** peri_out_sel_ch0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ + uint32_t peri_out_sel_ch0:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_out_peri_sel_ch0_reg_t; + +/** Type of in_conf0_ch1 register + * Configuration register 0 of RX channel 1 + */ +typedef union { + struct { + /** in_rst_ch1 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. + */ + uint32_t in_rst_ch1:1; + /** in_loop_test_ch1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_ch1:1; + /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 1 to read + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t indscr_burst_en_ch1:1; + uint32_t reserved_3:1; + /** mem_trans_en_ch1 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t mem_trans_en_ch1:1; + /** in_etm_en_ch1 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel1. + * 0: Disable + * 1: Enable + */ + uint32_t in_etm_en_ch1:1; + /** in_data_burst_mode_sel_ch1 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t in_data_burst_mode_sel_ch1:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_conf0_ch1_reg_t; + +/** Type of in_conf1_ch1 register + * Configuration register 1 of RX channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_ch1 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 1. + * 0: Disable + * 1: Enable + */ + uint32_t in_check_owner_ch1:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_conf1_ch1_reg_t; + +/** Type of infifo_status_ch1 register + * Receive FIFO status of RX channel 1 + */ +typedef union { + struct { + /** infifo_full_ch1 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t infifo_full_ch1:1; + /** infifo_empty_ch1 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t infifo_empty_ch1:1; + uint32_t reserved_2:6; + /** infifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 1 + */ + uint32_t infifo_cnt_ch1:7; + uint32_t reserved_15:8; + /** in_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_ch1:1; + /** in_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_ch1:1; + /** in_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_ch1:1; + /** in_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_ch1:1; + /** in_buf_hungry_ch1 : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_ch1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} ahb_dma_infifo_status_ch1_reg_t; + +/** Type of in_pop_ch1 register + * Receive FIFO status of RX channel 1 + */ +typedef union { + struct { + /** infifo_rdata_ch1 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ + uint32_t infifo_rdata_ch1:12; + /** infifo_pop_ch1 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ + uint32_t infifo_pop_ch1:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_pop_ch1_reg_t; + +/** Type of in_link_ch1 register + * Receive FIFO status of RX channel 1 + */ +typedef union { + struct { + /** inlink_auto_ret_ch1 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ + uint32_t inlink_auto_ret_ch1:1; + /** inlink_stop_ch1 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t inlink_stop_ch1:1; + /** inlink_start_ch1 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t inlink_start_ch1:1; + /** inlink_restart_ch1 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t inlink_restart_ch1:1; + /** inlink_park_ch1 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t inlink_park_ch1:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} ahb_dma_in_link_ch1_reg_t; + +/** Type of in_state_ch1 register + * Receive status of RX channel 1 + */ +typedef union { + struct { + /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; + * reserved + */ + uint32_t inlink_dscr_addr_ch1:18; + /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_ch1:2; + /** in_state_ch1 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ + uint32_t in_state_ch1:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_in_state_ch1_reg_t; + +/** Type of in_suc_eof_des_addr_ch1 register + * Receive descriptor address when EOF occurs on RX channel 1 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_suc_eof_des_addr_ch1_reg_t; + +/** Type of in_err_eof_des_addr_ch1 register + * Receive descriptor address when errors occur of RX channel 1 + */ +typedef union { + struct { + /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ + uint32_t in_err_eof_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_err_eof_des_addr_ch1_reg_t; + +/** Type of in_dscr_ch1 register + * Current receive descriptor address of RX channel 1 + */ +typedef union { + struct { + /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ + uint32_t inlink_dscr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_dscr_ch1_reg_t; + +/** Type of in_dscr_bf0_ch1 register + * The last receive descriptor address of RX channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ + uint32_t inlink_dscr_bf0_ch1:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf0_ch1_reg_t; + +/** Type of in_dscr_bf1_ch1 register + * The second-to-last receive descriptor address of RX channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ + uint32_t inlink_dscr_bf1_ch1:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf1_ch1_reg_t; + +/** Type of in_peri_ch1 register + * Priority register of RX channel 1 + */ +typedef union { + struct { + /** rx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 1.The larger of the value, the higher of the + * priority.. + */ + uint32_t rx_pri_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_in_peri_ch1_reg_t; + +/** Type of in_peri_sel_ch1 register + * Peripheral selection register of RX channel 1 + */ +typedef union { + struct { + /** peri_in_sel_ch1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ + uint32_t peri_in_sel_ch1:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_in_peri_sel_ch1_reg_t; + +/** Type of out_conf0_ch1 register + * Configuration register 0 of TX channel 1 + */ +typedef union { + struct { + /** out_rst_ch1 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ + uint32_t out_rst_ch1:1; + /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch1:1; + /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ + uint32_t out_auto_wrback_ch1:1; + /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ + uint32_t out_eof_mode_ch1:1; + /** outdscr_burst_en_ch1 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 1 reading + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t outdscr_burst_en_ch1:1; + uint32_t reserved_5:1; + /** out_etm_en_ch1 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 1. + * 0: Disable + * 1: Enable + */ + uint32_t out_etm_en_ch1:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_ch1 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t out_data_burst_mode_sel_ch1:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_conf0_ch1_reg_t; + +/** Type of out_conf1_ch1 register + * Configuration register 1 of TX channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_ch1 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 1. + * 0: Disable + * 1: Enable + */ + uint32_t out_check_owner_ch1:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_out_conf1_ch1_reg_t; + +/** Type of outfifo_status_ch1 register + * Receive FIFO status of RX channel 1 + */ +typedef union { + struct { + /** outfifo_full_ch1 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t outfifo_full_ch1:1; + /** outfifo_empty_ch1 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t outfifo_empty_ch1:1; + uint32_t reserved_2:6; + /** outfifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 1 + */ + uint32_t outfifo_cnt_ch1:7; + uint32_t reserved_15:8; + /** out_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_ch1:1; + /** out_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_ch1:1; + /** out_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_ch1:1; + /** out_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_ch1:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ahb_dma_outfifo_status_ch1_reg_t; + +/** Type of out_push_ch1 register + * Push control register of TX channel 1 + */ +typedef union { + struct { + /** outfifo_wdata_ch1 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ + uint32_t outfifo_wdata_ch1:9; + /** outfifo_push_ch1 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ + uint32_t outfifo_push_ch1:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_push_ch1_reg_t; + +/** Type of out_link_ch1 register + * Push control register of TX channel 1 + */ +typedef union { + struct { + /** outlink_stop_ch1 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t outlink_stop_ch1:1; + /** outlink_start_ch1 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t outlink_start_ch1:1; + /** outlink_restart_ch1 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t outlink_restart_ch1:1; + /** outlink_park_ch1 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t outlink_park_ch1:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_link_ch1_reg_t; + +/** Type of out_state_ch1 register + * Transmit status of TX channel 1 + */ +typedef union { + struct { + /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ + uint32_t outlink_dscr_addr_ch1:18; + /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_ch1:2; + /** out_state_ch1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_ch1:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_out_state_ch1_reg_t; + +/** Type of out_eof_des_addr_ch1 register + * Transmit descriptor address when EOF occurs on TX channel 1 + */ +typedef union { + struct { + /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_eof_des_addr_ch1_reg_t; + +/** Type of out_eof_bfr_des_addr_ch1 register + * The last transmit descriptor address when EOF occurs on TX channel 1 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_eof_bfr_des_addr_ch1_reg_t; + +/** Type of out_dscr_ch1 register + * Current transmit descriptor address of TX channel 1 + */ +typedef union { + struct { + /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ + uint32_t outlink_dscr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_dscr_ch1_reg_t; + +/** Type of out_dscr_bf0_ch1 register + * The last transmit descriptor address of TX channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ + uint32_t outlink_dscr_bf0_ch1:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf0_ch1_reg_t; + +/** Type of out_dscr_bf1_ch1 register + * The second-to-last transmit descriptor address of TX channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ + uint32_t outlink_dscr_bf1_ch1:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf1_ch1_reg_t; + +/** Type of out_peri_ch1 register + * Priority register of TX channel 1 + */ +typedef union { + struct { + /** tx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 1.The larger of the value, the higher of the + * priority.. + */ + uint32_t tx_pri_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_peri_ch1_reg_t; + +/** Type of out_peri_sel_ch1 register + * Peripheral selection register of TX channel 1 + */ +typedef union { + struct { + /** peri_out_sel_ch1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ + uint32_t peri_out_sel_ch1:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_out_peri_sel_ch1_reg_t; + +/** Type of in_conf0_ch2 register + * Configuration register 0 of RX channel 2 + */ +typedef union { + struct { + /** in_rst_ch2 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. + */ + uint32_t in_rst_ch2:1; + /** in_loop_test_ch2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_ch2:1; + /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable INCR burst transfer for RX channel 2 to read + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t indscr_burst_en_ch2:1; + uint32_t reserved_3:1; + /** mem_trans_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t mem_trans_en_ch2:1; + /** in_etm_en_ch2 : R/W; bitpos: [5]; default: 0; + * Configures whether to enable ETM control for RX channel2. + * 0: Disable + * 1: Enable + */ + uint32_t in_etm_en_ch2:1; + /** in_data_burst_mode_sel_ch2 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t in_data_burst_mode_sel_ch2:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_in_conf0_ch2_reg_t; + +/** Type of in_conf1_ch2 register + * Configuration register 1 of RX channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_ch2 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for RX channel 2. + * 0: Disable + * 1: Enable + */ + uint32_t in_check_owner_ch2:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_conf1_ch2_reg_t; + +/** Type of infifo_status_ch2 register + * Receive FIFO status of RX channel 2 + */ +typedef union { + struct { + /** infifo_full_ch2 : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t infifo_full_ch2:1; + /** infifo_empty_ch2 : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t infifo_empty_ch2:1; + uint32_t reserved_2:6; + /** infifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 2 + */ + uint32_t infifo_cnt_ch2:7; + uint32_t reserved_15:8; + /** in_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_ch2:1; + /** in_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_ch2:1; + /** in_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_ch2:1; + /** in_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_ch2:1; + /** in_buf_hungry_ch2 : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_ch2:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} ahb_dma_infifo_status_ch2_reg_t; + +/** Type of in_pop_ch2 register + * Receive FIFO status of RX channel 2 + */ +typedef union { + struct { + /** infifo_rdata_ch2 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ + uint32_t infifo_rdata_ch2:12; + /** infifo_pop_ch2 : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ + uint32_t infifo_pop_ch2:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_pop_ch2_reg_t; + +/** Type of in_link_ch2 register + * Receive FIFO status of RX channel 2 + */ +typedef union { + struct { + /** inlink_auto_ret_ch2 : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ + uint32_t inlink_auto_ret_ch2:1; + /** inlink_stop_ch2 : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t inlink_stop_ch2:1; + /** inlink_start_ch2 : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t inlink_start_ch2:1; + /** inlink_restart_ch2 : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t inlink_restart_ch2:1; + /** inlink_park_ch2 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t inlink_park_ch2:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} ahb_dma_in_link_ch2_reg_t; + +/** Type of in_state_ch2 register + * Receive status of RX channel 2 + */ +typedef union { + struct { + /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; + * reserved + */ + uint32_t inlink_dscr_addr_ch2:18; + /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_ch2:2; + /** in_state_ch2 : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ + uint32_t in_state_ch2:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_in_state_ch2_reg_t; + +/** Type of in_suc_eof_des_addr_ch2 register + * Receive descriptor address when EOF occurs on RX channel 2 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_in_suc_eof_des_addr_ch2_reg_t; + +/** Type of in_err_eof_des_addr_ch2 register + * Receive descriptor address when errors occur of RX channel 2 + */ +typedef union { + struct { + /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ + uint32_t in_err_eof_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_in_err_eof_des_addr_ch2_reg_t; + +/** Type of in_dscr_ch2 register + * Current receive descriptor address of RX channel 2 + */ +typedef union { + struct { + /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ + uint32_t inlink_dscr_ch2:32; + }; + uint32_t val; +} ahb_dma_in_dscr_ch2_reg_t; + +/** Type of in_dscr_bf0_ch2 register + * The last receive descriptor address of RX channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ + uint32_t inlink_dscr_bf0_ch2:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf0_ch2_reg_t; + +/** Type of in_dscr_bf1_ch2 register + * The second-to-last receive descriptor address of RX channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ + uint32_t inlink_dscr_bf1_ch2:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf1_ch2_reg_t; + +/** Type of in_peri_ch2 register + * Priority register of RX channel 2 + */ +typedef union { + struct { + /** rx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 2.The larger of the value, the higher of the + * priority.. + */ + uint32_t rx_pri_ch2:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_in_peri_ch2_reg_t; + +/** Type of in_peri_sel_ch2 register + * Peripheral selection register of RX channel 2 + */ +typedef union { + struct { + /** peri_in_sel_ch2 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + */ + uint32_t peri_in_sel_ch2:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_in_peri_sel_ch2_reg_t; + +/** Type of out_conf0_ch2 register + * Configuration register 0 of TX channel 2 + */ +typedef union { + struct { + /** out_rst_ch2 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ + uint32_t out_rst_ch2:1; + /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch2:1; + /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ + uint32_t out_auto_wrback_ch2:1; + /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ + uint32_t out_eof_mode_ch2:1; + /** outdscr_burst_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel 2 reading + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t outdscr_burst_en_ch2:1; + uint32_t reserved_5:1; + /** out_etm_en_ch2 : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel 2. + * 0: Disable + * 1: Enable + */ + uint32_t out_etm_en_ch2:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_ch2 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t out_data_burst_mode_sel_ch2:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_conf0_ch2_reg_t; + +/** Type of out_conf1_ch2 register + * Configuration register 1 of TX channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_ch2 : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel 2. + * 0: Disable + * 1: Enable + */ + uint32_t out_check_owner_ch2:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_out_conf1_ch2_reg_t; + +/** Type of outfifo_status_ch2 register + * Receive FIFO status of RX channel 2 + */ +typedef union { + struct { + /** outfifo_full_ch2 : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t outfifo_full_ch2:1; + /** outfifo_empty_ch2 : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t outfifo_empty_ch2:1; + uint32_t reserved_2:6; + /** outfifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 2 + */ + uint32_t outfifo_cnt_ch2:7; + uint32_t reserved_15:8; + /** out_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_ch2:1; + /** out_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_ch2:1; + /** out_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_ch2:1; + /** out_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_ch2:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ahb_dma_outfifo_status_ch2_reg_t; + +/** Type of out_push_ch2 register + * Push control register of TX channel 2 + */ +typedef union { + struct { + /** outfifo_wdata_ch2 : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ + uint32_t outfifo_wdata_ch2:9; + /** outfifo_push_ch2 : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ + uint32_t outfifo_push_ch2:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_push_ch2_reg_t; + +/** Type of out_link_ch2 register + * Push control register of TX channel 2 + */ +typedef union { + struct { + /** outlink_stop_ch2 : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t outlink_stop_ch2:1; + /** outlink_start_ch2 : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t outlink_start_ch2:1; + /** outlink_restart_ch2 : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t outlink_restart_ch2:1; + /** outlink_park_ch2 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t outlink_park_ch2:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_link_ch2_reg_t; + +/** Type of out_state_ch2 register + * Transmit status of TX channel 2 + */ +typedef union { + struct { + /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ + uint32_t outlink_dscr_addr_ch2:18; + /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_ch2:2; + /** out_state_ch2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_ch2:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_out_state_ch2_reg_t; + +/** Type of out_eof_des_addr_ch2 register + * Transmit descriptor address when EOF occurs on TX channel 2 + */ +typedef union { + struct { + /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_out_eof_des_addr_ch2_reg_t; + +/** Type of out_eof_bfr_des_addr_ch2 register + * The last transmit descriptor address when EOF occurs on TX channel 2 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_out_eof_bfr_des_addr_ch2_reg_t; + +/** Type of out_dscr_ch2 register + * Current transmit descriptor address of TX channel 2 + */ +typedef union { + struct { + /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ + uint32_t outlink_dscr_ch2:32; + }; + uint32_t val; +} ahb_dma_out_dscr_ch2_reg_t; + +/** Type of out_dscr_bf0_ch2 register + * The last transmit descriptor address of TX channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ + uint32_t outlink_dscr_bf0_ch2:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf0_ch2_reg_t; + +/** Type of out_dscr_bf1_ch2 register + * The second-to-last transmit descriptor address of TX channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ + uint32_t outlink_dscr_bf1_ch2:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf1_ch2_reg_t; + +/** Type of out_peri_ch2 register + * Priority register of TX channel 2 + */ +typedef union { + struct { + /** tx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 2.The larger of the value, the higher of the + * priority.. + */ + uint32_t tx_pri_ch2:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_peri_ch2_reg_t; + +/** Type of out_peri_sel_ch2 register + * Peripheral selection register of TX channel 2 + */ +typedef union { + struct { + /** peri_out_sel_ch2 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: Dummy + * 11~15: Dummy + * \ + */ + uint32_t peri_out_sel_ch2:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_out_peri_sel_ch2_reg_t; + +/** Type of tx_ch_arb_weight_ch0 register + * TX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel0 + */ + uint32_t tx_arb_weight_value_ch0:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_tx_ch_arb_weight_ch0_reg_t; + +/** Type of tx_arb_weight_opt_dir_ch0 register + * TX channel 0 weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weight_opt_dis_ch0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t; + +/** Type of tx_ch_arb_weight_ch1 register + * TX channel 1 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel1 + */ + uint32_t tx_arb_weight_value_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_tx_ch_arb_weight_ch1_reg_t; + +/** Type of tx_arb_weight_opt_dir_ch1 register + * TX channel 1 weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weight_opt_dis_ch1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t; + +/** Type of tx_ch_arb_weight_ch2 register + * TX channel 2 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_ch2 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel2 + */ + uint32_t tx_arb_weight_value_ch2:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_tx_ch_arb_weight_ch2_reg_t; + +/** Type of tx_arb_weight_opt_dir_ch2 register + * TX channel 2 weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weight_opt_dis_ch2 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weight_opt_dis_ch2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t; + +/** Type of rx_ch_arb_weight_ch0 register + * RX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel0 + */ + uint32_t rx_arb_weight_value_ch0:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weight_ch0_reg_t; + +/** Type of rx_arb_weight_opt_dir_ch0 register + * RX channel 0 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weight_opt_dis_ch0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t; + +/** Type of rx_ch_arb_weight_ch1 register + * RX channel 1 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel1 + */ + uint32_t rx_arb_weight_value_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weight_ch1_reg_t; + +/** Type of rx_arb_weight_opt_dir_ch1 register + * RX channel 1 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weight_opt_dis_ch1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t; + +/** Type of in_link_addr_ch0 register + * Link list descriptor address configuration of RX channel 0 + */ +typedef union { + struct { + /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ + uint32_t inlink_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_link_addr_ch0_reg_t; + +/** Type of in_link_addr_ch1 register + * Link list descriptor address configuration of RX channel 1 + */ +typedef union { + struct { + /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ + uint32_t inlink_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_link_addr_ch1_reg_t; + +/** Type of in_link_addr_ch2 register + * Link list descriptor address configuration of RX channel 2 + */ +typedef union { + struct { + /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ + uint32_t inlink_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_in_link_addr_ch2_reg_t; + +/** Type of out_link_addr_ch0 register + * Link list descriptor address configuration of TX channel 0 + */ +typedef union { + struct { + /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t outlink_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_link_addr_ch0_reg_t; + +/** Type of out_link_addr_ch1 register + * Link list descriptor address configuration of TX channel 1 + */ +typedef union { + struct { + /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t outlink_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_link_addr_ch1_reg_t; + +/** Type of out_link_addr_ch2 register + * Link list descriptor address configuration of TX channel 2 + */ +typedef union { + struct { + /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t outlink_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_out_link_addr_ch2_reg_t; + +/** Type of intr_mem_start_addr register + * Accessible address space start address configuration register + */ +typedef union { + struct { + /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Accessible address space start address configuration register + */ + uint32_t access_intr_mem_start_addr:32; + }; + uint32_t val; +} ahb_dma_intr_mem_start_addr_reg_t; + +/** Type of intr_mem_end_addr register + * Accessible address space end address configuration register + */ +typedef union { + struct { + /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of accessible address space. + */ + uint32_t access_intr_mem_end_addr:32; + }; + uint32_t val; +} ahb_dma_intr_mem_end_addr_reg_t; + +/** Type of arb_timeout register + * TX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} ahb_dma_arb_timeout_reg_t; + +/** Type of weight_en register + * TX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable + */ + uint32_t weight_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_weight_en_reg_t; + +/** Type of module_clk_en register + * Module clock force on register + */ +typedef union { + struct { + /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7; + * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock + */ + uint32_t ahb_apb_sync_clk_en:3; + /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7; + * Configures whether to force on out_dscr 2~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ + uint32_t out_dscr_clk_en:3; + /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7; + * Configures whether to force on out_ctrl 2~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ + uint32_t out_ctrl_clk_en:3; + /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7; + * Configures whether to force on in_dscr 2~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ + uint32_t in_dscr_clk_en:3; + /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7; + * Configures whether to force on in_ctrl 2~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ + uint32_t in_ctrl_clk_en:3; + uint32_t reserved_15:12; + /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ + uint32_t cmd_arb_clk_en:1; + /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ + uint32_t ahbinf_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} ahb_dma_module_clk_en_reg_t; + +/** Type of ahbinf_resp_err_status0 register + * AHB response error status 0 register + */ +typedef union { + struct { + /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ + uint32_t ahbinf_resp_err_addr:32; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status0_reg_t; + +/** Type of ahbinf_resp_err_status1 register + * AHB response error status 1 register + */ +typedef union { + struct { + /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ + uint32_t ahbinf_resp_err_wr:1; + /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ + uint32_t ahbinf_resp_err_id:4; + /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0; + * Represents the AHB response error request channel id.bit[2]=1:TX channel. + * bit[2]=0:RX channel. + */ + uint32_t ahbinf_resp_err_ch_id:3; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status1_reg_t; + +/** Type of in_done_des_addr_ch0 register + * RX_done Inlink descriptor address of RX channel 0 + */ +typedef union { + struct { + /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_ch0_reg_t; + +/** Type of out_done_des_addr_ch0 register + * TX done outlink descriptor address of TX channel 0 + */ +typedef union { + struct { + /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_ch0_reg_t; + +/** Type of in_done_des_addr_ch1 register + * RX_done Inlink descriptor address of RX channel 1 + */ +typedef union { + struct { + /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_ch1_reg_t; + +/** Type of out_done_des_addr_ch1 register + * TX done outlink descriptor address of TX channel 1 + */ +typedef union { + struct { + /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_ch1_reg_t; + +/** Type of in_done_des_addr_ch2 register + * RX_done Inlink descriptor address of RX channel 2 + */ +typedef union { + struct { + /** in_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_ch2_reg_t; + +/** Type of out_done_des_addr_ch2 register + * TX done outlink descriptor address of TX channel 2 + */ +typedef union { + struct { + /** out_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_ch2:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_ch2_reg_t; + + +/** Group: Configuration Registers */ +/** Type of rx_ch_arb_weigh_chn register + * RX channel 2 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channeln + */ + uint32_t rx_ch_arb_weigh_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weigh_chn_reg_t; + +/** Type of rx_arb_weigh_opt_dir_chn register + * RX channel 2 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weigh_opt_dir_chn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; + +/** Type of arb_timeout_tx register + * TX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_tx:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} ahb_dma_arb_timeout_tx_reg_t; + +/** Type of arb_timeout_rx register + * RX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_rx:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} ahb_dma_arb_timeout_rx_reg_t; + +/** Type of weight_en_tx register + * TX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en_tx : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for TX. + * 0: Disable + * 1: Enable + */ + uint32_t weight_en_tx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_weight_en_tx_reg_t; + +/** Type of weight_en_rx register + * RX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en_rx : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for RX. + * 0: Disable + * 1: Enable + */ + uint32_t weight_en_rx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_weight_en_rx_reg_t; + + +typedef struct { + volatile ahb_dma_in_int_raw_ch0_reg_t in_int_raw_ch0; + volatile ahb_dma_in_int_st_ch0_reg_t in_int_st_ch0; + volatile ahb_dma_in_int_ena_ch0_reg_t in_int_ena_ch0; + volatile ahb_dma_in_int_clr_ch0_reg_t in_int_clr_ch0; + volatile ahb_dma_in_int_raw_ch1_reg_t in_int_raw_ch1; + volatile ahb_dma_in_int_st_ch1_reg_t in_int_st_ch1; + volatile ahb_dma_in_int_ena_ch1_reg_t in_int_ena_ch1; + volatile ahb_dma_in_int_clr_ch1_reg_t in_int_clr_ch1; + volatile ahb_dma_in_int_raw_ch2_reg_t in_int_raw_ch2; + volatile ahb_dma_in_int_st_ch2_reg_t in_int_st_ch2; + volatile ahb_dma_in_int_ena_ch2_reg_t in_int_ena_ch2; + volatile ahb_dma_in_int_clr_ch2_reg_t in_int_clr_ch2; + volatile ahb_dma_out_int_raw_ch0_reg_t out_int_raw_ch0; + volatile ahb_dma_out_int_st_ch0_reg_t out_int_st_ch0; + volatile ahb_dma_out_int_ena_ch0_reg_t out_int_ena_ch0; + volatile ahb_dma_out_int_clr_ch0_reg_t out_int_clr_ch0; + volatile ahb_dma_out_int_raw_ch1_reg_t out_int_raw_ch1; + volatile ahb_dma_out_int_st_ch1_reg_t out_int_st_ch1; + volatile ahb_dma_out_int_ena_ch1_reg_t out_int_ena_ch1; + volatile ahb_dma_out_int_clr_ch1_reg_t out_int_clr_ch1; + volatile ahb_dma_out_int_raw_ch2_reg_t out_int_raw_ch2; + volatile ahb_dma_out_int_st_ch2_reg_t out_int_st_ch2; + volatile ahb_dma_out_int_ena_ch2_reg_t out_int_ena_ch2; + volatile ahb_dma_out_int_clr_ch2_reg_t out_int_clr_ch2; + volatile ahb_dma_ahb_test_reg_t ahb_test; + volatile ahb_dma_misc_conf_reg_t misc_conf; + volatile ahb_dma_date_reg_t date; + uint32_t reserved_06c; + volatile ahb_dma_in_conf0_ch0_reg_t in_conf0_ch0; + volatile ahb_dma_in_conf1_ch0_reg_t in_conf1_ch0; + volatile ahb_dma_infifo_status_ch0_reg_t infifo_status_ch0; + volatile ahb_dma_in_pop_ch0_reg_t in_pop_ch0; + volatile ahb_dma_in_link_ch0_reg_t in_link_ch0; + volatile ahb_dma_in_state_ch0_reg_t in_state_ch0; + volatile ahb_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0; + volatile ahb_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0; + volatile ahb_dma_in_dscr_ch0_reg_t in_dscr_ch0; + volatile ahb_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0; + volatile ahb_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0; + volatile ahb_dma_in_peri_ch0_reg_t in_peri_ch0; + volatile ahb_dma_in_peri_sel_ch0_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[11]; + volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile ahb_dma_out_conf1_ch0_reg_t out_conf1_ch0; + volatile ahb_dma_outfifo_status_ch0_reg_t outfifo_status_ch0; + volatile ahb_dma_out_push_ch0_reg_t out_push_ch0; + volatile ahb_dma_out_link_ch0_reg_t out_link_ch0; + volatile ahb_dma_out_state_ch0_reg_t out_state_ch0; + volatile ahb_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0; + volatile ahb_dma_out_eof_bfr_des_addr_ch0_reg_t out_eof_bfr_des_addr_ch0; + volatile ahb_dma_out_dscr_ch0_reg_t out_dscr_ch0; + volatile ahb_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0; + volatile ahb_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0; + volatile ahb_dma_out_peri_ch0_reg_t out_peri_ch0; + volatile ahb_dma_out_peri_sel_ch0_reg_t out_peri_sel_ch0; + uint32_t reserved_104[11]; + volatile ahb_dma_in_conf0_ch1_reg_t in_conf0_ch1; + volatile ahb_dma_in_conf1_ch1_reg_t in_conf1_ch1; + volatile ahb_dma_infifo_status_ch1_reg_t infifo_status_ch1; + volatile ahb_dma_in_pop_ch1_reg_t in_pop_ch1; + volatile ahb_dma_in_link_ch1_reg_t in_link_ch1; + volatile ahb_dma_in_state_ch1_reg_t in_state_ch1; + volatile ahb_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1; + volatile ahb_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1; + volatile ahb_dma_in_dscr_ch1_reg_t in_dscr_ch1; + volatile ahb_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1; + volatile ahb_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1; + volatile ahb_dma_in_peri_ch1_reg_t in_peri_ch1; + volatile ahb_dma_in_peri_sel_ch1_reg_t in_peri_sel_ch1; + uint32_t reserved_164[11]; + volatile ahb_dma_out_conf0_ch1_reg_t out_conf0_ch1; + volatile ahb_dma_out_conf1_ch1_reg_t out_conf1_ch1; + volatile ahb_dma_outfifo_status_ch1_reg_t outfifo_status_ch1; + volatile ahb_dma_out_push_ch1_reg_t out_push_ch1; + volatile ahb_dma_out_link_ch1_reg_t out_link_ch1; + volatile ahb_dma_out_state_ch1_reg_t out_state_ch1; + volatile ahb_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1; + volatile ahb_dma_out_eof_bfr_des_addr_ch1_reg_t out_eof_bfr_des_addr_ch1; + volatile ahb_dma_out_dscr_ch1_reg_t out_dscr_ch1; + volatile ahb_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1; + volatile ahb_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1; + volatile ahb_dma_out_peri_ch1_reg_t out_peri_ch1; + volatile ahb_dma_out_peri_sel_ch1_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[11]; + volatile ahb_dma_in_conf0_ch2_reg_t in_conf0_ch2; + volatile ahb_dma_in_conf1_ch2_reg_t in_conf1_ch2; + volatile ahb_dma_infifo_status_ch2_reg_t infifo_status_ch2; + volatile ahb_dma_in_pop_ch2_reg_t in_pop_ch2; + volatile ahb_dma_in_link_ch2_reg_t in_link_ch2; + volatile ahb_dma_in_state_ch2_reg_t in_state_ch2; + volatile ahb_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2; + volatile ahb_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2; + volatile ahb_dma_in_dscr_ch2_reg_t in_dscr_ch2; + volatile ahb_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2; + volatile ahb_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2; + volatile ahb_dma_in_peri_ch2_reg_t in_peri_ch2; + volatile ahb_dma_in_peri_sel_ch2_reg_t in_peri_sel_ch2; + uint32_t reserved_224[11]; + volatile ahb_dma_out_conf0_ch2_reg_t out_conf0_ch2; + volatile ahb_dma_out_conf1_ch2_reg_t out_conf1_ch2; + volatile ahb_dma_outfifo_status_ch2_reg_t outfifo_status_ch2; + volatile ahb_dma_out_push_ch2_reg_t out_push_ch2; + volatile ahb_dma_out_link_ch2_reg_t out_link_ch2; + volatile ahb_dma_out_state_ch2_reg_t out_state_ch2; + volatile ahb_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2; + volatile ahb_dma_out_eof_bfr_des_addr_ch2_reg_t out_eof_bfr_des_addr_ch2; + volatile ahb_dma_out_dscr_ch2_reg_t out_dscr_ch2; + volatile ahb_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2; + volatile ahb_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2; + volatile ahb_dma_out_peri_ch2_reg_t out_peri_ch2; + volatile ahb_dma_out_peri_sel_ch2_reg_t out_peri_sel_ch2; + uint32_t reserved_284[22]; + volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0; + volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0; + uint32_t reserved_2e4[8]; + volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1; + volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1; + uint32_t reserved_30c[8]; + volatile ahb_dma_tx_ch_arb_weight_ch2_reg_t tx_ch_arb_weight_ch2; + volatile ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t tx_arb_weight_opt_dir_ch2; + uint32_t reserved_334[8]; + volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0; + volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0; + uint32_t reserved_35c[8]; + volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1; + volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1; + uint32_t reserved_384[8]; + volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2; + volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2; + volatile ahb_dma_in_link_addr_ch0_reg_t in_link_addr_ch0; + volatile ahb_dma_in_link_addr_ch1_reg_t in_link_addr_ch1; + volatile ahb_dma_in_link_addr_ch2_reg_t in_link_addr_ch2; + volatile ahb_dma_out_link_addr_ch0_reg_t out_link_addr_ch0; + volatile ahb_dma_out_link_addr_ch1_reg_t out_link_addr_ch1; + volatile ahb_dma_out_link_addr_ch2_reg_t out_link_addr_ch2; + volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr; + volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr; + volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx; + volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx; + volatile ahb_dma_weight_en_tx_reg_t weight_en_tx; + volatile ahb_dma_weight_en_rx_reg_t weight_en_rx; + volatile ahb_dma_arb_timeout_reg_t arb_timeout; + uint32_t reserved_3e0[8]; + volatile ahb_dma_weight_en_reg_t weight_en; + volatile ahb_dma_module_clk_en_reg_t module_clk_en; + volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0; + volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1; + volatile ahb_dma_in_done_des_addr_ch0_reg_t in_done_des_addr_ch0; + volatile ahb_dma_out_done_des_addr_ch0_reg_t out_done_des_addr_ch0; + volatile ahb_dma_in_done_des_addr_ch1_reg_t in_done_des_addr_ch1; + volatile ahb_dma_out_done_des_addr_ch1_reg_t out_done_des_addr_ch1; + volatile ahb_dma_in_done_des_addr_ch2_reg_t in_done_des_addr_ch2; + volatile ahb_dma_out_done_des_addr_ch2_reg_t out_done_des_addr_ch2; +} ahb_dma_dev_t; + +extern ahb_dma_dev_t AHB_DMA; + +#ifndef __cplusplus +_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/assist_debug_reg.h b/components/soc/esp32c5/register/soc/assist_debug_reg.h deleted file mode 100644 index 95529bc19c..0000000000 --- a/components/soc/esp32c5/register/soc/assist_debug_reg.h +++ /dev/null @@ -1,823 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register - * core0 monitor enable configuration register - */ -#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; - * Configures whether to monitor read operations in region 0 by the Data bus. \\ - * 0: Not monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; - * Configures whether to monitor write operations in region 0 by the Data bus.\\ - * 0: Not monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; - * Configures whether to monitor read operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; - * Configures whether to monitor write operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; - * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; - * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; - * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; - * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; - * Configures whether to monitor SP exceeding the lower bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; - * Configures whether to monitor SP exceeding the upper bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor enable - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enable - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register - * core0 monitor interrupt status register - */ -#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; - * The raw interrupt status of read operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; - * The raw interrupt status of write operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; - * The raw interrupt status of read operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; - * The raw interrupt status of write operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; - * The raw interrupt status of read operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; - * The raw interrupt status of write operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; - * The raw interrupt status of read operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; - * The raw interrupt status of write operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; - * The raw interrupt status of SP exceeding the lower bound address of SP monitored - * region. - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; - * The raw interrupt status of SP exceeding the upper bound address of SP monitored - * region. - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt status - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; - * DBUS busy monitor initerrupt status - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register - * core0 monitor interrupt enable register - */ -#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; - * Core0 dram0 area0 read monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; - * Core0 dram0 area0 write monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; - * Core0 dram0 area1 read monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; - * Core0 dram0 area1 write monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; - * Core0 PIF area0 read monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; - * Core0 PIF area0 write monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; - * Core0 PIF area1 read monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; - * Core0 PIF area1 write monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; - * Core0 stackpoint underflow monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; - * Core0 stackpoint overflow monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register - * core0 monitor interrupt clear register - */ -#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP - * monitored region. - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP - * monitored region. - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt clr - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt clr - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register - * Configures lower boundary address of region 0 monitored on Data bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the lower bound address of Data bus region 0. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register - * Configures upper boundary address of region 0 monitored on Data bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; - * Configures the upper bound address of Data bus region 0. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register - * Configures lower boundary address of region 1 monitored on Data bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the lower bound address of Data bus region 1. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register - * Configures upper boundary address of region 1 monitored on Data bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; - * Configures the upper bound address of Data bus region 1. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register - * Configures lower boundary address of region 0 monitored on Peripheral bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the lower bound address of Peripheral bus region 0. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register - * Configures upper boundary address of region 0 monitored on Peripheral bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; - * Configures the upper bound address of Peripheral bus region 0. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register - * Configures lower boundary address of region 1 monitored on Peripheral bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the lower bound address of Peripheral bus region 1. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register - * Configures upper boundary address of region 1 monitored on Peripheral bus - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; - * Configures the upper bound address of Peripheral bus region 1. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register - * Region monitoring HP CPU PC status register - */ -#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) -/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; - * Represents the PC value when an interrupt is triggered during region monitoring. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) -#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register - * Region monitoring HP CPU SP status register - */ -#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) -/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; - * Represents the SP value when an interrupt is triggered during region monitoring. - */ -#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) -#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register - * Configures stack monitoring lower boundary address - */ -#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) -/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * Configures the lower bound address of SP. - */ -#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) -#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register - * Configures stack monitoring upper boundary address - */ -#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) -/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the upper bound address of SP. - */ -#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) -#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_PC_REG register - * Stack monitoring HP CPU PC status register - */ -#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) -/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * Represents the PC value during stack monitoring. - */ -#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) -#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 - -/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register - * HP CPU PC logging enable register - */ -#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) -/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; - * Configures whether to enable PC logging.\\ - * 0: Disable\\ - * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ - */ -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; - * Configures whether to enable HP CPU debugging.\\ - * 0: Disable\\ - * 1: HP CPU outputs PC\\ - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 - -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * PC logging register - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; - * Represents the PC value at HP CPU reset. - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 - -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * PC logging register - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; - * Represents SP. - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 - -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31 - -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register2 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register3 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register - * exception monitor status register4 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register - * exception monitor status register5 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register - * exception monitor status register6 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register - * exception monitor status register7 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 - -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register - * cpu status register - */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; - * Represents the PC of the last command before the HP CPU enters exception. - */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 - -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register - * cpu status register - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; - * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ - * 1: In debugging mode\\ - * 0: Not in debugging mode\\ - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 -/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; - * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ - * 1: Active status\\ - * Other: Inactive status\\ - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 - -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register8 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_0 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 - -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register9 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_1 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 - -/** ASSIST_DEBUG_CLOCK_GATE_REG register - * Register clock control - */ -#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108) -/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to enable the register clock gating. \\ - * 0: Disable\\ - * 1: Enable\\ - */ -#define ASSIST_DEBUG_CLK_EN (BIT(0)) -#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) -#define ASSIST_DEBUG_CLK_EN_V 0x00000001U -#define ASSIST_DEBUG_CLK_EN_S 0 - -/** ASSIST_DEBUG_DATE_REG register - * Version control register - */ -#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) -/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; - * version register - */ -#define ASSIST_DEBUG_DATE 0x0FFFFFFFU -#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) -#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU -#define ASSIST_DEBUG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/bus_monitor_reg.h b/components/soc/esp32c5/register/soc/bus_monitor_reg.h new file mode 100644 index 0000000000..70f4deb2d1 --- /dev/null +++ b/components/soc/esp32c5/register/soc/bus_monitor_reg.h @@ -0,0 +1,629 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** BUS_MONITOR_CORE_0_MONTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x0) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Configures whether to monitor read operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Configures whether to monitor write operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Configures whether to monitor read operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Configures whether to monitor write operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Configures whether to monitor read operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Configures whether to monitor write operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Configures whether to monitor read operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Configures whether to monitor write operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Configures whether to monitor SP exceeding the lower bound address of SP monitored + * region. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Configures whether to monitor SP exceeding the upper bound address of SP monitored + * region. + * 0: Not Monitor + * 1: Monitor + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S 9 + +/** BUS_MONITOR_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x4) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status of read operations in region 0 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status of write operations in region 0 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status of read operations in region 1 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status of write operations in region 1 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * The raw interrupt status of read operations in region 0 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * The raw interrupt status of write operations in region 0 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * The raw interrupt status of read operations in region 1 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * The raw interrupt status of write operations in region 1 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * The raw interrupt status of SP exceeding the lower bound address of SP monitored + * region. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * The raw interrupt status of SP exceeding the upper bound address of SP monitored + * region. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S 9 + +/** BUS_MONITOR_CORE_0_INTR_ENA_REG register + * core0 monitor interrupt enable register + */ +#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x8) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 + +/** BUS_MONITOR_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clear register + */ +#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0xc) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Data bus. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP + * monitored region. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP + * monitored region. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S 9 + +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG register + * Configures lower boundary address of region 0 monitored on Data bus + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x10) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 0. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG register + * Configures upper boundary address of region 0 monitored on Data bus + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x14) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 0. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG register + * Configures lower boundary address of region 1 monitored on Data bus + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x18) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 1. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG register + * Configures upper boundary address of region 1 monitored on Data bus + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x1c) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 1. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG register + * Configures lower boundary address of region 0 monitored on Peripheral bus + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x20) +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 0. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S 0 + +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG register + * Configures upper boundary address of region 0 monitored on Peripheral bus + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x24) +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 0. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S 0 + +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG register + * Configures lower boundary address of region 1 monitored on Peripheral bus + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x28) +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 1. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S 0 + +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG register + * Configures upper boundary address of region 1 monitored on Peripheral bus + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x2c) +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 1. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S 0 + +/** BUS_MONITOR_CORE_0_AREA_PC_REG register + * Region monitoring HP CPU PC status register + */ +#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x30) +/** BUS_MONITOR_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value when an interrupt is triggered during region monitoring. + */ +#define BUS_MONITOR_CORE_0_AREA_PC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PC_M (BUS_MONITOR_CORE_0_AREA_PC_V << BUS_MONITOR_CORE_0_AREA_PC_S) +#define BUS_MONITOR_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PC_S 0 + +/** BUS_MONITOR_CORE_0_AREA_SP_REG register + * Region monitoring HP CPU SP status register + */ +#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0x34) +/** BUS_MONITOR_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * Represents the SP value when an interrupt is triggered during region monitoring. + */ +#define BUS_MONITOR_CORE_0_AREA_SP 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_SP_M (BUS_MONITOR_CORE_0_AREA_SP_V << BUS_MONITOR_CORE_0_AREA_SP_S) +#define BUS_MONITOR_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_SP_S 0 + +/** BUS_MONITOR_CORE_0_SP_MIN_REG register + * Configures stack monitoring lower boundary address + */ +#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x38) +/** BUS_MONITOR_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of SP. + */ +#define BUS_MONITOR_CORE_0_SP_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MIN_M (BUS_MONITOR_CORE_0_SP_MIN_V << BUS_MONITOR_CORE_0_SP_MIN_S) +#define BUS_MONITOR_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MIN_S 0 + +/** BUS_MONITOR_CORE_0_SP_MAX_REG register + * Configures stack monitoring upper boundary address + */ +#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x3c) +/** BUS_MONITOR_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the upper bound address of SP. + */ +#define BUS_MONITOR_CORE_0_SP_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MAX_M (BUS_MONITOR_CORE_0_SP_MAX_V << BUS_MONITOR_CORE_0_SP_MAX_S) +#define BUS_MONITOR_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MAX_S 0 + +/** BUS_MONITOR_CORE_0_SP_PC_REG register + * Stack monitoring HP CPU PC status register + */ +#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x40) +/** BUS_MONITOR_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value during stack monitoring. + */ +#define BUS_MONITOR_CORE_0_SP_PC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_PC_M (BUS_MONITOR_CORE_0_SP_PC_V << BUS_MONITOR_CORE_0_SP_PC_S) +#define BUS_MONITOR_CORE_0_SP_PC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_PC_S 0 + +/** BUS_MONITOR_CORE_0_RCD_EN_REG register + * HP CPU PC logging enable register + */ +#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0x44) +/** BUS_MONITOR_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable PC logging. + * 0: Disable + * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time + */ +#define BUS_MONITOR_CORE_0_RCD_RECORDEN (BIT(0)) +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_M (BUS_MONITOR_CORE_0_RCD_RECORDEN_V << BUS_MONITOR_CORE_0_RCD_RECORDEN_S) +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_V 0x00000001U +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_S 0 +/** BUS_MONITOR_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Configures whether to enable HP CPU debugging. + * 0: Disable + * 1: HP CPU outputs PC + */ +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_M (BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V << BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S 1 + +/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG register + * PC logging register + */ +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0x48) +/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value at HP CPU reset. + */ +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_M (BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V << BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S 0 + +/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG register + * PC logging register + */ +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0x4c) +/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * Represents SP. + */ +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_M (BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V << BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S 0 + +/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0x70) +/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * Represents the PC of the last command before the HP CPU enters exception. + */ +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_M (BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V << BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S) +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** BUS_MONITOR_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0x74) +/** BUS_MONITOR_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * Represents whether RISC-V CPU (HP CPU) is in debugging mode. + * 1: In debugging mode + * 0: Not in debugging mode + */ +#define BUS_MONITOR_CORE_0_DEBUG_MODE (BIT(0)) +#define BUS_MONITOR_CORE_0_DEBUG_MODE_M (BUS_MONITOR_CORE_0_DEBUG_MODE_V << BUS_MONITOR_CORE_0_DEBUG_MODE_S) +#define BUS_MONITOR_CORE_0_DEBUG_MODE_V 0x00000001U +#define BUS_MONITOR_CORE_0_DEBUG_MODE_S 0 +/** BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * Represents the status of the RISC-V CPU (HP CPU) debug module. + * 1: Active status + * Other: Inactive status + */ +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_M (BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V << BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register8 + */ +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x100) +/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register9 + */ +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x104) +/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU +#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +/** BUS_MONITOR_CLOCK_GATE_REG register + * Register clock control + */ +#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_MONITOR_BASE + 0x108) +/** BUS_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable + */ +#define BUS_MONITOR_CLK_EN (BIT(0)) +#define BUS_MONITOR_CLK_EN_M (BUS_MONITOR_CLK_EN_V << BUS_MONITOR_CLK_EN_S) +#define BUS_MONITOR_CLK_EN_V 0x00000001U +#define BUS_MONITOR_CLK_EN_S 0 + +/** BUS_MONITOR_DATE_REG register + * Version control register + */ +#define BUS_MONITOR_DATE_REG (DR_REG_BUS_MONITOR_BASE + 0x3fc) +/** BUS_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ +#define BUS_MONITOR_DATE 0x0FFFFFFFU +#define BUS_MONITOR_DATE_M (BUS_MONITOR_DATE_V << BUS_MONITOR_DATE_S) +#define BUS_MONITOR_DATE_V 0x0FFFFFFFU +#define BUS_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/assist_debug_struct.h b/components/soc/esp32c5/register/soc/bus_monitor_struct.h similarity index 60% rename from components/soc/esp32c5/register/soc/assist_debug_struct.h rename to components/soc/esp32c5/register/soc/bus_monitor_struct.h index ca55d0cb8f..4a49be11aa 100644 --- a/components/soc/esp32c5/register/soc/assist_debug_struct.h +++ b/components/soc/esp32c5/register/soc/bus_monitor_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,79 +17,71 @@ extern "C" { typedef union { struct { /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; - * Configures whether to monitor read operations in region 0 by the Data bus. \\ - * 0: Not monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ uint32_t core_0_area_dram0_0_rd_ena:1; /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; - * Configures whether to monitor write operations in region 0 by the Data bus.\\ - * 0: Not monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ uint32_t core_0_area_dram0_0_wr_ena:1; /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; - * Configures whether to monitor read operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_dram0_1_rd_ena:1; /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; - * Configures whether to monitor write operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_dram0_1_wr_ena:1; /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; - * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_0_rd_ena:1; /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; - * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_0_wr_ena:1; /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; - * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_1_rd_ena:1; /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; - * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_1_wr_ena:1; /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; * Configures whether to monitor SP exceeding the lower bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * region. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_sp_spill_min_ena:1; /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; * Configures whether to monitor SP exceeding the upper bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * region. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_sp_spill_max_ena:1; - /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor enable - */ - uint32_t core_0_iram0_exception_monitor_ena:1; - /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enable - */ - uint32_t core_0_dram0_exception_monitor_ena:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_montr_ena_reg_t; +} bus_monitor_core_0_montr_ena_reg_t; /** Type of core_0_area_dram0_0_min register * Configures lower boundary address of region 0 monitored on Data bus @@ -102,7 +94,7 @@ typedef union { uint32_t core_0_area_dram0_0_min:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_0_min_reg_t; +} bus_monitor_core_0_area_dram0_0_min_reg_t; /** Type of core_0_area_dram0_0_max register * Configures upper boundary address of region 0 monitored on Data bus @@ -115,7 +107,7 @@ typedef union { uint32_t core_0_area_dram0_0_max:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_0_max_reg_t; +} bus_monitor_core_0_area_dram0_0_max_reg_t; /** Type of core_0_area_dram0_1_min register * Configures lower boundary address of region 1 monitored on Data bus @@ -128,7 +120,7 @@ typedef union { uint32_t core_0_area_dram0_1_min:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_1_min_reg_t; +} bus_monitor_core_0_area_dram0_1_min_reg_t; /** Type of core_0_area_dram0_1_max register * Configures upper boundary address of region 1 monitored on Data bus @@ -141,7 +133,7 @@ typedef union { uint32_t core_0_area_dram0_1_max:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_1_max_reg_t; +} bus_monitor_core_0_area_dram0_1_max_reg_t; /** Type of core_0_area_pif_0_min register * Configures lower boundary address of region 0 monitored on Peripheral bus @@ -154,7 +146,7 @@ typedef union { uint32_t core_0_area_pif_0_min:32; }; uint32_t val; -} assist_debug_core_0_area_pif_0_min_reg_t; +} bus_monitor_core_0_area_pif_0_min_reg_t; /** Type of core_0_area_pif_0_max register * Configures upper boundary address of region 0 monitored on Peripheral bus @@ -167,7 +159,7 @@ typedef union { uint32_t core_0_area_pif_0_max:32; }; uint32_t val; -} assist_debug_core_0_area_pif_0_max_reg_t; +} bus_monitor_core_0_area_pif_0_max_reg_t; /** Type of core_0_area_pif_1_min register * Configures lower boundary address of region 1 monitored on Peripheral bus @@ -180,7 +172,7 @@ typedef union { uint32_t core_0_area_pif_1_min:32; }; uint32_t val; -} assist_debug_core_0_area_pif_1_min_reg_t; +} bus_monitor_core_0_area_pif_1_min_reg_t; /** Type of core_0_area_pif_1_max register * Configures upper boundary address of region 1 monitored on Peripheral bus @@ -193,7 +185,7 @@ typedef union { uint32_t core_0_area_pif_1_max:32; }; uint32_t val; -} assist_debug_core_0_area_pif_1_max_reg_t; +} bus_monitor_core_0_area_pif_1_max_reg_t; /** Type of core_0_area_pc register * Region monitoring HP CPU PC status register @@ -206,7 +198,7 @@ typedef union { uint32_t core_0_area_pc:32; }; uint32_t val; -} assist_debug_core_0_area_pc_reg_t; +} bus_monitor_core_0_area_pc_reg_t; /** Type of core_0_area_sp register * Region monitoring HP CPU SP status register @@ -219,7 +211,7 @@ typedef union { uint32_t core_0_area_sp:32; }; uint32_t val; -} assist_debug_core_0_area_sp_reg_t; +} bus_monitor_core_0_area_sp_reg_t; /** Type of core_0_sp_min register * Configures stack monitoring lower boundary address @@ -232,7 +224,7 @@ typedef union { uint32_t core_0_sp_min:32; }; uint32_t val; -} assist_debug_core_0_sp_min_reg_t; +} bus_monitor_core_0_sp_min_reg_t; /** Type of core_0_sp_max register * Configures stack monitoring upper boundary address @@ -245,7 +237,7 @@ typedef union { uint32_t core_0_sp_max:32; }; uint32_t val; -} assist_debug_core_0_sp_max_reg_t; +} bus_monitor_core_0_sp_max_reg_t; /** Type of core_0_sp_pc register * Stack monitoring HP CPU PC status register @@ -258,7 +250,7 @@ typedef union { uint32_t core_0_sp_pc:32; }; uint32_t val; -} assist_debug_core_0_sp_pc_reg_t; +} bus_monitor_core_0_sp_pc_reg_t; /** Group: interrupt configuration register */ @@ -309,18 +301,10 @@ typedef union { * region. */ uint32_t core_0_sp_spill_max_raw:1; - /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt status - */ - uint32_t core_0_iram0_exception_monitor_raw:1; - /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0; - * DBUS busy monitor initerrupt status - */ - uint32_t core_0_dram0_exception_monitor_raw:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_raw_reg_t; +} bus_monitor_core_0_intr_raw_reg_t; /** Type of core_0_intr_ena register * core0 monitor interrupt enable register @@ -367,18 +351,10 @@ typedef union { * Core0 stackpoint overflow monitor interrupt enable */ uint32_t core_0_sp_spill_max_intr_ena:1; - /** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt enable - */ - uint32_t core_0_iram0_exception_monitor_intr_ena:1; - /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enable - */ - uint32_t core_0_dram0_exception_monitor_intr_ena:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_ena_reg_t; +} bus_monitor_core_0_intr_ena_reg_t; /** Type of core_0_intr_clr register * core0 monitor interrupt clear register @@ -427,18 +403,10 @@ typedef union { * monitored region. */ uint32_t core_0_sp_spill_max_clr:1; - /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt clr - */ - uint32_t core_0_iram0_exception_monitor_clr:1; - /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt clr - */ - uint32_t core_0_dram0_exception_monitor_clr:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_clr_reg_t; +} bus_monitor_core_0_intr_clr_reg_t; /** Group: pc recording configuration register */ @@ -448,21 +416,21 @@ typedef union { typedef union { struct { /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; - * Configures whether to enable PC logging.\\ - * 0: Disable\\ - * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ + * Configures whether to enable PC logging. + * 0: Disable + * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time */ uint32_t core_0_rcd_recorden:1; /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; - * Configures whether to enable HP CPU debugging.\\ - * 0: Disable\\ - * 1: HP CPU outputs PC\\ + * Configures whether to enable HP CPU debugging. + * 0: Disable + * 1: HP CPU outputs PC */ uint32_t core_0_rcd_pdebugen:1; uint32_t reserved_2:30; }; uint32_t val; -} assist_debug_core_0_rcd_en_reg_t; +} bus_monitor_core_0_rcd_en_reg_t; /** Group: pc recording status register */ @@ -477,7 +445,7 @@ typedef union { uint32_t core_0_rcd_pdebugpc:32; }; uint32_t val; -} assist_debug_core_0_rcd_pdebugpc_reg_t; +} bus_monitor_core_0_rcd_pdebugpc_reg_t; /** Type of core_0_rcd_pdebugsp register * PC logging register @@ -490,142 +458,10 @@ typedef union { uint32_t core_0_rcd_pdebugsp:32; }; uint32_t val; -} assist_debug_core_0_rcd_pdebugsp_reg_t; +} bus_monitor_core_0_rcd_pdebugsp_reg_t; /** Group: exception monitor register */ -/** Type of core_0_iram0_exception_monitor_0 register - * exception monitor status register0 - */ -typedef union { - struct { - /** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_0 - */ - uint32_t core_0_iram0_recording_addr_0:30; - /** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_0 - */ - uint32_t core_0_iram0_recording_wr_0:1; - /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_0 - */ - uint32_t core_0_iram0_recording_loadstore_0:1; - }; - uint32_t val; -} assist_debug_core_0_iram0_exception_monitor_0_reg_t; - -/** Type of core_0_iram0_exception_monitor_1 register - * exception monitor status register1 - */ -typedef union { - struct { - /** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_1 - */ - uint32_t core_0_iram0_recording_addr_1:30; - /** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_1 - */ - uint32_t core_0_iram0_recording_wr_1:1; - /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_1 - */ - uint32_t core_0_iram0_recording_loadstore_1:1; - }; - uint32_t val; -} assist_debug_core_0_iram0_exception_monitor_1_reg_t; - -/** Type of core_0_dram0_exception_monitor_0 register - * exception monitor status register2 - */ -typedef union { - struct { - /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_0 - */ - uint32_t core_0_dram0_recording_wr_0:1; - /** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_0 - */ - uint32_t core_0_dram0_recording_byteen_0:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_0_reg_t; - -/** Type of core_0_dram0_exception_monitor_1 register - * exception monitor status register3 - */ -typedef union { - struct { - /** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_0 - */ - uint32_t core_0_dram0_recording_addr_0:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_1_reg_t; - -/** Type of core_0_dram0_exception_monitor_2 register - * exception monitor status register4 - */ -typedef union { - struct { - /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_0 - */ - uint32_t core_0_dram0_recording_pc_0:32; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_2_reg_t; - -/** Type of core_0_dram0_exception_monitor_3 register - * exception monitor status register5 - */ -typedef union { - struct { - /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_1 - */ - uint32_t core_0_dram0_recording_wr_1:1; - /** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_1 - */ - uint32_t core_0_dram0_recording_byteen_1:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_3_reg_t; - -/** Type of core_0_dram0_exception_monitor_4 register - * exception monitor status register6 - */ -typedef union { - struct { - /** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_1 - */ - uint32_t core_0_dram0_recording_addr_1:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_4_reg_t; - -/** Type of core_0_dram0_exception_monitor_5 register - * exception monitor status register7 - */ -typedef union { - struct { - /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_1 - */ - uint32_t core_0_dram0_recording_pc_1:32; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_5_reg_t; - /** Type of core_x_iram0_dram0_exception_monitor_0 register * exception monitor status register8 */ @@ -638,7 +474,7 @@ typedef union { uint32_t reserved_20:12; }; uint32_t val; -} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t; +} bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t; /** Type of core_x_iram0_dram0_exception_monitor_1 register * exception monitor status register9 @@ -652,7 +488,7 @@ typedef union { uint32_t reserved_20:12; }; uint32_t val; -} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t; +} bus_monitor_core_x_iram0_dram0_exception_monitor_1_reg_t; /** Group: cpu status registers */ @@ -667,7 +503,7 @@ typedef union { uint32_t core_0_lastpc_before_exc:32; }; uint32_t val; -} assist_debug_core_0_lastpc_before_exception_reg_t; +} bus_monitor_core_0_lastpc_before_exception_reg_t; /** Type of core_0_debug_mode register * cpu status register @@ -675,21 +511,21 @@ typedef union { typedef union { struct { /** core_0_debug_mode : RO; bitpos: [0]; default: 0; - * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ - * 1: In debugging mode\\ - * 0: Not in debugging mode\\ + * Represents whether RISC-V CPU (HP CPU) is in debugging mode. + * 1: In debugging mode + * 0: Not in debugging mode */ uint32_t core_0_debug_mode:1; /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; - * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ - * 1: Active status\\ - * Other: Inactive status\\ + * Represents the status of the RISC-V CPU (HP CPU) debug module. + * 1: Active status + * Other: Inactive status */ uint32_t core_0_debug_module_active:1; uint32_t reserved_2:30; }; uint32_t val; -} assist_debug_core_0_debug_mode_reg_t; +} bus_monitor_core_0_debug_mode_reg_t; /** Group: Configuration Registers */ @@ -699,15 +535,15 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to enable the register clock gating. \\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} assist_debug_clock_gate_reg_t; +} bus_monitor_clock_gate_reg_t; /** Type of date register * Version control register @@ -721,52 +557,45 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} assist_debug_date_reg_t; +} bus_monitor_date_reg_t; typedef struct { - volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena; - volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; - volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; - volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; - volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; - volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; - volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; - volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; - volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; - volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; - volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; - volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; - volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; - volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; - volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; - volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; - volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; - volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; - volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; - volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; - volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0; - volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1; - volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0; - volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1; - volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2; - volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3; - volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4; - volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5; - volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; - volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + volatile bus_monitor_core_0_montr_ena_reg_t core_0_montr_ena; + volatile bus_monitor_core_0_intr_raw_reg_t core_0_intr_raw; + volatile bus_monitor_core_0_intr_ena_reg_t core_0_intr_ena; + volatile bus_monitor_core_0_intr_clr_reg_t core_0_intr_clr; + volatile bus_monitor_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile bus_monitor_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile bus_monitor_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile bus_monitor_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile bus_monitor_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile bus_monitor_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile bus_monitor_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile bus_monitor_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile bus_monitor_core_0_area_pc_reg_t core_0_area_pc; + volatile bus_monitor_core_0_area_sp_reg_t core_0_area_sp; + volatile bus_monitor_core_0_sp_min_reg_t core_0_sp_min; + volatile bus_monitor_core_0_sp_max_reg_t core_0_sp_max; + volatile bus_monitor_core_0_sp_pc_reg_t core_0_sp_pc; + volatile bus_monitor_core_0_rcd_en_reg_t core_0_rcd_en; + volatile bus_monitor_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile bus_monitor_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + uint32_t reserved_050[8]; + volatile bus_monitor_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile bus_monitor_core_0_debug_mode_reg_t core_0_debug_mode; uint32_t reserved_078[34]; - volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; - volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; - volatile assist_debug_clock_gate_reg_t clock_gate; + volatile bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; + volatile bus_monitor_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; + volatile bus_monitor_clock_gate_reg_t clock_gate; uint32_t reserved_10c[188]; - volatile assist_debug_date_reg_t date; -} assist_debug_dev_t; + volatile bus_monitor_date_reg_t date; +} bus_monitor_dev_t; -extern assist_debug_dev_t ASSIST_DEBUG; +extern bus_monitor_dev_t BUS_MONITOR; #ifndef __cplusplus -_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/cpu_apm_reg.h b/components/soc/esp32c5/register/soc/cpu_apm_reg.h new file mode 100644 index 0000000000..9c6a7cbe52 --- /dev/null +++ b/components/soc/esp32c5/register/soc/cpu_apm_reg.h @@ -0,0 +1,1242 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CPU_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) +/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ +#define CPU_APM_REGION_FILTER_EN 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) +#define CPU_APM_REGION_FILTER_EN_V 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_S 0 + +/** CPU_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4) +/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_M (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S) +#define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_S 0 +/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) +#define CPU_APM_REGION0_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_S 12 +/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_M (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S) +#define CPU_APM_REGION0_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_S 19 + +/** CPU_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8) +/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_M (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S) +#define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_S 0 +/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) +#define CPU_APM_REGION0_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_S 12 +/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_M (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S) +#define CPU_APM_REGION0_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_S 19 + +/** CPU_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) +/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_X (BIT(0)) +#define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) +#define CPU_APM_REGION0_R0_X_V 0x00000001U +#define CPU_APM_REGION0_R0_X_S 0 +/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_W (BIT(1)) +#define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) +#define CPU_APM_REGION0_R0_W_V 0x00000001U +#define CPU_APM_REGION0_R0_W_S 1 +/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_R (BIT(2)) +#define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) +#define CPU_APM_REGION0_R0_R_V 0x00000001U +#define CPU_APM_REGION0_R0_R_S 2 +/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_X (BIT(4)) +#define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) +#define CPU_APM_REGION0_R1_X_V 0x00000001U +#define CPU_APM_REGION0_R1_X_S 4 +/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_W (BIT(5)) +#define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) +#define CPU_APM_REGION0_R1_W_V 0x00000001U +#define CPU_APM_REGION0_R1_W_S 5 +/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_R (BIT(6)) +#define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) +#define CPU_APM_REGION0_R1_R_V 0x00000001U +#define CPU_APM_REGION0_R1_R_S 6 +/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_X (BIT(8)) +#define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) +#define CPU_APM_REGION0_R2_X_V 0x00000001U +#define CPU_APM_REGION0_R2_X_S 8 +/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_W (BIT(9)) +#define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) +#define CPU_APM_REGION0_R2_W_V 0x00000001U +#define CPU_APM_REGION0_R2_W_S 9 +/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_R (BIT(10)) +#define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) +#define CPU_APM_REGION0_R2_R_V 0x00000001U +#define CPU_APM_REGION0_R2_R_S 10 +/** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION0_LOCK (BIT(11)) +#define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) +#define CPU_APM_REGION0_LOCK_V 0x00000001U +#define CPU_APM_REGION0_LOCK_S 11 + +/** CPU_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10) +/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_M (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S) +#define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_S 0 +/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) +#define CPU_APM_REGION1_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_S 12 +/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_M (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S) +#define CPU_APM_REGION1_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_S 19 + +/** CPU_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14) +/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_M (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S) +#define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_S 0 +/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) +#define CPU_APM_REGION1_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_S 12 +/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_M (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S) +#define CPU_APM_REGION1_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_S 19 + +/** CPU_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) +/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_X (BIT(0)) +#define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) +#define CPU_APM_REGION1_R0_X_V 0x00000001U +#define CPU_APM_REGION1_R0_X_S 0 +/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_W (BIT(1)) +#define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) +#define CPU_APM_REGION1_R0_W_V 0x00000001U +#define CPU_APM_REGION1_R0_W_S 1 +/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_R (BIT(2)) +#define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) +#define CPU_APM_REGION1_R0_R_V 0x00000001U +#define CPU_APM_REGION1_R0_R_S 2 +/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_X (BIT(4)) +#define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) +#define CPU_APM_REGION1_R1_X_V 0x00000001U +#define CPU_APM_REGION1_R1_X_S 4 +/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_W (BIT(5)) +#define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) +#define CPU_APM_REGION1_R1_W_V 0x00000001U +#define CPU_APM_REGION1_R1_W_S 5 +/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_R (BIT(6)) +#define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) +#define CPU_APM_REGION1_R1_R_V 0x00000001U +#define CPU_APM_REGION1_R1_R_S 6 +/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_X (BIT(8)) +#define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) +#define CPU_APM_REGION1_R2_X_V 0x00000001U +#define CPU_APM_REGION1_R2_X_S 8 +/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_W (BIT(9)) +#define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) +#define CPU_APM_REGION1_R2_W_V 0x00000001U +#define CPU_APM_REGION1_R2_W_S 9 +/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_R (BIT(10)) +#define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) +#define CPU_APM_REGION1_R2_R_V 0x00000001U +#define CPU_APM_REGION1_R2_R_S 10 +/** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION1_LOCK (BIT(11)) +#define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) +#define CPU_APM_REGION1_LOCK_V 0x00000001U +#define CPU_APM_REGION1_LOCK_S 11 + +/** CPU_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c) +/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_M (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S) +#define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_S 0 +/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) +#define CPU_APM_REGION2_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_S 12 +/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_M (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S) +#define CPU_APM_REGION2_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_S 19 + +/** CPU_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20) +/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_M (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S) +#define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_S 0 +/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) +#define CPU_APM_REGION2_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_S 12 +/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_M (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S) +#define CPU_APM_REGION2_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_S 19 + +/** CPU_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) +/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_X (BIT(0)) +#define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) +#define CPU_APM_REGION2_R0_X_V 0x00000001U +#define CPU_APM_REGION2_R0_X_S 0 +/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_W (BIT(1)) +#define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) +#define CPU_APM_REGION2_R0_W_V 0x00000001U +#define CPU_APM_REGION2_R0_W_S 1 +/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_R (BIT(2)) +#define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) +#define CPU_APM_REGION2_R0_R_V 0x00000001U +#define CPU_APM_REGION2_R0_R_S 2 +/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_X (BIT(4)) +#define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) +#define CPU_APM_REGION2_R1_X_V 0x00000001U +#define CPU_APM_REGION2_R1_X_S 4 +/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_W (BIT(5)) +#define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) +#define CPU_APM_REGION2_R1_W_V 0x00000001U +#define CPU_APM_REGION2_R1_W_S 5 +/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_R (BIT(6)) +#define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) +#define CPU_APM_REGION2_R1_R_V 0x00000001U +#define CPU_APM_REGION2_R1_R_S 6 +/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_X (BIT(8)) +#define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) +#define CPU_APM_REGION2_R2_X_V 0x00000001U +#define CPU_APM_REGION2_R2_X_S 8 +/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_W (BIT(9)) +#define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) +#define CPU_APM_REGION2_R2_W_V 0x00000001U +#define CPU_APM_REGION2_R2_W_S 9 +/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_R (BIT(10)) +#define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) +#define CPU_APM_REGION2_R2_R_V 0x00000001U +#define CPU_APM_REGION2_R2_R_S 10 +/** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION2_LOCK (BIT(11)) +#define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) +#define CPU_APM_REGION2_LOCK_V 0x00000001U +#define CPU_APM_REGION2_LOCK_S 11 + +/** CPU_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28) +/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_M (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S) +#define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_S 0 +/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) +#define CPU_APM_REGION3_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_S 12 +/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_M (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S) +#define CPU_APM_REGION3_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_S 19 + +/** CPU_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c) +/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_M (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S) +#define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_S 0 +/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) +#define CPU_APM_REGION3_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_S 12 +/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_M (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S) +#define CPU_APM_REGION3_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_S 19 + +/** CPU_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) +/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_X (BIT(0)) +#define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) +#define CPU_APM_REGION3_R0_X_V 0x00000001U +#define CPU_APM_REGION3_R0_X_S 0 +/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_W (BIT(1)) +#define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) +#define CPU_APM_REGION3_R0_W_V 0x00000001U +#define CPU_APM_REGION3_R0_W_S 1 +/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_R (BIT(2)) +#define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) +#define CPU_APM_REGION3_R0_R_V 0x00000001U +#define CPU_APM_REGION3_R0_R_S 2 +/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_X (BIT(4)) +#define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) +#define CPU_APM_REGION3_R1_X_V 0x00000001U +#define CPU_APM_REGION3_R1_X_S 4 +/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_W (BIT(5)) +#define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) +#define CPU_APM_REGION3_R1_W_V 0x00000001U +#define CPU_APM_REGION3_R1_W_S 5 +/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_R (BIT(6)) +#define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) +#define CPU_APM_REGION3_R1_R_V 0x00000001U +#define CPU_APM_REGION3_R1_R_S 6 +/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_X (BIT(8)) +#define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) +#define CPU_APM_REGION3_R2_X_V 0x00000001U +#define CPU_APM_REGION3_R2_X_S 8 +/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_W (BIT(9)) +#define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) +#define CPU_APM_REGION3_R2_W_V 0x00000001U +#define CPU_APM_REGION3_R2_W_S 9 +/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_R (BIT(10)) +#define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) +#define CPU_APM_REGION3_R2_R_V 0x00000001U +#define CPU_APM_REGION3_R2_R_S 10 +/** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION3_LOCK (BIT(11)) +#define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) +#define CPU_APM_REGION3_LOCK_V 0x00000001U +#define CPU_APM_REGION3_LOCK_S 11 + +/** CPU_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34) +/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_M (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S) +#define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_S 0 +/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) +#define CPU_APM_REGION4_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_S 12 +/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_M (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S) +#define CPU_APM_REGION4_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_S 19 + +/** CPU_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38) +/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_M (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S) +#define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_S 0 +/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) +#define CPU_APM_REGION4_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_S 12 +/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_M (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S) +#define CPU_APM_REGION4_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_S 19 + +/** CPU_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) +/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_X (BIT(0)) +#define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) +#define CPU_APM_REGION4_R0_X_V 0x00000001U +#define CPU_APM_REGION4_R0_X_S 0 +/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_W (BIT(1)) +#define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) +#define CPU_APM_REGION4_R0_W_V 0x00000001U +#define CPU_APM_REGION4_R0_W_S 1 +/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_R (BIT(2)) +#define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) +#define CPU_APM_REGION4_R0_R_V 0x00000001U +#define CPU_APM_REGION4_R0_R_S 2 +/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_X (BIT(4)) +#define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) +#define CPU_APM_REGION4_R1_X_V 0x00000001U +#define CPU_APM_REGION4_R1_X_S 4 +/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_W (BIT(5)) +#define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) +#define CPU_APM_REGION4_R1_W_V 0x00000001U +#define CPU_APM_REGION4_R1_W_S 5 +/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_R (BIT(6)) +#define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) +#define CPU_APM_REGION4_R1_R_V 0x00000001U +#define CPU_APM_REGION4_R1_R_S 6 +/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_X (BIT(8)) +#define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) +#define CPU_APM_REGION4_R2_X_V 0x00000001U +#define CPU_APM_REGION4_R2_X_S 8 +/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_W (BIT(9)) +#define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) +#define CPU_APM_REGION4_R2_W_V 0x00000001U +#define CPU_APM_REGION4_R2_W_S 9 +/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_R (BIT(10)) +#define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) +#define CPU_APM_REGION4_R2_R_V 0x00000001U +#define CPU_APM_REGION4_R2_R_S 10 +/** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION4_LOCK (BIT(11)) +#define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) +#define CPU_APM_REGION4_LOCK_V 0x00000001U +#define CPU_APM_REGION4_LOCK_S 11 + +/** CPU_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40) +/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_M (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S) +#define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_S 0 +/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) +#define CPU_APM_REGION5_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_S 12 +/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_M (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S) +#define CPU_APM_REGION5_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_S 19 + +/** CPU_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44) +/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_M (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S) +#define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_S 0 +/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) +#define CPU_APM_REGION5_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_S 12 +/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_M (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S) +#define CPU_APM_REGION5_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_S 19 + +/** CPU_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) +/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_X (BIT(0)) +#define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) +#define CPU_APM_REGION5_R0_X_V 0x00000001U +#define CPU_APM_REGION5_R0_X_S 0 +/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_W (BIT(1)) +#define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) +#define CPU_APM_REGION5_R0_W_V 0x00000001U +#define CPU_APM_REGION5_R0_W_S 1 +/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_R (BIT(2)) +#define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) +#define CPU_APM_REGION5_R0_R_V 0x00000001U +#define CPU_APM_REGION5_R0_R_S 2 +/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_X (BIT(4)) +#define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) +#define CPU_APM_REGION5_R1_X_V 0x00000001U +#define CPU_APM_REGION5_R1_X_S 4 +/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_W (BIT(5)) +#define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) +#define CPU_APM_REGION5_R1_W_V 0x00000001U +#define CPU_APM_REGION5_R1_W_S 5 +/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_R (BIT(6)) +#define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) +#define CPU_APM_REGION5_R1_R_V 0x00000001U +#define CPU_APM_REGION5_R1_R_S 6 +/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_X (BIT(8)) +#define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) +#define CPU_APM_REGION5_R2_X_V 0x00000001U +#define CPU_APM_REGION5_R2_X_S 8 +/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_W (BIT(9)) +#define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) +#define CPU_APM_REGION5_R2_W_V 0x00000001U +#define CPU_APM_REGION5_R2_W_S 9 +/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_R (BIT(10)) +#define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) +#define CPU_APM_REGION5_R2_R_V 0x00000001U +#define CPU_APM_REGION5_R2_R_S 10 +/** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION5_LOCK (BIT(11)) +#define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) +#define CPU_APM_REGION5_LOCK_V 0x00000001U +#define CPU_APM_REGION5_LOCK_S 11 + +/** CPU_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c) +/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_M (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S) +#define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_S 0 +/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) +#define CPU_APM_REGION6_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_S 12 +/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_M (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S) +#define CPU_APM_REGION6_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_S 19 + +/** CPU_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50) +/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_M (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S) +#define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_S 0 +/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) +#define CPU_APM_REGION6_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_S 12 +/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_M (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S) +#define CPU_APM_REGION6_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_S 19 + +/** CPU_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) +/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_X (BIT(0)) +#define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) +#define CPU_APM_REGION6_R0_X_V 0x00000001U +#define CPU_APM_REGION6_R0_X_S 0 +/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_W (BIT(1)) +#define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) +#define CPU_APM_REGION6_R0_W_V 0x00000001U +#define CPU_APM_REGION6_R0_W_S 1 +/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_R (BIT(2)) +#define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) +#define CPU_APM_REGION6_R0_R_V 0x00000001U +#define CPU_APM_REGION6_R0_R_S 2 +/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_X (BIT(4)) +#define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) +#define CPU_APM_REGION6_R1_X_V 0x00000001U +#define CPU_APM_REGION6_R1_X_S 4 +/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_W (BIT(5)) +#define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) +#define CPU_APM_REGION6_R1_W_V 0x00000001U +#define CPU_APM_REGION6_R1_W_S 5 +/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_R (BIT(6)) +#define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) +#define CPU_APM_REGION6_R1_R_V 0x00000001U +#define CPU_APM_REGION6_R1_R_S 6 +/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_X (BIT(8)) +#define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) +#define CPU_APM_REGION6_R2_X_V 0x00000001U +#define CPU_APM_REGION6_R2_X_S 8 +/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_W (BIT(9)) +#define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) +#define CPU_APM_REGION6_R2_W_V 0x00000001U +#define CPU_APM_REGION6_R2_W_S 9 +/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_R (BIT(10)) +#define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) +#define CPU_APM_REGION6_R2_R_V 0x00000001U +#define CPU_APM_REGION6_R2_R_S 10 +/** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION6_LOCK (BIT(11)) +#define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) +#define CPU_APM_REGION6_LOCK_V 0x00000001U +#define CPU_APM_REGION6_LOCK_S 11 + +/** CPU_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58) +/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_M (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S) +#define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_S 0 +/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) +#define CPU_APM_REGION7_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_S 12 +/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_M (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S) +#define CPU_APM_REGION7_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_S 19 + +/** CPU_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c) +/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_M (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S) +#define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_S 0 +/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) +#define CPU_APM_REGION7_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_S 12 +/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_M (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S) +#define CPU_APM_REGION7_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_S 19 + +/** CPU_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) +/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_X (BIT(0)) +#define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) +#define CPU_APM_REGION7_R0_X_V 0x00000001U +#define CPU_APM_REGION7_R0_X_S 0 +/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_W (BIT(1)) +#define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) +#define CPU_APM_REGION7_R0_W_V 0x00000001U +#define CPU_APM_REGION7_R0_W_S 1 +/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_R (BIT(2)) +#define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) +#define CPU_APM_REGION7_R0_R_V 0x00000001U +#define CPU_APM_REGION7_R0_R_S 2 +/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_X (BIT(4)) +#define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) +#define CPU_APM_REGION7_R1_X_V 0x00000001U +#define CPU_APM_REGION7_R1_X_S 4 +/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_W (BIT(5)) +#define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) +#define CPU_APM_REGION7_R1_W_V 0x00000001U +#define CPU_APM_REGION7_R1_W_S 5 +/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_R (BIT(6)) +#define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) +#define CPU_APM_REGION7_R1_R_V 0x00000001U +#define CPU_APM_REGION7_R1_R_S 6 +/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_X (BIT(8)) +#define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) +#define CPU_APM_REGION7_R2_X_V 0x00000001U +#define CPU_APM_REGION7_R2_X_S 8 +/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_W (BIT(9)) +#define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) +#define CPU_APM_REGION7_R2_W_V 0x00000001U +#define CPU_APM_REGION7_R2_W_S 9 +/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_R (BIT(10)) +#define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) +#define CPU_APM_REGION7_R2_R_V 0x00000001U +#define CPU_APM_REGION7_R2_R_S 10 +/** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION7_LOCK (BIT(11)) +#define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) +#define CPU_APM_REGION7_LOCK_V 0x00000001U +#define CPU_APM_REGION7_LOCK_S 11 + +/** CPU_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) +/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define CPU_APM_M0_FUNC_EN (BIT(0)) +#define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) +#define CPU_APM_M0_FUNC_EN_V 0x00000001U +#define CPU_APM_M0_FUNC_EN_S 0 +/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define CPU_APM_M1_FUNC_EN (BIT(1)) +#define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) +#define CPU_APM_M1_FUNC_EN_V 0x00000001U +#define CPU_APM_M1_FUNC_EN_S 1 + +/** CPU_APM_M0_STATUS_REG register + * M0 status register + */ +#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) +/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) +#define CPU_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) +/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) +/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) +#define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_S 0 +/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M0_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) +#define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_S 16 +/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M0_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) +#define CPU_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_S 18 + +/** CPU_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) +/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) +#define CPU_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M1_STATUS_REG register + * M1 status register + */ +#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) +/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) +#define CPU_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) +/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) +/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) +#define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_S 0 +/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M1_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) +#define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_S 16 +/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M1_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) +#define CPU_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_S 18 + +/** CPU_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) +/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) +#define CPU_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_S 0 + +/** CPU_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) +/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M0_APM_INT_EN (BIT(0)) +#define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) +#define CPU_APM_M0_APM_INT_EN_V 0x00000001U +#define CPU_APM_M0_APM_INT_EN_S 0 +/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M1_APM_INT_EN (BIT(1)) +#define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) +#define CPU_APM_M1_APM_INT_EN_V 0x00000001U +#define CPU_APM_M1_APM_INT_EN_S 1 + +/** CPU_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) +/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define CPU_APM_CLK_EN (BIT(0)) +#define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) +#define CPU_APM_CLK_EN_V 0x00000001U +#define CPU_APM_CLK_EN_S 0 + +/** CPU_APM_DATE_REG register + * Version control register + */ +#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x7fc) +/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37769360; + * Version control register. + */ +#define CPU_APM_DATE 0x0FFFFFFFU +#define CPU_APM_DATE_M (CPU_APM_DATE_V << CPU_APM_DATE_S) +#define CPU_APM_DATE_V 0x0FFFFFFFU +#define CPU_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/cpu_apm_struct.h b/components/soc/esp32c5/register/soc/cpu_apm_struct.h new file mode 100644 index 0000000000..c8198eeecb --- /dev/null +++ b/components/soc/esp32c5/register/soc/cpu_apm_struct.h @@ -0,0 +1,404 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ + uint32_t region_filter_en:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} cpu_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region n. + */ + uint32_t regionn_addr_start_l:12; + /** regionn_addr_start : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region n. + */ + uint32_t regionn_addr_start:7; + /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region n. + */ + uint32_t regionn_addr_start_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_start_reg_t; + +/** Type of regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region n. + */ + uint32_t regionn_addr_end_l:12; + /** regionn_addr_end : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region n. + */ + uint32_t regionn_addr_end:7; + /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region n. + */ + uint32_t regionn_addr_end_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_x:1; + /** regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_w:1; + /** regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_r:1; + uint32_t reserved_3:1; + /** regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_x:1; + /** regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_w:1; + /** regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_r:1; + uint32_t reserved_7:1; + /** regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_x:1; + /** regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_w:1; + /** regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_r:1; + /** regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cpu_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_func_en:1; + /** m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37769360; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cpu_apm_date_reg_t; + + +typedef struct { + volatile cpu_apm_region_filter_en_reg_t region_filter_en; + volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end; + volatile cpu_apm_regionn_attr_reg_t region0_attr; + volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end; + volatile cpu_apm_regionn_attr_reg_t region1_attr; + volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end; + volatile cpu_apm_regionn_attr_reg_t region2_attr; + volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end; + volatile cpu_apm_regionn_attr_reg_t region3_attr; + volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end; + volatile cpu_apm_regionn_attr_reg_t region4_attr; + volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end; + volatile cpu_apm_regionn_attr_reg_t region5_attr; + volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end; + volatile cpu_apm_regionn_attr_reg_t region6_attr; + volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end; + volatile cpu_apm_regionn_attr_reg_t region7_attr; + uint32_t reserved_064[24]; + volatile cpu_apm_func_ctrl_reg_t func_ctrl; + volatile cpu_apm_m0_status_reg_t m0_status; + volatile cpu_apm_m0_status_clr_reg_t m0_status_clr; + volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile cpu_apm_m1_status_reg_t m1_status; + volatile cpu_apm_m1_status_clr_reg_t m1_status_clr; + volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1; + uint32_t reserved_0e8[12]; + volatile cpu_apm_int_en_reg_t int_en; + uint32_t reserved_11c[439]; + volatile cpu_apm_clock_gate_reg_t clock_gate; + volatile cpu_apm_date_reg_t date; +} cpu_apm_dev_t; + +extern cpu_apm_dev_t CPU_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(cpu_apm_dev_t) == 0x800, "Invalid size of cpu_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/ecc_mult_reg.h b/components/soc/esp32c5/register/soc/ecc_mult_reg.h index 0da5d23e77..4570901f04 100644 --- a/components/soc/esp32c5/register/soc/ecc_mult_reg.h +++ b/components/soc/esp32c5/register/soc/ecc_mult_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -65,69 +65,71 @@ extern "C" { #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; * Configures whether to start calculation of ECC Accelerator. This bit will be - * self-cleared after the calculation is done. \\ - * 0: No effect\\ - * 1: Start calculation of ECC Accelerator\\ + * self-cleared after the calculation is done. + * 0: No effect + * 1: Start calculation of ECC Accelerator */ #define ECC_MULT_START (BIT(0)) #define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) #define ECC_MULT_START_V 0x00000001U #define ECC_MULT_START_S 0 /** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; - * Configures whether to reset ECC Accelerator. \\ - * 0: No effect\\ - * 1: Reset\\ + * Configures whether to reset ECC Accelerator. + * 0: No effect + * 1: Reset */ #define ECC_MULT_RESET (BIT(1)) #define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) #define ECC_MULT_RESET_V 0x00000001U #define ECC_MULT_RESET_S 1 -/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; - * Configures the key length mode bit of ECC Accelerator. \\ - * 0: P-192\\ - * 1: P-256\\ +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. + * 0: P-192 + * 1: P-256 + * 2: P-384 + * 3: SM2 */ -#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH 0x00000003U #define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) -#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_V 0x00000003U #define ECC_MULT_KEY_LENGTH_S 2 -/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; - * Configures the mod base of mod operation, only valid in work_mode 8-11. \\ - * 0: n(order of curve)\\ - * 1: p(mod base of curve)\\ +/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. + * 0: n(order of curve) + * 1: p(mod base of curve) */ -#define ECC_MULT_MOD_BASE (BIT(3)) +#define ECC_MULT_MOD_BASE (BIT(4)) #define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) #define ECC_MULT_MOD_BASE_V 0x00000001U -#define ECC_MULT_MOD_BASE_S 3 -/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; - * Configures the work mode of ECC Accelerator.\\ - * 0: Point Multi mode\\ - * 1: Reserved\\ - * 2: Point Verif mode\\ - * 3: Point Verif + Multi mode\\ - * 4: Jacobian Point Multi mode\\ - * 5: Reserved\\ - * 6: Jacobian Point Verif mode\\ - * 7: Point Verif + Jacobian Point Multi mode\\ - * 8: Mod Add mode\\ - * 9. Mod Sub mode\\ - * 10: Mod Multi mode\\ - * 11: Mod Div mode\\ +#define ECC_MULT_MOD_BASE_S 4 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0; + * Configures the work mode of ECC Accelerator. + * 0: Point Multi mode + * 1: Reserved + * 2: Point Verif mode + * 3: Point Verif + Multi mode + * 4: Jacobian Point Multi mode + * 5: Reserved + * 6: Jacobian Point Verif mode + * 7: Point Verif + Jacobian Point Multi mode + * 8: Mod Add mode + * 9. Mod Sub mode + * 10: Mod Multi mode + * 11: Mod Div mode */ #define ECC_MULT_WORK_MODE 0x0000000FU #define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) #define ECC_MULT_WORK_MODE_V 0x0000000FU -#define ECC_MULT_WORK_MODE_S 4 -/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; - * Configures the security mode of ECC Accelerator.\\ - * 0: no secure function enabled.\\ - * 1: enable constant-time calculation in all point multiplication modes.\\ +#define ECC_MULT_WORK_MODE_S 5 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0; + * Configures the security mode of ECC Accelerator. + * 0: no secure function enabled. + * 1: enable constant-time calculation in all point multiplication modes. */ -#define ECC_MULT_SECURITY_MODE (BIT(8)) +#define ECC_MULT_SECURITY_MODE (BIT(9)) #define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) #define ECC_MULT_SECURITY_MODE_V 0x00000001U -#define ECC_MULT_SECURITY_MODE_S 8 +#define ECC_MULT_SECURITY_MODE_S 9 /** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; * Represents the verification result of ECC Accelerator, valid only when calculation * is done. @@ -137,18 +139,18 @@ extern "C" { #define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U #define ECC_MULT_VERIFICATION_RESULT_S 29 /** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; - * Configures whether to force on register clock gate. \\ - * 0: No effect\\ - * 1: Force on\\ + * Configures whether to force on register clock gate. + * 0: No effect + * 1: Force on */ #define ECC_MULT_CLK_EN (BIT(30)) #define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) #define ECC_MULT_CLK_EN_V 0x00000001U #define ECC_MULT_CLK_EN_S 30 /** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0; - * Configures whether to force on ECC memory clock gate. \\ - * 0: No effect\\ - * 1: Force on\\ + * Configures whether to force on ECC memory clock gate. + * 0: No effect + * 1: Force on */ #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) @@ -159,7 +161,7 @@ extern "C" { * Version control register */ #define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) -/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37752928; +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792; * ECC mult version control register */ #define ECC_MULT_DATE 0x0FFFFFFFU @@ -171,37 +173,37 @@ extern "C" { * The memory that stores k. */ #define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) -#define ECC_MULT_K_MEM_SIZE_BYTES 32 +#define ECC_MULT_K_MEM_SIZE_BYTES 48 /** ECC_MULT_PX_MEM register * The memory that stores Px. */ -#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) -#define ECC_MULT_PX_MEM_SIZE_BYTES 32 +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130) +#define ECC_MULT_PX_MEM_SIZE_BYTES 48 /** ECC_MULT_PY_MEM register * The memory that stores Py. */ -#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) -#define ECC_MULT_PY_MEM_SIZE_BYTES 32 +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160) +#define ECC_MULT_PY_MEM_SIZE_BYTES 48 /** ECC_MULT_QX_MEM register * The memory that stores Qx. */ -#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160) -#define ECC_MULT_QX_MEM_SIZE_BYTES 32 +#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190) +#define ECC_MULT_QX_MEM_SIZE_BYTES 48 /** ECC_MULT_QY_MEM register * The memory that stores Qy. */ -#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180) -#define ECC_MULT_QY_MEM_SIZE_BYTES 32 +#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0) +#define ECC_MULT_QY_MEM_SIZE_BYTES 48 /** ECC_MULT_QZ_MEM register * The memory that stores Qz. */ -#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1a0) -#define ECC_MULT_QZ_MEM_SIZE_BYTES 32 +#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0) +#define ECC_MULT_QZ_MEM_SIZE_BYTES 48 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/register/soc/ecc_mult_struct.h b/components/soc/esp32c5/register/soc/ecc_mult_struct.h index 929767509e..ed1de3e3c2 100644 --- a/components/soc/esp32c5/register/soc/ecc_mult_struct.h +++ b/components/soc/esp32c5/register/soc/ecc_mult_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -78,67 +78,69 @@ typedef union { struct { /** start : R/W/SC; bitpos: [0]; default: 0; * Configures whether to start calculation of ECC Accelerator. This bit will be - * self-cleared after the calculation is done. \\ - * 0: No effect\\ - * 1: Start calculation of ECC Accelerator\\ + * self-cleared after the calculation is done. + * 0: No effect + * 1: Start calculation of ECC Accelerator */ uint32_t start:1; /** reset : WT; bitpos: [1]; default: 0; - * Configures whether to reset ECC Accelerator. \\ - * 0: No effect\\ - * 1: Reset\\ + * Configures whether to reset ECC Accelerator. + * 0: No effect + * 1: Reset */ uint32_t reset:1; - /** key_length : R/W; bitpos: [2]; default: 0; - * Configures the key length mode bit of ECC Accelerator. \\ - * 0: P-192\\ - * 1: P-256\\ + /** key_length : R/W; bitpos: [3:2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. + * 0: P-192 + * 1: P-256 + * 2: P-384 + * 3: SM2 */ - uint32_t key_length:1; - /** mod_base : R/W; bitpos: [3]; default: 0; - * Configures the mod base of mod operation, only valid in work_mode 8-11. \\ - * 0: n(order of curve)\\ - * 1: p(mod base of curve)\\ + uint32_t key_length:2; + /** mod_base : R/W; bitpos: [4]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. + * 0: n(order of curve) + * 1: p(mod base of curve) */ uint32_t mod_base:1; - /** work_mode : R/W; bitpos: [7:4]; default: 0; - * Configures the work mode of ECC Accelerator.\\ - * 0: Point Multi mode\\ - * 1: Reserved\\ - * 2: Point Verif mode\\ - * 3: Point Verif + Multi mode\\ - * 4: Jacobian Point Multi mode\\ - * 5: Reserved\\ - * 6: Jacobian Point Verif mode\\ - * 7: Point Verif + Jacobian Point Multi mode\\ - * 8: Mod Add mode\\ - * 9. Mod Sub mode\\ - * 10: Mod Multi mode\\ - * 11: Mod Div mode\\ + /** work_mode : R/W; bitpos: [8:5]; default: 0; + * Configures the work mode of ECC Accelerator. + * 0: Point Multi mode + * 1: Reserved + * 2: Point Verif mode + * 3: Point Verif + Multi mode + * 4: Jacobian Point Multi mode + * 5: Reserved + * 6: Jacobian Point Verif mode + * 7: Point Verif + Jacobian Point Multi mode + * 8: Mod Add mode + * 9. Mod Sub mode + * 10: Mod Multi mode + * 11: Mod Div mode */ uint32_t work_mode:4; - /** security_mode : R/W; bitpos: [8]; default: 0; - * Configures the security mode of ECC Accelerator.\\ - * 0: no secure function enabled.\\ - * 1: enable constant-time calculation in all point multiplication modes.\\ + /** security_mode : R/W; bitpos: [9]; default: 0; + * Configures the security mode of ECC Accelerator. + * 0: no secure function enabled. + * 1: enable constant-time calculation in all point multiplication modes. */ uint32_t security_mode:1; - uint32_t reserved_9:20; + uint32_t reserved_10:19; /** verification_result : RO/SS; bitpos: [29]; default: 0; * Represents the verification result of ECC Accelerator, valid only when calculation * is done. */ uint32_t verification_result:1; /** clk_en : R/W; bitpos: [30]; default: 0; - * Configures whether to force on register clock gate. \\ - * 0: No effect\\ - * 1: Force on\\ + * Configures whether to force on register clock gate. + * 0: No effect + * 1: Force on */ uint32_t clk_en:1; /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0; - * Configures whether to force on ECC memory clock gate. \\ - * 0: No effect\\ - * 1: Force on\\ + * Configures whether to force on ECC memory clock gate. + * 0: No effect + * 1: Force on */ uint32_t mem_clock_gate_force_on:1; }; @@ -152,7 +154,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37752928; + /** date : R/W; bitpos: [27:0]; default: 37781792; * ECC mult version control register */ uint32_t date:28; @@ -171,18 +173,18 @@ typedef struct { volatile ecc_mult_conf_reg_t conf; uint32_t reserved_020[55]; volatile ecc_mult_date_reg_t date; - volatile uint32_t k[8]; - volatile uint32_t px[8]; - volatile uint32_t py[8]; - volatile uint32_t qx[8]; - volatile uint32_t qy[8]; - volatile uint32_t qz[8]; + volatile uint32_t k[12]; + volatile uint32_t px[12]; + volatile uint32_t py[12]; + volatile uint32_t qx[12]; + volatile uint32_t qy[12]; + volatile uint32_t qz[12]; } ecc_mult_dev_t; extern ecc_mult_dev_t ECC; #ifndef __cplusplus -_Static_assert(sizeof(ecc_mult_dev_t) == 0x1c0, "Invalid size of ecc_mult_dev_t structure"); +_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h new file mode 100644 index 0000000000..401786a165 --- /dev/null +++ b/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h @@ -0,0 +1,360 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ +#define ECDSA_WORK_MODE 0x00000003U +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000003U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. + */ +#define ECDSA_ECC_CURVE 0x00000003U +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000003U +#define ECDSA_ECC_CURVE_S 2 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(4)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 4 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(5)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 5 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ +#define ECDSA_DETERMINISTIC_K (BIT(6)) +#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) +#define ECDSA_DETERMINISTIC_K_V 0x00000001U +#define ECDSA_DETERMINISTIC_K_S 6 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) +#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) +#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PREP_DONE_INT_RAW_S 0 +/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) +#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) +#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PROC_DONE_INT_RAW_S 1 +/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_RAW (BIT(2)) +#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) +#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U +#define ECDSA_POST_DONE_INT_RAW_S 2 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 3 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ST (BIT(0)) +#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) +#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ST_S 0 +/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ST (BIT(1)) +#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) +#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ST_S 1 +/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ST (BIT(2)) +#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) +#define ECDSA_POST_DONE_INT_ST_V 0x00000001U +#define ECDSA_POST_DONE_INT_ST_S 2 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 3 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) +#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) +#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ENA_S 0 +/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) +#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) +#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ENA_S 1 +/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ENA (BIT(2)) +#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) +#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U +#define ECDSA_POST_DONE_INT_ENA_S 2 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 3 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) +#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) +#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PREP_DONE_INT_CLR_S 0 +/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) +#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) +#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PROC_DONE_INT_CLR_S 1 +/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_CLR (BIT(2)) +#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) +#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U +#define ECDSA_POST_DONE_INT_CLR_S 2 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 3 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. + */ +#define ECDSA_SHA_MODE 0x0000000FU +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x0000000FU +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) +#define ECDSA_R_MEM_SIZE_BYTES 48 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) +#define ECDSA_S_MEM_SIZE_BYTES 48 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) +#define ECDSA_Z_MEM_SIZE_BYTES 48 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) +#define ECDSA_QAX_MEM_SIZE_BYTES 48 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) +#define ECDSA_QAY_MEM_SIZE_BYTES 48 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h new file mode 100644 index 0000000000..6659f30a90 --- /dev/null +++ b/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h @@ -0,0 +1,348 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ + uint32_t work_mode:2; + /** ecc_curve : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. + */ + uint32_t ecc_curve:2; + /** software_set_k : R/W; bitpos: [4]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [5]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + /** deterministic_k : R/W; bitpos: [6]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ + uint32_t deterministic_k:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. + */ + uint32_t sha_mode:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37785984; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[16]; + uint32_t reserved_2c0[72]; + volatile uint32_t r[12]; + volatile uint32_t s[12]; + volatile uint32_t z[12]; + volatile uint32_t qax[12]; + volatile uint32_t qay[12]; +} ecdsa_dev_t; + +extern ecdsa_dev_t ECDSA; + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/efuse_reg_eco2.h b/components/soc/esp32c5/register/soc/efuse_reg_eco2.h new file mode 100644 index 0000000000..604025b361 --- /dev/null +++ b/components/soc/esp32c5/register/soc/efuse_reg_eco2.h @@ -0,0 +1,4407 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Represents pgm_data0 + */ +#define EFUSE_PGM_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Represents pgm_data1 + */ +#define EFUSE_PGM_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Represents pgm_data2 + */ +#define EFUSE_PGM_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Represents pgm_data3 + */ +#define EFUSE_PGM_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Represents pgm_data4 + */ +#define EFUSE_PGM_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Represents pgm_data5 + */ +#define EFUSE_PGM_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Represents pgm_data6 + */ +#define EFUSE_PGM_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Represents pgm_data7 + */ +#define EFUSE_PGM_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Represents pgm_check_value0 + */ +#define EFUSE_PGM_CHECK_VALUE0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Represents pgm_check_value1 + */ +#define EFUSE_PGM_CHECK_VALUE1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Represents pgm_check_value2 + */ +#define EFUSE_PGM_CHECK_VALUE2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * Represents rd_wr_dis + */ +#define EFUSE_RD_WR_DIS_REG(i) (DR_REG_EFUSE_BASE(i) + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is + * disabled. For mapping between the bits of this field and the eFuse blocks, please + * refer to Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI : RO; bitpos: [7]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the high part of the field). + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI (BIT(7)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Represents whether cache is disabled. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note + * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only + * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [10]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(10)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot\_mode\_download is disabled. + * 0: Enabled + * 1: Disabled + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Represents whether TWAI$^®$ function is disabled. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when all of + * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, + * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and + * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Represents whether VDD SPI pin is functioned as GPIO. + * 1: Functioned + * 0: Not functioned + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [28:27]; default: 0; + * Represents RTC watchdog timeout threshold. + * 0: The originally configured STG0 threshold × 2 + * 1: The originally configured STG0 threshold × 4 + * 2: The originally configured STG0 threshold × 8 + * 3: The originally configured STG0 threshold × 16 + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 27 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO : RO; bitpos: [31:29]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the low part of the field). + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S 29 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x34) +/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0; + * Represents whether the new key deployment of key manager is disabled. + * Bit0: Represents whether the new ECDSA key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is + * disabled + * 0: Enabled + * 1: Disabled + * Bit2: Represents whether the new HMAC key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit3: Represents whether the new DS key deployment is disabled + * 0: Enabled + * 1: Disabled + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; + * Represents the cycle at which the Key Manager switches random numbers. + * 0: Controlled by the + * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For + * more information, please refer to Chapter \ref{mod:keymng} + * \textit{\nameref{mod:keymng}} + * 1: 8 Key Manager clock cycles + * 2: 16 Key Manager clock cycles + * 3: 32 Key Manager clock cycles + */ +#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; + * Represents whether the corresponding key can be deployed only once. + * Bit0: Represents whether the ECDSA key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit2: Represents whether the HMAC key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit3: Represents whether the DS key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; + * Represents whether the corresponding key must come from Key Manager. + * Bit0: Represents whether the ECDSA key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key + * Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit2: Represents whether the HMAC key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit3: Represents whether the DS key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; + * Represents whether to disable the use of the initialization key written by software + * and instead force use efuse\_init\_key. + * 0: Enable + * 1: Disable + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [15]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader. + * 1: Enable + * 0: Disable + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(15)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S 15 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [18:16]; default: 0; + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 16 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [19]; default: 0; + * Represents whether revoking Secure Boot key digest 0 is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(19)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 19 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [20]; default: 0; + * Represents whether revoking Secure Boot key digest 1 is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(20)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 20 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [21]; default: 0; + * Represents whether revoking Secure Boot key digest 2 is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 21 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [26:22]; default: 0; + * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_S 22 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:27]; default: 0; + * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_S 27 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [4:0]; default: 0; + * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000001FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [9:5]; default: 0; + * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_S 5 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [14:10]; default: 0; + * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_S 10 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [19:15]; default: 0; + * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_S 15 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [21:20]; default: 0; + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC\_DPA\_OFF + * 1: Security level is SEC\_DPA\_LOW + * 2: Security level is SEC\_DPA\_MIDDLE + * 3: Security level is SEC\_DPA\_HIGH + * For more information, please refer to Chapter \ref{mod:sysreg} + * \textit{\nameref{mod:sysreg}} > Section + * \ref{sec:sysreg-anti-dpa-attack-security-control} + * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 20 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI : RO; bitpos: [24:22]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The high part of the field). + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S 22 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [25]; default: 0; + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_SECURE_BOOT_EN (BIT(25)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 25 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [26]; default: 0; + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(26)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 26 +/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0; + * Represents which key flash encryption uses. + * 0: XTS-AES-256 key + * 1: XTS-AES-128 key + */ +#define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(27)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_S 27 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up. Measurement unit: ms. When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disable or enable. 1. Disable + * 0: Enable. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1. Disable + * 0: Enable. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable + * 0: Enable. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; + * Represents whether the keys in the Key Manager are locked after deployment. + * 0: Not locked + * 1: Locked + */ +#define EFUSE_LOCK_KM_KEY (BIT(3)) +#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) +#define EFUSE_LOCK_KM_KEY_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * Disable + * 0: Enable. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled. Only downloading into flash is + * supported. Reading/writing RAM or registers is not supported (i.e. stub download is + * not supported). + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO27 is reset at low level. + * 2: Enable printing when GPIO27 is reset at high level. + * 3: Force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced. + * 0: Not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 8 +/** EFUSE_SECURE_VERSION : RO; bitpos: [17:9]; default: 0; + * Represents the app secure version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x000001FFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x000001FFU +#define EFUSE_SECURE_VERSION_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 +/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. + * 1: Enabled + * 0: Disabled + */ +#define EFUSE_HYS_EN_PAD (BIT(26)) +#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) +#define EFUSE_HYS_EN_PAD_V 0x00000001U +#define EFUSE_HYS_EN_PAD_S 26 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; + * Represents the pseudo round level of XTS-AES anti-DPA attack. + * 0: Disabled + * 1: Low + * 2: Moderate + * 3: High + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 +/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; + * Represents whether XTS-AES anti-DPA attack clock is enabled. + * 0: Disable + * 1: Enabled + */ +#define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) +#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_S 29 +/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0; + * Represents if the chip supports ECDSA P384 + */ +#define EFUSE_ECDSA_P384_ENABLE (BIT(31)) +#define EFUSE_ECDSA_P384_ENABLE_M (EFUSE_ECDSA_P384_ENABLE_V << EFUSE_ECDSA_P384_ENABLE_S) +#define EFUSE_ECDSA_P384_ENABLE_V 0x00000001U +#define EFUSE_ECDSA_P384_ENABLE_S 31 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x40) +/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0; + * Represents whether the HUK generate mode is valid. + * Odd count of bits with a value of 1: Invalid + * Even count of bits with a value of 1: Valid + */ +#define EFUSE_HUK_GEN_STATE 0x000001FFU +#define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) +#define EFUSE_HUK_GEN_STATE_V 0x000001FFU +#define EFUSE_HUK_GEN_STATE_S 0 +/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0; + * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or + * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} + * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter + * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. + * Odd count of bits with a value of 1: 48 MHz + * Even count of bits with a value of 1: 40 MHz + */ +#define EFUSE_XTAL_48M_SEL 0x00000007U +#define EFUSE_XTAL_48M_SEL_M (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S) +#define EFUSE_XTAL_48M_SEL_V 0x00000007U +#define EFUSE_XTAL_48M_SEL_S 9 +/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0; + * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. + * For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 0: Strapping PAD state + * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse + */ +#define EFUSE_XTAL_48M_SEL_MODE (BIT(12)) +#define EFUSE_XTAL_48M_SEL_MODE_M (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S) +#define EFUSE_XTAL_48M_SEL_MODE_V 0x00000001U +#define EFUSE_XTAL_48M_SEL_MODE_S 12 +/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [13]; default: 0; + * Represents whether to force ECC to use constant-time mode for point multiplication + * calculation. + * 0: Not force + * 1: Force + */ +#define EFUSE_ECC_FORCE_CONST_TIME (BIT(13)) +#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) +#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_S 13 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO : RO; bitpos: [22:14]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The low part of the field). + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S 14 + +/** EFUSE_RD_MAC_SYS0_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Represents MAC address. Low 32-bit. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SYS1_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Represents MAC address. High 16-bit. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Represents the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SYS2_REG register + * Represents rd_mac_sys + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define EFUSE_RD_MAC_SYS2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x4c) +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_MAC_RESERVED_0 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 + +/** EFUSE_RD_MAC_SYS3_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SYS4_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SYS5_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Represents rd_sys_part1_data0 + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Represents rd_sys_part1_data1 + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Represents rd_sys_part1_data2 + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Represents rd_sys_part1_data3 + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Represents rd_sys_part1_data4 + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Represents rd_sys_part1_data5 + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Represents rd_sys_part1_data6 + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Represents rd_sys_part1_data7 + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Represents rd_usr_data0 + */ +#define EFUSE_RD_USR_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Represents rd_usr_data1 + */ +#define EFUSE_RD_USR_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Represents rd_usr_data2 + */ +#define EFUSE_RD_USR_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Represents rd_usr_data3 + */ +#define EFUSE_RD_USR_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Represents rd_usr_data4 + */ +#define EFUSE_RD_USR_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Represents rd_usr_data5 + */ +#define EFUSE_RD_USR_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Represents rd_usr_data6 + */ +#define EFUSE_RD_USR_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Represents rd_usr_data7 + */ +#define EFUSE_RD_USR_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Represents rd_key0_data0 + */ +#define EFUSE_RD_KEY0_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Represents rd_key0_data1 + */ +#define EFUSE_RD_KEY0_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Represents rd_key0_data2 + */ +#define EFUSE_RD_KEY0_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Represents rd_key0_data3 + */ +#define EFUSE_RD_KEY0_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Represents rd_key0_data4 + */ +#define EFUSE_RD_KEY0_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Represents rd_key0_data5 + */ +#define EFUSE_RD_KEY0_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Represents rd_key0_data6 + */ +#define EFUSE_RD_KEY0_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Represents rd_key0_data7 + */ +#define EFUSE_RD_KEY0_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Represents rd_key1_data0 + */ +#define EFUSE_RD_KEY1_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Represents rd_key1_data1 + */ +#define EFUSE_RD_KEY1_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Represents rd_key1_data2 + */ +#define EFUSE_RD_KEY1_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Represents rd_key1_data3 + */ +#define EFUSE_RD_KEY1_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Represents rd_key1_data4 + */ +#define EFUSE_RD_KEY1_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Represents rd_key1_data5 + */ +#define EFUSE_RD_KEY1_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Represents rd_key1_data6 + */ +#define EFUSE_RD_KEY1_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Represents rd_key1_data7 + */ +#define EFUSE_RD_KEY1_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Represents rd_key2_data0 + */ +#define EFUSE_RD_KEY2_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Represents rd_key2_data1 + */ +#define EFUSE_RD_KEY2_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Represents rd_key2_data2 + */ +#define EFUSE_RD_KEY2_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Represents rd_key2_data3 + */ +#define EFUSE_RD_KEY2_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Represents rd_key2_data4 + */ +#define EFUSE_RD_KEY2_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Represents rd_key2_data5 + */ +#define EFUSE_RD_KEY2_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Represents rd_key2_data6 + */ +#define EFUSE_RD_KEY2_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Represents rd_key2_data7 + */ +#define EFUSE_RD_KEY2_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Represents rd_key3_data0 + */ +#define EFUSE_RD_KEY3_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Represents rd_key3_data1 + */ +#define EFUSE_RD_KEY3_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Represents rd_key3_data2 + */ +#define EFUSE_RD_KEY3_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Represents rd_key3_data3 + */ +#define EFUSE_RD_KEY3_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Represents rd_key3_data4 + */ +#define EFUSE_RD_KEY3_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Represents rd_key3_data5 + */ +#define EFUSE_RD_KEY3_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Represents rd_key3_data6 + */ +#define EFUSE_RD_KEY3_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Represents rd_key3_data7 + */ +#define EFUSE_RD_KEY3_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Represents rd_key4_data0 + */ +#define EFUSE_RD_KEY4_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Represents rd_key4_data1 + */ +#define EFUSE_RD_KEY4_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Represents rd_key4_data2 + */ +#define EFUSE_RD_KEY4_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Represents rd_key4_data3 + */ +#define EFUSE_RD_KEY4_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Represents rd_key4_data4 + */ +#define EFUSE_RD_KEY4_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Represents rd_key4_data5 + */ +#define EFUSE_RD_KEY4_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Represents rd_key4_data6 + */ +#define EFUSE_RD_KEY4_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Represents rd_key4_data7 + */ +#define EFUSE_RD_KEY4_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Represents rd_key5_data0 + */ +#define EFUSE_RD_KEY5_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Represents rd_key5_data1 + */ +#define EFUSE_RD_KEY5_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Represents rd_key5_data2 + */ +#define EFUSE_RD_KEY5_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Represents rd_key5_data3 + */ +#define EFUSE_RD_KEY5_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Represents rd_key5_data4 + */ +#define EFUSE_RD_KEY5_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Represents rd_key5_data5 + */ +#define EFUSE_RD_KEY5_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Represents rd_key5_data6 + */ +#define EFUSE_RD_KEY5_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Represents rd_key5_data7 + */ +#define EFUSE_RD_KEY5_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Represents rd_sys_part2_data0 + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Represents rd_sys_part2_data1 + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Represents rd_sys_part2_data2 + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Represents rd_sys_part2_data3 + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Represents rd_sys_part2_data4 + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Represents rd_sys_part2_data5 + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Represents rd_sys_part2_data6 + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Represents rd_sys_part2_data7 + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_DATA_ERR0_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Represents the programming error of EFUSE_RD_DIS + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR (BIT(7)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_DIS_ICACHE + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_JTAG + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR (BIT(10)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_DIS_TWAI + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Represents the programming error of EFUSE_SOFT_DIS_JTAG + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_DIS_PAD_JTAG + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_USB_EXCHG_PINS + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 27 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR : RO; bitpos: [31:29]; + * default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S 29 + +/** EFUSE_RD_REPEAT_DATA_ERR1_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x180) +/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0; + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE + */ +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0; + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0; + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR (BIT(15)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S 15 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [18:16]; default: 0; + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 16 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(19)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 19 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 20 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [21]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 21 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [26:22]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0 + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 22 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:27]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1 + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 27 + +/** EFUSE_RD_REPEAT_DATA_ERR2_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [4:0]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2 + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [9:5]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3 + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 5 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [14:10]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4 + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 10 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [19:15]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5 + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 15 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [21:20]; default: 0; + * Represents the programming error of EFUSE_SEC_DPA_LEVEL + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 20 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR : RO; bitpos: [24:22]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S 22 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_EN + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 25 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(26)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 26 +/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 + */ +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR (BIT(27)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S 27 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Represents the programming error of EFUSE_FLASH_TPUW + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_DATA_ERR3_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_LOCK_KM_KEY + */ +#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) +#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) +#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_ERR_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Represents the programming error of EFUSE_UART_PRINT_CONTROL + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_FORCE_SEND_RESUME + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [17:9]; default: 0; + * Represents the programming error of EFUSE_SECURE_VERSION + */ +#define EFUSE_SECURE_VERSION_ERR 0x000001FFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x000001FFU +#define EFUSE_SECURE_VERSION_ERR_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 +/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_HYS_EN_PAD + */ +#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) +#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) +#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U +#define EFUSE_HYS_EN_PAD_ERR_S 26 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 27 +/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE + */ +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR (BIT(29)) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 29 +/** EFUSE_ECDSA_P384_ENABLE_ERR : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECDSA_P384_ENABLE + */ +#define EFUSE_ECDSA_P384_ENABLE_ERR (BIT(31)) +#define EFUSE_ECDSA_P384_ENABLE_ERR_M (EFUSE_ECDSA_P384_ENABLE_ERR_V << EFUSE_ECDSA_P384_ENABLE_ERR_S) +#define EFUSE_ECDSA_P384_ENABLE_ERR_V 0x00000001U +#define EFUSE_ECDSA_P384_ENABLE_ERR_S 31 + +/** EFUSE_RD_REPEAT_DATA_ERR4_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x18c) +/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE + */ +#define EFUSE_HUK_GEN_STATE_ERR 0x000001FFU +#define EFUSE_HUK_GEN_STATE_ERR_M (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S) +#define EFUSE_HUK_GEN_STATE_ERR_V 0x000001FFU +#define EFUSE_HUK_GEN_STATE_ERR_S 0 +/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL + */ +#define EFUSE_XTAL_48M_SEL_ERR 0x00000007U +#define EFUSE_XTAL_48M_SEL_ERR_M (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S) +#define EFUSE_XTAL_48M_SEL_ERR_V 0x00000007U +#define EFUSE_XTAL_48M_SEL_ERR_S 9 +/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE + */ +#define EFUSE_XTAL_48M_SEL_MODE_ERR (BIT(12)) +#define EFUSE_XTAL_48M_SEL_MODE_ERR_M (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S) +#define EFUSE_XTAL_48M_SEL_MODE_ERR_V 0x00000001U +#define EFUSE_XTAL_48M_SEL_MODE_ERR_S 12 +/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + */ +#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(13)) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 13 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR : RO; bitpos: [22:14]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S 14 + +/** EFUSE_RD_RS_DATA_ERR0_REG register + * Represents rd_rs_data_err + */ +#define EFUSE_RD_RS_DATA_ERR0_REG(i) (DR_REG_EFUSE_BASE(i) + 0x190) +/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) +#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + */ +#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) +#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_RD_MAC_SYS_FAIL_S 3 +/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data + */ +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. + */ +#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 +/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data + */ +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) +#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data + */ +#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 +/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) +#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY0_DATA_FAIL_S 15 +/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data + */ +#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 +/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) +#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY1_DATA_FAIL_S 19 +/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data + */ +#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 +/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) +#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY2_DATA_FAIL_S 23 +/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data + */ +#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 +/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) +#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY3_DATA_FAIL_S 27 +/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data + */ +#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 +/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) +#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY4_DATA_FAIL_S 31 + +/** EFUSE_RD_RS_DATA_ERR1_REG register + * Represents rd_rs_data_err + */ +#define EFUSE_RD_RS_DATA_ERR1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x194) +/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data + */ +#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 +/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. + */ +#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) +#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY5_DATA_FAIL_S 3 +/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data + */ +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. + */ +#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG(i) (DR_REG_EFUSE_BASE(i) + 0x198) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37818960; + * Represents eFuse version. Date:2024-12-19 16:08:23, + * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuration register + */ +#define EFUSE_CONF_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 + +/** EFUSE_ECDSA_REG register + * eFuse status register. + */ +#define EFUSE_ECDSA_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1d0) +/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. + */ +#define EFUSE_CFG_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_M (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S) +#define EFUSE_CFG_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_S 0 +/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. + */ +#define EFUSE_CFG_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_M (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S) +#define EFUSE_CFG_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_S 4 +/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. + */ +#define EFUSE_CFG_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_M (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S) +#define EFUSE_CFG_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_S 8 +/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. + */ +#define EFUSE_CFG_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_M (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S) +#define EFUSE_CFG_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_S 12 +/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. + */ +#define EFUSE_CUR_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_M (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S) +#define EFUSE_CUR_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_S 16 +/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. + */ +#define EFUSE_CUR_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_M (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S) +#define EFUSE_CUR_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_S 20 +/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. + */ +#define EFUSE_CUR_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_M (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S) +#define EFUSE_CUR_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_S 24 +/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. + */ +#define EFUSE_CUR_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_M (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S) +#define EFUSE_CUR_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_S 28 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1d4) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Represents the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1d8) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to send read commands. + * 1: Send + * 0: No effect + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Configures whether to send programming commands. + * 1: Send + * 0: No effect + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1dc) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of EFUSE_READ_DONE_INT. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of EFUSE_PGM_DONE_INT. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1e0) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of EFUSE_READ_DONE_INT. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of EFUSE_PGM_DONE_INT. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1e4) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable EFUSE_READ_DONE_INT. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable EFUSE_PGM_DONE_INT. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1e8) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear EFUSE_READ_DONE_INT. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear EFUSE_PGM_DONE_INT. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1ec) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1f0) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1f4) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG(i) (DR_REG_EFUSE_BASE(i) + 0x1fc) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures which block number to bypass the Reed-Solomon (RS) correction step. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_APB2OTP_WR_DIS_REG register + * eFuse apb2otp block0 data register1. + */ +#define EFUSE_APB2OTP_WR_DIS_REG(i) (DR_REG_EFUSE_BASE(i) + 0x500) +/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S) +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register + * eFuse apb2otp block0 data register2. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x504) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register + * eFuse apb2otp block0 data register3. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x508) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register + * eFuse apb2otp block0 data register4. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x50c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register + * eFuse apb2otp block0 data register5. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x510) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register + * eFuse apb2otp block0 data register6. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x514) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register + * eFuse apb2otp block0 data register7. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x518) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register + * eFuse apb2otp block0 data register8. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x51c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register + * eFuse apb2otp block0 data register9. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x520) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register + * eFuse apb2otp block0 data register10. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x524) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register + * eFuse apb2otp block0 data register11. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x528) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register + * eFuse apb2otp block0 data register12. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x52c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register + * eFuse apb2otp block0 data register13. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x530) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register + * eFuse apb2otp block0 data register14. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x534) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register + * eFuse apb2otp block0 data register15. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x538) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register + * eFuse apb2otp block0 data register16. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x53c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register + * eFuse apb2otp block0 data register17. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x540) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register + * eFuse apb2otp block0 data register18. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x544) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register + * eFuse apb2otp block0 data register19. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x548) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register + * eFuse apb2otp block0 data register20. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x54c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register + * eFuse apb2otp block0 data register21. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x550) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S 0 + +/** EFUSE_APB2OTP_BLK1_W1_REG register + * eFuse apb2otp block1 data register1. + */ +#define EFUSE_APB2OTP_BLK1_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x554) +/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W1_M (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S) +#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W1_S 0 + +/** EFUSE_APB2OTP_BLK1_W2_REG register + * eFuse apb2otp block1 data register2. + */ +#define EFUSE_APB2OTP_BLK1_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x558) +/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W2_M (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S) +#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W2_S 0 + +/** EFUSE_APB2OTP_BLK1_W3_REG register + * eFuse apb2otp block1 data register3. + */ +#define EFUSE_APB2OTP_BLK1_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x55c) +/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W3_M (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S) +#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W3_S 0 + +/** EFUSE_APB2OTP_BLK1_W4_REG register + * eFuse apb2otp block1 data register4. + */ +#define EFUSE_APB2OTP_BLK1_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x560) +/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W4_M (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S) +#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W4_S 0 + +/** EFUSE_APB2OTP_BLK1_W5_REG register + * eFuse apb2otp block1 data register5. + */ +#define EFUSE_APB2OTP_BLK1_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x564) +/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W5_M (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S) +#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W5_S 0 + +/** EFUSE_APB2OTP_BLK1_W6_REG register + * eFuse apb2otp block1 data register6. + */ +#define EFUSE_APB2OTP_BLK1_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x568) +/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W6_M (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S) +#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W6_S 0 + +/** EFUSE_APB2OTP_BLK1_W7_REG register + * eFuse apb2otp block1 data register7. + */ +#define EFUSE_APB2OTP_BLK1_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x56c) +/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W7_M (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S) +#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W7_S 0 + +/** EFUSE_APB2OTP_BLK1_W8_REG register + * eFuse apb2otp block1 data register8. + */ +#define EFUSE_APB2OTP_BLK1_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x570) +/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W8_M (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S) +#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W8_S 0 + +/** EFUSE_APB2OTP_BLK1_W9_REG register + * eFuse apb2otp block1 data register9. + */ +#define EFUSE_APB2OTP_BLK1_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x574) +/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W9_M (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S) +#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W9_S 0 + +/** EFUSE_APB2OTP_BLK2_W1_REG register + * eFuse apb2otp block2 data register1. + */ +#define EFUSE_APB2OTP_BLK2_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x578) +/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W1_M (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S) +#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W1_S 0 + +/** EFUSE_APB2OTP_BLK2_W2_REG register + * eFuse apb2otp block2 data register2. + */ +#define EFUSE_APB2OTP_BLK2_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x57c) +/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W2_M (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S) +#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W2_S 0 + +/** EFUSE_APB2OTP_BLK2_W3_REG register + * eFuse apb2otp block2 data register3. + */ +#define EFUSE_APB2OTP_BLK2_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x580) +/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W3_M (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S) +#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W3_S 0 + +/** EFUSE_APB2OTP_BLK2_W4_REG register + * eFuse apb2otp block2 data register4. + */ +#define EFUSE_APB2OTP_BLK2_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x584) +/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W4_M (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S) +#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W4_S 0 + +/** EFUSE_APB2OTP_BLK2_W5_REG register + * eFuse apb2otp block2 data register5. + */ +#define EFUSE_APB2OTP_BLK2_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x588) +/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W5_M (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S) +#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W5_S 0 + +/** EFUSE_APB2OTP_BLK2_W6_REG register + * eFuse apb2otp block2 data register6. + */ +#define EFUSE_APB2OTP_BLK2_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x58c) +/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W6_M (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S) +#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W6_S 0 + +/** EFUSE_APB2OTP_BLK2_W7_REG register + * eFuse apb2otp block2 data register7. + */ +#define EFUSE_APB2OTP_BLK2_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x590) +/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W7_M (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S) +#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W7_S 0 + +/** EFUSE_APB2OTP_BLK2_W8_REG register + * eFuse apb2otp block2 data register8. + */ +#define EFUSE_APB2OTP_BLK2_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x594) +/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W8_M (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S) +#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W8_S 0 + +/** EFUSE_APB2OTP_BLK2_W9_REG register + * eFuse apb2otp block2 data register9. + */ +#define EFUSE_APB2OTP_BLK2_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x598) +/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W9_M (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S) +#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W9_S 0 + +/** EFUSE_APB2OTP_BLK2_W10_REG register + * eFuse apb2otp block2 data register10. + */ +#define EFUSE_APB2OTP_BLK2_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x59c) +/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W10_M (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S) +#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W10_S 0 + +/** EFUSE_APB2OTP_BLK2_W11_REG register + * eFuse apb2otp block2 data register11. + */ +#define EFUSE_APB2OTP_BLK2_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5a0) +/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W11_M (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S) +#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W11_S 0 + +/** EFUSE_APB2OTP_BLK3_W1_REG register + * eFuse apb2otp block3 data register1. + */ +#define EFUSE_APB2OTP_BLK3_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5a4) +/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W1_M (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S) +#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W1_S 0 + +/** EFUSE_APB2OTP_BLK3_W2_REG register + * eFuse apb2otp block3 data register2. + */ +#define EFUSE_APB2OTP_BLK3_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5a8) +/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W2_M (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S) +#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W2_S 0 + +/** EFUSE_APB2OTP_BLK3_W3_REG register + * eFuse apb2otp block3 data register3. + */ +#define EFUSE_APB2OTP_BLK3_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5ac) +/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W3_M (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S) +#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W3_S 0 + +/** EFUSE_APB2OTP_BLK3_W4_REG register + * eFuse apb2otp block3 data register4. + */ +#define EFUSE_APB2OTP_BLK3_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5b0) +/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W4_M (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S) +#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W4_S 0 + +/** EFUSE_APB2OTP_BLK3_W5_REG register + * eFuse apb2otp block3 data register5. + */ +#define EFUSE_APB2OTP_BLK3_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5b4) +/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W5_M (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S) +#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W5_S 0 + +/** EFUSE_APB2OTP_BLK3_W6_REG register + * eFuse apb2otp block3 data register6. + */ +#define EFUSE_APB2OTP_BLK3_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5b8) +/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W6_M (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S) +#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W6_S 0 + +/** EFUSE_APB2OTP_BLK3_W7_REG register + * eFuse apb2otp block3 data register7. + */ +#define EFUSE_APB2OTP_BLK3_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5bc) +/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W7_M (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S) +#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W7_S 0 + +/** EFUSE_APB2OTP_BLK3_W8_REG register + * eFuse apb2otp block3 data register8. + */ +#define EFUSE_APB2OTP_BLK3_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5c0) +/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W8_M (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S) +#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W8_S 0 + +/** EFUSE_APB2OTP_BLK3_W9_REG register + * eFuse apb2otp block3 data register9. + */ +#define EFUSE_APB2OTP_BLK3_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5c4) +/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W9_M (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S) +#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W9_S 0 + +/** EFUSE_APB2OTP_BLK3_W10_REG register + * eFuse apb2otp block3 data register10. + */ +#define EFUSE_APB2OTP_BLK3_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5c8) +/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W10_M (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S) +#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W10_S 0 + +/** EFUSE_APB2OTP_BLK3_W11_REG register + * eFuse apb2otp block3 data register11. + */ +#define EFUSE_APB2OTP_BLK3_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5cc) +/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W11_M (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S) +#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W11_S 0 + +/** EFUSE_APB2OTP_BLK4_W1_REG register + * eFuse apb2otp BLOCK7 data register1. + */ +#define EFUSE_APB2OTP_BLK4_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5d0) +/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W1_M (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S) +#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W1_S 0 + +/** EFUSE_APB2OTP_BLK4_W2_REG register + * eFuse apb2otp block4 data register2. + */ +#define EFUSE_APB2OTP_BLK4_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5d4) +/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W2_M (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S) +#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W2_S 0 + +/** EFUSE_APB2OTP_BLK4_W3_REG register + * eFuse apb2otp block4 data register3. + */ +#define EFUSE_APB2OTP_BLK4_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5d8) +/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W3_M (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S) +#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W3_S 0 + +/** EFUSE_APB2OTP_BLK4_W4_REG register + * eFuse apb2otp block4 data register4. + */ +#define EFUSE_APB2OTP_BLK4_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5dc) +/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W4_M (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S) +#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W4_S 0 + +/** EFUSE_APB2OTP_BLK4_W5_REG register + * eFuse apb2otp block4 data register5. + */ +#define EFUSE_APB2OTP_BLK4_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5e0) +/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W5_M (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S) +#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W5_S 0 + +/** EFUSE_APB2OTP_BLK4_W6_REG register + * eFuse apb2otp block4 data register6. + */ +#define EFUSE_APB2OTP_BLK4_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5e4) +/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W6_M (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S) +#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W6_S 0 + +/** EFUSE_APB2OTP_BLK4_W7_REG register + * eFuse apb2otp block4 data register7. + */ +#define EFUSE_APB2OTP_BLK4_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5e8) +/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W7_M (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S) +#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W7_S 0 + +/** EFUSE_APB2OTP_BLK4_W8_REG register + * eFuse apb2otp block4 data register8. + */ +#define EFUSE_APB2OTP_BLK4_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5ec) +/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W8_M (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S) +#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W8_S 0 + +/** EFUSE_APB2OTP_BLK4_W9_REG register + * eFuse apb2otp block4 data register9. + */ +#define EFUSE_APB2OTP_BLK4_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5f0) +/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W9_M (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S) +#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W9_S 0 + +/** EFUSE_APB2OTP_BLK4_W10_REG register + * eFuse apb2otp block4 data registe10. + */ +#define EFUSE_APB2OTP_BLK4_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5f4) +/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W10_M (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S) +#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W10_S 0 + +/** EFUSE_APB2OTP_BLK4_W11_REG register + * eFuse apb2otp block4 data register11. + */ +#define EFUSE_APB2OTP_BLK4_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5f8) +/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W11_M (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S) +#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W11_S 0 + +/** EFUSE_APB2OTP_BLK5_W1_REG register + * eFuse apb2otp block5 data register1. + */ +#define EFUSE_APB2OTP_BLK5_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x5fc) +/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W1_M (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S) +#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W1_S 0 + +/** EFUSE_APB2OTP_BLK5_W2_REG register + * eFuse apb2otp block5 data register2. + */ +#define EFUSE_APB2OTP_BLK5_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x600) +/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W2_M (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S) +#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W2_S 0 + +/** EFUSE_APB2OTP_BLK5_W3_REG register + * eFuse apb2otp block5 data register3. + */ +#define EFUSE_APB2OTP_BLK5_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x604) +/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W3_M (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S) +#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W3_S 0 + +/** EFUSE_APB2OTP_BLK5_W4_REG register + * eFuse apb2otp block5 data register4. + */ +#define EFUSE_APB2OTP_BLK5_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x608) +/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W4_M (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S) +#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W4_S 0 + +/** EFUSE_APB2OTP_BLK5_W5_REG register + * eFuse apb2otp block5 data register5. + */ +#define EFUSE_APB2OTP_BLK5_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x60c) +/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W5_M (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S) +#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W5_S 0 + +/** EFUSE_APB2OTP_BLK5_W6_REG register + * eFuse apb2otp block5 data register6. + */ +#define EFUSE_APB2OTP_BLK5_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x610) +/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W6_M (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S) +#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W6_S 0 + +/** EFUSE_APB2OTP_BLK5_W7_REG register + * eFuse apb2otp block5 data register7. + */ +#define EFUSE_APB2OTP_BLK5_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x614) +/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W7_M (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S) +#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W7_S 0 + +/** EFUSE_APB2OTP_BLK5_W8_REG register + * eFuse apb2otp block5 data register8. + */ +#define EFUSE_APB2OTP_BLK5_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x618) +/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W8_M (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S) +#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W8_S 0 + +/** EFUSE_APB2OTP_BLK5_W9_REG register + * eFuse apb2otp block5 data register9. + */ +#define EFUSE_APB2OTP_BLK5_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x61c) +/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W9_M (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S) +#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W9_S 0 + +/** EFUSE_APB2OTP_BLK5_W10_REG register + * eFuse apb2otp block5 data register10. + */ +#define EFUSE_APB2OTP_BLK5_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x620) +/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W10_M (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S) +#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W10_S 0 + +/** EFUSE_APB2OTP_BLK5_W11_REG register + * eFuse apb2otp block5 data register11. + */ +#define EFUSE_APB2OTP_BLK5_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x624) +/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W11_M (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S) +#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W11_S 0 + +/** EFUSE_APB2OTP_BLK6_W1_REG register + * eFuse apb2otp block6 data register1. + */ +#define EFUSE_APB2OTP_BLK6_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x628) +/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W1_M (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S) +#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W1_S 0 + +/** EFUSE_APB2OTP_BLK6_W2_REG register + * eFuse apb2otp block6 data register2. + */ +#define EFUSE_APB2OTP_BLK6_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x62c) +/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W2_M (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S) +#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W2_S 0 + +/** EFUSE_APB2OTP_BLK6_W3_REG register + * eFuse apb2otp block6 data register3. + */ +#define EFUSE_APB2OTP_BLK6_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x630) +/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W3_M (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S) +#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W3_S 0 + +/** EFUSE_APB2OTP_BLK6_W4_REG register + * eFuse apb2otp block6 data register4. + */ +#define EFUSE_APB2OTP_BLK6_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x634) +/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W4_M (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S) +#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W4_S 0 + +/** EFUSE_APB2OTP_BLK6_W5_REG register + * eFuse apb2otp block6 data register5. + */ +#define EFUSE_APB2OTP_BLK6_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x638) +/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W5_M (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S) +#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W5_S 0 + +/** EFUSE_APB2OTP_BLK6_W6_REG register + * eFuse apb2otp block6 data register6. + */ +#define EFUSE_APB2OTP_BLK6_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x63c) +/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W6_M (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S) +#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W6_S 0 + +/** EFUSE_APB2OTP_BLK6_W7_REG register + * eFuse apb2otp block6 data register7. + */ +#define EFUSE_APB2OTP_BLK6_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x640) +/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W7_M (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S) +#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W7_S 0 + +/** EFUSE_APB2OTP_BLK6_W8_REG register + * eFuse apb2otp block6 data register8. + */ +#define EFUSE_APB2OTP_BLK6_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x644) +/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W8_M (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S) +#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W8_S 0 + +/** EFUSE_APB2OTP_BLK6_W9_REG register + * eFuse apb2otp block6 data register9. + */ +#define EFUSE_APB2OTP_BLK6_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x648) +/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W9_M (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S) +#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W9_S 0 + +/** EFUSE_APB2OTP_BLK6_W10_REG register + * eFuse apb2otp block6 data register10. + */ +#define EFUSE_APB2OTP_BLK6_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x64c) +/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W10_M (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S) +#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W10_S 0 + +/** EFUSE_APB2OTP_BLK6_W11_REG register + * eFuse apb2otp block6 data register11. + */ +#define EFUSE_APB2OTP_BLK6_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x650) +/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W11_M (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S) +#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W11_S 0 + +/** EFUSE_APB2OTP_BLK7_W1_REG register + * eFuse apb2otp block7 data register1. + */ +#define EFUSE_APB2OTP_BLK7_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x654) +/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W1_M (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S) +#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W1_S 0 + +/** EFUSE_APB2OTP_BLK7_W2_REG register + * eFuse apb2otp block7 data register2. + */ +#define EFUSE_APB2OTP_BLK7_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x658) +/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W2_M (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S) +#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W2_S 0 + +/** EFUSE_APB2OTP_BLK7_W3_REG register + * eFuse apb2otp block7 data register3. + */ +#define EFUSE_APB2OTP_BLK7_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x65c) +/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W3_M (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S) +#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W3_S 0 + +/** EFUSE_APB2OTP_BLK7_W4_REG register + * eFuse apb2otp block7 data register4. + */ +#define EFUSE_APB2OTP_BLK7_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x660) +/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W4_M (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S) +#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W4_S 0 + +/** EFUSE_APB2OTP_BLK7_W5_REG register + * eFuse apb2otp block7 data register5. + */ +#define EFUSE_APB2OTP_BLK7_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x664) +/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W5_M (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S) +#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W5_S 0 + +/** EFUSE_APB2OTP_BLK7_W6_REG register + * eFuse apb2otp block7 data register6. + */ +#define EFUSE_APB2OTP_BLK7_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x668) +/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W6_M (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S) +#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W6_S 0 + +/** EFUSE_APB2OTP_BLK7_W7_REG register + * eFuse apb2otp block7 data register7. + */ +#define EFUSE_APB2OTP_BLK7_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x66c) +/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W7_M (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S) +#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W7_S 0 + +/** EFUSE_APB2OTP_BLK7_W8_REG register + * eFuse apb2otp block7 data register8. + */ +#define EFUSE_APB2OTP_BLK7_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x670) +/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W8_M (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S) +#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W8_S 0 + +/** EFUSE_APB2OTP_BLK7_W9_REG register + * eFuse apb2otp block7 data register9. + */ +#define EFUSE_APB2OTP_BLK7_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x674) +/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W9_M (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S) +#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W9_S 0 + +/** EFUSE_APB2OTP_BLK7_W10_REG register + * eFuse apb2otp block7 data register10. + */ +#define EFUSE_APB2OTP_BLK7_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x678) +/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W10_M (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S) +#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W10_S 0 + +/** EFUSE_APB2OTP_BLK7_W11_REG register + * eFuse apb2otp block7 data register11. + */ +#define EFUSE_APB2OTP_BLK7_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x67c) +/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W11_M (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S) +#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W11_S 0 + +/** EFUSE_APB2OTP_BLK8_W1_REG register + * eFuse apb2otp block8 data register1. + */ +#define EFUSE_APB2OTP_BLK8_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x680) +/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W1_M (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S) +#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W1_S 0 + +/** EFUSE_APB2OTP_BLK8_W2_REG register + * eFuse apb2otp block8 data register2. + */ +#define EFUSE_APB2OTP_BLK8_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x684) +/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W2_M (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S) +#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W2_S 0 + +/** EFUSE_APB2OTP_BLK8_W3_REG register + * eFuse apb2otp block8 data register3. + */ +#define EFUSE_APB2OTP_BLK8_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x688) +/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W3_M (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S) +#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W3_S 0 + +/** EFUSE_APB2OTP_BLK8_W4_REG register + * eFuse apb2otp block8 data register4. + */ +#define EFUSE_APB2OTP_BLK8_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x68c) +/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W4_M (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S) +#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W4_S 0 + +/** EFUSE_APB2OTP_BLK8_W5_REG register + * eFuse apb2otp block8 data register5. + */ +#define EFUSE_APB2OTP_BLK8_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x690) +/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W5_M (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S) +#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W5_S 0 + +/** EFUSE_APB2OTP_BLK8_W6_REG register + * eFuse apb2otp block8 data register6. + */ +#define EFUSE_APB2OTP_BLK8_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x694) +/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W6_M (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S) +#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W6_S 0 + +/** EFUSE_APB2OTP_BLK8_W7_REG register + * eFuse apb2otp block8 data register7. + */ +#define EFUSE_APB2OTP_BLK8_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x698) +/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W7_M (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S) +#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W7_S 0 + +/** EFUSE_APB2OTP_BLK8_W8_REG register + * eFuse apb2otp block8 data register8. + */ +#define EFUSE_APB2OTP_BLK8_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x69c) +/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W8_M (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S) +#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W8_S 0 + +/** EFUSE_APB2OTP_BLK8_W9_REG register + * eFuse apb2otp block8 data register9. + */ +#define EFUSE_APB2OTP_BLK8_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6a0) +/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W9_M (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S) +#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W9_S 0 + +/** EFUSE_APB2OTP_BLK8_W10_REG register + * eFuse apb2otp block8 data register10. + */ +#define EFUSE_APB2OTP_BLK8_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6a4) +/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W10_M (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S) +#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W10_S 0 + +/** EFUSE_APB2OTP_BLK8_W11_REG register + * eFuse apb2otp block8 data register11. + */ +#define EFUSE_APB2OTP_BLK8_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6a8) +/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W11_M (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S) +#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W11_S 0 + +/** EFUSE_APB2OTP_BLK9_W1_REG register + * eFuse apb2otp block9 data register1. + */ +#define EFUSE_APB2OTP_BLK9_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6ac) +/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W1_M (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S) +#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W1_S 0 + +/** EFUSE_APB2OTP_BLK9_W2_REG register + * eFuse apb2otp block9 data register2. + */ +#define EFUSE_APB2OTP_BLK9_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6b0) +/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W2_M (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S) +#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W2_S 0 + +/** EFUSE_APB2OTP_BLK9_W3_REG register + * eFuse apb2otp block9 data register3. + */ +#define EFUSE_APB2OTP_BLK9_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6b4) +/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W3_M (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S) +#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W3_S 0 + +/** EFUSE_APB2OTP_BLK9_W4_REG register + * eFuse apb2otp block9 data register4. + */ +#define EFUSE_APB2OTP_BLK9_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6b8) +/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W4_M (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S) +#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W4_S 0 + +/** EFUSE_APB2OTP_BLK9_W5_REG register + * eFuse apb2otp block9 data register5. + */ +#define EFUSE_APB2OTP_BLK9_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6bc) +/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W5_M (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S) +#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W5_S 0 + +/** EFUSE_APB2OTP_BLK9_W6_REG register + * eFuse apb2otp block9 data register6. + */ +#define EFUSE_APB2OTP_BLK9_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6c0) +/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W6_M (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S) +#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W6_S 0 + +/** EFUSE_APB2OTP_BLK9_W7_REG register + * eFuse apb2otp block9 data register7. + */ +#define EFUSE_APB2OTP_BLK9_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6c4) +/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W7_M (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S) +#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W7_S 0 + +/** EFUSE_APB2OTP_BLK9_W8_REG register + * eFuse apb2otp block9 data register8. + */ +#define EFUSE_APB2OTP_BLK9_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6c8) +/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W8_M (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S) +#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W8_S 0 + +/** EFUSE_APB2OTP_BLK9_W9_REG register + * eFuse apb2otp block9 data register9. + */ +#define EFUSE_APB2OTP_BLK9_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6cc) +/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W9_M (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S) +#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W9_S 0 + +/** EFUSE_APB2OTP_BLK9_W10_REG register + * eFuse apb2otp block9 data register10. + */ +#define EFUSE_APB2OTP_BLK9_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6d0) +/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W10_M (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S) +#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W10_S 0 + +/** EFUSE_APB2OTP_BLK9_W11_REG register + * eFuse apb2otp block9 data register11. + */ +#define EFUSE_APB2OTP_BLK9_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6d4) +/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W11_M (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S) +#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W11_S 0 + +/** EFUSE_APB2OTP_BLK10_W1_REG register + * eFuse apb2otp block10 data register1. + */ +#define EFUSE_APB2OTP_BLK10_W1_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6d8) +/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W1_M (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S) +#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W1_S 0 + +/** EFUSE_APB2OTP_BLK10_W2_REG register + * eFuse apb2otp block10 data register2. + */ +#define EFUSE_APB2OTP_BLK10_W2_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6dc) +/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W2_M (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S) +#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W2_S 0 + +/** EFUSE_APB2OTP_BLK10_W3_REG register + * eFuse apb2otp block10 data register3. + */ +#define EFUSE_APB2OTP_BLK10_W3_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6e0) +/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W3_M (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S) +#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W3_S 0 + +/** EFUSE_APB2OTP_BLK10_W4_REG register + * eFuse apb2otp block10 data register4. + */ +#define EFUSE_APB2OTP_BLK10_W4_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6e4) +/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W4_M (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S) +#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W4_S 0 + +/** EFUSE_APB2OTP_BLK10_W5_REG register + * eFuse apb2otp block10 data register5. + */ +#define EFUSE_APB2OTP_BLK10_W5_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6e8) +/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W5_M (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S) +#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W5_S 0 + +/** EFUSE_APB2OTP_BLK10_W6_REG register + * eFuse apb2otp block10 data register6. + */ +#define EFUSE_APB2OTP_BLK10_W6_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6ec) +/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W6_M (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S) +#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W6_S 0 + +/** EFUSE_APB2OTP_BLK10_W7_REG register + * eFuse apb2otp block10 data register7. + */ +#define EFUSE_APB2OTP_BLK10_W7_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6f0) +/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W7_M (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S) +#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W7_S 0 + +/** EFUSE_APB2OTP_BLK10_W8_REG register + * eFuse apb2otp block10 data register8. + */ +#define EFUSE_APB2OTP_BLK10_W8_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6f4) +/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W8_M (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S) +#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W8_S 0 + +/** EFUSE_APB2OTP_BLK10_W9_REG register + * eFuse apb2otp block10 data register9. + */ +#define EFUSE_APB2OTP_BLK10_W9_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6f8) +/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W9_M (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S) +#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W9_S 0 + +/** EFUSE_APB2OTP_BLK10_W10_REG register + * eFuse apb2otp block10 data register10. + */ +#define EFUSE_APB2OTP_BLK10_W10_REG(i) (DR_REG_EFUSE_BASE(i) + 0x6fc) +/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W10_M (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S) +#define EFUSE_APB2OTP_BLOCK10_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W10_S 0 + +/** EFUSE_APB2OTP_BLK10_W11_REG register + * eFuse apb2otp block10 data register11. + */ +#define EFUSE_APB2OTP_BLK10_W11_REG(i) (DR_REG_EFUSE_BASE(i) + 0x700) +/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W11_M (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S) +#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W11_S 0 + +/** EFUSE_APB2OTP_EN_REG register + * eFuse apb2otp enable configuration register. + */ +#define EFUSE_APB2OTP_EN_REG(i) (DR_REG_EFUSE_BASE(i) + 0x708) +/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ +#define EFUSE_APB2OTP_APB2OTP_EN (BIT(0)) +#define EFUSE_APB2OTP_APB2OTP_EN_M (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S) +#define EFUSE_APB2OTP_APB2OTP_EN_V 0x00000001U +#define EFUSE_APB2OTP_APB2OTP_EN_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/efuse_struct_eco2.h b/components/soc/esp32c5/register/soc/efuse_struct_eco2.h new file mode 100644 index 0000000000..0d48c19129 --- /dev/null +++ b/components/soc/esp32c5/register/soc/efuse_struct_eco2.h @@ -0,0 +1,3723 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: program_data registers */ +/** Type of pgm_datan register + * Represents pgm_datan + */ +typedef union { + struct { + /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth 32-bit data to be programmed. + */ + uint32_t pgm_data_n:32; + }; + uint32_t val; +} efuse_pgm_datan_reg_t; + +/** Type of pgm_check_valuen register + * Represents pgm_check_valuen + */ +typedef union { + struct { + /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth RS code to be programmed. + */ + uint32_t pgm_rs_data_n:32; + }; + uint32_t val; +} efuse_pgm_check_valuen_reg_t; + + +/** Group: block0 registers */ +/** Type of rd_wr_dis register + * Represents rd_wr_dis + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is + * disabled. For mapping between the bits of this field and the eFuse blocks, please + * refer to Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled + */ + uint32_t rd_dis:7; + /** bootloader_anti_rollback_secure_version_hi : RO; bitpos: [7]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the high part of the field). + */ + uint32_t bootloader_anti_rollback_secure_version_hi:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Represents whether cache is disabled. + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note + * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only + * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_usb_jtag:1; + /** bootloader_anti_rollback_en : RO; bitpos: [10]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t bootloader_anti_rollback_en:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot\_mode\_download is disabled. + * 0: Enabled + * 1: Disabled + */ + uint32_t spi_download_mspi_dis:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Represents whether TWAI$^®$ function is disabled. + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when all of + * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, + * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and + * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Enabled + * 0: Disabled + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Represents whether VDD SPI pin is functioned as GPIO. + * 1: Functioned + * 0: Not functioned + */ + uint32_t vdd_spi_as_gpio:1; + /** wdt_delay_sel : RO; bitpos: [28:27]; default: 0; + * Represents RTC watchdog timeout threshold. + * 0: The originally configured STG0 threshold × 2 + * 1: The originally configured STG0 threshold × 4 + * 2: The originally configured STG0 threshold × 8 + * 3: The originally configured STG0 threshold × 16 + */ + uint32_t wdt_delay_sel:2; + /** bootloader_anti_rollback_secure_version_lo : RO; bitpos: [31:29]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the low part of the field). + */ + uint32_t bootloader_anti_rollback_secure_version_lo:3; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0; + * Represents whether the new key deployment of key manager is disabled. + * Bit0: Represents whether the new ECDSA key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is + * disabled + * 0: Enabled + * 1: Disabled + * Bit2: Represents whether the new HMAC key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit3: Represents whether the new DS key deployment is disabled + * 0: Enabled + * 1: Disabled + */ + uint32_t km_disable_deploy_mode:4; + /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; + * Represents the cycle at which the Key Manager switches random numbers. + * 0: Controlled by the + * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For + * more information, please refer to Chapter \ref{mod:keymng} + * \textit{\nameref{mod:keymng}} + * 1: 8 Key Manager clock cycles + * 2: 16 Key Manager clock cycles + * 3: 32 Key Manager clock cycles + */ + uint32_t km_rnd_switch_cycle:2; + /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; + * Represents whether the corresponding key can be deployed only once. + * Bit0: Represents whether the ECDSA key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit2: Represents whether the HMAC key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit3: Represents whether the DS key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + */ + uint32_t km_deploy_only_once:4; + /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; + * Represents whether the corresponding key must come from Key Manager. + * Bit0: Represents whether the ECDSA key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key + * Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit2: Represents whether the HMAC key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit3: Represents whether the DS key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + */ + uint32_t force_use_key_manager_key:4; + /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; + * Represents whether to disable the use of the initialization key written by software + * and instead force use efuse\_init\_key. + * 0: Enable + * 1: Disable + */ + uint32_t force_disable_sw_init_key:1; + /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [15]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader. + * 1: Enable + * 0: Disable + */ + uint32_t bootloader_anti_rollback_update_in_rom:1; + /** spi_boot_crypt_cnt : RO; bitpos: [18:16]; default: 0; + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [19]; default: 0; + * Represents whether revoking Secure Boot key digest 0 is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [20]; default: 0; + * Represents whether revoking Secure Boot key digest 1 is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [21]; default: 0; + * Represents whether revoking Secure Boot key digest 2 is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [26:22]; default: 0; + * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_0:5; + /** key_purpose_1 : RO; bitpos: [31:27]; default: 0; + * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_1:5; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [4:0]; default: 0; + * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_2:5; + /** key_purpose_3 : RO; bitpos: [9:5]; default: 0; + * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_3:5; + /** key_purpose_4 : RO; bitpos: [14:10]; default: 0; + * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_4:5; + /** key_purpose_5 : RO; bitpos: [19:15]; default: 0; + * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. + */ + uint32_t key_purpose_5:5; + /** sec_dpa_level : RO; bitpos: [21:20]; default: 0; + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC\_DPA\_OFF + * 1: Security level is SEC\_DPA\_LOW + * 2: Security level is SEC\_DPA\_MIDDLE + * 3: Security level is SEC\_DPA\_HIGH + * For more information, please refer to Chapter \ref{mod:sysreg} + * \textit{\nameref{mod:sysreg}} > Section + * \ref{sec:sysreg-anti-dpa-attack-security-control} + * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. + */ + uint32_t sec_dpa_level:2; + /** recovery_bootloader_flash_sector_hi : RO; bitpos: [24:22]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The high part of the field). + */ + uint32_t recovery_bootloader_flash_sector_hi:3; + /** secure_boot_en : RO; bitpos: [25]; default: 0; + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [26]; default: 0; + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t secure_boot_aggressive_revoke:1; + /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0; + * Represents which key flash encryption uses. + * 0: XTS-AES-256 key + * 1: XTS-AES-128 key + */ + uint32_t km_xts_key_length_256:1; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up. Measurement unit: ms. When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disable or enable. 1. Disable + * 0: Enable. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1. Disable + * 0: Enable. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable + * 0: Enable. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** lock_km_key : RO; bitpos: [3]; default: 0; + * Represents whether the keys in the Key Manager are locked after deployment. + * 0: Not locked + * 1: Locked + */ + uint32_t lock_km_key:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * Disable + * 0: Enable. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled. Only downloading into flash is + * supported. Reading/writing RAM or registers is not supported (i.e. stub download is + * not supported). + * 1: Enabled + * 0: Disabled + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO27 is reset at low level. + * 2: Enable printing when GPIO27 is reset at high level. + * 3: Force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced. + * 0: Not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [17:9]; default: 0; + * Represents the app secure version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:9; + uint32_t reserved_18:7; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. + * 1: Enabled + * 0: Disabled + */ + uint32_t hys_en_pad:1; + /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; + * Represents the pseudo round level of XTS-AES anti-DPA attack. + * 0: Disabled + * 1: Low + * 2: Moderate + * 3: High + */ + uint32_t xts_dpa_pseudo_level:2; + /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; + * Represents whether XTS-AES anti-DPA attack clock is enabled. + * 0: Disable + * 1: Enabled + */ + uint32_t xts_dpa_clk_enable:1; + uint32_t reserved_30:1; + /** ecdsa_p384_enable : RO; bitpos: [31]; default: 0; + * Represents if the chip supports ECDSA P384 + */ + uint32_t ecdsa_p384_enable:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** huk_gen_state : RO; bitpos: [8:0]; default: 0; + * Represents whether the HUK generate mode is valid. + * Odd count of bits with a value of 1: Invalid + * Even count of bits with a value of 1: Valid + */ + uint32_t huk_gen_state:9; + /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0; + * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or + * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} + * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter + * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. + * Odd count of bits with a value of 1: 48 MHz + * Even count of bits with a value of 1: 40 MHz + */ + uint32_t xtal_48m_sel:3; + /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0; + * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. + * For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 0: Strapping PAD state + * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse + */ + uint32_t xtal_48m_sel_mode:1; + /** ecc_force_const_time : RO; bitpos: [13]; default: 0; + * Represents whether to force ECC to use constant-time mode for point multiplication + * calculation. + * 0: Not force + * 1: Force + */ + uint32_t ecc_force_const_time:1; + /** recovery_bootloader_flash_sector_lo : RO; bitpos: [22:14]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The low part of the field). + */ + uint32_t recovery_bootloader_flash_sector_lo:9; + uint32_t reserved_23:9; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + + +/** Group: block1 registers */ +/** Type of rd_mac_sys0 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Represents MAC address. Low 32-bit. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys0_reg_t; + +/** Type of rd_mac_sys1 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Represents MAC address. High 16-bit. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Represents the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys1_reg_t; + +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mac_reserved_0:14; + /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mac_reserved_1:18; + }; + uint32_t val; +} efuse_rd_mac_sys2_reg_t; + +/** Type of rd_mac_sys3 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys3_reg_t; + +/** Type of rd_mac_sys4 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys4_reg_t; + +/** Type of rd_mac_sys5 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys5_reg_t; + + +/** Group: block2 registers */ +/** Type of rd_sys_part1_datan register + * Represents rd_sys_part1_datan + */ +typedef union { + struct { + /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_n:32; + }; + uint32_t val; +} efuse_rd_sys_part1_datan_reg_t; + + +/** Group: block3 registers */ +/** Type of rd_usr_datan register + * Represents rd_usr_datan + */ +typedef union { + struct { + /** usr_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_datan:32; + }; + uint32_t val; +} efuse_rd_usr_datan_reg_t; + + +/** Group: block4 registers */ +/** Type of rd_key0_datan register + * Represents rd_key0_datan + */ +typedef union { + struct { + /** key0_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_datan:32; + }; + uint32_t val; +} efuse_rd_key0_datan_reg_t; + + +/** Group: block5 registers */ +/** Type of rd_key1_datan register + * Represents rd_key1_datan + */ +typedef union { + struct { + /** key1_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_datan:32; + }; + uint32_t val; +} efuse_rd_key1_datan_reg_t; + + +/** Group: block6 registers */ +/** Type of rd_key2_datan register + * Represents rd_key2_datan + */ +typedef union { + struct { + /** key2_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_datan:32; + }; + uint32_t val; +} efuse_rd_key2_datan_reg_t; + + +/** Group: block7 registers */ +/** Type of rd_key3_datan register + * Represents rd_key3_datan + */ +typedef union { + struct { + /** key3_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_datan:32; + }; + uint32_t val; +} efuse_rd_key3_datan_reg_t; + + +/** Group: block8 registers */ +/** Type of rd_key4_datan register + * Represents rd_key4_datan + */ +typedef union { + struct { + /** key4_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_datan:32; + }; + uint32_t val; +} efuse_rd_key4_datan_reg_t; + + +/** Group: block9 registers */ +/** Type of rd_key5_datan register + * Represents rd_key5_datan + */ +typedef union { + struct { + /** key5_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_datan:32; + }; + uint32_t val; +} efuse_rd_key5_datan_reg_t; + + +/** Group: block10 registers */ +/** Type of rd_sys_part2_datan register + * Represents rd_sys_part2_datan + */ +typedef union { + struct { + /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_n:32; + }; + uint32_t val; +} efuse_rd_sys_part2_datan_reg_t; + + +/** Group: block0 error report registers */ +/** Type of rd_repeat_data_err0 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Represents the programming error of EFUSE_RD_DIS + */ + uint32_t rd_dis_err:7; + /** bootloader_anti_rollback_secure_version_hi_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI + */ + uint32_t bootloader_anti_rollback_secure_version_hi_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_DIS_ICACHE + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_JTAG + */ + uint32_t dis_usb_jtag_err:1; + /** bootloader_anti_rollback_en_err : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ + uint32_t bootloader_anti_rollback_en_err:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t dis_usb_serial_jtag_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_DIS_TWAI + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Represents the programming error of EFUSE_SOFT_DIS_JTAG + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_DIS_PAD_JTAG + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_USB_EXCHG_PINS + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + */ + uint32_t vdd_spi_as_gpio_err:1; + /** wdt_delay_sel_err : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ + uint32_t wdt_delay_sel_err:2; + /** bootloader_anti_rollback_secure_version_lo_err : RO; bitpos: [31:29]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO + */ + uint32_t bootloader_anti_rollback_secure_version_lo_err:3; + }; + uint32_t val; +} efuse_rd_repeat_data_err0_reg_t; + +/** Type of rd_repeat_data_err1 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE + */ + uint32_t km_disable_deploy_mode_err:4; + /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0; + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE + */ + uint32_t km_rnd_switch_cycle_err:2; + /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0; + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE + */ + uint32_t km_deploy_only_once_err:4; + /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0; + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY + */ + uint32_t force_use_key_manager_key_err:4; + /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY + */ + uint32_t force_disable_sw_init_key_err:1; + /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ + uint32_t bootloader_anti_rollback_update_in_rom_err:1; + /** spi_boot_crypt_cnt_err : RO; bitpos: [18:16]; default: 0; + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [21]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [26:22]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0 + */ + uint32_t key_purpose_0_err:5; + /** key_purpose_1_err : RO; bitpos: [31:27]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1 + */ + uint32_t key_purpose_1_err:5; + }; + uint32_t val; +} efuse_rd_repeat_data_err1_reg_t; + +/** Type of rd_repeat_data_err2 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [4:0]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2 + */ + uint32_t key_purpose_2_err:5; + /** key_purpose_3_err : RO; bitpos: [9:5]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3 + */ + uint32_t key_purpose_3_err:5; + /** key_purpose_4_err : RO; bitpos: [14:10]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4 + */ + uint32_t key_purpose_4_err:5; + /** key_purpose_5_err : RO; bitpos: [19:15]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5 + */ + uint32_t key_purpose_5_err:5; + /** sec_dpa_level_err : RO; bitpos: [21:20]; default: 0; + * Represents the programming error of EFUSE_SEC_DPA_LEVEL + */ + uint32_t sec_dpa_level_err:2; + /** recovery_bootloader_flash_sector_hi_err : RO; bitpos: [24:22]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI + */ + uint32_t recovery_bootloader_flash_sector_hi_err:3; + /** secure_boot_en_err : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_EN + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 + */ + uint32_t km_xts_key_length_256_err:1; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Represents the programming error of EFUSE_FLASH_TPUW + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_data_err2_reg_t; + +/** Type of rd_repeat_data_err3 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + */ + uint32_t dis_direct_boot_err:1; + /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + */ + uint32_t dis_usb_serial_jtag_rom_print_err:1; + /** lock_km_key_err : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_LOCK_KM_KEY + */ + uint32_t lock_km_key_err:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Represents the programming error of EFUSE_UART_PRINT_CONTROL + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_FORCE_SEND_RESUME + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [17:9]; default: 0; + * Represents the programming error of EFUSE_SECURE_VERSION + */ + uint32_t secure_version_err:9; + uint32_t reserved_18:7; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_HYS_EN_PAD + */ + uint32_t hys_en_pad_err:1; + /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + */ + uint32_t xts_dpa_pseudo_level_err:2; + /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE + */ + uint32_t xts_dpa_clk_enable_err:1; + uint32_t reserved_30:1; + /** ecdsa_p384_enable_err : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECDSA_P384_ENABLE + */ + uint32_t ecdsa_p384_enable_err:1; + }; + uint32_t val; +} efuse_rd_repeat_data_err3_reg_t; + +/** Type of rd_repeat_data_err4 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE + */ + uint32_t huk_gen_state_err:9; + /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL + */ + uint32_t xtal_48m_sel_err:3; + /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE + */ + uint32_t xtal_48m_sel_mode_err:1; + /** ecc_force_const_time_err : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + */ + uint32_t ecc_force_const_time_err:1; + /** recovery_bootloader_flash_sector_lo_err : RO; bitpos: [22:14]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO + */ + uint32_t recovery_bootloader_flash_sector_lo_err:9; + uint32_t reserved_23:9; + }; + uint32_t val; +} efuse_rd_repeat_data_err4_reg_t; + + +/** Group: RS block error report registers */ +/** Type of rd_rs_data_err0 register + * Represents rd_rs_data_err + */ +typedef union { + struct { + /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys + */ + uint32_t rd_mac_sys_err_num:3; + /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + */ + uint32_t rd_mac_sys_fail:1; + /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data + */ + uint32_t rd_sys_part1_data_err_num:3; + /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. + */ + uint32_t rd_sys_part1_data_fail:1; + /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data + */ + uint32_t rd_usr_data_err_num:3; + /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_usr_data_fail:1; + /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data + */ + uint32_t rd_key0_data_err_num:3; + /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key0_data_fail:1; + /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data + */ + uint32_t rd_key1_data_err_num:3; + /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key1_data_fail:1; + /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data + */ + uint32_t rd_key2_data_err_num:3; + /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key2_data_fail:1; + /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data + */ + uint32_t rd_key3_data_err_num:3; + /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key3_data_fail:1; + /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data + */ + uint32_t rd_key4_data_err_num:3; + /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key4_data_fail:1; + }; + uint32_t val; +} efuse_rd_rs_data_err0_reg_t; + +/** Type of rd_rs_data_err1 register + * Represents rd_rs_data_err + */ +typedef union { + struct { + /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data + */ + uint32_t rd_key5_data_err_num:3; + /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key5_data_fail:1; + /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data + */ + uint32_t rd_sys_part2_data_err_num:3; + /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. + */ + uint32_t rd_sys_part2_data_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_data_err1_reg_t; + + +/** Group: EFUSE Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37818960; + * Represents eFuse version. Date:2024-12-19 16:08:23, + * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +/** Group: EFUSE Clock Registers */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + + +/** Group: EFUSE Configure Registers */ +/** Type of conf register + * eFuse operation mode configuration register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures which block number to bypass the Reed-Solomon (RS) correction step. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + + +/** Group: EFUSE ECDSA Configure Registers */ +/** Type of ecdsa register + * eFuse status register. + */ +typedef union { + struct { + /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. + */ + uint32_t cfg_ecdsa_p192_blk:4; + /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. + */ + uint32_t cfg_ecdsa_p256_blk:4; + /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. + */ + uint32_t cfg_ecdsa_p384_l_blk:4; + /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. + */ + uint32_t cfg_ecdsa_p384_h_blk:4; + /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. + */ + uint32_t cur_ecdsa_p192_blk:4; + /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. + */ + uint32_t cur_ecdsa_p256_blk:4; + /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. + */ + uint32_t cur_ecdsa_p384_l_blk:4; + /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. + */ + uint32_t cur_ecdsa_p384_h_blk:4; + }; + uint32_t val; +} efuse_ecdsa_reg_t; + + +/** Group: EFUSE Status Registers */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Represents the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: EFUSE Command Registers */ +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to send read commands. + * 1: Send + * 0: No effect + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Configures whether to send programming commands. + * 1: Send + * 0: No effect + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of EFUSE_READ_DONE_INT. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of EFUSE_PGM_DONE_INT. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of EFUSE_READ_DONE_INT. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of EFUSE_PGM_DONE_INT. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable EFUSE_READ_DONE_INT. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable EFUSE_PGM_DONE_INT. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear EFUSE_READ_DONE_INT. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear EFUSE_PGM_DONE_INT. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ +/** Type of apb2otp_wr_dis register + * eFuse apb2otp block0 data register1. + */ +typedef union { + struct { + /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t apb2otp_block0_wr_dis:32; + }; + uint32_t val; +} efuse_apb2otp_wr_dis_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ +/** Type of apb2otp_blk0_backup1_w1 register + * eFuse apb2otp block0 data register2. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t apb2otp_block0_backup1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ +/** Type of apb2otp_blk0_backup1_w2 register + * eFuse apb2otp block0 data register3. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t apb2otp_block0_backup1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ +/** Type of apb2otp_blk0_backup1_w3 register + * eFuse apb2otp block0 data register4. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t apb2otp_block0_backup1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ +/** Type of apb2otp_blk0_backup1_w4 register + * eFuse apb2otp block0 data register5. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t apb2otp_block0_backup1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ +/** Type of apb2otp_blk0_backup1_w5 register + * eFuse apb2otp block0 data register6. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t apb2otp_block0_backup1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ +/** Type of apb2otp_blk0_backup2_w1 register + * eFuse apb2otp block0 data register7. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t apb2otp_block0_backup2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ +/** Type of apb2otp_blk0_backup2_w2 register + * eFuse apb2otp block0 data register8. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t apb2otp_block0_backup2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ +/** Type of apb2otp_blk0_backup2_w3 register + * eFuse apb2otp block0 data register9. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t apb2otp_block0_backup2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ +/** Type of apb2otp_blk0_backup2_w4 register + * eFuse apb2otp block0 data register10. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t apb2otp_block0_backup2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ +/** Type of apb2otp_blk0_backup2_w5 register + * eFuse apb2otp block0 data register11. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t apb2otp_block0_backup2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ +/** Type of apb2otp_blk0_backup3_w1 register + * eFuse apb2otp block0 data register12. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t apb2otp_block0_backup3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ +/** Type of apb2otp_blk0_backup3_w2 register + * eFuse apb2otp block0 data register13. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t apb2otp_block0_backup3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ +/** Type of apb2otp_blk0_backup3_w3 register + * eFuse apb2otp block0 data register14. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t apb2otp_block0_backup3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ +/** Type of apb2otp_blk0_backup3_w4 register + * eFuse apb2otp block0 data register15. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t apb2otp_block0_backup3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ +/** Type of apb2otp_blk0_backup3_w5 register + * eFuse apb2otp block0 data register16. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t apb2otp_block0_backup3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ +/** Type of apb2otp_blk0_backup4_w1 register + * eFuse apb2otp block0 data register17. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t apb2otp_block0_backup4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ +/** Type of apb2otp_blk0_backup4_w2 register + * eFuse apb2otp block0 data register18. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t apb2otp_block0_backup4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ +/** Type of apb2otp_blk0_backup4_w3 register + * eFuse apb2otp block0 data register19. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t apb2otp_block0_backup4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ +/** Type of apb2otp_blk0_backup4_w4 register + * eFuse apb2otp block0 data register20. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t apb2otp_block0_backup4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ +/** Type of apb2otp_blk0_backup4_w5 register + * eFuse apb2otp block0 data register21. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t apb2otp_block0_backup4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word1 Data */ +/** Type of apb2otp_blk1_w1 register + * eFuse apb2otp block1 data register1. + */ +typedef union { + struct { + /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t apb2otp_block1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word2 Data */ +/** Type of apb2otp_blk1_w2 register + * eFuse apb2otp block1 data register2. + */ +typedef union { + struct { + /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t apb2otp_block1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word3 Data */ +/** Type of apb2otp_blk1_w3 register + * eFuse apb2otp block1 data register3. + */ +typedef union { + struct { + /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t apb2otp_block1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word4 Data */ +/** Type of apb2otp_blk1_w4 register + * eFuse apb2otp block1 data register4. + */ +typedef union { + struct { + /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t apb2otp_block1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word5 Data */ +/** Type of apb2otp_blk1_w5 register + * eFuse apb2otp block1 data register5. + */ +typedef union { + struct { + /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t apb2otp_block1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word6 Data */ +/** Type of apb2otp_blk1_w6 register + * eFuse apb2otp block1 data register6. + */ +typedef union { + struct { + /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t apb2otp_block1_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word7 Data */ +/** Type of apb2otp_blk1_w7 register + * eFuse apb2otp block1 data register7. + */ +typedef union { + struct { + /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t apb2otp_block1_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word8 Data */ +/** Type of apb2otp_blk1_w8 register + * eFuse apb2otp block1 data register8. + */ +typedef union { + struct { + /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t apb2otp_block1_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word9 Data */ +/** Type of apb2otp_blk1_w9 register + * eFuse apb2otp block1 data register9. + */ +typedef union { + struct { + /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t apb2otp_block1_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word1 Data */ +/** Type of apb2otp_blk2_w1 register + * eFuse apb2otp block2 data register1. + */ +typedef union { + struct { + /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t apb2otp_block2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word2 Data */ +/** Type of apb2otp_blk2_w2 register + * eFuse apb2otp block2 data register2. + */ +typedef union { + struct { + /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t apb2otp_block2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word3 Data */ +/** Type of apb2otp_blk2_w3 register + * eFuse apb2otp block2 data register3. + */ +typedef union { + struct { + /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t apb2otp_block2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word4 Data */ +/** Type of apb2otp_blk2_w4 register + * eFuse apb2otp block2 data register4. + */ +typedef union { + struct { + /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t apb2otp_block2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word5 Data */ +/** Type of apb2otp_blk2_w5 register + * eFuse apb2otp block2 data register5. + */ +typedef union { + struct { + /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t apb2otp_block2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word6 Data */ +/** Type of apb2otp_blk2_w6 register + * eFuse apb2otp block2 data register6. + */ +typedef union { + struct { + /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t apb2otp_block2_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word7 Data */ +/** Type of apb2otp_blk2_w7 register + * eFuse apb2otp block2 data register7. + */ +typedef union { + struct { + /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t apb2otp_block2_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word8 Data */ +/** Type of apb2otp_blk2_w8 register + * eFuse apb2otp block2 data register8. + */ +typedef union { + struct { + /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t apb2otp_block2_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word9 Data */ +/** Type of apb2otp_blk2_w9 register + * eFuse apb2otp block2 data register9. + */ +typedef union { + struct { + /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t apb2otp_block2_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word10 Data */ +/** Type of apb2otp_blk2_w10 register + * eFuse apb2otp block2 data register10. + */ +typedef union { + struct { + /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t apb2otp_block2_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word11 Data */ +/** Type of apb2otp_blk2_w11 register + * eFuse apb2otp block2 data register11. + */ +typedef union { + struct { + /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t apb2otp_block2_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w11_reg_t; + +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word1 Data */ +/** Type of apb2otp_blk3_w1 register + * eFuse apb2otp block3 data register1. + */ +typedef union { + struct { + /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t apb2otp_block3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word2 Data */ +/** Type of apb2otp_blk3_w2 register + * eFuse apb2otp block3 data register2. + */ +typedef union { + struct { + /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t apb2otp_block3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word3 Data */ +/** Type of apb2otp_blk3_w3 register + * eFuse apb2otp block3 data register3. + */ +typedef union { + struct { + /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t apb2otp_block3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word4 Data */ +/** Type of apb2otp_blk3_w4 register + * eFuse apb2otp block3 data register4. + */ +typedef union { + struct { + /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t apb2otp_block3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word5 Data */ +/** Type of apb2otp_blk3_w5 register + * eFuse apb2otp block3 data register5. + */ +typedef union { + struct { + /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t apb2otp_block3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word6 Data */ +/** Type of apb2otp_blk3_w6 register + * eFuse apb2otp block3 data register6. + */ +typedef union { + struct { + /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t apb2otp_block3_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word7 Data */ +/** Type of apb2otp_blk3_w7 register + * eFuse apb2otp block3 data register7. + */ +typedef union { + struct { + /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t apb2otp_block3_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word8 Data */ +/** Type of apb2otp_blk3_w8 register + * eFuse apb2otp block3 data register8. + */ +typedef union { + struct { + /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t apb2otp_block3_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word9 Data */ +/** Type of apb2otp_blk3_w9 register + * eFuse apb2otp block3 data register9. + */ +typedef union { + struct { + /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t apb2otp_block3_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word10 Data */ +/** Type of apb2otp_blk3_w10 register + * eFuse apb2otp block3 data register10. + */ +typedef union { + struct { + /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t apb2otp_block3_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word11 Data */ +/** Type of apb2otp_blk3_w11 register + * eFuse apb2otp block3 data register11. + */ +typedef union { + struct { + /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t apb2otp_block3_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w11_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */ +/** Type of apb2otp_blk4_w1 register + * eFuse apb2otp BLOCK7 data register1. + */ +typedef union { + struct { + /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t apb2otp_block4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */ +/** Type of apb2otp_blk4_w2 register + * eFuse apb2otp block4 data register2. + */ +typedef union { + struct { + /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t apb2otp_block4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */ +/** Type of apb2otp_blk4_w3 register + * eFuse apb2otp block4 data register3. + */ +typedef union { + struct { + /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t apb2otp_block4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */ +/** Type of apb2otp_blk4_w4 register + * eFuse apb2otp block4 data register4. + */ +typedef union { + struct { + /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t apb2otp_block4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */ +/** Type of apb2otp_blk4_w5 register + * eFuse apb2otp block4 data register5. + */ +typedef union { + struct { + /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t apb2otp_block4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */ +/** Type of apb2otp_blk4_w6 register + * eFuse apb2otp block4 data register6. + */ +typedef union { + struct { + /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t apb2otp_block4_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w6_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */ +/** Type of apb2otp_blk4_w7 register + * eFuse apb2otp block4 data register7. + */ +typedef union { + struct { + /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t apb2otp_block4_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w7_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */ +/** Type of apb2otp_blk4_w8 register + * eFuse apb2otp block4 data register8. + */ +typedef union { + struct { + /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t apb2otp_block4_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w8_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */ +/** Type of apb2otp_blk4_w9 register + * eFuse apb2otp block4 data register9. + */ +typedef union { + struct { + /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t apb2otp_block4_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w9_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */ +/** Type of apb2otp_blk4_w10 register + * eFuse apb2otp block4 data registe10. + */ +typedef union { + struct { + /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t apb2otp_block4_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w10_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */ +/** Type of apb2otp_blk4_w11 register + * eFuse apb2otp block4 data register11. + */ +typedef union { + struct { + /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t apb2otp_block4_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word1 Data */ +/** Type of apb2otp_blk5_w1 register + * eFuse apb2otp block5 data register1. + */ +typedef union { + struct { + /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t apb2otp_block5_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word2 Data */ +/** Type of apb2otp_blk5_w2 register + * eFuse apb2otp block5 data register2. + */ +typedef union { + struct { + /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t apb2otp_block5_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word3 Data */ +/** Type of apb2otp_blk5_w3 register + * eFuse apb2otp block5 data register3. + */ +typedef union { + struct { + /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t apb2otp_block5_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word4 Data */ +/** Type of apb2otp_blk5_w4 register + * eFuse apb2otp block5 data register4. + */ +typedef union { + struct { + /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t apb2otp_block5_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word5 Data */ +/** Type of apb2otp_blk5_w5 register + * eFuse apb2otp block5 data register5. + */ +typedef union { + struct { + /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t apb2otp_block5_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word6 Data */ +/** Type of apb2otp_blk5_w6 register + * eFuse apb2otp block5 data register6. + */ +typedef union { + struct { + /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t apb2otp_block5_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word7 Data */ +/** Type of apb2otp_blk5_w7 register + * eFuse apb2otp block5 data register7. + */ +typedef union { + struct { + /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t apb2otp_block5_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word8 Data */ +/** Type of apb2otp_blk5_w8 register + * eFuse apb2otp block5 data register8. + */ +typedef union { + struct { + /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t apb2otp_block5_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word9 Data */ +/** Type of apb2otp_blk5_w9 register + * eFuse apb2otp block5 data register9. + */ +typedef union { + struct { + /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t apb2otp_block5_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word10 Data */ +/** Type of apb2otp_blk5_w10 register + * eFuse apb2otp block5 data register10. + */ +typedef union { + struct { + /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t apb2otp_block5_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word11 Data */ +/** Type of apb2otp_blk5_w11 register + * eFuse apb2otp block5 data register11. + */ +typedef union { + struct { + /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t apb2otp_block5_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word1 Data */ +/** Type of apb2otp_blk6_w1 register + * eFuse apb2otp block6 data register1. + */ +typedef union { + struct { + /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t apb2otp_block6_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word2 Data */ +/** Type of apb2otp_blk6_w2 register + * eFuse apb2otp block6 data register2. + */ +typedef union { + struct { + /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t apb2otp_block6_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word3 Data */ +/** Type of apb2otp_blk6_w3 register + * eFuse apb2otp block6 data register3. + */ +typedef union { + struct { + /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t apb2otp_block6_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word4 Data */ +/** Type of apb2otp_blk6_w4 register + * eFuse apb2otp block6 data register4. + */ +typedef union { + struct { + /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t apb2otp_block6_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word5 Data */ +/** Type of apb2otp_blk6_w5 register + * eFuse apb2otp block6 data register5. + */ +typedef union { + struct { + /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t apb2otp_block6_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word6 Data */ +/** Type of apb2otp_blk6_w6 register + * eFuse apb2otp block6 data register6. + */ +typedef union { + struct { + /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t apb2otp_block6_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word7 Data */ +/** Type of apb2otp_blk6_w7 register + * eFuse apb2otp block6 data register7. + */ +typedef union { + struct { + /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t apb2otp_block6_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word8 Data */ +/** Type of apb2otp_blk6_w8 register + * eFuse apb2otp block6 data register8. + */ +typedef union { + struct { + /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t apb2otp_block6_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word9 Data */ +/** Type of apb2otp_blk6_w9 register + * eFuse apb2otp block6 data register9. + */ +typedef union { + struct { + /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t apb2otp_block6_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word10 Data */ +/** Type of apb2otp_blk6_w10 register + * eFuse apb2otp block6 data register10. + */ +typedef union { + struct { + /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t apb2otp_block6_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word11 Data */ +/** Type of apb2otp_blk6_w11 register + * eFuse apb2otp block6 data register11. + */ +typedef union { + struct { + /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t apb2otp_block6_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word1 Data */ +/** Type of apb2otp_blk7_w1 register + * eFuse apb2otp block7 data register1. + */ +typedef union { + struct { + /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t apb2otp_block7_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word2 Data */ +/** Type of apb2otp_blk7_w2 register + * eFuse apb2otp block7 data register2. + */ +typedef union { + struct { + /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t apb2otp_block7_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word3 Data */ +/** Type of apb2otp_blk7_w3 register + * eFuse apb2otp block7 data register3. + */ +typedef union { + struct { + /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t apb2otp_block7_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word4 Data */ +/** Type of apb2otp_blk7_w4 register + * eFuse apb2otp block7 data register4. + */ +typedef union { + struct { + /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t apb2otp_block7_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word5 Data */ +/** Type of apb2otp_blk7_w5 register + * eFuse apb2otp block7 data register5. + */ +typedef union { + struct { + /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t apb2otp_block7_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word6 Data */ +/** Type of apb2otp_blk7_w6 register + * eFuse apb2otp block7 data register6. + */ +typedef union { + struct { + /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t apb2otp_block7_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word7 Data */ +/** Type of apb2otp_blk7_w7 register + * eFuse apb2otp block7 data register7. + */ +typedef union { + struct { + /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t apb2otp_block7_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word8 Data */ +/** Type of apb2otp_blk7_w8 register + * eFuse apb2otp block7 data register8. + */ +typedef union { + struct { + /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t apb2otp_block7_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word9 Data */ +/** Type of apb2otp_blk7_w9 register + * eFuse apb2otp block7 data register9. + */ +typedef union { + struct { + /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t apb2otp_block7_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word10 Data */ +/** Type of apb2otp_blk7_w10 register + * eFuse apb2otp block7 data register10. + */ +typedef union { + struct { + /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t apb2otp_block7_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word11 Data */ +/** Type of apb2otp_blk7_w11 register + * eFuse apb2otp block7 data register11. + */ +typedef union { + struct { + /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t apb2otp_block7_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word1 Data */ +/** Type of apb2otp_blk8_w1 register + * eFuse apb2otp block8 data register1. + */ +typedef union { + struct { + /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t apb2otp_block8_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word2 Data */ +/** Type of apb2otp_blk8_w2 register + * eFuse apb2otp block8 data register2. + */ +typedef union { + struct { + /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t apb2otp_block8_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word3 Data */ +/** Type of apb2otp_blk8_w3 register + * eFuse apb2otp block8 data register3. + */ +typedef union { + struct { + /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t apb2otp_block8_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word4 Data */ +/** Type of apb2otp_blk8_w4 register + * eFuse apb2otp block8 data register4. + */ +typedef union { + struct { + /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t apb2otp_block8_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word5 Data */ +/** Type of apb2otp_blk8_w5 register + * eFuse apb2otp block8 data register5. + */ +typedef union { + struct { + /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t apb2otp_block8_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word6 Data */ +/** Type of apb2otp_blk8_w6 register + * eFuse apb2otp block8 data register6. + */ +typedef union { + struct { + /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t apb2otp_block8_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word7 Data */ +/** Type of apb2otp_blk8_w7 register + * eFuse apb2otp block8 data register7. + */ +typedef union { + struct { + /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t apb2otp_block8_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word8 Data */ +/** Type of apb2otp_blk8_w8 register + * eFuse apb2otp block8 data register8. + */ +typedef union { + struct { + /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t apb2otp_block8_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word9 Data */ +/** Type of apb2otp_blk8_w9 register + * eFuse apb2otp block8 data register9. + */ +typedef union { + struct { + /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t apb2otp_block8_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word10 Data */ +/** Type of apb2otp_blk8_w10 register + * eFuse apb2otp block8 data register10. + */ +typedef union { + struct { + /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t apb2otp_block8_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word11 Data */ +/** Type of apb2otp_blk8_w11 register + * eFuse apb2otp block8 data register11. + */ +typedef union { + struct { + /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t apb2otp_block8_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word1 Data */ +/** Type of apb2otp_blk9_w1 register + * eFuse apb2otp block9 data register1. + */ +typedef union { + struct { + /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t apb2otp_block9_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word2 Data */ +/** Type of apb2otp_blk9_w2 register + * eFuse apb2otp block9 data register2. + */ +typedef union { + struct { + /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t apb2otp_block9_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word3 Data */ +/** Type of apb2otp_blk9_w3 register + * eFuse apb2otp block9 data register3. + */ +typedef union { + struct { + /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t apb2otp_block9_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word4 Data */ +/** Type of apb2otp_blk9_w4 register + * eFuse apb2otp block9 data register4. + */ +typedef union { + struct { + /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t apb2otp_block9_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word5 Data */ +/** Type of apb2otp_blk9_w5 register + * eFuse apb2otp block9 data register5. + */ +typedef union { + struct { + /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t apb2otp_block9_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word6 Data */ +/** Type of apb2otp_blk9_w6 register + * eFuse apb2otp block9 data register6. + */ +typedef union { + struct { + /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t apb2otp_block9_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word7 Data */ +/** Type of apb2otp_blk9_w7 register + * eFuse apb2otp block9 data register7. + */ +typedef union { + struct { + /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t apb2otp_block9_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word8 Data */ +/** Type of apb2otp_blk9_w8 register + * eFuse apb2otp block9 data register8. + */ +typedef union { + struct { + /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t apb2otp_block9_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word9 Data */ +/** Type of apb2otp_blk9_w9 register + * eFuse apb2otp block9 data register9. + */ +typedef union { + struct { + /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t apb2otp_block9_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word10 Data */ +/** Type of apb2otp_blk9_w10 register + * eFuse apb2otp block9 data register10. + */ +typedef union { + struct { + /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t apb2otp_block9_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word11 Data */ +/** Type of apb2otp_blk9_w11 register + * eFuse apb2otp block9 data register11. + */ +typedef union { + struct { + /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t apb2otp_block9_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word1 Data */ +/** Type of apb2otp_blk10_w1 register + * eFuse apb2otp block10 data register1. + */ +typedef union { + struct { + /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t apb2otp_block10_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word2 Data */ +/** Type of apb2otp_blk10_w2 register + * eFuse apb2otp block10 data register2. + */ +typedef union { + struct { + /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t apb2otp_block10_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word3 Data */ +/** Type of apb2otp_blk10_w3 register + * eFuse apb2otp block10 data register3. + */ +typedef union { + struct { + /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t apb2otp_block10_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word4 Data */ +/** Type of apb2otp_blk10_w4 register + * eFuse apb2otp block10 data register4. + */ +typedef union { + struct { + /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t apb2otp_block10_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word5 Data */ +/** Type of apb2otp_blk10_w5 register + * eFuse apb2otp block10 data register5. + */ +typedef union { + struct { + /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t apb2otp_block10_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word6 Data */ +/** Type of apb2otp_blk10_w6 register + * eFuse apb2otp block10 data register6. + */ +typedef union { + struct { + /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t apb2otp_block10_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word7 Data */ +/** Type of apb2otp_blk10_w7 register + * eFuse apb2otp block10 data register7. + */ +typedef union { + struct { + /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t apb2otp_block10_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word8 Data */ +/** Type of apb2otp_blk10_w8 register + * eFuse apb2otp block10 data register8. + */ +typedef union { + struct { + /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t apb2otp_block10_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word9 Data */ +/** Type of apb2otp_blk10_w9 register + * eFuse apb2otp block10 data register9. + */ +typedef union { + struct { + /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t apb2otp_block10_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word10 Data */ +/** Type of apb2otp_blk10_w10 register + * eFuse apb2otp block10 data register10. + */ +typedef union { + struct { + /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t apb2otp_block10_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Function Enable Signal */ +/** Type of apb2otp_en register + * eFuse apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ + uint32_t apb2otp_apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} efuse_apb2otp_en_reg_t; + + +typedef struct { + volatile efuse_pgm_datan_reg_t pgm_datan[8]; + volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; + volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; + volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; + volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; + volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; + volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; + volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; + volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; + volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; + volatile efuse_date_reg_t date; + uint32_t reserved_19c[11]; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_ecdsa_reg_t ecdsa; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + uint32_t reserved_200[192]; + volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; + volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; + volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; + volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; + volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; + volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; + volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; + volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; + volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; + volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; + volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; + volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; + volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; + volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; + volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; + volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; + volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; + volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; + volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; + volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; + volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; + volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; + volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; + volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; + volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; + volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; + volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; + volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; + volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; + volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; + volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; + volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; + volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; + volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; + volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; + volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; + volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; + volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; + volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; + volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; + volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; + volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; + volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; + volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; + volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; + volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; + volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; + volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; + volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; + volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; + volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; + volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; + volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; + volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; + volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; + volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; + volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; + volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; + volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; + volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; + volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; + volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; + volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; + volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; + volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; + volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; + volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; + volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; + volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; + volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; + volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; + volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; + volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; + volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; + volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; + volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; + volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; + volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; + volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; + volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; + volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; + volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; + volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; + volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; + volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; + volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; + volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; + volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; + volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; + volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; + volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; + volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; + volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; + volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; + volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; + volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; + volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; + volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; + volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; + volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; + volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; + volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; + volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; + volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; + volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; + volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; + volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; + volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; + volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; + volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; + volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; + volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; + volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; + volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; + volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; + volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; + volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; + volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; + volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; + volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; + volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; + volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; + volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; + volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; + volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; + volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; + volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; + volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; + volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; + uint32_t reserved_704; + volatile efuse_apb2otp_en_reg_t apb2otp_en; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/hp_system_reg.h b/components/soc/esp32c5/register/soc/hp_system_reg.h index 8e43bc1dd4..ad22a3334c 100644 --- a/components/soc/esp32c5/register/soc/hp_system_reg.h +++ b/components/soc/esp32c5/register/soc/hp_system_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,9 +16,9 @@ extern "C" { */ #define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) /** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) @@ -32,10 +32,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 /** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) @@ -43,9 +42,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 /** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) @@ -58,6 +57,7 @@ extern "C" { #define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) /** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_CACHE_USAGE (BIT(0)) #define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) @@ -84,11 +84,11 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) /** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ #define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U #define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) @@ -96,9 +96,9 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_LEVEL_S 0 /** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ #define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) #define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) @@ -126,9 +126,9 @@ extern "C" { #define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) @@ -173,9 +173,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 /** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) @@ -183,9 +183,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) @@ -219,11 +219,14 @@ extern "C" { /** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register * MODEM_PERI_TIMEOUT configuration register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24) /** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; * Set the timeout threshold for bus access, corresponding to the number of clock * cycles of the clock domain. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU #define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S) @@ -231,6 +234,7 @@ extern "C" { #define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0 /** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; * Set this bit as 1 to clear timeout interrupt + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16)) #define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S) @@ -238,6 +242,7 @@ extern "C" { #define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Set this bit as 1 to enable timeout protection for accessing modem registers + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S) @@ -246,10 +251,13 @@ extern "C" { /** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register * MODEM_PERI_TIMEOUT_ADDR register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28) /** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; * Record the address information of abnormal access + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU #define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S) @@ -258,11 +266,14 @@ extern "C" { /** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register * MODEM_PERI_TIMEOUT_UID register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) /** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; * Record master id[4:0] & master permission[6:5] when trigger timeout. This register * will be cleared after the interrupt is cleared. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU #define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S) @@ -293,9 +304,9 @@ extern "C" { */ #define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38) /** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ #define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) #define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) @@ -321,9 +332,9 @@ extern "C" { #define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40) /** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable debug RunStall functionality between HP CPU and - * LP CPU.\\ - * 0: Disable\\ - * 1: Enable\\ + * LP CPU. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0)) #define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S) @@ -340,10 +351,13 @@ extern "C" { /** HP_SYSTEM_MEM_TEST_CONF_REG register * MEM_TEST configuration register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44) /** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0; * This field controls hp system memory WPULSE parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U #define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S) @@ -351,6 +365,7 @@ extern "C" { #define HP_SYSTEM_HP_MEM_WPULSE_S 0 /** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4; * This field controls hp system memory WA parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_HP_MEM_WA 0x00000007U #define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S) @@ -358,12 +373,25 @@ extern "C" { #define HP_SYSTEM_HP_MEM_WA_S 3 /** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0; * This field controls hp system memory RA parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_HP_MEM_RA 0x00000003U #define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S) #define HP_SYSTEM_HP_MEM_RA_V 0x00000003U #define HP_SYSTEM_HP_MEM_RA_S 6 +/** HP_SYSTEM_SDIO_SPRF_CTRL_REG register + * reserved + */ +#define HP_SYSTEM_SDIO_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x6c) +/** HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 12816; + * sdio mem separate control signal. + */ +#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_S) +#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_S 0 + /** HP_SYSTEM_SPROM_CTRL_REG register * reserved */ @@ -431,12 +459,36 @@ extern "C" { #define HP_SYSTEM_BITSCRAMBLER_TX_SEL_V 0x0000000FU #define HP_SYSTEM_BITSCRAMBLER_TX_SEL_S 4 +/** HP_SYSTEM_AXI_MST_PRI_REG register + * AXI mst priority configuration register + */ +#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x88) +/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_DMA_PRIORITY (BIT(0)) +#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S) +#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U +#define HP_SYSTEM_DMA_PRIORITY_S 0 +/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_CACHE_PRIORITY (BIT(1)) +#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S) +#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U +#define HP_SYSTEM_CACHE_PRIORITY_S 1 + /** HP_SYSTEM_RND_ECO_REG register * redcy eco register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0) /** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_REDCY_ENA (BIT(0)) #define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) @@ -444,6 +496,7 @@ extern "C" { #define HP_SYSTEM_REDCY_ENA_S 0 /** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_REDCY_RESULT (BIT(1)) #define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) @@ -452,10 +505,13 @@ extern "C" { /** HP_SYSTEM_RND_ECO_LOW_REG register * redcy eco low register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4) /** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU #define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) @@ -464,10 +520,13 @@ extern "C" { /** HP_SYSTEM_RND_ECO_HIGH_REG register * redcy eco high register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8) /** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU #define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) @@ -476,10 +535,13 @@ extern "C" { /** HP_SYSTEM_DEBUG_REG register * HP-SYSTEM debug register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x3f4) /** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1; * Reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_FPGA_DEBUG (BIT(0)) #define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S) @@ -488,10 +550,13 @@ extern "C" { /** HP_SYSTEM_CLOCK_GATE_REG register * HP-SYSTEM clock gating configure register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8) /** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; * Set this bit as 1 to force on clock gating. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_CLK_EN (BIT(0)) #define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/hp_system_struct.h b/components/soc/esp32c5/register/soc/hp_system_struct.h index ad24cc5160..ccd99025ce 100644 --- a/components/soc/esp32c5/register/soc/hp_system_struct.h +++ b/components/soc/esp32c5/register/soc/hp_system_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,9 +17,9 @@ extern "C" { typedef union { struct { /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ uint32_t enable_spi_manual_encrypt:1; /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; @@ -27,17 +27,16 @@ typedef union { */ uint32_t enable_download_db_encrypt:1; /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ uint32_t enable_download_g0cb_decrypt:1; /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ uint32_t enable_download_manual_encrypt:1; uint32_t reserved_4:28; @@ -52,6 +51,7 @@ typedef union { struct { /** cache_usage : HRO; bitpos: [0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usage:1; uint32_t reserved_1:7; @@ -76,18 +76,18 @@ typedef union { struct { /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ uint32_t sec_dpa_level:2; /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ uint32_t sec_dpa_cfg_sel:1; uint32_t reserved_3:29; @@ -119,9 +119,9 @@ typedef union { typedef union { struct { /** rom_table_lock : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ uint32_t rom_table_lock:1; uint32_t reserved_1:31; @@ -150,9 +150,9 @@ typedef union { struct { /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable debug RunStall functionality between HP CPU and - * LP CPU.\\ - * 0: Disable\\ - * 1: Enable\\ + * LP CPU. + * 0: Disable + * 1: Enable */ uint32_t core_debug_runstall_enable:1; /** core_runstalled : RO; bitpos: [1]; default: 0; @@ -172,14 +172,17 @@ typedef union { struct { /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0; * This field controls hp system memory WPULSE parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t hp_mem_wpulse:3; /** hp_mem_wa : R/W; bitpos: [5:3]; default: 4; * This field controls hp system memory WA parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t hp_mem_wa:3; /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0; * This field controls hp system memory RA parameter. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t hp_mem_ra:2; uint32_t reserved_8:24; @@ -187,6 +190,19 @@ typedef union { uint32_t val; } hp_system_mem_test_conf_reg_t; +/** Type of sdio_sprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sdio_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 12816; + * sdio mem separate control signal. + */ + uint32_t sdio_sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_system_sdio_sprf_ctrl_reg_t; + /** Type of sprom_ctrl register * reserved */ @@ -257,6 +273,26 @@ typedef union { uint32_t val; } hp_system_bitscrambler_peri_sel_reg_t; +/** Type of axi_mst_pri register + * AXI mst priority configuration register + */ +typedef union { + struct { + /** dma_priority : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ + uint32_t dma_priority:1; + /** cache_priority : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ + uint32_t cache_priority:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_axi_mst_pri_reg_t; + /** Type of clock_gate register * HP-SYSTEM clock gating configure register */ @@ -264,6 +300,7 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; * Set this bit as 1 to force on clock gating. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -289,9 +326,9 @@ typedef union { uint32_t cpu_peri_timeout_int_clear:1; /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ uint32_t cpu_peri_timeout_protect_en:1; uint32_t reserved_18:14; @@ -338,16 +375,16 @@ typedef union { */ uint32_t hp_peri_timeout_thres:16; /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ uint32_t hp_peri_timeout_int_clear:1; /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ uint32_t hp_peri_timeout_protect_en:1; uint32_t reserved_18:14; @@ -391,14 +428,17 @@ typedef union { /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Set the timeout threshold for bus access, corresponding to the number of clock * cycles of the clock domain. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_peri_timeout_thres:16; /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; * Set this bit as 1 to clear timeout interrupt + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_peri_timeout_int_clear:1; /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Set this bit as 1 to enable timeout protection for accessing modem registers + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_peri_timeout_protect_en:1; uint32_t reserved_18:14; @@ -413,6 +453,7 @@ typedef union { struct { /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Record the address information of abnormal access + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_peri_timeout_addr:32; }; @@ -427,6 +468,7 @@ typedef union { /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Record master id[4:0] & master permission[6:5] when trigger timeout. This register * will be cleared after the interrupt is cleared. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_peri_timeout_uid:7; uint32_t reserved_7:25; @@ -443,10 +485,12 @@ typedef union { struct { /** redcy_ena : W/R; bitpos: [0]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t redcy_ena:1; /** redcy_result : RO; bitpos: [1]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t redcy_result:1; uint32_t reserved_2:30; @@ -461,6 +505,7 @@ typedef union { struct { /** redcy_low : W/R; bitpos: [31:0]; default: 0; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t redcy_low:32; }; @@ -474,6 +519,7 @@ typedef union { struct { /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; * Only reserved for ECO. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t redcy_high:32; }; @@ -489,6 +535,7 @@ typedef union { struct { /** fpga_debug : R/W; bitpos: [0]; default: 1; * Reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fpga_debug:1; uint32_t reserved_1:31; @@ -532,13 +579,16 @@ typedef struct { volatile hp_system_rom_table_reg_t rom_table; volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; volatile hp_system_mem_test_conf_reg_t mem_test_conf; - uint32_t reserved_048[10]; + uint32_t reserved_048[9]; + volatile hp_system_sdio_sprf_ctrl_reg_t sdio_sprf_ctrl; volatile hp_system_sprom_ctrl_reg_t sprom_ctrl; volatile hp_system_spram_ctrl_reg_t spram_ctrl; volatile hp_system_sprf_ctrl_reg_t sprf_ctrl; volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl; volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel; - uint32_t reserved_084[215]; + uint32_t reserved_084; + volatile hp_system_axi_mst_pri_reg_t axi_mst_pri; + uint32_t reserved_08c[213]; volatile hp_system_rnd_eco_reg_t rnd_eco; volatile hp_system_rnd_eco_low_reg_t rnd_eco_low; volatile hp_system_rnd_eco_high_reg_t rnd_eco_high; diff --git a/components/soc/esp32c5/register/soc/huk_reg.h b/components/soc/esp32c5/register/soc/huk_reg.h index b3fbb16fa6..20c44c4d3d 100644 --- a/components/soc/esp32c5/register/soc/huk_reg.h +++ b/components/soc/esp32c5/register/soc/huk_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -198,12 +198,20 @@ extern "C" { #define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S) #define HUK_RISK_LEVEL_V 0x00000007U #define HUK_RISK_LEVEL_S 2 +/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0; + * The update request of HUK info. 0: User can update HUK info according to the risk + * level. 1: The HUK info is expired, and user need to update it. + */ +#define HUK_UPDATE_REQ (BIT(5)) +#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S) +#define HUK_UPDATE_REQ_V 0x00000001U +#define HUK_UPDATE_REQ_S 5 /** HUK_DATE_REG register * Version control register */ #define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc) -/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704; +/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232; * HUK Generator version control register. */ #define HUK_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/huk_struct.h b/components/soc/esp32c5/register/soc/huk_struct.h index 6adbc28170..5be5968adf 100644 --- a/components/soc/esp32c5/register/soc/huk_struct.h +++ b/components/soc/esp32c5/register/soc/huk_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -191,7 +191,12 @@ typedef union { * are in the PUF SRAM. 7: Error Level, HUK is invalid. */ uint32_t risk_level:3; - uint32_t reserved_5:27; + /** update_req : RO; bitpos: [5]; default: 0; + * The update request of HUK info. 0: User can update HUK info according to the risk + * level. 1: The HUK info is expired, and user need to update it. + */ + uint32_t update_req:1; + uint32_t reserved_6:26; }; uint32_t val; } huk_status_reg_t; @@ -203,7 +208,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36720704; + /** date : R/W; bitpos: [27:0]; default: 37765232; * HUK Generator version control register. */ uint32_t date:28; diff --git a/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h index bada636475..6c6bc860bd 100644 --- a/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,6 +22,13 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register * WIFI_MAC_NMI mapping register @@ -34,6 +41,13 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register * WIFI_PWR_INTR mapping register @@ -46,6 +60,13 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register * WIFI_BB_INTR mapping register @@ -58,6 +79,13 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register * BT_MAC_INTR mapping register @@ -70,6 +98,13 @@ extern "C" { #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register * BT_BB_INTR mapping register @@ -82,6 +117,13 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) #define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register * BT_BB_NMI mapping register @@ -94,6 +136,13 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) #define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register * LP_TIMER_INTR mapping register @@ -106,6 +155,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_COEX_INTR_MAP_REG register * COEX_INTR mapping register @@ -118,6 +174,13 @@ extern "C" { #define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) #define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register * BLE_TIMER_INTR mapping register @@ -130,6 +193,13 @@ extern "C" { #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register * BLE_SEC_INTR mapping register @@ -142,6 +212,13 @@ extern "C" { #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register * I2C_MST_INTR mapping register @@ -154,6 +231,13 @@ extern "C" { #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register * ZB_MAC_INTR mapping register @@ -166,6 +250,13 @@ extern "C" { #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PMU_INTR_MAP_REG register * PMU_INTR mapping register @@ -178,6 +269,13 @@ extern "C" { #define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) #define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register * EFUSE_INTR mapping register @@ -190,6 +288,13 @@ extern "C" { #define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) #define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * LP_RTC_TIMER_INTR mapping register @@ -202,6 +307,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register * LP_UART_INTR mapping register @@ -214,6 +326,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_UART_INTR_MAP_M (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S) #define INTERRUPT_CORE0_LP_UART_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_UART_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_UART_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register * LP_I2C_INTR mapping register @@ -226,6 +345,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S) #define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register * LP_WDT_INTR mapping register @@ -238,6 +364,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * LP_PERI_TIMEOUT_INTR mapping register @@ -250,6 +383,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register * LP_APM_M0_INTR mapping register @@ -262,6 +402,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register * LP_APM_M1_INTR mapping register @@ -274,6 +421,13 @@ extern "C" { #define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S) #define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HUK_INTR_MAP_REG register * HUK_INTR mapping register @@ -286,6 +440,13 @@ extern "C" { #define INTERRUPT_CORE0_HUK_INTR_MAP_M (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S) #define INTERRUPT_CORE0_HUK_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HUK_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * CPU_INTR_FROM_CPU_0 mapping register @@ -298,6 +459,13 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * CPU_INTR_FROM_CPU_1 mapping register @@ -310,6 +478,13 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * CPU_INTR_FROM_CPU_2 mapping register @@ -322,6 +497,13 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * CPU_INTR_FROM_CPU_3 mapping register @@ -334,18 +516,32 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 - -/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register - * ASSIST_DEBUG_INTR mapping register +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) -/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register + * BUS_MONITOR_INTR mapping register + */ +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register * TRACE_INTR mapping register @@ -358,6 +554,13 @@ extern "C" { #define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) #define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register * CACHE_INTR mapping register @@ -370,6 +573,13 @@ extern "C" { #define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) #define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * CPU_PERI_TIMEOUT_INTR mapping register @@ -382,6 +592,13 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * GPIO_INTERRUPT_PRO mapping register @@ -394,6 +611,13 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register * GPIO_INTERRUPT_EXT mapping register @@ -406,6 +630,13 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PAU_INTR_MAP_REG register * PAU_INTR mapping register @@ -418,6 +649,13 @@ extern "C" { #define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) #define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * HP_PERI_TIMEOUT_INTR mapping register @@ -430,6 +668,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register * MODEM_PERI_TIMEOUT_INTR mapping register @@ -442,6 +687,13 @@ extern "C" { #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register * HP_APM_M0_INTR mapping register @@ -454,6 +706,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register * HP_APM_M1_INTR mapping register @@ -466,6 +725,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register * HP_APM_M2_INTR mapping register @@ -478,6 +744,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register * HP_APM_M3_INTR mapping register @@ -490,6 +763,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register * HP_APM_M4_INTR mapping register @@ -502,6 +782,13 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register * LP_APM0_INTR mapping register @@ -514,11 +801,56 @@ extern "C" { #define INTERRUPT_CORE0_LP_APM0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM0_INTR_MAP_S) #define INTERRUPT_CORE0_LP_APM0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_APM0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_APM0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register + * CPU_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register + * CPU_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register * MSPI_INTR mapping register */ -#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) /** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -526,11 +858,18 @@ extern "C" { #define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) #define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2S_INTR_MAP_REG register * I2S_INTR mapping register */ -#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) /** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -538,11 +877,18 @@ extern "C" { #define INTERRUPT_CORE0_I2S_INTR_MAP_M (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S) #define INTERRUPT_CORE0_I2S_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register * UHCI0_INTR mapping register */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) /** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -550,11 +896,18 @@ extern "C" { #define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S) #define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART0_INTR_MAP_REG register * UART0_INTR mapping register */ -#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) /** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -562,11 +915,18 @@ extern "C" { #define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) #define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART1_INTR_MAP_REG register * UART1_INTR mapping register */ -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) /** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -574,11 +934,18 @@ extern "C" { #define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) #define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register * LEDC_INTR mapping register */ -#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) /** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -586,11 +953,18 @@ extern "C" { #define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) #define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TWAI0_INTR_MAP_REG register * TWAI0_INTR mapping register */ -#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) /** INTERRUPT_CORE0_TWAI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -598,11 +972,18 @@ extern "C" { #define INTERRUPT_CORE0_TWAI0_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_INTR_MAP_S) #define INTERRUPT_CORE0_TWAI0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TWAI0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TWAI0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG register * TWAI0_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) /** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -610,11 +991,18 @@ extern "C" { #define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TWAI1_INTR_MAP_REG register * TWAI1_INTR mapping register */ -#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) /** INTERRUPT_CORE0_TWAI1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -622,11 +1010,18 @@ extern "C" { #define INTERRUPT_CORE0_TWAI1_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_INTR_MAP_S) #define INTERRUPT_CORE0_TWAI1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TWAI1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TWAI1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG register * TWAI1_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) /** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -634,11 +1029,18 @@ extern "C" { #define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register * USB_SERIAL_JTAG_INTR mapping register */ -#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -646,11 +1048,18 @@ extern "C" { #define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S) #define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S 0 +/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_RMT_INTR_MAP_REG register * RMT_INTR mapping register */ -#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) /** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -658,11 +1067,18 @@ extern "C" { #define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S) #define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register * I2C_EXT0_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -670,11 +1086,18 @@ extern "C" { #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register * TG0_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) /** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -682,11 +1105,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register * TG0_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -694,11 +1124,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register * TG1_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) /** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -706,11 +1143,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register * TG1_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -718,11 +1162,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * SYSTIMER_TARGET0_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -730,11 +1181,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * SYSTIMER_TARGET1_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -742,11 +1200,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * SYSTIMER_TARGET2_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -754,11 +1219,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register * APB_ADC_INTR mapping register */ -#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) /** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -766,11 +1238,18 @@ extern "C" { #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PWM_INTR_MAP_REG register * PWM_INTR mapping register */ -#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) /** INTERRUPT_CORE0_PWM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -778,11 +1257,18 @@ extern "C" { #define INTERRUPT_CORE0_PWM_INTR_MAP_M (INTERRUPT_CORE0_PWM_INTR_MAP_V << INTERRUPT_CORE0_PWM_INTR_MAP_S) #define INTERRUPT_CORE0_PWM_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PWM_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PWM_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register * PCNT_INTR mapping register */ -#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) /** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -790,11 +1276,18 @@ extern "C" { #define INTERRUPT_CORE0_PCNT_INTR_MAP_M (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S) #define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register * PARL_IO_TX_INTR mapping register */ -#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -802,11 +1295,18 @@ extern "C" { #define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S) #define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register * PARL_IO_RX_INTR mapping register */ -#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -814,11 +1314,56 @@ extern "C" { #define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S) #define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register + * SLC0_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register + * SLC1_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register * DMA_IN_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -826,11 +1371,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register * DMA_IN_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -838,11 +1390,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register * DMA_IN_CH2_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -850,11 +1409,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * DMA_OUT_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -862,11 +1428,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * DMA_OUT_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -874,11 +1447,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register * DMA_OUT_CH2_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -886,11 +1466,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register * GPSPI2_INTR mapping register */ -#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) /** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -898,11 +1485,18 @@ extern "C" { #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_AES_INTR_MAP_REG register * AES_INTR mapping register */ -#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) /** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -910,11 +1504,18 @@ extern "C" { #define INTERRUPT_CORE0_AES_INTR_MAP_M (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S) #define INTERRUPT_CORE0_AES_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AES_INTR_MAP_S 0 +/** INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SHA_INTR_MAP_REG register * SHA_INTR mapping register */ -#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) /** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -922,11 +1523,18 @@ extern "C" { #define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) #define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_RSA_INTR_MAP_REG register * RSA_INTR mapping register */ -#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) /** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -934,11 +1542,18 @@ extern "C" { #define INTERRUPT_CORE0_RSA_INTR_MAP_M (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S) #define INTERRUPT_CORE0_RSA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_RSA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_RSA_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECC_INTR_MAP_REG register * ECC_INTR mapping register */ -#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) /** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -946,11 +1561,18 @@ extern "C" { #define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) #define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register * ECDSA_INTR mapping register */ -#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) /** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -958,11 +1580,18 @@ extern "C" { #define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) #define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_KM_INTR_MAP_REG register * KM_INTR mapping register */ -#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) /** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -970,14 +1599,21 @@ extern "C" { #define INTERRUPT_CORE0_KM_INTR_MAP_M (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S) #define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_KM_INTR_MAP_S 0 +/** INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S 8 -/** INTERRUPT_CORE0_INT_STATUS_0_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register * Status register for interrupt sources 0 ~ 31 */ -#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) /** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -986,13 +1622,13 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_0_S 0 -/** INTERRUPT_CORE0_INT_STATUS_1_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register * Status register for interrupt sources 32 ~ 63 */ -#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) /** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -1001,25 +1637,94 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_1_S 0 -/** INTERRUPT_CORE0_INT_STATUS_2_REG register - * Status register for interrupt sources 64 ~ 95 +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 83 */ -#define INTERRUPT_CORE0_INT_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) -/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [19:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 83. Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ -#define INTERRUPT_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2 0x000FFFFFU #define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) -#define INTERRUPT_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_V 0x000FFFFFU #define INTERRUPT_CORE0_INT_STATUS_2_S 0 +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register + * PASS_IN_SEC status register for interrupt sources 64 ~ 83 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [19:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 83. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 0x000FFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V 0x000FFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register + * reserved + */ +#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_M (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S) +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S 0 + +/** INTERRUPT_CORE0_SECURE_STATUS_REG register + * reserved + */ +#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) +/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SECURE_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_M (INTERRUPT_CORE0_INT_SECURE_STATUS_V << INTERRUPT_CORE0_INT_SECURE_STATUS_S) +#define INTERRUPT_CORE0_INT_SECURE_STATUS_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_S 0 + /** INTERRUPT_CORE0_CLOCK_GATE_REG register * Interrupt clock gating configure register */ -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) /** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ @@ -1032,7 +1737,7 @@ extern "C" { * Version control register */ #define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) -/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36773985; +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 37814858; * Version control register */ #define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h index 06e03ffaa4..e8ecd82775 100644 --- a/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h +++ b/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,7 +20,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t wifi_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** wifi_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_wifi_mac_intr_map_reg_t; @@ -34,7 +39,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t wifi_mac_nmi_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** wifi_mac_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_mac_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_wifi_mac_nmi_map_reg_t; @@ -48,7 +58,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t wifi_pwr_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** wifi_pwr_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_pwr_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_wifi_pwr_intr_map_reg_t; @@ -62,7 +77,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t wifi_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** wifi_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_wifi_bb_intr_map_reg_t; @@ -76,7 +96,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t bt_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** bt_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_bt_mac_intr_map_reg_t; @@ -90,7 +115,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t bt_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** bt_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_bt_bb_intr_map_reg_t; @@ -104,7 +134,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t bt_bb_nmi_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** bt_bb_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_bb_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_bt_bb_nmi_map_reg_t; @@ -118,7 +153,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_timer_intr_map_reg_t; @@ -132,7 +172,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t coex_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** coex_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t coex_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_coex_intr_map_reg_t; @@ -146,7 +191,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t ble_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ble_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_ble_timer_intr_map_reg_t; @@ -160,7 +210,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t ble_sec_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** ble_sec_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ble_sec_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_ble_sec_intr_map_reg_t; @@ -174,7 +229,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t i2c_mst_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** i2c_mst_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2c_mst_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_i2c_mst_intr_map_reg_t; @@ -188,7 +248,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t zb_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** zb_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t zb_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_zb_mac_intr_map_reg_t; @@ -202,7 +267,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t pmu_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** pmu_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pmu_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_pmu_intr_map_reg_t; @@ -216,7 +286,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t efuse_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** efuse_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t efuse_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_efuse_intr_map_reg_t; @@ -230,7 +305,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_rtc_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_rtc_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_rtc_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_rtc_timer_intr_map_reg_t; @@ -244,7 +324,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_uart_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_uart_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_uart_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_uart_intr_map_reg_t; @@ -258,7 +343,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_i2c_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_i2c_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_i2c_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_i2c_intr_map_reg_t; @@ -272,7 +362,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_wdt_intr_map_reg_t; @@ -286,7 +381,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_peri_timeout_intr_map_reg_t; @@ -300,7 +400,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_apm_m0_intr_map_reg_t; @@ -314,7 +419,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_apm_m1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_apm_m1_intr_map_reg_t; @@ -328,7 +438,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t huk_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** huk_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t huk_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_huk_intr_map_reg_t; @@ -342,7 +457,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cpu_intr_from_cpu_0_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_0_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_0_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; @@ -356,7 +476,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cpu_intr_from_cpu_1_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_1_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_1_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; @@ -370,7 +495,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cpu_intr_from_cpu_2_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_2_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_2_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; @@ -384,7 +514,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cpu_intr_from_cpu_3_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_3_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_3_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; @@ -398,7 +533,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t bus_monitor_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** bus_monitor_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bus_monitor_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_bus_monitor_intr_map_reg_t; @@ -412,7 +552,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t trace_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t trace_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_trace_intr_map_reg_t; @@ -426,7 +571,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cache_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cache_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cache_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cache_intr_map_reg_t; @@ -440,7 +590,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t cpu_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** cpu_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_cpu_peri_timeout_intr_map_reg_t; @@ -454,7 +609,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t gpio_interrupt_pro_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** gpio_interrupt_pro_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpio_interrupt_pro_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_gpio_interrupt_pro_map_reg_t; @@ -468,7 +628,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t gpio_interrupt_ext_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** gpio_interrupt_ext_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpio_interrupt_ext_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_gpio_interrupt_ext_map_reg_t; @@ -482,7 +647,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t pau_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** pau_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pau_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_pau_intr_map_reg_t; @@ -496,7 +666,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_peri_timeout_intr_map_reg_t; @@ -510,7 +685,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t modem_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** modem_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t modem_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_modem_peri_timeout_intr_map_reg_t; @@ -524,7 +704,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_apm_m0_intr_map_reg_t; @@ -538,7 +723,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_apm_m1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_apm_m1_intr_map_reg_t; @@ -552,7 +742,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_apm_m2_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_apm_m2_intr_map_reg_t; @@ -566,7 +761,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_apm_m3_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_apm_m3_intr_map_reg_t; @@ -580,7 +780,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t hp_apm_m4_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** hp_apm_m4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m4_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_hp_apm_m4_intr_map_reg_t; @@ -594,11 +799,54 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t lp_apm0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** lp_apm0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_apm0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_lp_apm0_intr_map_reg_t; +/** Type of cpu_apm_m0_intr_map register + * CPU_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m0_intr_map_reg_t; + +/** Type of cpu_apm_m1_intr_map register + * CPU_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m1_intr_map_reg_t; + /** Type of mspi_intr_map register * MSPI_INTR mapping register */ @@ -608,7 +856,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t mspi_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** mspi_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t mspi_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_mspi_intr_map_reg_t; @@ -622,7 +875,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t i2s_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** i2s_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2s_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_i2s_intr_map_reg_t; @@ -636,7 +894,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t uhci0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** uhci0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uhci0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_uhci0_intr_map_reg_t; @@ -650,7 +913,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t uart0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** uart0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uart0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_uart0_intr_map_reg_t; @@ -664,7 +932,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t uart1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** uart1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uart1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_uart1_intr_map_reg_t; @@ -678,13 +951,18 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t ledc_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** ledc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ledc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_ledc_intr_map_reg_t; /** Type of twai0_intr_map register - * TWAI0_INTR mapping register + * twai0_INTR mapping register */ typedef union { struct { @@ -692,13 +970,18 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t twai0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** twai0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t twai0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_twai0_intr_map_reg_t; /** Type of twai0_timer_intr_map register - * TWAI0_TIMER_INTR mapping register + * twai0_TIMER_INTR mapping register */ typedef union { struct { @@ -706,13 +989,18 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t twai0_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** twai0_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t twai0_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_twai0_timer_intr_map_reg_t; /** Type of twai1_intr_map register - * TWAI1_INTR mapping register + * twai1_INTR mapping register */ typedef union { struct { @@ -720,13 +1008,18 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t twai1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** twai1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t twai1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_twai1_intr_map_reg_t; /** Type of twai1_timer_intr_map register - * TWAI1_TIMER_INTR mapping register + * twai1_TIMER_INTR mapping register */ typedef union { struct { @@ -734,7 +1027,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t twai1_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** twai1_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t twai1_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_twai1_timer_intr_map_reg_t; @@ -748,7 +1046,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t usb_serial_jtag_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** usb_serial_jtag_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t usb_serial_jtag_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_usb_serial_jtag_intr_map_reg_t; @@ -762,7 +1065,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t rmt_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** rmt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t rmt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_rmt_intr_map_reg_t; @@ -776,7 +1084,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t i2c_ext0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** i2c_ext0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2c_ext0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_i2c_ext0_intr_map_reg_t; @@ -790,7 +1103,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t tg0_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** tg0_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg0_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_tg0_t0_intr_map_reg_t; @@ -804,7 +1122,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t tg0_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** tg0_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg0_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_tg0_wdt_intr_map_reg_t; @@ -818,7 +1141,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t tg1_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** tg1_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg1_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_tg1_t0_intr_map_reg_t; @@ -832,7 +1160,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t tg1_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** tg1_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg1_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_tg1_wdt_intr_map_reg_t; @@ -846,7 +1179,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t systimer_target0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** systimer_target0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_systimer_target0_intr_map_reg_t; @@ -860,7 +1198,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t systimer_target1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** systimer_target1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_systimer_target1_intr_map_reg_t; @@ -874,7 +1217,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t systimer_target2_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** systimer_target2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_systimer_target2_intr_map_reg_t; @@ -888,7 +1236,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t apb_adc_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** apb_adc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t apb_adc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_apb_adc_intr_map_reg_t; @@ -902,7 +1255,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t pwm_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** pwm_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pwm_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_pwm_intr_map_reg_t; @@ -916,7 +1274,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t pcnt_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** pcnt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pcnt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_pcnt_intr_map_reg_t; @@ -930,7 +1293,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t parl_io_tx_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** parl_io_tx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t parl_io_tx_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_parl_io_tx_intr_map_reg_t; @@ -944,11 +1312,54 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t parl_io_rx_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** parl_io_rx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t parl_io_rx_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_parl_io_rx_intr_map_reg_t; +/** Type of slc0_intr_map register + * SLC0_INTR mapping register + */ +typedef union { + struct { + /** slc0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc0_intr_map:6; + uint32_t reserved_6:2; + /** slc0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t slc0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc0_intr_map_reg_t; + +/** Type of slc1_intr_map register + * SLC1_INTR mapping register + */ +typedef union { + struct { + /** slc1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc1_intr_map:6; + uint32_t reserved_6:2; + /** slc1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t slc1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc1_intr_map_reg_t; + /** Type of dma_in_ch0_intr_map register * DMA_IN_CH0_INTR mapping register */ @@ -958,7 +1369,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_in_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_in_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_in_ch0_intr_map_reg_t; @@ -972,7 +1388,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_in_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_in_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_in_ch1_intr_map_reg_t; @@ -986,7 +1407,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_in_ch2_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_in_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_in_ch2_intr_map_reg_t; @@ -1000,7 +1426,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_out_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_out_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_out_ch0_intr_map_reg_t; @@ -1014,7 +1445,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_out_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_out_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_out_ch1_intr_map_reg_t; @@ -1028,7 +1464,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t dma_out_ch2_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** dma_out_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_dma_out_ch2_intr_map_reg_t; @@ -1042,7 +1483,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t gpspi2_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** gpspi2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpspi2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_gpspi2_intr_map_reg_t; @@ -1056,7 +1502,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t aes_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** aes_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t aes_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_aes_intr_map_reg_t; @@ -1070,7 +1521,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t sha_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** sha_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t sha_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_sha_intr_map_reg_t; @@ -1084,7 +1540,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t rsa_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** rsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t rsa_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_rsa_intr_map_reg_t; @@ -1098,7 +1559,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t ecc_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** ecc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ecc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_ecc_intr_map_reg_t; @@ -1112,7 +1578,12 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t ecdsa_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** ecdsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ecdsa_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_ecdsa_intr_map_reg_t; @@ -1126,58 +1597,29 @@ typedef union { * Configures the interrupt source into one CPU interrupt. */ uint32_t km_intr_map:6; - uint32_t reserved_6:26; + uint32_t reserved_6:2; + /** km_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t km_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; } interrupt_core0_km_intr_map_reg_t; -/** Type of int_status_0 register - * Status register for interrupt sources 0 ~ 31 +/** Type of sig_idx_assert_in_sec register + * reserved */ typedef union { struct { - /** int_status_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered + /** int_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0; + * reserved */ - uint32_t int_status_0:32; + uint32_t int_sig_idx_assert_in_sec:6; + uint32_t reserved_6:26; }; uint32_t val; -} interrupt_core0_int_status_0_reg_t; - -/** Type of int_status_1 register - * Status register for interrupt sources 32 ~ 63 - */ -typedef union { - struct { - /** int_status_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_1:32; - }; - uint32_t val; -} interrupt_core0_int_status_1_reg_t; - -/** Type of int_status_2 register - * Status register for interrupt sources 64 ~ 95 - */ -typedef union { - struct { - /** int_status_2 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_2:32; - }; - uint32_t val; -} interrupt_core0_int_status_2_reg_t; +} interrupt_core0_sig_idx_assert_in_sec_reg_t; /** Type of clock_gate register * Interrupt clock gating configure register @@ -1194,13 +1636,126 @@ typedef union { } interrupt_core0_clock_gate_reg_t; +/** Group: Status Registers */ +/** Type of int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * Status register for interrupt sources 64 ~ 83 + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [19:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 83. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_2:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of src_pass_in_sec_status_0 register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_0:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_0_reg_t; + +/** Type of src_pass_in_sec_status_1 register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_1:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_1_reg_t; + +/** Type of src_pass_in_sec_status_2 register + * PASS_IN_SEC status register for interrupt sources 64 ~ 83 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_2 : RO; bitpos: [19:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 83. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_2:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_2_reg_t; + +/** Type of secure_status register + * reserved + */ +typedef union { + struct { + /** int_secure_status : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t int_secure_status:32; + }; + uint32_t val; +} interrupt_core0_secure_status_reg_t; + + /** Group: Version Register */ /** Type of interrupt_date register * Version control register */ typedef union { struct { - /** interrupt_date : R/W; bitpos: [27:0]; default: 36773985; + /** interrupt_date : R/W; bitpos: [27:0]; default: 37814858; * Version control register */ uint32_t interrupt_date:28; @@ -1253,6 +1808,8 @@ typedef struct { volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; volatile interrupt_core0_hp_apm_m4_intr_map_reg_t hp_apm_m4_intr_map; volatile interrupt_core0_lp_apm0_intr_map_reg_t lp_apm0_intr_map; + volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t cpu_apm_m0_intr_map; + volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t cpu_apm_m1_intr_map; volatile interrupt_core0_mspi_intr_map_reg_t mspi_intr_map; volatile interrupt_core0_i2s_intr_map_reg_t i2s_intr_map; volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map; @@ -1278,6 +1835,8 @@ typedef struct { volatile interrupt_core0_pcnt_intr_map_reg_t pcnt_intr_map; volatile interrupt_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map; volatile interrupt_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map; + volatile interrupt_core0_slc0_intr_map_reg_t slc0_intr_map; + volatile interrupt_core0_slc1_intr_map_reg_t slc1_intr_map; volatile interrupt_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; volatile interrupt_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; volatile interrupt_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; @@ -1291,11 +1850,16 @@ typedef struct { volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map; volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map; volatile interrupt_core0_km_intr_map_reg_t km_intr_map; - volatile interrupt_core0_int_status_0_reg_t int_status_0; - volatile interrupt_core0_int_status_1_reg_t int_status_1; - volatile interrupt_core0_int_status_2_reg_t int_status_2; + volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2; + volatile interrupt_core0_src_pass_in_sec_status_0_reg_t src_pass_in_sec_status_0; + volatile interrupt_core0_src_pass_in_sec_status_1_reg_t src_pass_in_sec_status_1; + volatile interrupt_core0_src_pass_in_sec_status_2_reg_t src_pass_in_sec_status_2; + volatile interrupt_core0_sig_idx_assert_in_sec_reg_t sig_idx_assert_in_sec; + volatile interrupt_core0_secure_status_reg_t secure_status; volatile interrupt_core0_clock_gate_reg_t clock_gate; - uint32_t reserved_150[427]; + uint32_t reserved_174[418]; volatile interrupt_core0_interrupt_date_reg_t interrupt_date; } interrupt_core0_dev_t; diff --git a/components/soc/esp32c5/register/soc/keymng_reg_eco2.h b/components/soc/esp32c5/register/soc/keymng_reg_eco2.h new file mode 100644 index 0000000000..a385df2586 --- /dev/null +++ b/components/soc/esp32c5/register/soc/keymng_reg_eco2.h @@ -0,0 +1,395 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_REG_CG_FORCE_ON (BIT(0)) +#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S) +#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_REG_CG_FORCE_ON_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) +/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ +#define KEYMNG_USE_EFUSE_KEY 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) +#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_S 0 +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 5 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(10)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 10 +/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_FLASH_KEY_LEN (BIT(11)) +#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S) +#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_S 11 +/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_PSRAM_KEY_LEN (BIT(12)) +#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S) +#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_S 12 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) +/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6 +/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ +#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7)) +#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S) +#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7 +/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ +#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8)) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S) +#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_192_VLD_S 0 +/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1)) +#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S) +#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_256_VLD_S 1 +/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_FLASH_VLD (BIT(2)) +#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S) +#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U +#define KEYMNG_KEY_FLASH_VLD_S 2 +/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_HMAC_VLD (BIT(3)) +#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S) +#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U +#define KEYMNG_KEY_HMAC_VLD_S 3 +/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_DS_VLD (BIT(4)) +#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S) +#define KEYMNG_KEY_DS_VLD_V 0x00000001U +#define KEYMNG_KEY_DS_VLD_S 4 +/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_PSRAM_VLD (BIT(5)) +#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S) +#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U +#define KEYMNG_KEY_PSRAM_VLD_S 5 +/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6)) +#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S) +#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_384_VLD_S 6 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/keymng_struct_eco2.h b/components/soc/esp32c5/register/soc/keymng_struct_eco2.h new file mode 100644 index 0000000000..faacfdf486 --- /dev/null +++ b/components/soc/esp32c5/register/soc/keymng_struct_eco2.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * Key Manager clock gate control register + */ +typedef union { + struct { + /** reg_cg_force_on : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t reg_cg_force_on:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Key Manager interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_raw_reg_t; + +/** Type of int_st register + * Key Manager interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_st_reg_t; + +/** Type of int_ena register + * Key Manager interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_ena_reg_t; + +/** Type of int_clr register + * Key Manager interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_clr_reg_t; + + +/** Group: Static configuration registers */ +/** Type of static register + * Key Manager static configuration register + */ +typedef union { + struct { + /** use_efuse_key : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ + uint32_t use_efuse_key:5; + /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ + uint32_t rnd_switch_cycle:5; + /** use_sw_init_key : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ + uint32_t use_sw_init_key:1; + /** flash_key_len : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t flash_key_len:1; + /** psram_key_len : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t psram_key_len:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} keymng_static_reg_t; + +/** Type of lock register + * Key Manager static configuration locker register + */ +typedef union { + struct { + /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ + uint32_t use_efuse_key_lock:5; + /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ + uint32_t rnd_switch_cycle_lock:1; + /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ + uint32_t use_sw_init_key_lock:1; + /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ + uint32_t flash_key_len_lock:1; + /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ + uint32_t psram_key_len_lock:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} keymng_lock_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** kgen_mode : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ + uint32_t kgen_mode:3; + /** key_purpose : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ + uint32_t key_purpose:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * Key Manager control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to conti Key Manager operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** conti : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ + uint32_t conti:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * Key Manager state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * Key Manager operation result register + */ +typedef union { + struct { + /** proc_result : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ + uint32_t proc_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_result_reg_t; + +/** Type of key_vld register + * Key Manager key status register + */ +typedef union { + struct { + /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_192_vld:1; + /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_256_vld:1; + /** key_flash_vld : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_flash_vld:1; + /** key_hmac_vld : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_hmac_vld:1; + /** key_ds_vld : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ds_vld:1; + /** key_psram_vld : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_psram_vld:1; + /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_384_vld:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_key_vld_reg_t; + +/** Type of huk_vld register + * Key Manager HUK status register + */ +typedef union { + struct { + /** huk_valid : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ + uint32_t huk_valid:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_huk_vld_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} keymng_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile keymng_clk_reg_t clk; + volatile keymng_int_raw_reg_t int_raw; + volatile keymng_int_st_reg_t int_st; + volatile keymng_int_ena_reg_t int_ena; + volatile keymng_int_clr_reg_t int_clr; + volatile keymng_static_reg_t static_conf; + volatile keymng_lock_reg_t lock; + volatile keymng_conf_reg_t conf; + volatile keymng_start_reg_t start; + volatile keymng_state_reg_t state; + volatile keymng_result_reg_t result; + volatile keymng_key_vld_reg_t key_vld; + volatile keymng_huk_vld_reg_t huk_vld; + uint32_t reserved_038[49]; + volatile keymng_date_reg_t date; + volatile uint32_t assist_info[16]; + volatile uint32_t public_info[16]; + volatile uint32_t sw_init_key[8]; +} keymng_dev_t; + +extern keymng_dev_t KEYMNG; + +#ifndef __cplusplus +_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/lp_analog_peri_reg_eco2.h b/components/soc/esp32c5/register/soc/lp_analog_peri_reg_eco2.h new file mode 100644 index 0000000000..1c27ca2f21 --- /dev/null +++ b/components/soc/esp32c5/register/soc/lp_analog_peri_reg_eco2.h @@ -0,0 +1,249 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * Configure brownout mode0 + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * enable suspend spi when brownout interrupt or not + * 1:enable + * 0:disable + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * enable power down RF when brownout interrupt or not + * 1:enable + * 0:disable + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * set the undervoltage hold time for triggering brownout interrupt + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * set the undervoltage hold time for triggering brownout reset + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * clear brownout count or not + * 1: clear + * 0: no operation + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * enable brownout interrupt or not + * 1: enable + * 0: disable + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * select brownout reset level + * 1: system reset + * 0: chip reset + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * enable brownout reset or not + * 1: enable + * 0: disable + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * Configure brownout mode1 + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * enable brownout mode1 reset or not + * 1: enable + * 0: disable + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * Configure power glitch + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8) +/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0; + * enable powerglitch or not + */ +#define LP_ANA_PWR_GLITCH_RESET_ENA 0x0000000FU +#define LP_ANA_PWR_GLITCH_RESET_ENA_M (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S) +#define LP_ANA_PWR_GLITCH_RESET_ENA_V 0x0000000FU +#define LP_ANA_PWR_GLITCH_RESET_ENA_S 27 +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_FIB_ENABLE_REG register + * configure FIB REG + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * configure analog fib by software + */ +#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_S 0 + +/** LP_ANA_INT_RAW_REG register + * interrpt raw register + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10) +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * brownout mode0 interrupt raw register + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * interrpt status register + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14) +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * brownout mode0 interrupt status register + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * interrpt enable register + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18) +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * brownout mode0 interrupt enable register + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * interrpt clear register + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c) +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * brownout mode0 interrupt clear register + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * lp interrupt raw register + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt raw register + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * lp interrupt status register + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt status register + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * lp interrupt enable register + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt enable register + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * lp interrupt clear register + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt clear register + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * version register + */ +#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:1]; default: 18387264; + * version register + */ +#define LP_ANA_LP_ANA_DATE 0x3FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x3FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 1 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/lp_analog_peri_struct_eco2.h b/components/soc/esp32c5/register/soc/lp_analog_peri_struct_eco2.h new file mode 100644 index 0000000000..d117f33d29 --- /dev/null +++ b/components/soc/esp32c5/register/soc/lp_analog_peri_struct_eco2.h @@ -0,0 +1,271 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * Configure brownout mode0 + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * enable suspend spi when brownout interrupt or not + * 1:enable + * 0:disable + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * enable power down RF when brownout interrupt or not + * 1:enable + * 0:disable + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * set the undervoltage hold time for triggering brownout interrupt + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * set the undervoltage hold time for triggering brownout reset + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * clear brownout count or not + * 1: clear + * 0: no operation + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * enable brownout interrupt or not + * 1: enable + * 0: disable + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * select brownout reset level + * 1: system reset + * 0: chip reset + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * enable brownout reset or not + * 1: enable + * 0: disable + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * Configure brownout mode1 + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * enable brownout mode1 reset or not + * 1: enable + * 0: disable + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ck_glitch_cntl register + * Configure power glitch + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** pwr_glitch_reset_ena : R/W; bitpos: [30:27]; default: 0; + * enable powerglitch or not + */ + uint32_t pwr_glitch_reset_ena:4; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of fib_enable register + * configure FIB REG + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * configure analog fib by software + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * interrpt raw register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * brownout mode0 interrupt raw register + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * interrpt status register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * brownout mode0 interrupt status register + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * interrpt enable register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * brownout mode0 interrupt enable register + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * interrpt clear register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * brownout mode0 interrupt clear register + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * lp interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt raw register + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * lp interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt status register + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * lp interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt enable register + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * lp interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * brownout mode0 lp interrupt clear register + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * version register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** lp_ana_date : R/W; bitpos: [30:1]; default: 18387264; + * version register + */ + uint32_t lp_ana_date:30; + /** clk_en : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_030[243]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/lp_aon_reg.h b/components/soc/esp32c5/register/soc/lp_aon_reg.h index 32d0007632..eb8c4c13ad 100644 --- a/components/soc/esp32c5/register/soc/lp_aon_reg.h +++ b/components/soc/esp32c5/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -160,10 +160,13 @@ extern "C" { /** LP_AON_GPIO_HOLD1_REG register * reserved + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) /** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_GPIO_HOLD1 0xFFFFFFFFU #define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) @@ -174,22 +177,28 @@ extern "C" { * configure system register */ #define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) -/** LP_AON_FORCE_DOWNLOAD_BOOT_STATUS : RO; bitpos: [29]; default: 0; - * get force download mode status +/** LP_AON_FORCE_DOWNLOAD_BOOT_STATUS : RO; bitpos: [28:27]; default: 0; + * get force download mode status, + * bit1:download boot1 + * bit0:download boot0 + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS (BIT(29)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS 0x00000003U #define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_M (LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V << LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S) -#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V 0x00000001U -#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S 29 -/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; +#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V 0x00000003U +#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S 27 +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30:29]; default: 0; * enable chip entry download mode or not - * 1: enable - * 0: no operation + * 00: no operation + * 01:force download boot0(uart/usb) + * 10:force download boot1(uart/sdio) + * 11: no operation + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT 0x00000003U #define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) -#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U -#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000003U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 29 /** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; * enable hp system reset by software or not * 1: reset @@ -224,6 +233,7 @@ extern "C" { #define LP_AON_CPU_CORE0_SW_RESET_S 28 /** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) @@ -233,6 +243,7 @@ extern "C" { * configure core boot address * 1: ROM * 0: lp memory + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) @@ -242,6 +253,7 @@ extern "C" { * disable bypass core dreset * 1: enable bypass * 0: disable bypass + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) #define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) @@ -363,10 +375,13 @@ extern "C" { /** LP_AON_SDIO_ACTIVE_REG register * configure sdio act dnum + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) /** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_SDIO_ACT_DNUM 0x000003FFU #define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) @@ -403,10 +418,13 @@ extern "C" { /** LP_AON_SAR_CCT_REG register * configure sar cct + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) /** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; * configure sar cct + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_SAR2_PWDET_CCT 0x00000007U #define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) @@ -415,12 +433,15 @@ extern "C" { /** LP_AON_MODEM_BUS_REG register * configure modem sync bridge + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58) /** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0; * enable modem sync bridge or not * 1: enable * 0: disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31)) #define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S) @@ -429,10 +450,13 @@ extern "C" { /** LP_AON_SPRAM_CTRL_REG register * configure lp memory power status + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60) /** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; * configure lp memory power status + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU #define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S) @@ -441,10 +465,13 @@ extern "C" { /** LP_AON_SPRF_CTRL_REG register * configure memory in lp system power status + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64) /** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; * configure memory in lp system power status + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU #define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S) @@ -453,10 +480,13 @@ extern "C" { /** LP_AON_DEBUG_SEL0_REG register * reserved + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_DEBUG_SEL0_REG (DR_REG_LP_AON_BASE + 0x68) /** LP_AON_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_LP_DEBUG_SEL0 0x0000007FU #define LP_AON_LP_DEBUG_SEL0_M (LP_AON_LP_DEBUG_SEL0_V << LP_AON_LP_DEBUG_SEL0_S) @@ -464,6 +494,7 @@ extern "C" { #define LP_AON_LP_DEBUG_SEL0_S 0 /** LP_AON_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_LP_DEBUG_SEL1 0x0000007FU #define LP_AON_LP_DEBUG_SEL1_M (LP_AON_LP_DEBUG_SEL1_V << LP_AON_LP_DEBUG_SEL1_S) @@ -471,6 +502,7 @@ extern "C" { #define LP_AON_LP_DEBUG_SEL1_S 7 /** LP_AON_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_LP_DEBUG_SEL2 0x0000007FU #define LP_AON_LP_DEBUG_SEL2_M (LP_AON_LP_DEBUG_SEL2_V << LP_AON_LP_DEBUG_SEL2_S) @@ -478,6 +510,7 @@ extern "C" { #define LP_AON_LP_DEBUG_SEL2_S 14 /** LP_AON_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_LP_DEBUG_SEL3 0x0000007FU #define LP_AON_LP_DEBUG_SEL3_M (LP_AON_LP_DEBUG_SEL3_V << LP_AON_LP_DEBUG_SEL3_S) @@ -486,10 +519,13 @@ extern "C" { /** LP_AON_DEBUG_SEL1_REG register * need des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define LP_AON_DEBUG_SEL1_REG (DR_REG_LP_AON_BASE + 0x6c) /** LP_AON_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_LP_DEBUG_SEL4 0x0000007FU #define LP_AON_LP_DEBUG_SEL4_M (LP_AON_LP_DEBUG_SEL4_V << LP_AON_LP_DEBUG_SEL4_S) @@ -549,6 +585,7 @@ extern "C" { #define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20 /** LP_AON_AON_BYPASS : R/W; bitpos: [31]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_AON_BYPASS (BIT(31)) #define LP_AON_AON_BYPASS_M (LP_AON_AON_BYPASS_V << LP_AON_AON_BYPASS_S) @@ -600,11 +637,47 @@ extern "C" { #define LP_AON_HUK_MEM_FORCE_PU_V 0x00000001U #define LP_AON_HUK_MEM_FORCE_PU_S 3 +/** LP_AON_PUF_MEM_SW_REG register + * configure the power switch of PUFMEM + */ +#define LP_AON_PUF_MEM_SW_REG (DR_REG_LP_AON_BASE + 0x80) +/** LP_AON_PUF_MEM_SW : R/W; bitpos: [0]; default: 1; + * power switch of PD_LPPUFMEM + */ +#define LP_AON_PUF_MEM_SW (BIT(0)) +#define LP_AON_PUF_MEM_SW_M (LP_AON_PUF_MEM_SW_V << LP_AON_PUF_MEM_SW_S) +#define LP_AON_PUF_MEM_SW_V 0x00000001U +#define LP_AON_PUF_MEM_SW_S 0 + +/** LP_AON_PUF_MEM_ISO_REG register + * configure the iso of PD_PUFMEM + */ +#define LP_AON_PUF_MEM_ISO_REG (DR_REG_LP_AON_BASE + 0x84) +/** LP_AON_PUF_MEM_ISO : R/W; bitpos: [0]; default: 0; + * ISO enable of PD_LPPUFMEM to PD_SYS + */ +#define LP_AON_PUF_MEM_ISO (BIT(0)) +#define LP_AON_PUF_MEM_ISO_M (LP_AON_PUF_MEM_ISO_V << LP_AON_PUF_MEM_ISO_S) +#define LP_AON_PUF_MEM_ISO_V 0x00000001U +#define LP_AON_PUF_MEM_ISO_S 0 + +/** LP_AON_PUF_MEM_DISCHARGE_REG register + * configure the discharge gate of PUFMEM + */ +#define LP_AON_PUF_MEM_DISCHARGE_REG (DR_REG_LP_AON_BASE + 0x88) +/** LP_AON_PUF_MEM_DISCHARGE : R/W; bitpos: [0]; default: 0; + * discharge gate of LPPUFMEM + */ +#define LP_AON_PUF_MEM_DISCHARGE (BIT(0)) +#define LP_AON_PUF_MEM_DISCHARGE_M (LP_AON_PUF_MEM_DISCHARGE_V << LP_AON_PUF_MEM_DISCHARGE_S) +#define LP_AON_PUF_MEM_DISCHARGE_V 0x00000001U +#define LP_AON_PUF_MEM_DISCHARGE_S 0 + /** LP_AON_DATE_REG register * reserved */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36774512; +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37818656; * version register */ #define LP_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/lp_aon_struct.h b/components/soc/esp32c5/register/soc/lp_aon_struct.h index 22fa8d0176..d6664034b8 100644 --- a/components/soc/esp32c5/register/soc/lp_aon_struct.h +++ b/components/soc/esp32c5/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -178,6 +178,7 @@ typedef union { struct { /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t gpio_hold1:32; }; @@ -189,17 +190,23 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:29; - /** force_download_boot_status : RO; bitpos: [29]; default: 0; - * get force download mode status + uint32_t reserved_0:27; + /** force_download_boot_status : RO; bitpos: [28:27]; default: 0; + * get force download mode status, + * bit1:download boot1 + * bit0:download boot0 + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t force_download_boot_status:1; - /** force_download_boot : R/W; bitpos: [30]; default: 0; + uint32_t force_download_boot_status:2; + /** force_download_boot : R/W; bitpos: [30:29]; default: 0; * enable chip entry download mode or not - * 1: enable - * 0: no operation + * 00: no operation + * 01:force download boot0(uart/usb) + * 10:force download boot1(uart/sdio) + * 11: no operation + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t force_download_boot:1; + uint32_t force_download_boot:2; /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; * enable hp system reset by software or not * 1: reset @@ -230,18 +237,21 @@ typedef union { uint32_t cpu_core0_sw_reset:1; /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cpu_core0_ocd_halt_on_reset:1; /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; * configure core boot address * 1: ROM * 0: lp memory + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cpu_core0_stat_vector_sel:1; /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; * disable bypass core dreset * 1: enable bypass * 0: disable bypass + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cpu_core0_dreset_mask:1; }; @@ -356,6 +366,7 @@ typedef union { uint32_t reserved_0:22; /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sdio_act_dnum:10; }; @@ -394,6 +405,7 @@ typedef union { uint32_t reserved_0:29; /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; * configure sar cct + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sar2_pwdet_cct:3; }; @@ -410,6 +422,7 @@ typedef union { * enable modem sync bridge or not * 1: enable * 0: disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t modem_sync_bridge_en:1; }; @@ -423,18 +436,22 @@ typedef union { struct { /** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t lp_debug_sel0:7; /** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t lp_debug_sel1:7; /** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t lp_debug_sel2:7; /** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t lp_debug_sel3:7; uint32_t reserved_28:4; @@ -449,6 +466,7 @@ typedef union { struct { /** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0; * need des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t lp_debug_sel4:7; uint32_t reserved_7:25; @@ -498,6 +516,7 @@ typedef union { uint32_t reserved_30:1; /** aon_bypass : R/W; bitpos: [31]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t aon_bypass:1; }; @@ -543,12 +562,54 @@ typedef union { uint32_t val; } lp_aon_mem_ctrl_reg_t; +/** Type of puf_mem_sw register + * configure the power switch of PUFMEM + */ +typedef union { + struct { + /** puf_mem_sw_reg : R/W; bitpos: [0]; default: 1; + * power switch of PD_LPPUFMEM + */ + uint32_t puf_mem_sw_reg:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_aon_puf_mem_sw_reg_t; + +/** Type of puf_mem_iso register + * configure the iso of PD_PUFMEM + */ +typedef union { + struct { + /** puf_mem_iso_reg : R/W; bitpos: [0]; default: 0; + * ISO enable of PD_LPPUFMEM to PD_SYS + */ + uint32_t puf_mem_iso_reg:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_aon_puf_mem_iso_reg_t; + +/** Type of puf_mem_discharge register + * configure the discharge gate of PUFMEM + */ +typedef union { + struct { + /** puf_mem_discharge_reg : R/W; bitpos: [0]; default: 0; + * discharge gate of LPPUFMEM + */ + uint32_t puf_mem_discharge_reg:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_aon_puf_mem_discharge_reg_t; + /** Type of date register * reserved */ typedef union { struct { - /** date : R/W; bitpos: [30:0]; default: 36774512; + /** date : R/W; bitpos: [30:0]; default: 37818656; * version register */ uint32_t date:31; @@ -569,6 +630,7 @@ typedef union { struct { /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * configure lp memory power status + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t spram_mem_aux_ctrl:32; }; @@ -582,6 +644,7 @@ typedef union { struct { /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * configure memory in lp system power status + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sprf_mem_aux_ctrl:32; }; @@ -622,7 +685,10 @@ typedef struct { volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1; volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2; volatile lp_aon_mem_ctrl_reg_t mem_ctrl; - uint32_t reserved_080[223]; + volatile lp_aon_puf_mem_sw_reg_t puf_mem_sw; + volatile lp_aon_puf_mem_iso_reg_t puf_mem_iso; + volatile lp_aon_puf_mem_discharge_reg_t puf_mem_discharge; + uint32_t reserved_08c[220]; volatile lp_aon_date_reg_t date; } lp_aon_dev_t; diff --git a/components/soc/esp32c5/register/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h index c9ef64a791..789db5cd27 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,14 +15,14 @@ extern "C" { * Region filter enable register */ #define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) -/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; - * Configure bit $n(0-3) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n(0-7) to enable region $n. + * 0: disable + * 1: enable */ -#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN 0x000000FFU #define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) -#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_V 0x000000FFU #define LP_APM0_REGION_FILTER_EN_S 0 /** LP_APM0_REGION0_ADDR_START_REG register @@ -421,6 +421,402 @@ extern "C" { #define LP_APM0_REGION3_LOCK_V 0x00000001U #define LP_APM0_REGION3_LOCK_S 11 +/** LP_APM0_REGION4_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34) +/** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 4 + */ +#define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S) +#define LP_APM0_REGION4_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION4_ADDR_START_S 0 + +/** LP_APM0_REGION4_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38) +/** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 4 + */ +#define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S) +#define LP_APM0_REGION4_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION4_ADDR_END_S 0 + +/** LP_APM0_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c) +/** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define LP_APM0_REGION4_R0_X (BIT(0)) +#define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S) +#define LP_APM0_REGION4_R0_X_V 0x00000001U +#define LP_APM0_REGION4_R0_X_S 0 +/** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define LP_APM0_REGION4_R0_W (BIT(1)) +#define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S) +#define LP_APM0_REGION4_R0_W_V 0x00000001U +#define LP_APM0_REGION4_R0_W_S 1 +/** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define LP_APM0_REGION4_R0_R (BIT(2)) +#define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S) +#define LP_APM0_REGION4_R0_R_V 0x00000001U +#define LP_APM0_REGION4_R0_R_S 2 +/** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define LP_APM0_REGION4_R1_X (BIT(4)) +#define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S) +#define LP_APM0_REGION4_R1_X_V 0x00000001U +#define LP_APM0_REGION4_R1_X_S 4 +/** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define LP_APM0_REGION4_R1_W (BIT(5)) +#define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S) +#define LP_APM0_REGION4_R1_W_V 0x00000001U +#define LP_APM0_REGION4_R1_W_S 5 +/** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define LP_APM0_REGION4_R1_R (BIT(6)) +#define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S) +#define LP_APM0_REGION4_R1_R_V 0x00000001U +#define LP_APM0_REGION4_R1_R_S 6 +/** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define LP_APM0_REGION4_R2_X (BIT(8)) +#define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S) +#define LP_APM0_REGION4_R2_X_V 0x00000001U +#define LP_APM0_REGION4_R2_X_S 8 +/** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define LP_APM0_REGION4_R2_W (BIT(9)) +#define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S) +#define LP_APM0_REGION4_R2_W_V 0x00000001U +#define LP_APM0_REGION4_R2_W_S 9 +/** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define LP_APM0_REGION4_R2_R (BIT(10)) +#define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S) +#define LP_APM0_REGION4_R2_R_V 0x00000001U +#define LP_APM0_REGION4_R2_R_S 10 +/** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION4_LOCK (BIT(11)) +#define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S) +#define LP_APM0_REGION4_LOCK_V 0x00000001U +#define LP_APM0_REGION4_LOCK_S 11 + +/** LP_APM0_REGION5_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40) +/** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 5 + */ +#define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S) +#define LP_APM0_REGION5_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION5_ADDR_START_S 0 + +/** LP_APM0_REGION5_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44) +/** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 5 + */ +#define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S) +#define LP_APM0_REGION5_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION5_ADDR_END_S 0 + +/** LP_APM0_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48) +/** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define LP_APM0_REGION5_R0_X (BIT(0)) +#define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S) +#define LP_APM0_REGION5_R0_X_V 0x00000001U +#define LP_APM0_REGION5_R0_X_S 0 +/** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define LP_APM0_REGION5_R0_W (BIT(1)) +#define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S) +#define LP_APM0_REGION5_R0_W_V 0x00000001U +#define LP_APM0_REGION5_R0_W_S 1 +/** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define LP_APM0_REGION5_R0_R (BIT(2)) +#define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S) +#define LP_APM0_REGION5_R0_R_V 0x00000001U +#define LP_APM0_REGION5_R0_R_S 2 +/** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define LP_APM0_REGION5_R1_X (BIT(4)) +#define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S) +#define LP_APM0_REGION5_R1_X_V 0x00000001U +#define LP_APM0_REGION5_R1_X_S 4 +/** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define LP_APM0_REGION5_R1_W (BIT(5)) +#define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S) +#define LP_APM0_REGION5_R1_W_V 0x00000001U +#define LP_APM0_REGION5_R1_W_S 5 +/** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define LP_APM0_REGION5_R1_R (BIT(6)) +#define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S) +#define LP_APM0_REGION5_R1_R_V 0x00000001U +#define LP_APM0_REGION5_R1_R_S 6 +/** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define LP_APM0_REGION5_R2_X (BIT(8)) +#define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S) +#define LP_APM0_REGION5_R2_X_V 0x00000001U +#define LP_APM0_REGION5_R2_X_S 8 +/** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define LP_APM0_REGION5_R2_W (BIT(9)) +#define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S) +#define LP_APM0_REGION5_R2_W_V 0x00000001U +#define LP_APM0_REGION5_R2_W_S 9 +/** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define LP_APM0_REGION5_R2_R (BIT(10)) +#define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S) +#define LP_APM0_REGION5_R2_R_V 0x00000001U +#define LP_APM0_REGION5_R2_R_S 10 +/** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION5_LOCK (BIT(11)) +#define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S) +#define LP_APM0_REGION5_LOCK_V 0x00000001U +#define LP_APM0_REGION5_LOCK_S 11 + +/** LP_APM0_REGION6_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c) +/** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 6 + */ +#define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S) +#define LP_APM0_REGION6_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION6_ADDR_START_S 0 + +/** LP_APM0_REGION6_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50) +/** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 6 + */ +#define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S) +#define LP_APM0_REGION6_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION6_ADDR_END_S 0 + +/** LP_APM0_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54) +/** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define LP_APM0_REGION6_R0_X (BIT(0)) +#define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S) +#define LP_APM0_REGION6_R0_X_V 0x00000001U +#define LP_APM0_REGION6_R0_X_S 0 +/** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define LP_APM0_REGION6_R0_W (BIT(1)) +#define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S) +#define LP_APM0_REGION6_R0_W_V 0x00000001U +#define LP_APM0_REGION6_R0_W_S 1 +/** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define LP_APM0_REGION6_R0_R (BIT(2)) +#define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S) +#define LP_APM0_REGION6_R0_R_V 0x00000001U +#define LP_APM0_REGION6_R0_R_S 2 +/** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define LP_APM0_REGION6_R1_X (BIT(4)) +#define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S) +#define LP_APM0_REGION6_R1_X_V 0x00000001U +#define LP_APM0_REGION6_R1_X_S 4 +/** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define LP_APM0_REGION6_R1_W (BIT(5)) +#define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S) +#define LP_APM0_REGION6_R1_W_V 0x00000001U +#define LP_APM0_REGION6_R1_W_S 5 +/** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define LP_APM0_REGION6_R1_R (BIT(6)) +#define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S) +#define LP_APM0_REGION6_R1_R_V 0x00000001U +#define LP_APM0_REGION6_R1_R_S 6 +/** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define LP_APM0_REGION6_R2_X (BIT(8)) +#define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S) +#define LP_APM0_REGION6_R2_X_V 0x00000001U +#define LP_APM0_REGION6_R2_X_S 8 +/** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define LP_APM0_REGION6_R2_W (BIT(9)) +#define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S) +#define LP_APM0_REGION6_R2_W_V 0x00000001U +#define LP_APM0_REGION6_R2_W_S 9 +/** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define LP_APM0_REGION6_R2_R (BIT(10)) +#define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S) +#define LP_APM0_REGION6_R2_R_V 0x00000001U +#define LP_APM0_REGION6_R2_R_S 10 +/** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION6_LOCK (BIT(11)) +#define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S) +#define LP_APM0_REGION6_LOCK_V 0x00000001U +#define LP_APM0_REGION6_LOCK_S 11 + +/** LP_APM0_REGION7_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58) +/** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 7 + */ +#define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S) +#define LP_APM0_REGION7_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION7_ADDR_START_S 0 + +/** LP_APM0_REGION7_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c) +/** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 7 + */ +#define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S) +#define LP_APM0_REGION7_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION7_ADDR_END_S 0 + +/** LP_APM0_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60) +/** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define LP_APM0_REGION7_R0_X (BIT(0)) +#define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S) +#define LP_APM0_REGION7_R0_X_V 0x00000001U +#define LP_APM0_REGION7_R0_X_S 0 +/** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define LP_APM0_REGION7_R0_W (BIT(1)) +#define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S) +#define LP_APM0_REGION7_R0_W_V 0x00000001U +#define LP_APM0_REGION7_R0_W_S 1 +/** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define LP_APM0_REGION7_R0_R (BIT(2)) +#define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S) +#define LP_APM0_REGION7_R0_R_V 0x00000001U +#define LP_APM0_REGION7_R0_R_S 2 +/** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define LP_APM0_REGION7_R1_X (BIT(4)) +#define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S) +#define LP_APM0_REGION7_R1_X_V 0x00000001U +#define LP_APM0_REGION7_R1_X_S 4 +/** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define LP_APM0_REGION7_R1_W (BIT(5)) +#define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S) +#define LP_APM0_REGION7_R1_W_V 0x00000001U +#define LP_APM0_REGION7_R1_W_S 5 +/** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define LP_APM0_REGION7_R1_R (BIT(6)) +#define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S) +#define LP_APM0_REGION7_R1_R_V 0x00000001U +#define LP_APM0_REGION7_R1_R_S 6 +/** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define LP_APM0_REGION7_R2_X (BIT(8)) +#define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S) +#define LP_APM0_REGION7_R2_X_V 0x00000001U +#define LP_APM0_REGION7_R2_X_S 8 +/** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define LP_APM0_REGION7_R2_W (BIT(9)) +#define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S) +#define LP_APM0_REGION7_R2_W_V 0x00000001U +#define LP_APM0_REGION7_R2_W_S 9 +/** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define LP_APM0_REGION7_R2_R (BIT(10)) +#define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S) +#define LP_APM0_REGION7_R2_R_V 0x00000001U +#define LP_APM0_REGION7_R2_R_S 10 +/** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION7_LOCK (BIT(11)) +#define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S) +#define LP_APM0_REGION7_LOCK_V 0x00000001U +#define LP_APM0_REGION7_LOCK_S 11 + /** LP_APM0_FUNC_CTRL_REG register * APM function control register */ @@ -438,9 +834,9 @@ extern "C" { */ #define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) /** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ #define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) @@ -463,12 +859,12 @@ extern "C" { * M0 exception_info0 register */ #define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) -/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; * Represents exception region */ -#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) -#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_S 0 /** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; * Represents exception mode @@ -502,9 +898,9 @@ extern "C" { */ #define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) /** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable.\\ - * 0: disable \\ - * 1: enable \\ + * Configures APM M0 interrupt enable. + * 0: disable + * 1: enable */ #define LP_APM0_M0_APM_INT_EN (BIT(0)) #define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) @@ -516,9 +912,9 @@ extern "C" { */ #define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) /** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ #define LP_APM0_CLK_EN (BIT(0)) #define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h index 0eb11e3fb3..542cbede30 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,13 +16,13 @@ extern "C" { */ typedef union { struct { - /** region_filter_en : R/W; bitpos: [3:0]; default: 1; - * Configure bit $n(0-3) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + /** region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n(0-7) to enable region $n. + * 0: disable + * 1: enable */ - uint32_t region_filter_en:4; - uint32_t reserved_4:28; + uint32_t region_filter_en:8; + uint32_t reserved_8:24; }; uint32_t val; } lp_apm0_region_filter_en_reg_t; @@ -133,9 +133,9 @@ typedef union { typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -166,11 +166,11 @@ typedef union { */ typedef union { struct { - /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + /** m0_exception_region : RO; bitpos: [7:0]; default: 0; * Represents exception region */ - uint32_t m0_exception_region:4; - uint32_t reserved_4:12; + uint32_t m0_exception_region:8; + uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; * Represents exception mode */ @@ -207,9 +207,9 @@ typedef union { typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable.\\ - * 0: disable \\ - * 1: enable \\ + * Configures APM M0 interrupt enable. + * 0: disable + * 1: enable */ uint32_t m0_apm_int_en:1; uint32_t reserved_1:31; @@ -225,9 +225,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -266,7 +266,19 @@ typedef struct { volatile lp_apm0_regionn_addr_start_reg_t region3_addr_start; volatile lp_apm0_regionn_addr_end_reg_t region3_addr_end; volatile lp_apm0_regionn_attr_reg_t region3_attr; - uint32_t reserved_034[36]; + volatile lp_apm0_regionn_addr_start_reg_t region4_addr_start; + volatile lp_apm0_regionn_addr_end_reg_t region4_addr_end; + volatile lp_apm0_regionn_attr_reg_t region4_attr; + volatile lp_apm0_regionn_addr_start_reg_t region5_addr_start; + volatile lp_apm0_regionn_addr_end_reg_t region5_addr_end; + volatile lp_apm0_regionn_attr_reg_t region5_attr; + volatile lp_apm0_regionn_addr_start_reg_t region6_addr_start; + volatile lp_apm0_regionn_addr_end_reg_t region6_addr_end; + volatile lp_apm0_regionn_attr_reg_t region6_attr; + volatile lp_apm0_regionn_addr_start_reg_t region7_addr_start; + volatile lp_apm0_regionn_addr_end_reg_t region7_addr_end; + volatile lp_apm0_regionn_attr_reg_t region7_attr; + uint32_t reserved_064[24]; volatile lp_apm0_func_ctrl_reg_t func_ctrl; volatile lp_apm0_m0_status_reg_t m0_status; volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; diff --git a/components/soc/esp32c5/register/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h index c9a193577e..9e4e42c55e 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,14 +15,14 @@ extern "C" { * Region filter enable register */ #define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) -/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; - * Configure bit $n (0-3) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable */ -#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN 0x000000FFU #define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) -#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_V 0x000000FFU #define LP_APM_REGION_FILTER_EN_S 0 /** LP_APM_REGION0_ADDR_START_REG register @@ -421,6 +421,402 @@ extern "C" { #define LP_APM_REGION3_LOCK_V 0x00000001U #define LP_APM_REGION3_LOCK_S 11 +/** LP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION4_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x34) +/** LP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 4. + */ +#define LP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION4_ADDR_START_M (LP_APM_REGION4_ADDR_START_V << LP_APM_REGION4_ADDR_START_S) +#define LP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION4_ADDR_START_S 0 + +/** LP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION4_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x38) +/** LP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 4. + */ +#define LP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION4_ADDR_END_M (LP_APM_REGION4_ADDR_END_V << LP_APM_REGION4_ADDR_END_S) +#define LP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION4_ADDR_END_S 0 + +/** LP_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION4_ATTR_REG (DR_REG_LP_APM_BASE + 0x3c) +/** LP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define LP_APM_REGION4_R0_X (BIT(0)) +#define LP_APM_REGION4_R0_X_M (LP_APM_REGION4_R0_X_V << LP_APM_REGION4_R0_X_S) +#define LP_APM_REGION4_R0_X_V 0x00000001U +#define LP_APM_REGION4_R0_X_S 0 +/** LP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define LP_APM_REGION4_R0_W (BIT(1)) +#define LP_APM_REGION4_R0_W_M (LP_APM_REGION4_R0_W_V << LP_APM_REGION4_R0_W_S) +#define LP_APM_REGION4_R0_W_V 0x00000001U +#define LP_APM_REGION4_R0_W_S 1 +/** LP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define LP_APM_REGION4_R0_R (BIT(2)) +#define LP_APM_REGION4_R0_R_M (LP_APM_REGION4_R0_R_V << LP_APM_REGION4_R0_R_S) +#define LP_APM_REGION4_R0_R_V 0x00000001U +#define LP_APM_REGION4_R0_R_S 2 +/** LP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define LP_APM_REGION4_R1_X (BIT(4)) +#define LP_APM_REGION4_R1_X_M (LP_APM_REGION4_R1_X_V << LP_APM_REGION4_R1_X_S) +#define LP_APM_REGION4_R1_X_V 0x00000001U +#define LP_APM_REGION4_R1_X_S 4 +/** LP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define LP_APM_REGION4_R1_W (BIT(5)) +#define LP_APM_REGION4_R1_W_M (LP_APM_REGION4_R1_W_V << LP_APM_REGION4_R1_W_S) +#define LP_APM_REGION4_R1_W_V 0x00000001U +#define LP_APM_REGION4_R1_W_S 5 +/** LP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define LP_APM_REGION4_R1_R (BIT(6)) +#define LP_APM_REGION4_R1_R_M (LP_APM_REGION4_R1_R_V << LP_APM_REGION4_R1_R_S) +#define LP_APM_REGION4_R1_R_V 0x00000001U +#define LP_APM_REGION4_R1_R_S 6 +/** LP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define LP_APM_REGION4_R2_X (BIT(8)) +#define LP_APM_REGION4_R2_X_M (LP_APM_REGION4_R2_X_V << LP_APM_REGION4_R2_X_S) +#define LP_APM_REGION4_R2_X_V 0x00000001U +#define LP_APM_REGION4_R2_X_S 8 +/** LP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define LP_APM_REGION4_R2_W (BIT(9)) +#define LP_APM_REGION4_R2_W_M (LP_APM_REGION4_R2_W_V << LP_APM_REGION4_R2_W_S) +#define LP_APM_REGION4_R2_W_V 0x00000001U +#define LP_APM_REGION4_R2_W_S 9 +/** LP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define LP_APM_REGION4_R2_R (BIT(10)) +#define LP_APM_REGION4_R2_R_M (LP_APM_REGION4_R2_R_V << LP_APM_REGION4_R2_R_S) +#define LP_APM_REGION4_R2_R_V 0x00000001U +#define LP_APM_REGION4_R2_R_S 10 +/** LP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION4_LOCK (BIT(11)) +#define LP_APM_REGION4_LOCK_M (LP_APM_REGION4_LOCK_V << LP_APM_REGION4_LOCK_S) +#define LP_APM_REGION4_LOCK_V 0x00000001U +#define LP_APM_REGION4_LOCK_S 11 + +/** LP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION5_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x40) +/** LP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 5. + */ +#define LP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION5_ADDR_START_M (LP_APM_REGION5_ADDR_START_V << LP_APM_REGION5_ADDR_START_S) +#define LP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION5_ADDR_START_S 0 + +/** LP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION5_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x44) +/** LP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 5. + */ +#define LP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION5_ADDR_END_M (LP_APM_REGION5_ADDR_END_V << LP_APM_REGION5_ADDR_END_S) +#define LP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION5_ADDR_END_S 0 + +/** LP_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION5_ATTR_REG (DR_REG_LP_APM_BASE + 0x48) +/** LP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define LP_APM_REGION5_R0_X (BIT(0)) +#define LP_APM_REGION5_R0_X_M (LP_APM_REGION5_R0_X_V << LP_APM_REGION5_R0_X_S) +#define LP_APM_REGION5_R0_X_V 0x00000001U +#define LP_APM_REGION5_R0_X_S 0 +/** LP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define LP_APM_REGION5_R0_W (BIT(1)) +#define LP_APM_REGION5_R0_W_M (LP_APM_REGION5_R0_W_V << LP_APM_REGION5_R0_W_S) +#define LP_APM_REGION5_R0_W_V 0x00000001U +#define LP_APM_REGION5_R0_W_S 1 +/** LP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define LP_APM_REGION5_R0_R (BIT(2)) +#define LP_APM_REGION5_R0_R_M (LP_APM_REGION5_R0_R_V << LP_APM_REGION5_R0_R_S) +#define LP_APM_REGION5_R0_R_V 0x00000001U +#define LP_APM_REGION5_R0_R_S 2 +/** LP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define LP_APM_REGION5_R1_X (BIT(4)) +#define LP_APM_REGION5_R1_X_M (LP_APM_REGION5_R1_X_V << LP_APM_REGION5_R1_X_S) +#define LP_APM_REGION5_R1_X_V 0x00000001U +#define LP_APM_REGION5_R1_X_S 4 +/** LP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define LP_APM_REGION5_R1_W (BIT(5)) +#define LP_APM_REGION5_R1_W_M (LP_APM_REGION5_R1_W_V << LP_APM_REGION5_R1_W_S) +#define LP_APM_REGION5_R1_W_V 0x00000001U +#define LP_APM_REGION5_R1_W_S 5 +/** LP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define LP_APM_REGION5_R1_R (BIT(6)) +#define LP_APM_REGION5_R1_R_M (LP_APM_REGION5_R1_R_V << LP_APM_REGION5_R1_R_S) +#define LP_APM_REGION5_R1_R_V 0x00000001U +#define LP_APM_REGION5_R1_R_S 6 +/** LP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define LP_APM_REGION5_R2_X (BIT(8)) +#define LP_APM_REGION5_R2_X_M (LP_APM_REGION5_R2_X_V << LP_APM_REGION5_R2_X_S) +#define LP_APM_REGION5_R2_X_V 0x00000001U +#define LP_APM_REGION5_R2_X_S 8 +/** LP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define LP_APM_REGION5_R2_W (BIT(9)) +#define LP_APM_REGION5_R2_W_M (LP_APM_REGION5_R2_W_V << LP_APM_REGION5_R2_W_S) +#define LP_APM_REGION5_R2_W_V 0x00000001U +#define LP_APM_REGION5_R2_W_S 9 +/** LP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define LP_APM_REGION5_R2_R (BIT(10)) +#define LP_APM_REGION5_R2_R_M (LP_APM_REGION5_R2_R_V << LP_APM_REGION5_R2_R_S) +#define LP_APM_REGION5_R2_R_V 0x00000001U +#define LP_APM_REGION5_R2_R_S 10 +/** LP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION5_LOCK (BIT(11)) +#define LP_APM_REGION5_LOCK_M (LP_APM_REGION5_LOCK_V << LP_APM_REGION5_LOCK_S) +#define LP_APM_REGION5_LOCK_V 0x00000001U +#define LP_APM_REGION5_LOCK_S 11 + +/** LP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION6_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4c) +/** LP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 6. + */ +#define LP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION6_ADDR_START_M (LP_APM_REGION6_ADDR_START_V << LP_APM_REGION6_ADDR_START_S) +#define LP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION6_ADDR_START_S 0 + +/** LP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION6_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x50) +/** LP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 6. + */ +#define LP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION6_ADDR_END_M (LP_APM_REGION6_ADDR_END_V << LP_APM_REGION6_ADDR_END_S) +#define LP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION6_ADDR_END_S 0 + +/** LP_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION6_ATTR_REG (DR_REG_LP_APM_BASE + 0x54) +/** LP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define LP_APM_REGION6_R0_X (BIT(0)) +#define LP_APM_REGION6_R0_X_M (LP_APM_REGION6_R0_X_V << LP_APM_REGION6_R0_X_S) +#define LP_APM_REGION6_R0_X_V 0x00000001U +#define LP_APM_REGION6_R0_X_S 0 +/** LP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define LP_APM_REGION6_R0_W (BIT(1)) +#define LP_APM_REGION6_R0_W_M (LP_APM_REGION6_R0_W_V << LP_APM_REGION6_R0_W_S) +#define LP_APM_REGION6_R0_W_V 0x00000001U +#define LP_APM_REGION6_R0_W_S 1 +/** LP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define LP_APM_REGION6_R0_R (BIT(2)) +#define LP_APM_REGION6_R0_R_M (LP_APM_REGION6_R0_R_V << LP_APM_REGION6_R0_R_S) +#define LP_APM_REGION6_R0_R_V 0x00000001U +#define LP_APM_REGION6_R0_R_S 2 +/** LP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define LP_APM_REGION6_R1_X (BIT(4)) +#define LP_APM_REGION6_R1_X_M (LP_APM_REGION6_R1_X_V << LP_APM_REGION6_R1_X_S) +#define LP_APM_REGION6_R1_X_V 0x00000001U +#define LP_APM_REGION6_R1_X_S 4 +/** LP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define LP_APM_REGION6_R1_W (BIT(5)) +#define LP_APM_REGION6_R1_W_M (LP_APM_REGION6_R1_W_V << LP_APM_REGION6_R1_W_S) +#define LP_APM_REGION6_R1_W_V 0x00000001U +#define LP_APM_REGION6_R1_W_S 5 +/** LP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define LP_APM_REGION6_R1_R (BIT(6)) +#define LP_APM_REGION6_R1_R_M (LP_APM_REGION6_R1_R_V << LP_APM_REGION6_R1_R_S) +#define LP_APM_REGION6_R1_R_V 0x00000001U +#define LP_APM_REGION6_R1_R_S 6 +/** LP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define LP_APM_REGION6_R2_X (BIT(8)) +#define LP_APM_REGION6_R2_X_M (LP_APM_REGION6_R2_X_V << LP_APM_REGION6_R2_X_S) +#define LP_APM_REGION6_R2_X_V 0x00000001U +#define LP_APM_REGION6_R2_X_S 8 +/** LP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define LP_APM_REGION6_R2_W (BIT(9)) +#define LP_APM_REGION6_R2_W_M (LP_APM_REGION6_R2_W_V << LP_APM_REGION6_R2_W_S) +#define LP_APM_REGION6_R2_W_V 0x00000001U +#define LP_APM_REGION6_R2_W_S 9 +/** LP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define LP_APM_REGION6_R2_R (BIT(10)) +#define LP_APM_REGION6_R2_R_M (LP_APM_REGION6_R2_R_V << LP_APM_REGION6_R2_R_S) +#define LP_APM_REGION6_R2_R_V 0x00000001U +#define LP_APM_REGION6_R2_R_S 10 +/** LP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION6_LOCK (BIT(11)) +#define LP_APM_REGION6_LOCK_M (LP_APM_REGION6_LOCK_V << LP_APM_REGION6_LOCK_S) +#define LP_APM_REGION6_LOCK_V 0x00000001U +#define LP_APM_REGION6_LOCK_S 11 + +/** LP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION7_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x58) +/** LP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 7. + */ +#define LP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION7_ADDR_START_M (LP_APM_REGION7_ADDR_START_V << LP_APM_REGION7_ADDR_START_S) +#define LP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION7_ADDR_START_S 0 + +/** LP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION7_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x5c) +/** LP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 7. + */ +#define LP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION7_ADDR_END_M (LP_APM_REGION7_ADDR_END_V << LP_APM_REGION7_ADDR_END_S) +#define LP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION7_ADDR_END_S 0 + +/** LP_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION7_ATTR_REG (DR_REG_LP_APM_BASE + 0x60) +/** LP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define LP_APM_REGION7_R0_X (BIT(0)) +#define LP_APM_REGION7_R0_X_M (LP_APM_REGION7_R0_X_V << LP_APM_REGION7_R0_X_S) +#define LP_APM_REGION7_R0_X_V 0x00000001U +#define LP_APM_REGION7_R0_X_S 0 +/** LP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define LP_APM_REGION7_R0_W (BIT(1)) +#define LP_APM_REGION7_R0_W_M (LP_APM_REGION7_R0_W_V << LP_APM_REGION7_R0_W_S) +#define LP_APM_REGION7_R0_W_V 0x00000001U +#define LP_APM_REGION7_R0_W_S 1 +/** LP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define LP_APM_REGION7_R0_R (BIT(2)) +#define LP_APM_REGION7_R0_R_M (LP_APM_REGION7_R0_R_V << LP_APM_REGION7_R0_R_S) +#define LP_APM_REGION7_R0_R_V 0x00000001U +#define LP_APM_REGION7_R0_R_S 2 +/** LP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define LP_APM_REGION7_R1_X (BIT(4)) +#define LP_APM_REGION7_R1_X_M (LP_APM_REGION7_R1_X_V << LP_APM_REGION7_R1_X_S) +#define LP_APM_REGION7_R1_X_V 0x00000001U +#define LP_APM_REGION7_R1_X_S 4 +/** LP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define LP_APM_REGION7_R1_W (BIT(5)) +#define LP_APM_REGION7_R1_W_M (LP_APM_REGION7_R1_W_V << LP_APM_REGION7_R1_W_S) +#define LP_APM_REGION7_R1_W_V 0x00000001U +#define LP_APM_REGION7_R1_W_S 5 +/** LP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define LP_APM_REGION7_R1_R (BIT(6)) +#define LP_APM_REGION7_R1_R_M (LP_APM_REGION7_R1_R_V << LP_APM_REGION7_R1_R_S) +#define LP_APM_REGION7_R1_R_V 0x00000001U +#define LP_APM_REGION7_R1_R_S 6 +/** LP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define LP_APM_REGION7_R2_X (BIT(8)) +#define LP_APM_REGION7_R2_X_M (LP_APM_REGION7_R2_X_V << LP_APM_REGION7_R2_X_S) +#define LP_APM_REGION7_R2_X_V 0x00000001U +#define LP_APM_REGION7_R2_X_S 8 +/** LP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define LP_APM_REGION7_R2_W (BIT(9)) +#define LP_APM_REGION7_R2_W_M (LP_APM_REGION7_R2_W_V << LP_APM_REGION7_R2_W_S) +#define LP_APM_REGION7_R2_W_V 0x00000001U +#define LP_APM_REGION7_R2_W_S 9 +/** LP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define LP_APM_REGION7_R2_R (BIT(10)) +#define LP_APM_REGION7_R2_R_M (LP_APM_REGION7_R2_R_V << LP_APM_REGION7_R2_R_S) +#define LP_APM_REGION7_R2_R_V 0x00000001U +#define LP_APM_REGION7_R2_R_S 10 +/** LP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION7_LOCK (BIT(11)) +#define LP_APM_REGION7_LOCK_M (LP_APM_REGION7_LOCK_V << LP_APM_REGION7_LOCK_S) +#define LP_APM_REGION7_LOCK_V 0x00000001U +#define LP_APM_REGION7_LOCK_S 11 + /** LP_APM_FUNC_CTRL_REG register * APM function control register */ @@ -445,9 +841,9 @@ extern "C" { */ #define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) /** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ #define LP_APM_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) @@ -470,12 +866,12 @@ extern "C" { * M0 exception_info0 register */ #define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) -/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; * Represents exception region. */ -#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) -#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_S 0 /** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; * Represents exception mode. @@ -509,9 +905,9 @@ extern "C" { */ #define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) /** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ #define LP_APM_M1_EXCEPTION_STATUS 0x00000003U #define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) @@ -534,12 +930,12 @@ extern "C" { * M1 exception_info0 register */ #define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) -/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; +/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; * Represents exception region. */ -#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) -#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_S 0 /** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; * Represents exception mode. @@ -573,18 +969,18 @@ extern "C" { */ #define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) /** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable */ #define LP_APM_M0_APM_INT_EN (BIT(0)) #define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) #define LP_APM_M0_APM_INT_EN_V 0x00000001U #define LP_APM_M0_APM_INT_EN_S 0 /** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable */ #define LP_APM_M1_APM_INT_EN (BIT(1)) #define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) @@ -596,9 +992,9 @@ extern "C" { */ #define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) /** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ #define LP_APM_CLK_EN (BIT(0)) #define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h index b9cb33d078..3c7bc3fcc2 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,13 +16,13 @@ extern "C" { */ typedef union { struct { - /** region_filter_en : R/W; bitpos: [3:0]; default: 1; - * Configure bit $n (0-3) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + /** region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable */ - uint32_t region_filter_en:4; - uint32_t reserved_4:28; + uint32_t region_filter_en:8; + uint32_t reserved_8:24; }; uint32_t val; } lp_apm_region_filter_en_reg_t; @@ -137,9 +137,9 @@ typedef union { typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -170,11 +170,11 @@ typedef union { */ typedef union { struct { - /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + /** m0_exception_region : RO; bitpos: [7:0]; default: 0; * Represents exception region. */ - uint32_t m0_exception_region:4; - uint32_t reserved_4:12; + uint32_t m0_exception_region:8; + uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; * Represents exception mode. */ @@ -211,9 +211,9 @@ typedef union { typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -244,11 +244,11 @@ typedef union { */ typedef union { struct { - /** m1_exception_region : RO; bitpos: [3:0]; default: 0; + /** m1_exception_region : RO; bitpos: [7:0]; default: 0; * Represents exception region. */ - uint32_t m1_exception_region:4; - uint32_t reserved_4:12; + uint32_t m1_exception_region:8; + uint32_t reserved_8:8; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; * Represents exception mode. */ @@ -285,15 +285,15 @@ typedef union { typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -309,9 +309,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -350,7 +350,19 @@ typedef struct { volatile lp_apm_regionn_addr_start_reg_t region3_addr_start; volatile lp_apm_regionn_addr_end_reg_t region3_addr_end; volatile lp_apm_regionn_attr_reg_t region3_attr; - uint32_t reserved_034[36]; + volatile lp_apm_regionn_addr_start_reg_t region4_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region4_addr_end; + volatile lp_apm_regionn_attr_reg_t region4_attr; + volatile lp_apm_regionn_addr_start_reg_t region5_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region5_addr_end; + volatile lp_apm_regionn_attr_reg_t region5_attr; + volatile lp_apm_regionn_addr_start_reg_t region6_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region6_addr_end; + volatile lp_apm_regionn_attr_reg_t region6_attr; + volatile lp_apm_regionn_addr_start_reg_t region7_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region7_addr_end; + volatile lp_apm_regionn_attr_reg_t region7_attr; + uint32_t reserved_064[24]; volatile lp_apm_func_ctrl_reg_t func_ctrl; volatile lp_apm_m0_status_reg_t m0_status; volatile lp_apm_m0_status_clr_reg_t m0_status_clr; diff --git a/components/soc/esp32c5/register/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h index 5b5902c94a..e9eb72abe8 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_reg.h +++ b/components/soc/esp32c5/register/soc/lp_tee_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,11 @@ extern "C" { */ #define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) /** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M0 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define LP_TEE_M0_MODE 0x00000003U #define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) @@ -34,19 +34,1160 @@ extern "C" { #define LP_TEE_M0_LOCK_V 0x00000001U #define LP_TEE_M0_LOCK_S 2 -/** LP_TEE_CLOCK_GATE_REG register - * Clock gating register +/** LP_TEE_EFUSE_CTRL_REG register + * efuse read/write control register */ -#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) -/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ +#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4) +/** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; + * Configures efuse registers read permission in tee mode. + * 0: can not be read + * 1: can be read */ -#define LP_TEE_CLK_EN (BIT(0)) -#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) -#define LP_TEE_CLK_EN_V 0x00000001U -#define LP_TEE_CLK_EN_S 0 +#define LP_TEE_READ_TEE_EFUSE (BIT(0)) +#define LP_TEE_READ_TEE_EFUSE_M (LP_TEE_READ_TEE_EFUSE_V << LP_TEE_READ_TEE_EFUSE_S) +#define LP_TEE_READ_TEE_EFUSE_V 0x00000001U +#define LP_TEE_READ_TEE_EFUSE_S 0 +/** LP_TEE_READ_REE0_EFUSE : R/W; bitpos: [1]; default: 0; + * Configures efuse registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_EFUSE (BIT(1)) +#define LP_TEE_READ_REE0_EFUSE_M (LP_TEE_READ_REE0_EFUSE_V << LP_TEE_READ_REE0_EFUSE_S) +#define LP_TEE_READ_REE0_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE0_EFUSE_S 1 +/** LP_TEE_READ_REE1_EFUSE : R/W; bitpos: [2]; default: 0; + * Configures efuse registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_EFUSE (BIT(2)) +#define LP_TEE_READ_REE1_EFUSE_M (LP_TEE_READ_REE1_EFUSE_V << LP_TEE_READ_REE1_EFUSE_S) +#define LP_TEE_READ_REE1_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE1_EFUSE_S 2 +/** LP_TEE_READ_REE2_EFUSE : R/W; bitpos: [3]; default: 0; + * Configures efuse registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_EFUSE (BIT(3)) +#define LP_TEE_READ_REE2_EFUSE_M (LP_TEE_READ_REE2_EFUSE_V << LP_TEE_READ_REE2_EFUSE_S) +#define LP_TEE_READ_REE2_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE2_EFUSE_S 3 +/** LP_TEE_WRITE_TEE_EFUSE : R/W; bitpos: [4]; default: 1; + * Configures efuse registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_EFUSE (BIT(4)) +#define LP_TEE_WRITE_TEE_EFUSE_M (LP_TEE_WRITE_TEE_EFUSE_V << LP_TEE_WRITE_TEE_EFUSE_S) +#define LP_TEE_WRITE_TEE_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_TEE_EFUSE_S 4 +/** LP_TEE_WRITE_REE0_EFUSE : R/W; bitpos: [5]; default: 0; + * Configures efuse registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_EFUSE (BIT(5)) +#define LP_TEE_WRITE_REE0_EFUSE_M (LP_TEE_WRITE_REE0_EFUSE_V << LP_TEE_WRITE_REE0_EFUSE_S) +#define LP_TEE_WRITE_REE0_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE0_EFUSE_S 5 +/** LP_TEE_WRITE_REE1_EFUSE : R/W; bitpos: [6]; default: 0; + * Configures efuse registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_EFUSE (BIT(6)) +#define LP_TEE_WRITE_REE1_EFUSE_M (LP_TEE_WRITE_REE1_EFUSE_V << LP_TEE_WRITE_REE1_EFUSE_S) +#define LP_TEE_WRITE_REE1_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE1_EFUSE_S 6 +/** LP_TEE_WRITE_REE2_EFUSE : R/W; bitpos: [7]; default: 0; + * Configures efuse registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_EFUSE (BIT(7)) +#define LP_TEE_WRITE_REE2_EFUSE_M (LP_TEE_WRITE_REE2_EFUSE_V << LP_TEE_WRITE_REE2_EFUSE_S) +#define LP_TEE_WRITE_REE2_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE2_EFUSE_S 7 + +/** LP_TEE_PMU_CTRL_REG register + * pmu read/write control register + */ +#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8) +/** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; + * Configures pmu registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_PMU (BIT(0)) +#define LP_TEE_READ_TEE_PMU_M (LP_TEE_READ_TEE_PMU_V << LP_TEE_READ_TEE_PMU_S) +#define LP_TEE_READ_TEE_PMU_V 0x00000001U +#define LP_TEE_READ_TEE_PMU_S 0 +/** LP_TEE_READ_REE0_PMU : R/W; bitpos: [1]; default: 0; + * Configures pmu registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_PMU (BIT(1)) +#define LP_TEE_READ_REE0_PMU_M (LP_TEE_READ_REE0_PMU_V << LP_TEE_READ_REE0_PMU_S) +#define LP_TEE_READ_REE0_PMU_V 0x00000001U +#define LP_TEE_READ_REE0_PMU_S 1 +/** LP_TEE_READ_REE1_PMU : R/W; bitpos: [2]; default: 0; + * Configures pmu registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_PMU (BIT(2)) +#define LP_TEE_READ_REE1_PMU_M (LP_TEE_READ_REE1_PMU_V << LP_TEE_READ_REE1_PMU_S) +#define LP_TEE_READ_REE1_PMU_V 0x00000001U +#define LP_TEE_READ_REE1_PMU_S 2 +/** LP_TEE_READ_REE2_PMU : R/W; bitpos: [3]; default: 0; + * Configures pmu registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_PMU (BIT(3)) +#define LP_TEE_READ_REE2_PMU_M (LP_TEE_READ_REE2_PMU_V << LP_TEE_READ_REE2_PMU_S) +#define LP_TEE_READ_REE2_PMU_V 0x00000001U +#define LP_TEE_READ_REE2_PMU_S 3 +/** LP_TEE_WRITE_TEE_PMU : R/W; bitpos: [4]; default: 1; + * Configures pmu registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_PMU (BIT(4)) +#define LP_TEE_WRITE_TEE_PMU_M (LP_TEE_WRITE_TEE_PMU_V << LP_TEE_WRITE_TEE_PMU_S) +#define LP_TEE_WRITE_TEE_PMU_V 0x00000001U +#define LP_TEE_WRITE_TEE_PMU_S 4 +/** LP_TEE_WRITE_REE0_PMU : R/W; bitpos: [5]; default: 0; + * Configures pmu registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_PMU (BIT(5)) +#define LP_TEE_WRITE_REE0_PMU_M (LP_TEE_WRITE_REE0_PMU_V << LP_TEE_WRITE_REE0_PMU_S) +#define LP_TEE_WRITE_REE0_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE0_PMU_S 5 +/** LP_TEE_WRITE_REE1_PMU : R/W; bitpos: [6]; default: 0; + * Configures pmu registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_PMU (BIT(6)) +#define LP_TEE_WRITE_REE1_PMU_M (LP_TEE_WRITE_REE1_PMU_V << LP_TEE_WRITE_REE1_PMU_S) +#define LP_TEE_WRITE_REE1_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE1_PMU_S 6 +/** LP_TEE_WRITE_REE2_PMU : R/W; bitpos: [7]; default: 0; + * Configures pmu registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_PMU (BIT(7)) +#define LP_TEE_WRITE_REE2_PMU_M (LP_TEE_WRITE_REE2_PMU_V << LP_TEE_WRITE_REE2_PMU_S) +#define LP_TEE_WRITE_REE2_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE2_PMU_S 7 + +/** LP_TEE_CLKRST_CTRL_REG register + * clkrst read/write control register + */ +#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc) +/** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; + * Configures clkrst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_CLKRST (BIT(0)) +#define LP_TEE_READ_TEE_CLKRST_M (LP_TEE_READ_TEE_CLKRST_V << LP_TEE_READ_TEE_CLKRST_S) +#define LP_TEE_READ_TEE_CLKRST_V 0x00000001U +#define LP_TEE_READ_TEE_CLKRST_S 0 +/** LP_TEE_READ_REE0_CLKRST : R/W; bitpos: [1]; default: 0; + * Configures clkrst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_CLKRST (BIT(1)) +#define LP_TEE_READ_REE0_CLKRST_M (LP_TEE_READ_REE0_CLKRST_V << LP_TEE_READ_REE0_CLKRST_S) +#define LP_TEE_READ_REE0_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE0_CLKRST_S 1 +/** LP_TEE_READ_REE1_CLKRST : R/W; bitpos: [2]; default: 0; + * Configures clkrst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_CLKRST (BIT(2)) +#define LP_TEE_READ_REE1_CLKRST_M (LP_TEE_READ_REE1_CLKRST_V << LP_TEE_READ_REE1_CLKRST_S) +#define LP_TEE_READ_REE1_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE1_CLKRST_S 2 +/** LP_TEE_READ_REE2_CLKRST : R/W; bitpos: [3]; default: 0; + * Configures clkrst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_CLKRST (BIT(3)) +#define LP_TEE_READ_REE2_CLKRST_M (LP_TEE_READ_REE2_CLKRST_V << LP_TEE_READ_REE2_CLKRST_S) +#define LP_TEE_READ_REE2_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE2_CLKRST_S 3 +/** LP_TEE_WRITE_TEE_CLKRST : R/W; bitpos: [4]; default: 1; + * Configures clkrst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_CLKRST (BIT(4)) +#define LP_TEE_WRITE_TEE_CLKRST_M (LP_TEE_WRITE_TEE_CLKRST_V << LP_TEE_WRITE_TEE_CLKRST_S) +#define LP_TEE_WRITE_TEE_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_TEE_CLKRST_S 4 +/** LP_TEE_WRITE_REE0_CLKRST : R/W; bitpos: [5]; default: 0; + * Configures clkrst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_CLKRST (BIT(5)) +#define LP_TEE_WRITE_REE0_CLKRST_M (LP_TEE_WRITE_REE0_CLKRST_V << LP_TEE_WRITE_REE0_CLKRST_S) +#define LP_TEE_WRITE_REE0_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE0_CLKRST_S 5 +/** LP_TEE_WRITE_REE1_CLKRST : R/W; bitpos: [6]; default: 0; + * Configures clkrst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_CLKRST (BIT(6)) +#define LP_TEE_WRITE_REE1_CLKRST_M (LP_TEE_WRITE_REE1_CLKRST_V << LP_TEE_WRITE_REE1_CLKRST_S) +#define LP_TEE_WRITE_REE1_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE1_CLKRST_S 6 +/** LP_TEE_WRITE_REE2_CLKRST : R/W; bitpos: [7]; default: 0; + * Configures clkrst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_CLKRST (BIT(7)) +#define LP_TEE_WRITE_REE2_CLKRST_M (LP_TEE_WRITE_REE2_CLKRST_V << LP_TEE_WRITE_REE2_CLKRST_S) +#define LP_TEE_WRITE_REE2_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE2_CLKRST_S 7 + +/** LP_TEE_LP_AON_CTRL_CTRL_REG register + * lp_aon_ctrl read/write control register + */ +#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10) +/** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; + * Configures lp_aon_ctrl registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_AON_CTRL (BIT(0)) +#define LP_TEE_READ_TEE_LP_AON_CTRL_M (LP_TEE_READ_TEE_LP_AON_CTRL_V << LP_TEE_READ_TEE_LP_AON_CTRL_S) +#define LP_TEE_READ_TEE_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_TEE_LP_AON_CTRL_S 0 +/** LP_TEE_READ_REE0_LP_AON_CTRL : R/W; bitpos: [1]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_AON_CTRL (BIT(1)) +#define LP_TEE_READ_REE0_LP_AON_CTRL_M (LP_TEE_READ_REE0_LP_AON_CTRL_V << LP_TEE_READ_REE0_LP_AON_CTRL_S) +#define LP_TEE_READ_REE0_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE0_LP_AON_CTRL_S 1 +/** LP_TEE_READ_REE1_LP_AON_CTRL : R/W; bitpos: [2]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_AON_CTRL (BIT(2)) +#define LP_TEE_READ_REE1_LP_AON_CTRL_M (LP_TEE_READ_REE1_LP_AON_CTRL_V << LP_TEE_READ_REE1_LP_AON_CTRL_S) +#define LP_TEE_READ_REE1_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE1_LP_AON_CTRL_S 2 +/** LP_TEE_READ_REE2_LP_AON_CTRL : R/W; bitpos: [3]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_AON_CTRL (BIT(3)) +#define LP_TEE_READ_REE2_LP_AON_CTRL_M (LP_TEE_READ_REE2_LP_AON_CTRL_V << LP_TEE_READ_REE2_LP_AON_CTRL_S) +#define LP_TEE_READ_REE2_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE2_LP_AON_CTRL_S 3 +/** LP_TEE_WRITE_TEE_LP_AON_CTRL : R/W; bitpos: [4]; default: 1; + * Configures lp_aon_ctrl registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_AON_CTRL (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_M (LP_TEE_WRITE_TEE_LP_AON_CTRL_V << LP_TEE_WRITE_TEE_LP_AON_CTRL_S) +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_S 4 +/** LP_TEE_WRITE_REE0_LP_AON_CTRL : R/W; bitpos: [5]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_AON_CTRL (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_M (LP_TEE_WRITE_REE0_LP_AON_CTRL_V << LP_TEE_WRITE_REE0_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_S 5 +/** LP_TEE_WRITE_REE1_LP_AON_CTRL : R/W; bitpos: [6]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_AON_CTRL (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_M (LP_TEE_WRITE_REE1_LP_AON_CTRL_V << LP_TEE_WRITE_REE1_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_S 6 +/** LP_TEE_WRITE_REE2_LP_AON_CTRL : R/W; bitpos: [7]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_AON_CTRL (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_M (LP_TEE_WRITE_REE2_LP_AON_CTRL_V << LP_TEE_WRITE_REE2_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7 + +/** LP_TEE_LP_TIMER_CTRL_REG register + * lp_timer read/write control register + */ +#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14) +/** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; + * Configures lp_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_TIMER (BIT(0)) +#define LP_TEE_READ_TEE_LP_TIMER_M (LP_TEE_READ_TEE_LP_TIMER_V << LP_TEE_READ_TEE_LP_TIMER_S) +#define LP_TEE_READ_TEE_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_TEE_LP_TIMER_S 0 +/** LP_TEE_READ_REE0_LP_TIMER : R/W; bitpos: [1]; default: 0; + * Configures lp_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_TIMER (BIT(1)) +#define LP_TEE_READ_REE0_LP_TIMER_M (LP_TEE_READ_REE0_LP_TIMER_V << LP_TEE_READ_REE0_LP_TIMER_S) +#define LP_TEE_READ_REE0_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE0_LP_TIMER_S 1 +/** LP_TEE_READ_REE1_LP_TIMER : R/W; bitpos: [2]; default: 0; + * Configures lp_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_TIMER (BIT(2)) +#define LP_TEE_READ_REE1_LP_TIMER_M (LP_TEE_READ_REE1_LP_TIMER_V << LP_TEE_READ_REE1_LP_TIMER_S) +#define LP_TEE_READ_REE1_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE1_LP_TIMER_S 2 +/** LP_TEE_READ_REE2_LP_TIMER : R/W; bitpos: [3]; default: 0; + * Configures lp_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_TIMER (BIT(3)) +#define LP_TEE_READ_REE2_LP_TIMER_M (LP_TEE_READ_REE2_LP_TIMER_V << LP_TEE_READ_REE2_LP_TIMER_S) +#define LP_TEE_READ_REE2_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE2_LP_TIMER_S 3 +/** LP_TEE_WRITE_TEE_LP_TIMER : R/W; bitpos: [4]; default: 1; + * Configures lp_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_TIMER (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_TIMER_M (LP_TEE_WRITE_TEE_LP_TIMER_V << LP_TEE_WRITE_TEE_LP_TIMER_S) +#define LP_TEE_WRITE_TEE_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_TIMER_S 4 +/** LP_TEE_WRITE_REE0_LP_TIMER : R/W; bitpos: [5]; default: 0; + * Configures lp_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_TIMER (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_TIMER_M (LP_TEE_WRITE_REE0_LP_TIMER_V << LP_TEE_WRITE_REE0_LP_TIMER_S) +#define LP_TEE_WRITE_REE0_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_TIMER_S 5 +/** LP_TEE_WRITE_REE1_LP_TIMER : R/W; bitpos: [6]; default: 0; + * Configures lp_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_TIMER (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_TIMER_M (LP_TEE_WRITE_REE1_LP_TIMER_V << LP_TEE_WRITE_REE1_LP_TIMER_S) +#define LP_TEE_WRITE_REE1_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_TIMER_S 6 +/** LP_TEE_WRITE_REE2_LP_TIMER : R/W; bitpos: [7]; default: 0; + * Configures lp_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_TIMER (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_TIMER_M (LP_TEE_WRITE_REE2_LP_TIMER_V << LP_TEE_WRITE_REE2_LP_TIMER_S) +#define LP_TEE_WRITE_REE2_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_TIMER_S 7 + +/** LP_TEE_LP_WDT_CTRL_REG register + * lp_wdt read/write control register + */ +#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18) +/** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; + * Configures lp_wdt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_WDT (BIT(0)) +#define LP_TEE_READ_TEE_LP_WDT_M (LP_TEE_READ_TEE_LP_WDT_V << LP_TEE_READ_TEE_LP_WDT_S) +#define LP_TEE_READ_TEE_LP_WDT_V 0x00000001U +#define LP_TEE_READ_TEE_LP_WDT_S 0 +/** LP_TEE_READ_REE0_LP_WDT : R/W; bitpos: [1]; default: 0; + * Configures lp_wdt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_WDT (BIT(1)) +#define LP_TEE_READ_REE0_LP_WDT_M (LP_TEE_READ_REE0_LP_WDT_V << LP_TEE_READ_REE0_LP_WDT_S) +#define LP_TEE_READ_REE0_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE0_LP_WDT_S 1 +/** LP_TEE_READ_REE1_LP_WDT : R/W; bitpos: [2]; default: 0; + * Configures lp_wdt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_WDT (BIT(2)) +#define LP_TEE_READ_REE1_LP_WDT_M (LP_TEE_READ_REE1_LP_WDT_V << LP_TEE_READ_REE1_LP_WDT_S) +#define LP_TEE_READ_REE1_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE1_LP_WDT_S 2 +/** LP_TEE_READ_REE2_LP_WDT : R/W; bitpos: [3]; default: 0; + * Configures lp_wdt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_WDT (BIT(3)) +#define LP_TEE_READ_REE2_LP_WDT_M (LP_TEE_READ_REE2_LP_WDT_V << LP_TEE_READ_REE2_LP_WDT_S) +#define LP_TEE_READ_REE2_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE2_LP_WDT_S 3 +/** LP_TEE_WRITE_TEE_LP_WDT : R/W; bitpos: [4]; default: 1; + * Configures lp_wdt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_WDT (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_WDT_M (LP_TEE_WRITE_TEE_LP_WDT_V << LP_TEE_WRITE_TEE_LP_WDT_S) +#define LP_TEE_WRITE_TEE_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_WDT_S 4 +/** LP_TEE_WRITE_REE0_LP_WDT : R/W; bitpos: [5]; default: 0; + * Configures lp_wdt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_WDT (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_WDT_M (LP_TEE_WRITE_REE0_LP_WDT_V << LP_TEE_WRITE_REE0_LP_WDT_S) +#define LP_TEE_WRITE_REE0_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_WDT_S 5 +/** LP_TEE_WRITE_REE1_LP_WDT : R/W; bitpos: [6]; default: 0; + * Configures lp_wdt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_WDT (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_WDT_M (LP_TEE_WRITE_REE1_LP_WDT_V << LP_TEE_WRITE_REE1_LP_WDT_S) +#define LP_TEE_WRITE_REE1_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_WDT_S 6 +/** LP_TEE_WRITE_REE2_LP_WDT : R/W; bitpos: [7]; default: 0; + * Configures lp_wdt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_WDT (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_WDT_M (LP_TEE_WRITE_REE2_LP_WDT_V << LP_TEE_WRITE_REE2_LP_WDT_S) +#define LP_TEE_WRITE_REE2_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_WDT_S 7 + +/** LP_TEE_LP_PERI_CTRL_REG register + * lp_peri read/write control register + */ +#define LP_TEE_LP_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c) +/** LP_TEE_READ_TEE_LP_PERI : R/W; bitpos: [0]; default: 1; + * Configures lp_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_PERI (BIT(0)) +#define LP_TEE_READ_TEE_LP_PERI_M (LP_TEE_READ_TEE_LP_PERI_V << LP_TEE_READ_TEE_LP_PERI_S) +#define LP_TEE_READ_TEE_LP_PERI_V 0x00000001U +#define LP_TEE_READ_TEE_LP_PERI_S 0 +/** LP_TEE_READ_REE0_LP_PERI : R/W; bitpos: [1]; default: 0; + * Configures lp_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_PERI (BIT(1)) +#define LP_TEE_READ_REE0_LP_PERI_M (LP_TEE_READ_REE0_LP_PERI_V << LP_TEE_READ_REE0_LP_PERI_S) +#define LP_TEE_READ_REE0_LP_PERI_V 0x00000001U +#define LP_TEE_READ_REE0_LP_PERI_S 1 +/** LP_TEE_READ_REE1_LP_PERI : R/W; bitpos: [2]; default: 0; + * Configures lp_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_PERI (BIT(2)) +#define LP_TEE_READ_REE1_LP_PERI_M (LP_TEE_READ_REE1_LP_PERI_V << LP_TEE_READ_REE1_LP_PERI_S) +#define LP_TEE_READ_REE1_LP_PERI_V 0x00000001U +#define LP_TEE_READ_REE1_LP_PERI_S 2 +/** LP_TEE_READ_REE2_LP_PERI : R/W; bitpos: [3]; default: 0; + * Configures lp_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_PERI (BIT(3)) +#define LP_TEE_READ_REE2_LP_PERI_M (LP_TEE_READ_REE2_LP_PERI_V << LP_TEE_READ_REE2_LP_PERI_S) +#define LP_TEE_READ_REE2_LP_PERI_V 0x00000001U +#define LP_TEE_READ_REE2_LP_PERI_S 3 +/** LP_TEE_WRITE_TEE_LP_PERI : R/W; bitpos: [4]; default: 1; + * Configures lp_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_PERI (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_PERI_M (LP_TEE_WRITE_TEE_LP_PERI_V << LP_TEE_WRITE_TEE_LP_PERI_S) +#define LP_TEE_WRITE_TEE_LP_PERI_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_PERI_S 4 +/** LP_TEE_WRITE_REE0_LP_PERI : R/W; bitpos: [5]; default: 0; + * Configures lp_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_PERI (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_PERI_M (LP_TEE_WRITE_REE0_LP_PERI_V << LP_TEE_WRITE_REE0_LP_PERI_S) +#define LP_TEE_WRITE_REE0_LP_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_PERI_S 5 +/** LP_TEE_WRITE_REE1_LP_PERI : R/W; bitpos: [6]; default: 0; + * Configures lp_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_PERI (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_PERI_M (LP_TEE_WRITE_REE1_LP_PERI_V << LP_TEE_WRITE_REE1_LP_PERI_S) +#define LP_TEE_WRITE_REE1_LP_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_PERI_S 6 +/** LP_TEE_WRITE_REE2_LP_PERI : R/W; bitpos: [7]; default: 0; + * Configures lp_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_PERI (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_PERI_M (LP_TEE_WRITE_REE2_LP_PERI_V << LP_TEE_WRITE_REE2_LP_PERI_S) +#define LP_TEE_WRITE_REE2_LP_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_PERI_S 7 + +/** LP_TEE_LP_ANA_PERI_CTRL_REG register + * lp_ana_peri read/write control register + */ +#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20) +/** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; + * Configures lp_ana_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_ANA_PERI (BIT(0)) +#define LP_TEE_READ_TEE_LP_ANA_PERI_M (LP_TEE_READ_TEE_LP_ANA_PERI_V << LP_TEE_READ_TEE_LP_ANA_PERI_S) +#define LP_TEE_READ_TEE_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_TEE_LP_ANA_PERI_S 0 +/** LP_TEE_READ_REE0_LP_ANA_PERI : R/W; bitpos: [1]; default: 0; + * Configures lp_ana_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_ANA_PERI (BIT(1)) +#define LP_TEE_READ_REE0_LP_ANA_PERI_M (LP_TEE_READ_REE0_LP_ANA_PERI_V << LP_TEE_READ_REE0_LP_ANA_PERI_S) +#define LP_TEE_READ_REE0_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE0_LP_ANA_PERI_S 1 +/** LP_TEE_READ_REE1_LP_ANA_PERI : R/W; bitpos: [2]; default: 0; + * Configures lp_ana_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_ANA_PERI (BIT(2)) +#define LP_TEE_READ_REE1_LP_ANA_PERI_M (LP_TEE_READ_REE1_LP_ANA_PERI_V << LP_TEE_READ_REE1_LP_ANA_PERI_S) +#define LP_TEE_READ_REE1_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE1_LP_ANA_PERI_S 2 +/** LP_TEE_READ_REE2_LP_ANA_PERI : R/W; bitpos: [3]; default: 0; + * Configures lp_ana_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_ANA_PERI (BIT(3)) +#define LP_TEE_READ_REE2_LP_ANA_PERI_M (LP_TEE_READ_REE2_LP_ANA_PERI_V << LP_TEE_READ_REE2_LP_ANA_PERI_S) +#define LP_TEE_READ_REE2_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE2_LP_ANA_PERI_S 3 +/** LP_TEE_WRITE_TEE_LP_ANA_PERI : R/W; bitpos: [4]; default: 1; + * Configures lp_ana_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_ANA_PERI (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_M (LP_TEE_WRITE_TEE_LP_ANA_PERI_V << LP_TEE_WRITE_TEE_LP_ANA_PERI_S) +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_S 4 +/** LP_TEE_WRITE_REE0_LP_ANA_PERI : R/W; bitpos: [5]; default: 0; + * Configures lp_ana_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_ANA_PERI (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_M (LP_TEE_WRITE_REE0_LP_ANA_PERI_V << LP_TEE_WRITE_REE0_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_S 5 +/** LP_TEE_WRITE_REE1_LP_ANA_PERI : R/W; bitpos: [6]; default: 0; + * Configures lp_ana_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_ANA_PERI (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_M (LP_TEE_WRITE_REE1_LP_ANA_PERI_V << LP_TEE_WRITE_REE1_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_S 6 +/** LP_TEE_WRITE_REE2_LP_ANA_PERI : R/W; bitpos: [7]; default: 0; + * Configures lp_ana_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_ANA_PERI (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_M (LP_TEE_WRITE_REE2_LP_ANA_PERI_V << LP_TEE_WRITE_REE2_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7 + +/** LP_TEE_LP_IO_CTRL_REG register + * lp_io read/write control register + */ +#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c) +/** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; + * Configures lp_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_IO (BIT(0)) +#define LP_TEE_READ_TEE_LP_IO_M (LP_TEE_READ_TEE_LP_IO_V << LP_TEE_READ_TEE_LP_IO_S) +#define LP_TEE_READ_TEE_LP_IO_V 0x00000001U +#define LP_TEE_READ_TEE_LP_IO_S 0 +/** LP_TEE_READ_REE0_LP_IO : R/W; bitpos: [1]; default: 0; + * Configures lp_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_IO (BIT(1)) +#define LP_TEE_READ_REE0_LP_IO_M (LP_TEE_READ_REE0_LP_IO_V << LP_TEE_READ_REE0_LP_IO_S) +#define LP_TEE_READ_REE0_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE0_LP_IO_S 1 +/** LP_TEE_READ_REE1_LP_IO : R/W; bitpos: [2]; default: 0; + * Configures lp_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_IO (BIT(2)) +#define LP_TEE_READ_REE1_LP_IO_M (LP_TEE_READ_REE1_LP_IO_V << LP_TEE_READ_REE1_LP_IO_S) +#define LP_TEE_READ_REE1_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE1_LP_IO_S 2 +/** LP_TEE_READ_REE2_LP_IO : R/W; bitpos: [3]; default: 0; + * Configures lp_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_IO (BIT(3)) +#define LP_TEE_READ_REE2_LP_IO_M (LP_TEE_READ_REE2_LP_IO_V << LP_TEE_READ_REE2_LP_IO_S) +#define LP_TEE_READ_REE2_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE2_LP_IO_S 3 +/** LP_TEE_WRITE_TEE_LP_IO : R/W; bitpos: [4]; default: 1; + * Configures lp_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_IO (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_IO_M (LP_TEE_WRITE_TEE_LP_IO_V << LP_TEE_WRITE_TEE_LP_IO_S) +#define LP_TEE_WRITE_TEE_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_IO_S 4 +/** LP_TEE_WRITE_REE0_LP_IO : R/W; bitpos: [5]; default: 0; + * Configures lp_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_IO (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_IO_M (LP_TEE_WRITE_REE0_LP_IO_V << LP_TEE_WRITE_REE0_LP_IO_S) +#define LP_TEE_WRITE_REE0_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_IO_S 5 +/** LP_TEE_WRITE_REE1_LP_IO : R/W; bitpos: [6]; default: 0; + * Configures lp_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_IO (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_IO_M (LP_TEE_WRITE_REE1_LP_IO_V << LP_TEE_WRITE_REE1_LP_IO_S) +#define LP_TEE_WRITE_REE1_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_IO_S 6 +/** LP_TEE_WRITE_REE2_LP_IO : R/W; bitpos: [7]; default: 0; + * Configures lp_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_IO (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_IO_M (LP_TEE_WRITE_REE2_LP_IO_V << LP_TEE_WRITE_REE2_LP_IO_S) +#define LP_TEE_WRITE_REE2_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_IO_S 7 + +/** LP_TEE_LP_TEE_CTRL_REG register + * lp_tee read/write control register + */ +#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34) +/** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; + * Configures lp_tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_TEE (BIT(0)) +#define LP_TEE_READ_TEE_LP_TEE_M (LP_TEE_READ_TEE_LP_TEE_V << LP_TEE_READ_TEE_LP_TEE_S) +#define LP_TEE_READ_TEE_LP_TEE_V 0x00000001U +#define LP_TEE_READ_TEE_LP_TEE_S 0 +/** LP_TEE_READ_REE0_LP_TEE : HRO; bitpos: [1]; default: 0; + * Configures lp_tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_TEE (BIT(1)) +#define LP_TEE_READ_REE0_LP_TEE_M (LP_TEE_READ_REE0_LP_TEE_V << LP_TEE_READ_REE0_LP_TEE_S) +#define LP_TEE_READ_REE0_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE0_LP_TEE_S 1 +/** LP_TEE_READ_REE1_LP_TEE : HRO; bitpos: [2]; default: 0; + * Configures lp_tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_TEE (BIT(2)) +#define LP_TEE_READ_REE1_LP_TEE_M (LP_TEE_READ_REE1_LP_TEE_V << LP_TEE_READ_REE1_LP_TEE_S) +#define LP_TEE_READ_REE1_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE1_LP_TEE_S 2 +/** LP_TEE_READ_REE2_LP_TEE : HRO; bitpos: [3]; default: 0; + * Configures lp_tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_TEE (BIT(3)) +#define LP_TEE_READ_REE2_LP_TEE_M (LP_TEE_READ_REE2_LP_TEE_V << LP_TEE_READ_REE2_LP_TEE_S) +#define LP_TEE_READ_REE2_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE2_LP_TEE_S 3 +/** LP_TEE_WRITE_TEE_LP_TEE : R/W; bitpos: [4]; default: 1; + * Configures lp_tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_TEE (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_TEE_M (LP_TEE_WRITE_TEE_LP_TEE_V << LP_TEE_WRITE_TEE_LP_TEE_S) +#define LP_TEE_WRITE_TEE_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_TEE_S 4 +/** LP_TEE_WRITE_REE0_LP_TEE : HRO; bitpos: [5]; default: 0; + * Configures lp_tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_TEE (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_TEE_M (LP_TEE_WRITE_REE0_LP_TEE_V << LP_TEE_WRITE_REE0_LP_TEE_S) +#define LP_TEE_WRITE_REE0_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_TEE_S 5 +/** LP_TEE_WRITE_REE1_LP_TEE : HRO; bitpos: [6]; default: 0; + * Configures lp_tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_TEE (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_TEE_M (LP_TEE_WRITE_REE1_LP_TEE_V << LP_TEE_WRITE_REE1_LP_TEE_S) +#define LP_TEE_WRITE_REE1_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_TEE_S 6 +/** LP_TEE_WRITE_REE2_LP_TEE : HRO; bitpos: [7]; default: 0; + * Configures lp_tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_TEE (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_TEE_M (LP_TEE_WRITE_REE2_LP_TEE_V << LP_TEE_WRITE_REE2_LP_TEE_S) +#define LP_TEE_WRITE_REE2_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_TEE_S 7 + +/** LP_TEE_UART_CTRL_REG register + * uart read/write control register + */ +#define LP_TEE_UART_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38) +/** LP_TEE_READ_TEE_UART : R/W; bitpos: [0]; default: 1; + * Configures uart registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_UART (BIT(0)) +#define LP_TEE_READ_TEE_UART_M (LP_TEE_READ_TEE_UART_V << LP_TEE_READ_TEE_UART_S) +#define LP_TEE_READ_TEE_UART_V 0x00000001U +#define LP_TEE_READ_TEE_UART_S 0 +/** LP_TEE_READ_REE0_UART : R/W; bitpos: [1]; default: 0; + * Configures uart registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_UART (BIT(1)) +#define LP_TEE_READ_REE0_UART_M (LP_TEE_READ_REE0_UART_V << LP_TEE_READ_REE0_UART_S) +#define LP_TEE_READ_REE0_UART_V 0x00000001U +#define LP_TEE_READ_REE0_UART_S 1 +/** LP_TEE_READ_REE1_UART : R/W; bitpos: [2]; default: 0; + * Configures uart registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_UART (BIT(2)) +#define LP_TEE_READ_REE1_UART_M (LP_TEE_READ_REE1_UART_V << LP_TEE_READ_REE1_UART_S) +#define LP_TEE_READ_REE1_UART_V 0x00000001U +#define LP_TEE_READ_REE1_UART_S 2 +/** LP_TEE_READ_REE2_UART : R/W; bitpos: [3]; default: 0; + * Configures uart registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_UART (BIT(3)) +#define LP_TEE_READ_REE2_UART_M (LP_TEE_READ_REE2_UART_V << LP_TEE_READ_REE2_UART_S) +#define LP_TEE_READ_REE2_UART_V 0x00000001U +#define LP_TEE_READ_REE2_UART_S 3 +/** LP_TEE_WRITE_TEE_UART : R/W; bitpos: [4]; default: 1; + * Configures uart registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_UART (BIT(4)) +#define LP_TEE_WRITE_TEE_UART_M (LP_TEE_WRITE_TEE_UART_V << LP_TEE_WRITE_TEE_UART_S) +#define LP_TEE_WRITE_TEE_UART_V 0x00000001U +#define LP_TEE_WRITE_TEE_UART_S 4 +/** LP_TEE_WRITE_REE0_UART : R/W; bitpos: [5]; default: 0; + * Configures uart registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_UART (BIT(5)) +#define LP_TEE_WRITE_REE0_UART_M (LP_TEE_WRITE_REE0_UART_V << LP_TEE_WRITE_REE0_UART_S) +#define LP_TEE_WRITE_REE0_UART_V 0x00000001U +#define LP_TEE_WRITE_REE0_UART_S 5 +/** LP_TEE_WRITE_REE1_UART : R/W; bitpos: [6]; default: 0; + * Configures uart registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_UART (BIT(6)) +#define LP_TEE_WRITE_REE1_UART_M (LP_TEE_WRITE_REE1_UART_V << LP_TEE_WRITE_REE1_UART_S) +#define LP_TEE_WRITE_REE1_UART_V 0x00000001U +#define LP_TEE_WRITE_REE1_UART_S 6 +/** LP_TEE_WRITE_REE2_UART : R/W; bitpos: [7]; default: 0; + * Configures uart registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_UART (BIT(7)) +#define LP_TEE_WRITE_REE2_UART_M (LP_TEE_WRITE_REE2_UART_V << LP_TEE_WRITE_REE2_UART_S) +#define LP_TEE_WRITE_REE2_UART_V 0x00000001U +#define LP_TEE_WRITE_REE2_UART_S 7 + +/** LP_TEE_I2C_EXT_CTRL_REG register + * i2c_ext read/write control register + */ +#define LP_TEE_I2C_EXT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x40) +/** LP_TEE_READ_TEE_I2C_EXT : R/W; bitpos: [0]; default: 1; + * Configures i2c_ext registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_I2C_EXT (BIT(0)) +#define LP_TEE_READ_TEE_I2C_EXT_M (LP_TEE_READ_TEE_I2C_EXT_V << LP_TEE_READ_TEE_I2C_EXT_S) +#define LP_TEE_READ_TEE_I2C_EXT_V 0x00000001U +#define LP_TEE_READ_TEE_I2C_EXT_S 0 +/** LP_TEE_READ_REE0_I2C_EXT : R/W; bitpos: [1]; default: 0; + * Configures i2c_ext registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_I2C_EXT (BIT(1)) +#define LP_TEE_READ_REE0_I2C_EXT_M (LP_TEE_READ_REE0_I2C_EXT_V << LP_TEE_READ_REE0_I2C_EXT_S) +#define LP_TEE_READ_REE0_I2C_EXT_V 0x00000001U +#define LP_TEE_READ_REE0_I2C_EXT_S 1 +/** LP_TEE_READ_REE1_I2C_EXT : R/W; bitpos: [2]; default: 0; + * Configures i2c_ext registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_I2C_EXT (BIT(2)) +#define LP_TEE_READ_REE1_I2C_EXT_M (LP_TEE_READ_REE1_I2C_EXT_V << LP_TEE_READ_REE1_I2C_EXT_S) +#define LP_TEE_READ_REE1_I2C_EXT_V 0x00000001U +#define LP_TEE_READ_REE1_I2C_EXT_S 2 +/** LP_TEE_READ_REE2_I2C_EXT : R/W; bitpos: [3]; default: 0; + * Configures i2c_ext registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_I2C_EXT (BIT(3)) +#define LP_TEE_READ_REE2_I2C_EXT_M (LP_TEE_READ_REE2_I2C_EXT_V << LP_TEE_READ_REE2_I2C_EXT_S) +#define LP_TEE_READ_REE2_I2C_EXT_V 0x00000001U +#define LP_TEE_READ_REE2_I2C_EXT_S 3 +/** LP_TEE_WRITE_TEE_I2C_EXT : R/W; bitpos: [4]; default: 1; + * Configures i2c_ext registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_I2C_EXT (BIT(4)) +#define LP_TEE_WRITE_TEE_I2C_EXT_M (LP_TEE_WRITE_TEE_I2C_EXT_V << LP_TEE_WRITE_TEE_I2C_EXT_S) +#define LP_TEE_WRITE_TEE_I2C_EXT_V 0x00000001U +#define LP_TEE_WRITE_TEE_I2C_EXT_S 4 +/** LP_TEE_WRITE_REE0_I2C_EXT : R/W; bitpos: [5]; default: 0; + * Configures i2c_ext registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_I2C_EXT (BIT(5)) +#define LP_TEE_WRITE_REE0_I2C_EXT_M (LP_TEE_WRITE_REE0_I2C_EXT_V << LP_TEE_WRITE_REE0_I2C_EXT_S) +#define LP_TEE_WRITE_REE0_I2C_EXT_V 0x00000001U +#define LP_TEE_WRITE_REE0_I2C_EXT_S 5 +/** LP_TEE_WRITE_REE1_I2C_EXT : R/W; bitpos: [6]; default: 0; + * Configures i2c_ext registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_I2C_EXT (BIT(6)) +#define LP_TEE_WRITE_REE1_I2C_EXT_M (LP_TEE_WRITE_REE1_I2C_EXT_V << LP_TEE_WRITE_REE1_I2C_EXT_S) +#define LP_TEE_WRITE_REE1_I2C_EXT_V 0x00000001U +#define LP_TEE_WRITE_REE1_I2C_EXT_S 6 +/** LP_TEE_WRITE_REE2_I2C_EXT : R/W; bitpos: [7]; default: 0; + * Configures i2c_ext registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_I2C_EXT (BIT(7)) +#define LP_TEE_WRITE_REE2_I2C_EXT_M (LP_TEE_WRITE_REE2_I2C_EXT_V << LP_TEE_WRITE_REE2_I2C_EXT_S) +#define LP_TEE_WRITE_REE2_I2C_EXT_V 0x00000001U +#define LP_TEE_WRITE_REE2_I2C_EXT_S 7 + +/** LP_TEE_I2C_ANA_MST_CTRL_REG register + * i2c_ana_mst read/write control register + */ +#define LP_TEE_I2C_ANA_MST_CTRL_REG (DR_REG_LP_TEE_BASE + 0x44) +/** LP_TEE_READ_TEE_I2C_ANA_MST : R/W; bitpos: [0]; default: 1; + * Configures i2c_ana_mst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_I2C_ANA_MST (BIT(0)) +#define LP_TEE_READ_TEE_I2C_ANA_MST_M (LP_TEE_READ_TEE_I2C_ANA_MST_V << LP_TEE_READ_TEE_I2C_ANA_MST_S) +#define LP_TEE_READ_TEE_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_READ_TEE_I2C_ANA_MST_S 0 +/** LP_TEE_READ_REE0_I2C_ANA_MST : R/W; bitpos: [1]; default: 0; + * Configures i2c_ana_mst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_I2C_ANA_MST (BIT(1)) +#define LP_TEE_READ_REE0_I2C_ANA_MST_M (LP_TEE_READ_REE0_I2C_ANA_MST_V << LP_TEE_READ_REE0_I2C_ANA_MST_S) +#define LP_TEE_READ_REE0_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_READ_REE0_I2C_ANA_MST_S 1 +/** LP_TEE_READ_REE1_I2C_ANA_MST : R/W; bitpos: [2]; default: 0; + * Configures i2c_ana_mst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_I2C_ANA_MST (BIT(2)) +#define LP_TEE_READ_REE1_I2C_ANA_MST_M (LP_TEE_READ_REE1_I2C_ANA_MST_V << LP_TEE_READ_REE1_I2C_ANA_MST_S) +#define LP_TEE_READ_REE1_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_READ_REE1_I2C_ANA_MST_S 2 +/** LP_TEE_READ_REE2_I2C_ANA_MST : R/W; bitpos: [3]; default: 0; + * Configures i2c_ana_mst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_I2C_ANA_MST (BIT(3)) +#define LP_TEE_READ_REE2_I2C_ANA_MST_M (LP_TEE_READ_REE2_I2C_ANA_MST_V << LP_TEE_READ_REE2_I2C_ANA_MST_S) +#define LP_TEE_READ_REE2_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_READ_REE2_I2C_ANA_MST_S 3 +/** LP_TEE_WRITE_TEE_I2C_ANA_MST : R/W; bitpos: [4]; default: 1; + * Configures i2c_ana_mst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_I2C_ANA_MST (BIT(4)) +#define LP_TEE_WRITE_TEE_I2C_ANA_MST_M (LP_TEE_WRITE_TEE_I2C_ANA_MST_V << LP_TEE_WRITE_TEE_I2C_ANA_MST_S) +#define LP_TEE_WRITE_TEE_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_WRITE_TEE_I2C_ANA_MST_S 4 +/** LP_TEE_WRITE_REE0_I2C_ANA_MST : R/W; bitpos: [5]; default: 0; + * Configures i2c_ana_mst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_I2C_ANA_MST (BIT(5)) +#define LP_TEE_WRITE_REE0_I2C_ANA_MST_M (LP_TEE_WRITE_REE0_I2C_ANA_MST_V << LP_TEE_WRITE_REE0_I2C_ANA_MST_S) +#define LP_TEE_WRITE_REE0_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_WRITE_REE0_I2C_ANA_MST_S 5 +/** LP_TEE_WRITE_REE1_I2C_ANA_MST : R/W; bitpos: [6]; default: 0; + * Configures i2c_ana_mst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_I2C_ANA_MST (BIT(6)) +#define LP_TEE_WRITE_REE1_I2C_ANA_MST_M (LP_TEE_WRITE_REE1_I2C_ANA_MST_V << LP_TEE_WRITE_REE1_I2C_ANA_MST_S) +#define LP_TEE_WRITE_REE1_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_WRITE_REE1_I2C_ANA_MST_S 6 +/** LP_TEE_WRITE_REE2_I2C_ANA_MST : R/W; bitpos: [7]; default: 0; + * Configures i2c_ana_mst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_I2C_ANA_MST (BIT(7)) +#define LP_TEE_WRITE_REE2_I2C_ANA_MST_M (LP_TEE_WRITE_REE2_I2C_ANA_MST_V << LP_TEE_WRITE_REE2_I2C_ANA_MST_S) +#define LP_TEE_WRITE_REE2_I2C_ANA_MST_V 0x00000001U +#define LP_TEE_WRITE_REE2_I2C_ANA_MST_S 7 + +/** LP_TEE_HUK_CTRL_REG register + * huk read/write control register + */ +#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x48) +/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; + * Configures huk registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_HUK (BIT(0)) +#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S) +#define LP_TEE_READ_TEE_HUK_V 0x00000001U +#define LP_TEE_READ_TEE_HUK_S 0 +/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0; + * Configures huk registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_HUK (BIT(1)) +#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S) +#define LP_TEE_READ_REE0_HUK_V 0x00000001U +#define LP_TEE_READ_REE0_HUK_S 1 +/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0; + * Configures huk registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_HUK (BIT(2)) +#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S) +#define LP_TEE_READ_REE1_HUK_V 0x00000001U +#define LP_TEE_READ_REE1_HUK_S 2 +/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0; + * Configures huk registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_HUK (BIT(3)) +#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S) +#define LP_TEE_READ_REE2_HUK_V 0x00000001U +#define LP_TEE_READ_REE2_HUK_S 3 +/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1; + * Configures huk registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_HUK (BIT(4)) +#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S) +#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U +#define LP_TEE_WRITE_TEE_HUK_S 4 +/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0; + * Configures huk registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_HUK (BIT(5)) +#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S) +#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE0_HUK_S 5 +/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0; + * Configures huk registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_HUK (BIT(6)) +#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S) +#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE1_HUK_S 6 +/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0; + * Configures huk registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_HUK (BIT(7)) +#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S) +#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE2_HUK_S 7 + +/** LP_TEE_LP_APM_CTRL_REG register + * lp_apm read/write control register + */ +#define LP_TEE_LP_APM_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4c) +/** LP_TEE_READ_TEE_LP_APM : R/W; bitpos: [0]; default: 1; + * Configures lp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_APM (BIT(0)) +#define LP_TEE_READ_TEE_LP_APM_M (LP_TEE_READ_TEE_LP_APM_V << LP_TEE_READ_TEE_LP_APM_S) +#define LP_TEE_READ_TEE_LP_APM_V 0x00000001U +#define LP_TEE_READ_TEE_LP_APM_S 0 +/** LP_TEE_READ_REE0_LP_APM : HRO; bitpos: [1]; default: 0; + * Configures lp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_APM (BIT(1)) +#define LP_TEE_READ_REE0_LP_APM_M (LP_TEE_READ_REE0_LP_APM_V << LP_TEE_READ_REE0_LP_APM_S) +#define LP_TEE_READ_REE0_LP_APM_V 0x00000001U +#define LP_TEE_READ_REE0_LP_APM_S 1 +/** LP_TEE_READ_REE1_LP_APM : HRO; bitpos: [2]; default: 0; + * Configures lp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_APM (BIT(2)) +#define LP_TEE_READ_REE1_LP_APM_M (LP_TEE_READ_REE1_LP_APM_V << LP_TEE_READ_REE1_LP_APM_S) +#define LP_TEE_READ_REE1_LP_APM_V 0x00000001U +#define LP_TEE_READ_REE1_LP_APM_S 2 +/** LP_TEE_READ_REE2_LP_APM : HRO; bitpos: [3]; default: 0; + * Configures lp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_APM (BIT(3)) +#define LP_TEE_READ_REE2_LP_APM_M (LP_TEE_READ_REE2_LP_APM_V << LP_TEE_READ_REE2_LP_APM_S) +#define LP_TEE_READ_REE2_LP_APM_V 0x00000001U +#define LP_TEE_READ_REE2_LP_APM_S 3 +/** LP_TEE_WRITE_TEE_LP_APM : R/W; bitpos: [4]; default: 1; + * Configures lp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_APM (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_APM_M (LP_TEE_WRITE_TEE_LP_APM_V << LP_TEE_WRITE_TEE_LP_APM_S) +#define LP_TEE_WRITE_TEE_LP_APM_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_APM_S 4 +/** LP_TEE_WRITE_REE0_LP_APM : HRO; bitpos: [5]; default: 0; + * Configures lp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_APM (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_APM_M (LP_TEE_WRITE_REE0_LP_APM_V << LP_TEE_WRITE_REE0_LP_APM_S) +#define LP_TEE_WRITE_REE0_LP_APM_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_APM_S 5 +/** LP_TEE_WRITE_REE1_LP_APM : HRO; bitpos: [6]; default: 0; + * Configures lp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_APM (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_APM_M (LP_TEE_WRITE_REE1_LP_APM_V << LP_TEE_WRITE_REE1_LP_APM_S) +#define LP_TEE_WRITE_REE1_LP_APM_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_APM_S 6 +/** LP_TEE_WRITE_REE2_LP_APM : HRO; bitpos: [7]; default: 0; + * Configures lp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_APM (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_APM_M (LP_TEE_WRITE_REE2_LP_APM_V << LP_TEE_WRITE_REE2_LP_APM_S) +#define LP_TEE_WRITE_REE2_LP_APM_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_APM_S 7 /** LP_TEE_FORCE_ACC_HP_REG register * Force access to hpmem configuration register @@ -54,20 +1195,48 @@ extern "C" { #define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) /** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; * Configures whether to allow LP CPU to force access to HP_MEM regardless of - * permission management.\\ - * 0: disable force access HP_MEM \\ - * 1: enable force access HP_MEM \\ + * permission management. + * 0: disable force access HP_MEM + * 1: enable force access HP_MEM */ #define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) #define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) #define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U #define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 +/** LP_TEE_BUS_ERR_CONF_REG register + * Clock gating register + */ +#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0) +/** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ +#define LP_TEE_BUS_ERR_RESP_EN (BIT(0)) +#define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S) +#define LP_TEE_BUS_ERR_RESP_EN_V 0x00000001U +#define LP_TEE_BUS_ERR_RESP_EN_S 0 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + /** LP_TEE_DATE_REG register * Version control register */ #define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) -/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 35725664; +/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 2363416; * Version control register */ #define LP_TEE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h index 6930c62186..8158b54d22 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_struct.h +++ b/components/soc/esp32c5/register/soc/lp_tee_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,11 +17,11 @@ extern "C" { typedef union { struct { /** m0_mode : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M0 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ uint32_t m0_mode:2; /** m0_lock : R/W; bitpos: [2]; default: 0; @@ -34,22 +34,876 @@ typedef union { } lp_tee_m0_mode_ctrl_reg_t; -/** Group: clock gating register */ -/** Type of clock_gate register - * Clock gating register +/** Group: read write control register */ +/** Type of efuse_ctrl register + * efuse read/write control register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + /** read_tee_efuse : R/W; bitpos: [0]; default: 1; + * Configures efuse registers read permission in tee mode. + * 0: can not be read + * 1: can be read */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t read_tee_efuse:1; + /** read_ree0_efuse : R/W; bitpos: [1]; default: 0; + * Configures efuse registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_efuse:1; + /** read_ree1_efuse : R/W; bitpos: [2]; default: 0; + * Configures efuse registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_efuse:1; + /** read_ree2_efuse : R/W; bitpos: [3]; default: 0; + * Configures efuse registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_efuse:1; + /** write_tee_efuse : R/W; bitpos: [4]; default: 1; + * Configures efuse registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_efuse:1; + /** write_ree0_efuse : R/W; bitpos: [5]; default: 0; + * Configures efuse registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_efuse:1; + /** write_ree1_efuse : R/W; bitpos: [6]; default: 0; + * Configures efuse registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_efuse:1; + /** write_ree2_efuse : R/W; bitpos: [7]; default: 0; + * Configures efuse registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_efuse:1; + uint32_t reserved_8:24; }; uint32_t val; -} lp_tee_clock_gate_reg_t; +} lp_tee_efuse_ctrl_reg_t; + +/** Type of pmu_ctrl register + * pmu read/write control register + */ +typedef union { + struct { + /** read_tee_pmu : R/W; bitpos: [0]; default: 1; + * Configures pmu registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pmu:1; + /** read_ree0_pmu : R/W; bitpos: [1]; default: 0; + * Configures pmu registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pmu:1; + /** read_ree1_pmu : R/W; bitpos: [2]; default: 0; + * Configures pmu registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pmu:1; + /** read_ree2_pmu : R/W; bitpos: [3]; default: 0; + * Configures pmu registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pmu:1; + /** write_tee_pmu : R/W; bitpos: [4]; default: 1; + * Configures pmu registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pmu:1; + /** write_ree0_pmu : R/W; bitpos: [5]; default: 0; + * Configures pmu registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pmu:1; + /** write_ree1_pmu : R/W; bitpos: [6]; default: 0; + * Configures pmu registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pmu:1; + /** write_ree2_pmu : R/W; bitpos: [7]; default: 0; + * Configures pmu registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pmu:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_pmu_ctrl_reg_t; + +/** Type of clkrst_ctrl register + * clkrst read/write control register + */ +typedef union { + struct { + /** read_tee_clkrst : R/W; bitpos: [0]; default: 1; + * Configures clkrst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_clkrst:1; + /** read_ree0_clkrst : R/W; bitpos: [1]; default: 0; + * Configures clkrst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_clkrst:1; + /** read_ree1_clkrst : R/W; bitpos: [2]; default: 0; + * Configures clkrst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_clkrst:1; + /** read_ree2_clkrst : R/W; bitpos: [3]; default: 0; + * Configures clkrst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_clkrst:1; + /** write_tee_clkrst : R/W; bitpos: [4]; default: 1; + * Configures clkrst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_clkrst:1; + /** write_ree0_clkrst : R/W; bitpos: [5]; default: 0; + * Configures clkrst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_clkrst:1; + /** write_ree1_clkrst : R/W; bitpos: [6]; default: 0; + * Configures clkrst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_clkrst:1; + /** write_ree2_clkrst : R/W; bitpos: [7]; default: 0; + * Configures clkrst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_clkrst:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_clkrst_ctrl_reg_t; + +/** Type of lp_aon_ctrl_ctrl register + * lp_aon_ctrl read/write control register + */ +typedef union { + struct { + /** read_tee_lp_aon_ctrl : R/W; bitpos: [0]; default: 1; + * Configures lp_aon_ctrl registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_aon_ctrl:1; + /** read_ree0_lp_aon_ctrl : R/W; bitpos: [1]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_aon_ctrl:1; + /** read_ree1_lp_aon_ctrl : R/W; bitpos: [2]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_aon_ctrl:1; + /** read_ree2_lp_aon_ctrl : R/W; bitpos: [3]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_aon_ctrl:1; + /** write_tee_lp_aon_ctrl : R/W; bitpos: [4]; default: 1; + * Configures lp_aon_ctrl registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_aon_ctrl:1; + /** write_ree0_lp_aon_ctrl : R/W; bitpos: [5]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_aon_ctrl:1; + /** write_ree1_lp_aon_ctrl : R/W; bitpos: [6]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_aon_ctrl:1; + /** write_ree2_lp_aon_ctrl : R/W; bitpos: [7]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_aon_ctrl:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_aon_ctrl_ctrl_reg_t; + +/** Type of lp_timer_ctrl register + * lp_timer read/write control register + */ +typedef union { + struct { + /** read_tee_lp_timer : R/W; bitpos: [0]; default: 1; + * Configures lp_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_timer:1; + /** read_ree0_lp_timer : R/W; bitpos: [1]; default: 0; + * Configures lp_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_timer:1; + /** read_ree1_lp_timer : R/W; bitpos: [2]; default: 0; + * Configures lp_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_timer:1; + /** read_ree2_lp_timer : R/W; bitpos: [3]; default: 0; + * Configures lp_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_timer:1; + /** write_tee_lp_timer : R/W; bitpos: [4]; default: 1; + * Configures lp_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_timer:1; + /** write_ree0_lp_timer : R/W; bitpos: [5]; default: 0; + * Configures lp_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_timer:1; + /** write_ree1_lp_timer : R/W; bitpos: [6]; default: 0; + * Configures lp_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_timer:1; + /** write_ree2_lp_timer : R/W; bitpos: [7]; default: 0; + * Configures lp_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_timer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_timer_ctrl_reg_t; + +/** Type of lp_wdt_ctrl register + * lp_wdt read/write control register + */ +typedef union { + struct { + /** read_tee_lp_wdt : R/W; bitpos: [0]; default: 1; + * Configures lp_wdt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_wdt:1; + /** read_ree0_lp_wdt : R/W; bitpos: [1]; default: 0; + * Configures lp_wdt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_wdt:1; + /** read_ree1_lp_wdt : R/W; bitpos: [2]; default: 0; + * Configures lp_wdt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_wdt:1; + /** read_ree2_lp_wdt : R/W; bitpos: [3]; default: 0; + * Configures lp_wdt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_wdt:1; + /** write_tee_lp_wdt : R/W; bitpos: [4]; default: 1; + * Configures lp_wdt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_wdt:1; + /** write_ree0_lp_wdt : R/W; bitpos: [5]; default: 0; + * Configures lp_wdt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_wdt:1; + /** write_ree1_lp_wdt : R/W; bitpos: [6]; default: 0; + * Configures lp_wdt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_wdt:1; + /** write_ree2_lp_wdt : R/W; bitpos: [7]; default: 0; + * Configures lp_wdt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_wdt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_wdt_ctrl_reg_t; + +/** Type of lp_peri_ctrl register + * lp_peri read/write control register + */ +typedef union { + struct { + /** read_tee_lp_peri : R/W; bitpos: [0]; default: 1; + * Configures lp_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_peri:1; + /** read_ree0_lp_peri : R/W; bitpos: [1]; default: 0; + * Configures lp_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_peri:1; + /** read_ree1_lp_peri : R/W; bitpos: [2]; default: 0; + * Configures lp_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_peri:1; + /** read_ree2_lp_peri : R/W; bitpos: [3]; default: 0; + * Configures lp_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_peri:1; + /** write_tee_lp_peri : R/W; bitpos: [4]; default: 1; + * Configures lp_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_peri:1; + /** write_ree0_lp_peri : R/W; bitpos: [5]; default: 0; + * Configures lp_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_peri:1; + /** write_ree1_lp_peri : R/W; bitpos: [6]; default: 0; + * Configures lp_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_peri:1; + /** write_ree2_lp_peri : R/W; bitpos: [7]; default: 0; + * Configures lp_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_peri:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_peri_ctrl_reg_t; + +/** Type of lp_ana_peri_ctrl register + * lp_ana_peri read/write control register + */ +typedef union { + struct { + /** read_tee_lp_ana_peri : R/W; bitpos: [0]; default: 1; + * Configures lp_ana_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_ana_peri:1; + /** read_ree0_lp_ana_peri : R/W; bitpos: [1]; default: 0; + * Configures lp_ana_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_ana_peri:1; + /** read_ree1_lp_ana_peri : R/W; bitpos: [2]; default: 0; + * Configures lp_ana_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_ana_peri:1; + /** read_ree2_lp_ana_peri : R/W; bitpos: [3]; default: 0; + * Configures lp_ana_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_ana_peri:1; + /** write_tee_lp_ana_peri : R/W; bitpos: [4]; default: 1; + * Configures lp_ana_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_ana_peri:1; + /** write_ree0_lp_ana_peri : R/W; bitpos: [5]; default: 0; + * Configures lp_ana_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_ana_peri:1; + /** write_ree1_lp_ana_peri : R/W; bitpos: [6]; default: 0; + * Configures lp_ana_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_ana_peri:1; + /** write_ree2_lp_ana_peri : R/W; bitpos: [7]; default: 0; + * Configures lp_ana_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_ana_peri:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_ana_peri_ctrl_reg_t; + +/** Type of lp_io_ctrl register + * lp_io read/write control register + */ +typedef union { + struct { + /** read_tee_lp_io : R/W; bitpos: [0]; default: 1; + * Configures lp_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_io:1; + /** read_ree0_lp_io : R/W; bitpos: [1]; default: 0; + * Configures lp_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_io:1; + /** read_ree1_lp_io : R/W; bitpos: [2]; default: 0; + * Configures lp_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_io:1; + /** read_ree2_lp_io : R/W; bitpos: [3]; default: 0; + * Configures lp_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_io:1; + /** write_tee_lp_io : R/W; bitpos: [4]; default: 1; + * Configures lp_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_io:1; + /** write_ree0_lp_io : R/W; bitpos: [5]; default: 0; + * Configures lp_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_io:1; + /** write_ree1_lp_io : R/W; bitpos: [6]; default: 0; + * Configures lp_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_io:1; + /** write_ree2_lp_io : R/W; bitpos: [7]; default: 0; + * Configures lp_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_io:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_io_ctrl_reg_t; + +/** Type of lp_tee_ctrl register + * lp_tee read/write control register + */ +typedef union { + struct { + /** read_tee_lp_tee : R/W; bitpos: [0]; default: 1; + * Configures lp_tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_tee:1; + /** read_ree0_lp_tee : HRO; bitpos: [1]; default: 0; + * Configures lp_tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_tee:1; + /** read_ree1_lp_tee : HRO; bitpos: [2]; default: 0; + * Configures lp_tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_tee:1; + /** read_ree2_lp_tee : HRO; bitpos: [3]; default: 0; + * Configures lp_tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_tee:1; + /** write_tee_lp_tee : R/W; bitpos: [4]; default: 1; + * Configures lp_tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_tee:1; + /** write_ree0_lp_tee : HRO; bitpos: [5]; default: 0; + * Configures lp_tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_tee:1; + /** write_ree1_lp_tee : HRO; bitpos: [6]; default: 0; + * Configures lp_tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_tee:1; + /** write_ree2_lp_tee : HRO; bitpos: [7]; default: 0; + * Configures lp_tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_tee:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_tee_ctrl_reg_t; + +/** Type of uart_ctrl register + * uart read/write control register + */ +typedef union { + struct { + /** read_tee_uart : R/W; bitpos: [0]; default: 1; + * Configures uart registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart:1; + /** read_ree0_uart : R/W; bitpos: [1]; default: 0; + * Configures uart registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart:1; + /** read_ree1_uart : R/W; bitpos: [2]; default: 0; + * Configures uart registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart:1; + /** read_ree2_uart : R/W; bitpos: [3]; default: 0; + * Configures uart registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart:1; + /** write_tee_uart : R/W; bitpos: [4]; default: 1; + * Configures uart registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart:1; + /** write_ree0_uart : R/W; bitpos: [5]; default: 0; + * Configures uart registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart:1; + /** write_ree1_uart : R/W; bitpos: [6]; default: 0; + * Configures uart registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart:1; + /** write_ree2_uart : R/W; bitpos: [7]; default: 0; + * Configures uart registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_uart_ctrl_reg_t; + +/** Type of i2c_ext_ctrl register + * i2c_ext read/write control register + */ +typedef union { + struct { + /** read_tee_i2c_ext : R/W; bitpos: [0]; default: 1; + * Configures i2c_ext registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c_ext:1; + /** read_ree0_i2c_ext : R/W; bitpos: [1]; default: 0; + * Configures i2c_ext registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c_ext:1; + /** read_ree1_i2c_ext : R/W; bitpos: [2]; default: 0; + * Configures i2c_ext registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c_ext:1; + /** read_ree2_i2c_ext : R/W; bitpos: [3]; default: 0; + * Configures i2c_ext registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c_ext:1; + /** write_tee_i2c_ext : R/W; bitpos: [4]; default: 1; + * Configures i2c_ext registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c_ext:1; + /** write_ree0_i2c_ext : R/W; bitpos: [5]; default: 0; + * Configures i2c_ext registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c_ext:1; + /** write_ree1_i2c_ext : R/W; bitpos: [6]; default: 0; + * Configures i2c_ext registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c_ext:1; + /** write_ree2_i2c_ext : R/W; bitpos: [7]; default: 0; + * Configures i2c_ext registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c_ext:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_i2c_ext_ctrl_reg_t; + +/** Type of i2c_ana_mst_ctrl register + * i2c_ana_mst read/write control register + */ +typedef union { + struct { + /** read_tee_i2c_ana_mst : R/W; bitpos: [0]; default: 1; + * Configures i2c_ana_mst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c_ana_mst:1; + /** read_ree0_i2c_ana_mst : R/W; bitpos: [1]; default: 0; + * Configures i2c_ana_mst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c_ana_mst:1; + /** read_ree1_i2c_ana_mst : R/W; bitpos: [2]; default: 0; + * Configures i2c_ana_mst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c_ana_mst:1; + /** read_ree2_i2c_ana_mst : R/W; bitpos: [3]; default: 0; + * Configures i2c_ana_mst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c_ana_mst:1; + /** write_tee_i2c_ana_mst : R/W; bitpos: [4]; default: 1; + * Configures i2c_ana_mst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c_ana_mst:1; + /** write_ree0_i2c_ana_mst : R/W; bitpos: [5]; default: 0; + * Configures i2c_ana_mst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c_ana_mst:1; + /** write_ree1_i2c_ana_mst : R/W; bitpos: [6]; default: 0; + * Configures i2c_ana_mst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c_ana_mst:1; + /** write_ree2_i2c_ana_mst : R/W; bitpos: [7]; default: 0; + * Configures i2c_ana_mst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c_ana_mst:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_i2c_ana_mst_ctrl_reg_t; + +/** Type of huk_ctrl register + * huk read/write control register + */ +typedef union { + struct { + /** read_tee_huk : R/W; bitpos: [0]; default: 1; + * Configures huk registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_huk:1; + /** read_ree0_huk : R/W; bitpos: [1]; default: 0; + * Configures huk registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_huk:1; + /** read_ree1_huk : R/W; bitpos: [2]; default: 0; + * Configures huk registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_huk:1; + /** read_ree2_huk : R/W; bitpos: [3]; default: 0; + * Configures huk registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_huk:1; + /** write_tee_huk : R/W; bitpos: [4]; default: 1; + * Configures huk registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_huk:1; + /** write_ree0_huk : R/W; bitpos: [5]; default: 0; + * Configures huk registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_huk:1; + /** write_ree1_huk : R/W; bitpos: [6]; default: 0; + * Configures huk registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_huk:1; + /** write_ree2_huk : R/W; bitpos: [7]; default: 0; + * Configures huk registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_huk:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_huk_ctrl_reg_t; + +/** Type of lp_apm_ctrl register + * lp_apm read/write control register + */ +typedef union { + struct { + /** read_tee_lp_apm : R/W; bitpos: [0]; default: 1; + * Configures lp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_lp_apm:1; + /** read_ree0_lp_apm : HRO; bitpos: [1]; default: 0; + * Configures lp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_lp_apm:1; + /** read_ree1_lp_apm : HRO; bitpos: [2]; default: 0; + * Configures lp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_lp_apm:1; + /** read_ree2_lp_apm : HRO; bitpos: [3]; default: 0; + * Configures lp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_lp_apm:1; + /** write_tee_lp_apm : R/W; bitpos: [4]; default: 1; + * Configures lp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_lp_apm:1; + /** write_ree0_lp_apm : HRO; bitpos: [5]; default: 0; + * Configures lp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_lp_apm:1; + /** write_ree1_lp_apm : HRO; bitpos: [6]; default: 0; + * Configures lp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_lp_apm:1; + /** write_ree2_lp_apm : HRO; bitpos: [7]; default: 0; + * Configures lp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_lp_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_apm_ctrl_reg_t; /** Group: Force access to hpmem configuration register */ @@ -60,9 +914,9 @@ typedef union { struct { /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; * Configures whether to allow LP CPU to force access to HP_MEM regardless of - * permission management.\\ - * 0: disable force access HP_MEM \\ - * 1: enable force access HP_MEM \\ + * permission management. + * 0: disable force access HP_MEM + * 1: enable force access HP_MEM */ uint32_t force_acc_hpmem_en:1; uint32_t reserved_1:31; @@ -71,13 +925,49 @@ typedef union { } lp_tee_force_acc_hp_reg_t; +/** Group: config register */ +/** Type of bus_err_conf register + * Clock gating register + */ +typedef union { + struct { + /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ + uint32_t bus_err_resp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_bus_err_conf_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + /** Group: Version control register */ /** Type of date register * Version control register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35725664; + /** date : R/W; bitpos: [27:0]; default: 2363416; * Version control register */ uint32_t date:28; @@ -89,10 +979,30 @@ typedef union { typedef struct { volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; - volatile lp_tee_clock_gate_reg_t clock_gate; - uint32_t reserved_008[34]; + volatile lp_tee_efuse_ctrl_reg_t efuse_ctrl; + volatile lp_tee_pmu_ctrl_reg_t pmu_ctrl; + volatile lp_tee_clkrst_ctrl_reg_t clkrst_ctrl; + volatile lp_tee_lp_aon_ctrl_ctrl_reg_t lp_aon_ctrl_ctrl; + volatile lp_tee_lp_timer_ctrl_reg_t lp_timer_ctrl; + volatile lp_tee_lp_wdt_ctrl_reg_t lp_wdt_ctrl; + volatile lp_tee_lp_peri_ctrl_reg_t lp_peri_ctrl; + volatile lp_tee_lp_ana_peri_ctrl_reg_t lp_ana_peri_ctrl; + uint32_t reserved_024[2]; + volatile lp_tee_lp_io_ctrl_reg_t lp_io_ctrl; + uint32_t reserved_030; + volatile lp_tee_lp_tee_ctrl_reg_t lp_tee_ctrl; + volatile lp_tee_uart_ctrl_reg_t uart_ctrl; + uint32_t reserved_03c; + volatile lp_tee_i2c_ext_ctrl_reg_t i2c_ext_ctrl; + volatile lp_tee_i2c_ana_mst_ctrl_reg_t i2c_ana_mst_ctrl; + volatile lp_tee_huk_ctrl_reg_t huk_ctrl; + volatile lp_tee_lp_apm_ctrl_reg_t lp_apm_ctrl; + uint32_t reserved_050[16]; volatile lp_tee_force_acc_hp_reg_t force_acc_hp; - uint32_t reserved_094[26]; + uint32_t reserved_094[23]; + volatile lp_tee_bus_err_conf_reg_t bus_err_conf; + uint32_t reserved_0f4; + volatile lp_tee_clock_gate_reg_t clock_gate; volatile lp_tee_date_reg_t date; } lp_tee_dev_t; diff --git a/components/soc/esp32c5/register/soc/lp_wdt_reg.h b/components/soc/esp32c5/register/soc/lp_wdt_reg.h index 8ac8bb5967..d78ce0deda 100644 --- a/components/soc/esp32c5/register/soc/lp_wdt_reg.h +++ b/components/soc/esp32c5/register/soc/lp_wdt_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ extern "C" { #define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) /** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU #define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S) @@ -24,21 +25,26 @@ extern "C" { #define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0 /** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_WDT_WDT_CHIP_RESET_EN (BIT(8)) #define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S) #define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U #define LP_WDT_WDT_CHIP_RESET_EN_S 8 /** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; - * Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable - * \\1:Disable + * Configure whether or not pause RWDT when chip is in sleep mode. + * 0:Enable + * 1:Disable */ #define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) #define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) #define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U #define LP_WDT_WDT_PAUSE_IN_SLP_S 9 /** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; - * Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable + * Configure whether or not to enable RWDT to reset CPU. + * 0:Disable + * 1:Enable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) #define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) @@ -46,67 +52,89 @@ extern "C" { #define LP_WDT_WDT_APPCPU_RESET_EN_S 10 /** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) #define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) #define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U #define LP_WDT_WDT_PROCPU_RESET_EN_S 11 /** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; - * Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable - * \\1:Enable + * Configure whether or not enable RWDT when chip is in SPI boot mode. + * 0:Disable + * 1:Enable */ #define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) #define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) #define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U #define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 /** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; - * Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + * Configure the HP core reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK */ #define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U #define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) #define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U #define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 /** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; - * Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + * Configure the HP CPU reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK */ #define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U #define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) #define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U #define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 /** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; - * Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage3. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ #define LP_WDT_WDT_STG3 0x00000007U #define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) #define LP_WDT_WDT_STG3_V 0x00000007U #define LP_WDT_WDT_STG3_S 19 /** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; - * Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage2. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ #define LP_WDT_WDT_STG2 0x00000007U #define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) #define LP_WDT_WDT_STG2_V 0x00000007U #define LP_WDT_WDT_STG2_S 22 /** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; - * Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage1. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ #define LP_WDT_WDT_STG1 0x00000007U #define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) #define LP_WDT_WDT_STG1_V 0x00000007U #define LP_WDT_WDT_STG1_S 25 /** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; - * Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage0. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ #define LP_WDT_WDT_STG0 0x00000007U #define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) #define LP_WDT_WDT_STG0_V 0x00000007U #define LP_WDT_WDT_STG0_S 28 /** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; - * Configure whether or not to enable RWDT.\\0:Disable \\1:Enable + * Configure whether or not to enable RWDT. + * 0:Disable + * 1:Enable */ #define LP_WDT_WDT_EN (BIT(31)) #define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) @@ -118,7 +146,8 @@ extern "C" { */ #define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) /** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; - * Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage0. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ #define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU #define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) @@ -130,7 +159,8 @@ extern "C" { */ #define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) /** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; - * Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage1. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ #define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU #define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) @@ -142,7 +172,8 @@ extern "C" { */ #define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) /** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage2. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ #define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU #define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) @@ -154,7 +185,8 @@ extern "C" { */ #define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) /** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage3. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ #define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU #define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) @@ -166,7 +198,9 @@ extern "C" { */ #define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) /** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; - * Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT + * Configure this bit to feed the RWDT. + * 0: Invalid + * 1: Feed RWDT */ #define LP_WDT_RTC_WDT_FEED (BIT(31)) #define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) @@ -178,9 +212,10 @@ extern "C" { */ #define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) /** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; - * Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1: - * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT - * configuration register which can`t be modified by software. + * Configure this field to lock or unlock RWDT`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. */ #define LP_WDT_WDT_WKEY 0xFFFFFFFFU #define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) @@ -192,44 +227,53 @@ extern "C" { */ #define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) /** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; - * Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes + * Represents the SWD whether has generated the reset signal. + * 0 :No + * 1: Yes */ #define LP_WDT_SWD_RESET_FLAG (BIT(0)) #define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) #define LP_WDT_SWD_RESET_FLAG_V 0x00000001U #define LP_WDT_SWD_RESET_FLAG_S 0 /** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; - * Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable - * \\1: Enable + * Configure this bit to enable to feed SWD automatically by hardware. + * 0: Disable + * 1: Enable */ #define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) #define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) #define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U #define LP_WDT_SWD_AUTO_FEED_EN_S 18 /** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; - * Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag + * Configure this bit to clear SWD reset flag. + * 0:Invalid + * 1: Clear the reset flag */ #define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) #define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) #define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U #define LP_WDT_SWD_RST_FLAG_CLR_S 19 /** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; - * Configure the SWD signal length that output to analog circuit. \\ Measurement unit: - * LP\_DYN\_FAST\_CLK + * Configure the SWD signal length that output to analog circuit. + * Measurement unit: LP\_DYN\_FAST\_CLK */ #define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU #define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) #define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU #define LP_WDT_SWD_SIGNAL_WIDTH_S 20 /** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD + * Configure this bit to disable the SWD. + * 0: Enable the SWD + * 1: Disable the SWD */ #define LP_WDT_SWD_DISABLE (BIT(30)) #define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) #define LP_WDT_SWD_DISABLE_V 0x00000001U #define LP_WDT_SWD_DISABLE_S 30 /** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; - * Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD + * Configure this bit to feed the SWD. + * 0: Invalid + * 1: Feed SWD */ #define LP_WDT_SWD_FEED (BIT(31)) #define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) @@ -241,9 +285,10 @@ extern "C" { */ #define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) /** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; - * Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1: - * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT - * configuration register which can`t be modified by software. + * Configure this field to lock or unlock SWD`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. */ #define LP_WDT_SWD_WKEY 0xFFFFFFFFU #define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) @@ -255,14 +300,18 @@ extern "C" { */ #define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) /** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes + * Represents the SWD whether or not generates timeout interrupt. + * 0:No + * 1: Yes */ #define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) #define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) #define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U #define LP_WDT_SUPER_WDT_INT_RAW_S 30 /** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes + * Represents the RWDT whether or not generates timeout interrupt. + * 0:No + * 1: Yes */ #define LP_WDT_LP_WDT_INT_RAW (BIT(31)) #define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) @@ -274,16 +323,18 @@ extern "C" { */ #define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) /** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; - * Represents the SWD whether or not has generated and sent timeout interrupt to - * CPU.\\ 0:No \\1: Yes + * Represents the SWD whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes */ #define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) #define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) #define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U #define LP_WDT_SUPER_WDT_INT_ST_S 30 /** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; - * Represents the RWDT whether or not has generated and sent timeout interrupt to - * CPU.\\ 0:No \\1: Yes + * Represents the RWDT whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes */ #define LP_WDT_LP_WDT_INT_ST (BIT(31)) #define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) @@ -295,16 +346,18 @@ extern "C" { */ #define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) /** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; - * Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable - * \\1:Enable + * Configure whether or not to enable the SWD to send timeout interrupt. + * 0:Disable + * 1:Enable */ #define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) #define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) #define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U #define LP_WDT_SUPER_WDT_INT_ENA_S 30 /** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; - * Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable - * \\1:Enable + * Configure whether or not to enable the RWDT to send timeout interrupt. + * 0:Disable + * 1:Enable */ #define LP_WDT_LP_WDT_INT_ENA (BIT(31)) #define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) @@ -316,16 +369,18 @@ extern "C" { */ #define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) /** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; - * Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0: - * No\\1: Yes + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU. + * 0: No + * 1: Yes */ #define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) #define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) #define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U #define LP_WDT_SUPER_WDT_INT_CLR_S 30 /** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; - * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0: - * No\\1: Yes + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU. + * 0: No + * 1: Yes */ #define LP_WDT_LP_WDT_INT_CLR (BIT(31)) #define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) @@ -345,6 +400,7 @@ extern "C" { #define LP_WDT_LP_WDT_DATE_S 0 /** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; * Reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_WDT_CLK_EN (BIT(31)) #define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_wdt_struct.h b/components/soc/esp32c5/register/soc/lp_wdt_struct.h index 34c7041573..c2c5446266 100644 --- a/components/soc/esp32c5/register/soc/lp_wdt_struct.h +++ b/components/soc/esp32c5/register/soc/lp_wdt_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,60 +18,88 @@ typedef union { struct { /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wdt_chip_reset_width:8; /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wdt_chip_reset_en:1; /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; - * Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable - * \\1:Disable + * Configure whether or not pause RWDT when chip is in sleep mode. + * 0:Enable + * 1:Disable */ uint32_t wdt_pause_in_slp:1; /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; - * Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable + * Configure whether or not to enable RWDT to reset CPU. + * 0:Disable + * 1:Enable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wdt_appcpu_reset_en:1; /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wdt_procpu_reset_en:1; /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; - * Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable - * \\1:Enable + * Configure whether or not enable RWDT when chip is in SPI boot mode. + * 0:Disable + * 1:Enable */ uint32_t wdt_flashboot_mod_en:1; /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; - * Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + * Configure the HP core reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK */ uint32_t wdt_sys_reset_length:3; /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; - * Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + * Configure the HP CPU reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK */ uint32_t wdt_cpu_reset_length:3; /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; - * Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage3. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ uint32_t wdt_stg3:3; /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; - * Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage2. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ uint32_t wdt_stg2:3; /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; - * Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage1. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ uint32_t wdt_stg1:3; /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; - * Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2 - * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + * Configure the timeout action of stage0. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. */ uint32_t wdt_stg0:3; /** wdt_en : R/W; bitpos: [31]; default: 0; - * Configure whether or not to enable RWDT.\\0:Disable \\1:Enable + * Configure whether or not to enable RWDT. + * 0:Disable + * 1:Enable */ uint32_t wdt_en:1; }; @@ -84,7 +112,8 @@ typedef union { typedef union { struct { /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; - * Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage0. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ uint32_t wdt_stg0_hold:32; }; @@ -97,7 +126,8 @@ typedef union { typedef union { struct { /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; - * Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage1. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ uint32_t wdt_stg1_hold:32; }; @@ -110,7 +140,8 @@ typedef union { typedef union { struct { /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; - * Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage2. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ uint32_t wdt_stg2_hold:32; }; @@ -123,7 +154,8 @@ typedef union { typedef union { struct { /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; - * Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK + * Configure the timeout time for stage3. + * Measurement unit: LP\_DYN\_SLOW\_CLK */ uint32_t wdt_stg3_hold:32; }; @@ -137,7 +169,9 @@ typedef union { struct { uint32_t reserved_0:31; /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; - * Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT + * Configure this bit to feed the RWDT. + * 0: Invalid + * 1: Feed RWDT */ uint32_t rtc_wdt_feed:1; }; @@ -150,9 +184,10 @@ typedef union { typedef union { struct { /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; - * Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1: - * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT - * configuration register which can`t be modified by software. + * Configure this field to lock or unlock RWDT`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. */ uint32_t wdt_wkey:32; }; @@ -165,30 +200,39 @@ typedef union { typedef union { struct { /** swd_reset_flag : RO; bitpos: [0]; default: 0; - * Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes + * Represents the SWD whether has generated the reset signal. + * 0 :No + * 1: Yes */ uint32_t swd_reset_flag:1; uint32_t reserved_1:17; /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; - * Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable - * \\1: Enable + * Configure this bit to enable to feed SWD automatically by hardware. + * 0: Disable + * 1: Enable */ uint32_t swd_auto_feed_en:1; /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; - * Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag + * Configure this bit to clear SWD reset flag. + * 0:Invalid + * 1: Clear the reset flag */ uint32_t swd_rst_flag_clr:1; /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; - * Configure the SWD signal length that output to analog circuit. \\ Measurement unit: - * LP\_DYN\_FAST\_CLK + * Configure the SWD signal length that output to analog circuit. + * Measurement unit: LP\_DYN\_FAST\_CLK */ uint32_t swd_signal_width:10; /** swd_disable : R/W; bitpos: [30]; default: 0; - * Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD + * Configure this bit to disable the SWD. + * 0: Enable the SWD + * 1: Disable the SWD */ uint32_t swd_disable:1; /** swd_feed : WT; bitpos: [31]; default: 0; - * Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD + * Configure this bit to feed the SWD. + * 0: Invalid + * 1: Feed SWD */ uint32_t swd_feed:1; }; @@ -201,9 +245,10 @@ typedef union { typedef union { struct { /** swd_wkey : R/W; bitpos: [31:0]; default: 0; - * Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1: - * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT - * configuration register which can`t be modified by software. + * Configure this field to lock or unlock SWD`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. */ uint32_t swd_wkey:32; }; @@ -217,11 +262,15 @@ typedef union { struct { uint32_t reserved_0:30; /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes + * Represents the SWD whether or not generates timeout interrupt. + * 0:No + * 1: Yes */ uint32_t super_wdt_int_raw:1; /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes + * Represents the RWDT whether or not generates timeout interrupt. + * 0:No + * 1: Yes */ uint32_t lp_wdt_int_raw:1; }; @@ -235,13 +284,15 @@ typedef union { struct { uint32_t reserved_0:30; /** super_wdt_int_st : RO; bitpos: [30]; default: 0; - * Represents the SWD whether or not has generated and sent timeout interrupt to - * CPU.\\ 0:No \\1: Yes + * Represents the SWD whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes */ uint32_t super_wdt_int_st:1; /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; - * Represents the RWDT whether or not has generated and sent timeout interrupt to - * CPU.\\ 0:No \\1: Yes + * Represents the RWDT whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes */ uint32_t lp_wdt_int_st:1; }; @@ -255,13 +306,15 @@ typedef union { struct { uint32_t reserved_0:30; /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; - * Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable - * \\1:Enable + * Configure whether or not to enable the SWD to send timeout interrupt. + * 0:Disable + * 1:Enable */ uint32_t super_wdt_int_ena:1; /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; - * Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable - * \\1:Enable + * Configure whether or not to enable the RWDT to send timeout interrupt. + * 0:Disable + * 1:Enable */ uint32_t lp_wdt_int_ena:1; }; @@ -275,13 +328,15 @@ typedef union { struct { uint32_t reserved_0:30; /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; - * Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0: - * No\\1: Yes + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU. + * 0: No + * 1: Yes */ uint32_t super_wdt_int_clr:1; /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; - * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0: - * No\\1: Yes + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU. + * 0: No + * 1: Yes */ uint32_t lp_wdt_int_clr:1; }; @@ -299,6 +354,7 @@ typedef union { uint32_t lp_wdt_date:31; /** clk_en : R/W; bitpos: [31]; default: 0; * Reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t clk_en:1; }; diff --git a/components/soc/esp32c5/register/soc/mem_monitor_reg.h b/components/soc/esp32c5/register/soc/mem_monitor_reg.h index 71a6e1890a..799fd33447 100644 --- a/components/soc/esp32c5/register/soc/mem_monitor_reg.h +++ b/components/soc/esp32c5/register/soc/mem_monitor_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,26 +16,26 @@ extern "C" { */ #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) /** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0; - * Configures monitoring modes.bit[0]: Configures write monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[1]: Configures word monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[2]: Configures halfword monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[3]: Configures byte monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ + * Configures monitoring modes.bit[0]: Configures write monitoring. + * 0: Disable + * 1: Enable + * bit[1]: Configures word monitoring. + * 0: Disable + * 1: Enable + * bit[2]: Configures halfword monitoring. + * 0: Disable + * 1: Enable + * bit[3]: Configures byte monitoring. + * 0: Disable + * 1: Enable */ #define MEM_MONITOR_LOG_MODE 0x0000000FU #define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) #define MEM_MONITOR_LOG_MODE_V 0x0000000FU #define MEM_MONITOR_LOG_MODE_S 0 /** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1; - * Configures the writing mode for recorded data.1: Loop mode\\ - * 0: Non-loop mode\\ + * Configures the writing mode for recorded data.1: Loop mode + * 0: Non-loop mode */ #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4)) #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) @@ -43,9 +43,9 @@ extern "C" { #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4 /** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0; * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to - * enable HP CPU bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * enable HP CPU bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU @@ -54,9 +54,9 @@ extern "C" { #define MEM_MONITOR_LOG_CORE_ENA_S 8 /** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0; * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether - * to enable DMA_0 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_0 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU @@ -65,9 +65,9 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_0_ENA_S 16 /** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0; * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether - * to enable DMA_1 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_1 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU @@ -81,9 +81,9 @@ extern "C" { #define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) /** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0; * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether - * to enable DMA_2 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_2 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU @@ -92,9 +92,9 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_2_ENA_S 0 /** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0; * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether - * to enable DMA_3 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_3 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU @@ -121,21 +121,21 @@ extern "C" { /** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: * Configures whether to mask the least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[1]: Configures whether to mask the second least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[2]: Configures whether to mask the second most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[3]: Configures whether to mask the most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask */ #define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU #define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) @@ -174,9 +174,9 @@ extern "C" { /** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the HP CPU bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the HP CPU bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S) @@ -184,8 +184,8 @@ extern "C" { #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0 /** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0; * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ - * 0: Not update\\ + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update + * 0: Not update */ #define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31)) #define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S) @@ -200,9 +200,9 @@ extern "C" { /** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_0 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_0 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S) @@ -211,9 +211,9 @@ extern "C" { /** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_1 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_1 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S) @@ -222,9 +222,9 @@ extern "C" { /** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_2 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_2 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S) @@ -233,9 +233,9 @@ extern "C" { /** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_3 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_3 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S) @@ -285,8 +285,8 @@ extern "C" { #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c) /** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to - * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ - * 0: Not update (default) \\ + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update + * 0: Not update (default) */ #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) @@ -298,17 +298,16 @@ extern "C" { */ #define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30) /** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; - * Represents whether data overflows the storage space.0: Not Overflow\\ - * 1: Overflow\\ + * Represents whether data overflows the storage space.0: Not Overflow + * 1: Overflow */ #define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) #define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) #define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U #define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 /** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; - * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not - * clear\\ - * 1: Clear\\ + * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear + * 1: Clear */ #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) @@ -320,8 +319,8 @@ extern "C" { */ #define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34) /** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the register clock gating.0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating.0: Disable + * 1: Enable */ #define MEM_MONITOR_CLK_EN (BIT(0)) #define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/mem_monitor_struct.h b/components/soc/esp32c5/register/soc/mem_monitor_struct.h index aa2a45052d..a3cb17ed04 100644 --- a/components/soc/esp32c5/register/soc/mem_monitor_struct.h +++ b/components/soc/esp32c5/register/soc/mem_monitor_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,47 +17,47 @@ extern "C" { typedef union { struct { /** log_mode : R/W; bitpos: [3:0]; default: 0; - * Configures monitoring modes.bit[0]: Configures write monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[1]: Configures word monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[2]: Configures halfword monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[3]: Configures byte monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ + * Configures monitoring modes.bit[0]: Configures write monitoring. + * 0: Disable + * 1: Enable + * bit[1]: Configures word monitoring. + * 0: Disable + * 1: Enable + * bit[2]: Configures halfword monitoring. + * 0: Disable + * 1: Enable + * bit[3]: Configures byte monitoring. + * 0: Disable + * 1: Enable */ uint32_t log_mode:4; /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1; - * Configures the writing mode for recorded data.1: Loop mode\\ - * 0: Non-loop mode\\ + * Configures the writing mode for recorded data.1: Loop mode + * 0: Non-loop mode */ uint32_t log_mem_loop_enable:1; uint32_t reserved_5:3; /** log_core_ena : R/W; bitpos: [15:8]; default: 0; * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to - * enable HP CPU bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * enable HP CPU bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ uint32_t log_core_ena:8; /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0; * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether - * to enable DMA_0 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_0 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ uint32_t log_dma_0_ena:8; /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0; * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether - * to enable DMA_1 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_1 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ uint32_t log_dma_1_ena:8; @@ -72,17 +72,17 @@ typedef union { struct { /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0; * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether - * to enable DMA_2 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_2 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ uint32_t log_dma_2_ena:8; /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0; * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether - * to enable DMA_3 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ + * to enable DMA_3 bus access logging. + * 0: Disable + * 1: Enable * Bit[7:1]: Reserved */ uint32_t log_dma_3_ena:8; @@ -112,21 +112,21 @@ typedef union { /** log_data_mask : R/W; bitpos: [3:0]; default: 0; * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: * Configures whether to mask the least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[1]: Configures whether to mask the second least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[2]: Configures whether to mask the second most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[3]: Configures whether to mask the most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask */ uint32_t log_data_mask:4; uint32_t reserved_4:28; @@ -169,16 +169,16 @@ typedef union { /** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the HP CPU bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the HP CPU bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ uint32_t log_mon_addr_core_update:8; uint32_t reserved_8:23; /** log_mon_addr_all_update : WT; bitpos: [31]; default: 0; * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ - * 0: Not update\\ + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update + * 0: Not update */ uint32_t log_mon_addr_all_update:1; }; @@ -194,33 +194,33 @@ typedef union { /** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_0 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_0 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ uint32_t log_mon_addr_dma_0_update:8; /** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_1 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_1 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ uint32_t log_mon_addr_dma_1_update:8; /** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_2 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_2 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ uint32_t log_mon_addr_dma_2_update:8; /** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0; * Configures the monitored address space of the certain master. Bit[0]: Configures * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_3 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * monitored address space of the DMA_3 bus.1: Update + * 0: Not update + * Bit[7:1]: Reserved */ uint32_t log_mon_addr_dma_3_update:8; }; @@ -274,8 +274,8 @@ typedef union { struct { /** log_mem_addr_update : WT; bitpos: [0]; default: 0; * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to - * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ - * 0: Not update (default) \\ + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update + * 0: Not update (default) */ uint32_t log_mem_addr_update:1; uint32_t reserved_1:31; @@ -289,14 +289,13 @@ typedef union { typedef union { struct { /** log_mem_full_flag : RO; bitpos: [0]; default: 0; - * Represents whether data overflows the storage space.0: Not Overflow\\ - * 1: Overflow\\ + * Represents whether data overflows the storage space.0: Not Overflow + * 1: Overflow */ uint32_t log_mem_full_flag:1; /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; - * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not - * clear\\ - * 1: Clear\\ + * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear + * 1: Clear */ uint32_t clr_log_mem_full_flag:1; uint32_t reserved_2:30; @@ -312,8 +311,8 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the register clock gating.0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating.0: Disable + * 1: Enable */ uint32_t clk_en:1; uint32_t reserved_1:31; diff --git a/components/soc/esp32c5/register/soc/parl_io_reg.h b/components/soc/esp32c5/register/soc/parl_io_reg.h index 1cdf9089ae..eafecf99ee 100644 --- a/components/soc/esp32c5/register/soc/parl_io_reg.h +++ b/components/soc/esp32c5/register/soc/parl_io_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -447,6 +447,25 @@ extern "C" { #define PARL_IO_TX_CLK_O_INV_V 0x00000001U #define PARL_IO_TX_CLK_O_INV_S 31 +/** PARL_IO_TX_CS_CFG_REG register + * Parallel IO tx_cs_o generate configuration + */ +#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c) +/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0; + * configure the delay between data tx end and tx_cs_o posedge + */ +#define PARL_IO_TX_CS_STOP_DELAY 0x0000FFFFU +#define PARL_IO_TX_CS_STOP_DELAY_M (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S) +#define PARL_IO_TX_CS_STOP_DELAY_V 0x0000FFFFU +#define PARL_IO_TX_CS_STOP_DELAY_S 0 +/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0; + * configure the delay between tx_cs_o negedge and data tx start + */ +#define PARL_IO_TX_CS_START_DELAY 0x0000FFFFU +#define PARL_IO_TX_CS_START_DELAY_M (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S) +#define PARL_IO_TX_CS_START_DELAY_V 0x0000FFFFU +#define PARL_IO_TX_CS_START_DELAY_S 16 + /** PARL_IO_CLK_REG register * Parallel IO clk configuration register */ @@ -463,7 +482,7 @@ extern "C" { * Version register. */ #define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) -/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920; +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160; * Version of this register file */ #define PARL_IO_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/parl_io_struct.h b/components/soc/esp32c5/register/soc/parl_io_struct.h index 786e68043a..e58956022c 100644 --- a/components/soc/esp32c5/register/soc/parl_io_struct.h +++ b/components/soc/esp32c5/register/soc/parl_io_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -436,6 +436,25 @@ typedef union { } parl_io_tx_clk_cfg_reg_t; +/** Group: PARL_TX_CS Configuration */ +/** Type of tx_cs_cfg register + * Parallel IO tx_cs_o generate configuration + */ +typedef union { + struct { + /** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0; + * configure the delay between data tx end and tx_cs_o posedge + */ + uint32_t tx_cs_stop_delay:16; + /** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0; + * configure the delay between tx_cs_o negedge and data tx start + */ + uint32_t tx_cs_start_delay:16; + }; + uint32_t val; +} parl_io_tx_cs_cfg_reg_t; + + /** Group: PARL_IO Clock Configuration */ /** Type of clk register * Parallel IO clk configuration register @@ -458,7 +477,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35725920; + /** date : R/W; bitpos: [27:0]; default: 37786160; * Version of this register file */ uint32_t date:28; @@ -488,7 +507,8 @@ typedef struct parl_io_dev_t { volatile parl_io_tx_st0_reg_t tx_st0; volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg; volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg; - uint32_t reserved_04c[53]; + volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg; + uint32_t reserved_050[52]; volatile parl_io_clk_reg_t clk; uint32_t reserved_124[182]; volatile parl_io_version_reg_t version; diff --git a/components/soc/esp32c5/register/soc/pcnt_reg_eco2.h b/components/soc/esp32c5/register/soc/pcnt_reg_eco2.h new file mode 100644 index 0000000000..e319c62392 --- /dev/null +++ b/components/soc/esp32c5/register/soc/pcnt_reg_eco2.h @@ -0,0 +1,1446 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * Configures the maximum threshold for the filter. Any pulses with width less than + * this will be ignored when the filter is enabled. + * Measurement unit: APB_CLK cycles. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * Configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * Configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * Configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * Configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the thr_h_lim value for unit 0. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the thr_l_lim value for unit 0. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U0_CONF3_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U0_CONF3_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_CNT_H_STEP_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 0. + */ +#define PCNT_CNT_H_STEP_U0 0x0000FFFFU +#define PCNT_CNT_H_STEP_U0_M (PCNT_CNT_H_STEP_U0_V << PCNT_CNT_H_STEP_U0_S) +#define PCNT_CNT_H_STEP_U0_V 0x0000FFFFU +#define PCNT_CNT_H_STEP_U0_S 0 +/** PCNT_CNT_L_STEP_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 0. + */ +#define PCNT_CNT_L_STEP_U0 0x0000FFFFU +#define PCNT_CNT_L_STEP_U0_M (PCNT_CNT_L_STEP_U0_V << PCNT_CNT_L_STEP_U0_S) +#define PCNT_CNT_L_STEP_U0_V 0x0000FFFFU +#define PCNT_CNT_L_STEP_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * Configures the maximum threshold for the filter. Any pulses with width less than + * this will be ignored when the filter is enabled. + * Measurement unit: APB_CLK cycles. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * Configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * Configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * Configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * Configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the thr_h_lim value for unit 1. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the thr_l_lim value for unit 1. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U1_CONF3_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U1_CONF3_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_H_STEP_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 1. + */ +#define PCNT_CNT_H_STEP_U1 0x0000FFFFU +#define PCNT_CNT_H_STEP_U1_M (PCNT_CNT_H_STEP_U1_V << PCNT_CNT_H_STEP_U1_S) +#define PCNT_CNT_H_STEP_U1_V 0x0000FFFFU +#define PCNT_CNT_H_STEP_U1_S 0 +/** PCNT_CNT_L_STEP_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 1. + */ +#define PCNT_CNT_L_STEP_U1 0x0000FFFFU +#define PCNT_CNT_L_STEP_U1_M (PCNT_CNT_L_STEP_U1_V << PCNT_CNT_L_STEP_U1_S) +#define PCNT_CNT_L_STEP_U1_V 0x0000FFFFU +#define PCNT_CNT_L_STEP_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * Configures the maximum threshold for the filter. Any pulses with width less than + * this will be ignored when the filter is enabled. + * Measurement unit: APB_CLK cycles. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * Configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * Configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * Configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * Configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the thr_h_lim value for unit 2. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the thr_l_lim value for unit 2. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U2_CONF3_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U2_CONF3_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_STEP_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 2. + */ +#define PCNT_CNT_H_STEP_U2 0x0000FFFFU +#define PCNT_CNT_H_STEP_U2_M (PCNT_CNT_H_STEP_U2_V << PCNT_CNT_H_STEP_U2_S) +#define PCNT_CNT_H_STEP_U2_V 0x0000FFFFU +#define PCNT_CNT_H_STEP_U2_S 0 +/** PCNT_CNT_L_STEP_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 2. + */ +#define PCNT_CNT_L_STEP_U2 0x0000FFFFU +#define PCNT_CNT_L_STEP_U2_M (PCNT_CNT_L_STEP_U2_V << PCNT_CNT_L_STEP_U2_S) +#define PCNT_CNT_L_STEP_U2_V 0x0000FFFFU +#define PCNT_CNT_L_STEP_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * Configures the maximum threshold for the filter. Any pulses with width less than + * this will be ignored when the filter is enabled. + * Measurement unit: APB_CLK cycles. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * Configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * Configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * Configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * Configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the thr_h_lim value for unit 3. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the thr_l_lim value for unit 3. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U3_CONF3_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U3_CONF3_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_CNT_H_STEP_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 3. + */ +#define PCNT_CNT_H_STEP_U3 0x0000FFFFU +#define PCNT_CNT_H_STEP_U3_M (PCNT_CNT_H_STEP_U3_V << PCNT_CNT_H_STEP_U3_S) +#define PCNT_CNT_H_STEP_U3_V 0x0000FFFFU +#define PCNT_CNT_H_STEP_U3_S 0 +/** PCNT_CNT_L_STEP_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 3. + */ +#define PCNT_CNT_L_STEP_U3 0x0000FFFFU +#define PCNT_CNT_L_STEP_U3_M (PCNT_CNT_L_STEP_U3_V << PCNT_CNT_L_STEP_U3_S) +#define PCNT_CNT_L_STEP_U3_V 0x0000FFFFU +#define PCNT_CNT_L_STEP_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * Represents the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * Represents the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * Represents the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * Represents the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * Represents the pulse counter status of PCNT_U0 corresponding to 0. + * 0: pulse counter decreases from positive to 0 + * 1: pulse counter increases from negative to 0 + * 2: pulse counter is negative + * 3: pulse counter is positive + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * Represents the latched value of thres1 event of PCNT_U0 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres1 and thres1 event is valid + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * Represents the latched value of thres0 event of PCNT_U0 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres0 and thres0 event is valid + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * Represents the latched value of low limit event of PCNT_U0 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_l_lim and low limit event is valid. + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * Represents the latched value of high limit event of PCNT_U0 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_h_lim and high limit event is valid. + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * Represents the latched value of zero threshold event of PCNT_U0 when threshold + * event interrupt is valid. + * 0: others + * 1: the current pulse counter equals to 0 and zero threshold event is valid. + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 +/** PCNT_CNT_THR_H_STEP_LAT_U0 : RO; bitpos: [7]; default: 0; + * Represents the latched value of step counter event of PCNT_U0 when step counter + * event interrupt is valid. 1: the current pulse counter decrement equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_H_STEP_LAT_U0 (BIT(7)) +#define PCNT_CNT_THR_H_STEP_LAT_U0_M (PCNT_CNT_THR_H_STEP_LAT_U0_V << PCNT_CNT_THR_H_STEP_LAT_U0_S) +#define PCNT_CNT_THR_H_STEP_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_STEP_LAT_U0_S 7 +/** PCNT_CNT_THR_L_STEP_LAT_U0 : RO; bitpos: [8]; default: 0; + * Represents the latched value of step counter event of PCNT_U0 when step counter + * event interrupt is valid. 1: the current pulse counter increment equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_L_STEP_LAT_U0 (BIT(8)) +#define PCNT_CNT_THR_L_STEP_LAT_U0_M (PCNT_CNT_THR_L_STEP_LAT_U0_V << PCNT_CNT_THR_L_STEP_LAT_U0_S) +#define PCNT_CNT_THR_L_STEP_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_STEP_LAT_U0_S 8 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x64) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * Represents the pulse counter status of PCNT_U1 corresponding to 0. + * 0: pulse counter decreases from positive to 0 + * 1: pulse counter increases from negative to 0 + * 2: pulse counter is negative + * 3: pulse counter is positive + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * Represents the latched value of thres1 event of PCNT_U1 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres1 and thres1 event is valid + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * Represents the latched value of thres0 event of PCNT_U1 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres0 and thres0 event is valid + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * Represents the latched value of low limit event of PCNT_U1 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_l_lim and low limit event is valid. + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * Represents the latched value of high limit event of PCNT_U1 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_h_lim and high limit event is valid. + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * Represents the latched value of zero threshold event of PCNT_U1 when threshold + * event interrupt is valid. + * 0: others + * 1: the current pulse counter equals to 0 and zero threshold event is valid. + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 +/** PCNT_CNT_THR_H_STEP_LAT_U1 : RO; bitpos: [7]; default: 0; + * Represents the latched value of step counter event of PCNT_U1 when step counter + * event interrupt is valid. 1: the current pulse counter decrement equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_H_STEP_LAT_U1 (BIT(7)) +#define PCNT_CNT_THR_H_STEP_LAT_U1_M (PCNT_CNT_THR_H_STEP_LAT_U1_V << PCNT_CNT_THR_H_STEP_LAT_U1_S) +#define PCNT_CNT_THR_H_STEP_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_STEP_LAT_U1_S 7 +/** PCNT_CNT_THR_L_STEP_LAT_U1 : RO; bitpos: [8]; default: 0; + * Represents the latched value of step counter event of PCNT_U1 when step counter + * event interrupt is valid. 1: the current pulse counter increment equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_L_STEP_LAT_U1 (BIT(8)) +#define PCNT_CNT_THR_L_STEP_LAT_U1_M (PCNT_CNT_THR_L_STEP_LAT_U1_V << PCNT_CNT_THR_L_STEP_LAT_U1_S) +#define PCNT_CNT_THR_L_STEP_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_STEP_LAT_U1_S 8 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x68) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * Represents the pulse counter status of PCNT_U2 corresponding to 0. + * 0: pulse counter decreases from positive to 0 + * 1: pulse counter increases from negative to 0 + * 2: pulse counter is negative + * 3: pulse counter is positive + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * Represents the latched value of thres1 event of PCNT_U2 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres1 and thres1 event is valid + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * Represents the latched value of thres0 event of PCNT_U2 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres0 and thres0 event is valid + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * Represents the latched value of low limit event of PCNT_U2 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_l_lim and low limit event is valid. + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * Represents the latched value of high limit event of PCNT_U2 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_h_lim and high limit event is valid. + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * Represents the latched value of zero threshold event of PCNT_U2 when threshold + * event interrupt is valid. + * 0: others + * 1: the current pulse counter equals to 0 and zero threshold event is valid. + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 +/** PCNT_CNT_THR_H_STEP_LAT_U2 : RO; bitpos: [7]; default: 0; + * Represents the latched value of step counter event of PCNT_U2 when step counter + * event interrupt is valid. 1: the current pulse counter decrement equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_H_STEP_LAT_U2 (BIT(7)) +#define PCNT_CNT_THR_H_STEP_LAT_U2_M (PCNT_CNT_THR_H_STEP_LAT_U2_V << PCNT_CNT_THR_H_STEP_LAT_U2_S) +#define PCNT_CNT_THR_H_STEP_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_STEP_LAT_U2_S 7 +/** PCNT_CNT_THR_L_STEP_LAT_U2 : RO; bitpos: [8]; default: 0; + * Represents the latched value of step counter event of PCNT_U2 when step counter + * event interrupt is valid. 1: the current pulse counter increment equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_L_STEP_LAT_U2 (BIT(8)) +#define PCNT_CNT_THR_L_STEP_LAT_U2_M (PCNT_CNT_THR_L_STEP_LAT_U2_V << PCNT_CNT_THR_L_STEP_LAT_U2_S) +#define PCNT_CNT_THR_L_STEP_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_STEP_LAT_U2_S 8 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x6c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * Represents the pulse counter status of PCNT_U3 corresponding to 0. + * 0: pulse counter decreases from positive to 0 + * 1: pulse counter increases from negative to 0 + * 2: pulse counter is negative + * 3: pulse counter is positive + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * Represents the latched value of thres1 event of PCNT_U3 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres1 and thres1 event is valid + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * Represents the latched value of thres0 event of PCNT_U3 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres0 and thres0 event is valid + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * Represents the latched value of low limit event of PCNT_U3 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_l_lim and low limit event is valid. + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * Represents the latched value of high limit event of PCNT_U3 when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_h_lim and high limit event is valid. + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * Represents the latched value of zero threshold event of PCNT_U3 when threshold + * event interrupt is valid. + * 0: others + * 1: the current pulse counter equals to 0 and zero threshold event is valid. + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 +/** PCNT_CNT_THR_H_STEP_LAT_U3 : RO; bitpos: [7]; default: 0; + * Represents the latched value of step counter event of PCNT_U3 when step counter + * event interrupt is valid. 1: the current pulse counter decrement equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_H_STEP_LAT_U3 (BIT(7)) +#define PCNT_CNT_THR_H_STEP_LAT_U3_M (PCNT_CNT_THR_H_STEP_LAT_U3_V << PCNT_CNT_THR_H_STEP_LAT_U3_S) +#define PCNT_CNT_THR_H_STEP_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_STEP_LAT_U3_S 7 +/** PCNT_CNT_THR_L_STEP_LAT_U3 : RO; bitpos: [8]; default: 0; + * Represents the latched value of step counter event of PCNT_U3 when step counter + * event interrupt is valid. 1: the current pulse counter increment equals to + * reg_cnt_step and step counter event is valid. 0: others + */ +#define PCNT_CNT_THR_L_STEP_LAT_U3 (BIT(8)) +#define PCNT_CNT_THR_L_STEP_LAT_U3_M (PCNT_CNT_THR_L_STEP_LAT_U3_V << PCNT_CNT_THR_L_STEP_LAT_U3_S) +#define PCNT_CNT_THR_L_STEP_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_STEP_LAT_U3_S 8 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x70) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U0 (BIT(8)) +#define PCNT_DALTA_CHANGE_EN_U0_M (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S) +#define PCNT_DALTA_CHANGE_EN_U0_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U0_S 8 +/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U1 (BIT(9)) +#define PCNT_DALTA_CHANGE_EN_U1_M (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S) +#define PCNT_DALTA_CHANGE_EN_U1_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U1_S 9 +/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U2 (BIT(10)) +#define PCNT_DALTA_CHANGE_EN_U2_M (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S) +#define PCNT_DALTA_CHANGE_EN_U2_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U2_S 10 +/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U3 (BIT(11)) +#define PCNT_DALTA_CHANGE_EN_U3_M (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S) +#define PCNT_DALTA_CHANGE_EN_U3_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U3_S 11 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 37778192; + * Version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/pcnt_struct_eco2.h b/components/soc/esp32c5/register/soc/pcnt_struct_eco2.h new file mode 100644 index 0000000000..11e9e818d8 --- /dev/null +++ b/components/soc/esp32c5/register/soc/pcnt_struct_eco2.h @@ -0,0 +1,523 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres_un : R/W; bitpos: [9:0]; default: 16; + * Configures the maximum threshold for the filter. Any pulses with width less than + * this will be ignored when the filter is enabled. + * Measurement unit: APB_CLK cycles. + */ + uint32_t filter_thres_un:10; + /** filter_en_un : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en_un:1; + /** thr_zero_en_un : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en_un:1; + /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ + uint32_t thr_h_lim_en_un:1; + /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ + uint32_t thr_l_lim_en_un:1; + /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en_un:1; + /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en_un:1; + /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ + uint32_t ch0_neg_mode_un:2; + /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0; + * Configures the behavior when the signal input of channel 0 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ + uint32_t ch0_pos_mode_un:2; + /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0; + * Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode_un:2; + /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0; + * Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode_un:2; + /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a negative edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ + uint32_t ch1_neg_mode_un:2; + /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0; + * Configures the behavior when the signal input of channel 1 detects a positive edge. + * 1: Increment the counter + * 2: Decrement the counter + * 0, 3: No effect + */ + uint32_t ch1_pos_mode_un:2; + /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0; + * Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the + * control signal is high. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode_un:2; + /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0; + * Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the + * control signal is low. + * 0: No modification + * 1: Invert behavior (increase -> decrease, decrease -> increase) + * 2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode_un:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0; + * Configures the thres0 value for unit n. + */ + uint32_t cnt_thres0_un:16; + /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0; + * Configures the thres1 value for unit n. + */ + uint32_t cnt_thres1_un:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0; + * Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ + uint32_t cnt_h_lim_un:16; + /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0; + * Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the + * counter will be cleared to 0. + */ + uint32_t cnt_l_lim_un:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of u0_conf3 register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_h_step_u0 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 0. + */ + uint32_t cnt_h_step_u0:16; + /** cnt_l_step_u0 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 0. + */ + uint32_t cnt_l_step_u0:16; + }; + uint32_t val; +} pcnt_u0_conf3_reg_t; + +/** Type of u1_conf3 register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_h_step_u1 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 1. + */ + uint32_t cnt_h_step_u1:16; + /** cnt_l_step_u1 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 1. + */ + uint32_t cnt_l_step_u1:16; + }; + uint32_t val; +} pcnt_u1_conf3_reg_t; + +/** Type of u2_conf3 register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_h_step_u2 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 2. + */ + uint32_t cnt_h_step_u2:16; + /** cnt_l_step_u2 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 2. + */ + uint32_t cnt_l_step_u2:16; + }; + uint32_t val; +} pcnt_u2_conf3_reg_t; + +/** Type of u3_conf3 register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_h_step_u3 : R/W; bitpos: [15:0]; default: 0; + * Configures the forward rotation step value for unit 3. + */ + uint32_t cnt_h_step_u3:16; + /** cnt_l_step_u3 : R/W; bitpos: [31:16]; default: 0; + * Configures the reverse rotation step value for unit 3. + */ + uint32_t cnt_l_step_u3:16; + }; + uint32_t val; +} pcnt_u3_conf3_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t dalta_change_en_u0:1; + /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t dalta_change_en_u1:1; + /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t dalta_change_en_u2:1; + /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t dalta_change_en_u3:1; + uint32_t reserved_12:4; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0; + * Represents the current pulse count value for unit n. + */ + uint32_t pulse_cnt_un:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0; + * Represents the pulse counter status of PCNT_Un corresponding to 0. + * 0: pulse counter decreases from positive to 0 + * 1: pulse counter increases from negative to 0 + * 2: pulse counter is negative + * 3: pulse counter is positive + */ + uint32_t cnt_thr_zero_mode_un:2; + /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0; + * Represents the latched value of thres1 event of PCNT_Un when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres1 and thres1 event is valid + */ + uint32_t cnt_thr_thres1_lat_un:1; + /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0; + * Represents the latched value of thres0 event of PCNT_Un when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thres0 and thres0 event is valid + */ + uint32_t cnt_thr_thres0_lat_un:1; + /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0; + * Represents the latched value of low limit event of PCNT_Un when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_l_lim and low limit event is valid. + */ + uint32_t cnt_thr_l_lim_lat_un:1; + /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0; + * Represents the latched value of high limit event of PCNT_Un when threshold event + * interrupt is valid. + * 0: others + * 1: the current pulse counter equals to thr_h_lim and high limit event is valid. + */ + uint32_t cnt_thr_h_lim_lat_un:1; + /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0; + * Represents the latched value of zero threshold event of PCNT_Un when threshold + * event interrupt is valid. + * 0: others + * 1: the current pulse counter equals to 0 and zero threshold event is valid. + */ + uint32_t cnt_thr_zero_lat_un:1; + /** cnt_thr_h_step_lat_un : RO; bitpos: [7]; default: 0; + * Represents the latched value of step counter event of PCNT_Un when step counter + * event interrupt is valid. 1: the current pulse counter decrement equals to + * reg_cnt_step and step counter event is valid. 0: others + */ + uint32_t cnt_thr_h_step_lat_un:1; + /** cnt_thr_l_step_lat_un : RO; bitpos: [8]; default: 0; + * Represents the latched value of step counter event of PCNT_Un when step counter + * event interrupt is valid. 1: the current pulse counter increment equals to + * reg_cnt_step and step counter event is valid. 0: others + */ + uint32_t cnt_thr_l_step_lat_un:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 37778192; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + + +typedef struct { + volatile pcnt_un_conf0_reg_t u0_conf0; + volatile pcnt_un_conf1_reg_t u0_conf1; + volatile pcnt_un_conf2_reg_t u0_conf2; + volatile pcnt_u0_conf3_reg_t u0_conf3; + volatile pcnt_un_conf0_reg_t u1_conf0; + volatile pcnt_un_conf1_reg_t u1_conf1; + volatile pcnt_un_conf2_reg_t u1_conf2; + volatile pcnt_u1_conf3_reg_t u1_conf3; + volatile pcnt_un_conf0_reg_t u2_conf0; + volatile pcnt_un_conf1_reg_t u2_conf1; + volatile pcnt_un_conf2_reg_t u2_conf2; + volatile pcnt_u2_conf3_reg_t u2_conf3; + volatile pcnt_un_conf0_reg_t u3_conf0; + volatile pcnt_un_conf1_reg_t u3_conf1; + volatile pcnt_un_conf2_reg_t u3_conf2; + volatile pcnt_u3_conf3_reg_t u3_conf3; + volatile pcnt_un_cnt_reg_t un_cnt[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t un_status[4]; + volatile pcnt_ctrl_reg_t ctrl; + uint32_t reserved_074[34]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/reg_base.h b/components/soc/esp32c5/register/soc/reg_base.h index e5df7a8592..e0523a1957 100644 --- a/components/soc/esp32c5/register/soc/reg_base.h +++ b/components/soc/esp32c5/register/soc/reg_base.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,6 +32,9 @@ #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_MCPWM_BASE 0x60014000 #define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_HINF_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x60017000 +#define DR_REG_SLC_HOST_BASE 0x60018000 #define DR_REG_PVT_MONITOR_BASE 0x60019000 #define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 @@ -65,6 +68,7 @@ #define DR_REG_TEE_BASE 0x60098000 #define DR_REG_HP_APM_BASE 0x60099000 #define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_CPU_APM_BASE 0x6009A000 #define DR_REG_MISC_BASE 0x6009F000 /** @@ -107,7 +111,7 @@ * */ #define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_BUS_MONITOR_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM #define DR_REG_CLINT_M_BASE 0x20000000 diff --git a/components/soc/esp32c5/register/soc/rsa_reg.h b/components/soc/esp32c5/register/soc/rsa_reg.h index 4b60855e4e..c100dbdbaa 100644 --- a/components/soc/esp32c5/register/soc/rsa_reg.h +++ b/components/soc/esp32c5/register/soc/rsa_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -64,9 +64,9 @@ extern "C" { */ #define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) /** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; - * Represents whether or not the RSA memory completes initialization.\\ - * 0: Not complete\\ - * 1: Completed\\ + * Represents whether or not the RSA memory completes initialization. + * 0: Not complete + * 1: Completed */ #define RSA_QUERY_CLEAN (BIT(0)) #define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) @@ -78,9 +78,9 @@ extern "C" { */ #define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) /** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; - * Configures whether or not to starts the modular exponentiation. \\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to starts the modular exponentiation. + * 0: No effect + * 1: Start */ #define RSA_SET_START_MODEXP (BIT(0)) #define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) @@ -92,9 +92,9 @@ extern "C" { */ #define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) /** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; - * Configures whether or not to start the modular multiplication.\\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to start the modular multiplication. + * 0: No effect + * 1: Start */ #define RSA_SET_START_MODMULT (BIT(0)) #define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) @@ -106,9 +106,9 @@ extern "C" { */ #define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) /** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; - * Configures whether or not to start the multiplication.\\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to start the multiplication. + * 0: No effect + * 1: Start */ #define RSA_SET_START_MULT (BIT(0)) #define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) @@ -120,9 +120,9 @@ extern "C" { */ #define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) /** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; - * Represents the RSA status.\\ - * 0: Busy\\ - * 1: Idle\\ + * Represents the RSA status. + * 0: Busy + * 1: Idle */ #define RSA_QUERY_IDLE (BIT(0)) #define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) @@ -146,9 +146,9 @@ extern "C" { */ #define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) /** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; - * Configures the constant_time option. \\ - * 0: Acceleration\\ - * 1: No acceleration (default)\\ + * Configures the constant_time option. + * 0: Acceleration + * 1: No acceleration (default) */ #define RSA_CONSTANT_TIME (BIT(0)) #define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) @@ -160,9 +160,9 @@ extern "C" { */ #define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) /** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; - * Configures the search option. \\ - * 0: No acceleration (default)\\ - * 1: Acceleration\\ + * Configures the search option. + * 0: No acceleration (default) + * 1: Acceleration * This option should be used together with RSA_SEARCH_POS_REG. */ #define RSA_SEARCH_ENABLE (BIT(0)) diff --git a/components/soc/esp32c5/register/soc/rsa_struct.h b/components/soc/esp32c5/register/soc/rsa_struct.h index 5cf369a78e..44f1d9ea58 100644 --- a/components/soc/esp32c5/register/soc/rsa_struct.h +++ b/components/soc/esp32c5/register/soc/rsa_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,9 +46,9 @@ typedef union { typedef union { struct { /** set_start_modexp : WT; bitpos: [0]; default: 0; - * Configures whether or not to starts the modular exponentiation. \\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to starts the modular exponentiation. + * 0: No effect + * 1: Start */ uint32_t set_start_modexp:1; uint32_t reserved_1:31; @@ -62,9 +62,9 @@ typedef union { typedef union { struct { /** set_start_modmult : WT; bitpos: [0]; default: 0; - * Configures whether or not to start the modular multiplication.\\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to start the modular multiplication. + * 0: No effect + * 1: Start */ uint32_t set_start_modmult:1; uint32_t reserved_1:31; @@ -78,9 +78,9 @@ typedef union { typedef union { struct { /** set_start_mult : WT; bitpos: [0]; default: 0; - * Configures whether or not to start the multiplication.\\ - * 0: No effect\\ - * 1: Start\\ + * Configures whether or not to start the multiplication. + * 0: No effect + * 1: Start */ uint32_t set_start_mult:1; uint32_t reserved_1:31; @@ -94,9 +94,9 @@ typedef union { typedef union { struct { /** query_idle : RO; bitpos: [0]; default: 0; - * Represents the RSA status.\\ - * 0: Busy\\ - * 1: Idle\\ + * Represents the RSA status. + * 0: Busy + * 1: Idle */ uint32_t query_idle:1; uint32_t reserved_1:31; @@ -110,9 +110,9 @@ typedef union { typedef union { struct { /** constant_time : R/W; bitpos: [0]; default: 1; - * Configures the constant_time option. \\ - * 0: Acceleration\\ - * 1: No acceleration (default)\\ + * Configures the constant_time option. + * 0: Acceleration + * 1: No acceleration (default) */ uint32_t constant_time:1; uint32_t reserved_1:31; @@ -126,9 +126,9 @@ typedef union { typedef union { struct { /** search_enable : R/W; bitpos: [0]; default: 0; - * Configures the search option. \\ - * 0: No acceleration (default)\\ - * 1: Acceleration\\ + * Configures the search option. + * 0: No acceleration (default) + * 1: Acceleration * This option should be used together with RSA_SEARCH_POS_REG. */ uint32_t search_enable:1; @@ -160,9 +160,9 @@ typedef union { typedef union { struct { /** query_clean : RO; bitpos: [0]; default: 0; - * Represents whether or not the RSA memory completes initialization.\\ - * 0: Not complete\\ - * 1: Completed\\ + * Represents whether or not the RSA memory completes initialization. + * 0: Not complete + * 1: Completed */ uint32_t query_clean:1; uint32_t reserved_1:31; diff --git a/components/soc/esp32c5/register/soc/sdio_hinf_reg.h b/components/soc/esp32c5/register/soc/sdio_hinf_reg.h new file mode 100644 index 0000000000..8c71517bcc --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_hinf_reg.h @@ -0,0 +1,576 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HINF_CFG_DATA0_REG register + * Configure sdio cis content + */ +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ +#define HINF_DEVICE_ID_FN1 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) +#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_S 0 +/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ +#define HINF_USER_ID_FN1 0x0000FFFFU +#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) +#define HINF_USER_ID_FN1_V 0x0000FFFFU +#define HINF_USER_ID_FN1_S 16 + +/** HINF_CFG_DATA1_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) +#define HINF_SDIO_ENABLE_V 0x00000001U +#define HINF_SDIO_ENABLE_S 0 +/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) +#define HINF_SDIO_IOREADY1_V 0x00000001U +#define HINF_SDIO_IOREADY1_S 1 +/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) +#define HINF_HIGHSPEED_ENABLE_V 0x00000001U +#define HINF_HIGHSPEED_ENABLE_S 2 +/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) +#define HINF_HIGHSPEED_MODE_V 0x00000001U +#define HINF_HIGHSPEED_MODE_S 3 +/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) +#define HINF_SDIO_CD_ENABLE_V 0x00000001U +#define HINF_SDIO_CD_ENABLE_S 4 +/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) +#define HINF_SDIO_IOREADY2_V 0x00000001U +#define HINF_SDIO_IOREADY2_S 5 +/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) +#define HINF_SDIO_INT_MASK_V 0x00000001U +#define HINF_SDIO_INT_MASK_S 6 +/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) +#define HINF_IOENABLE2_V 0x00000001U +#define HINF_IOENABLE2_S 7 +/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) +#define HINF_CD_DISABLE_V 0x00000001U +#define HINF_CD_DISABLE_S 8 +/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) +#define HINF_FUNC1_EPS_V 0x00000001U +#define HINF_FUNC1_EPS_S 9 +/** HINF_EMP : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) +#define HINF_EMP_V 0x00000001U +#define HINF_EMP_S 10 +/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) +#define HINF_IOENABLE1_V 0x00000001U +#define HINF_IOENABLE1_S 11 +/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ +#define HINF_SDIO_VER 0x00000FFFU +#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) +#define HINF_SDIO_VER_V 0x00000FFFU +#define HINF_SDIO_VER_S 12 +/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ +#define HINF_FUNC2_EPS (BIT(24)) +#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) +#define HINF_FUNC2_EPS_V 0x00000001U +#define HINF_FUNC2_EPS_S 24 +/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ +#define HINF_SDIO20_CONF 0x0000007FU +#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) +#define HINF_SDIO20_CONF_V 0x0000007FU +#define HINF_SDIO20_CONF_S 25 + +/** HINF_CFG_TIMING_REG register + * Timing configuration registers + */ +#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) +/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ +#define HINF_NCRC 0x00000007U +#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) +#define HINF_NCRC_V 0x00000007U +#define HINF_NCRC_S 0 +/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ +#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) +#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_S 3 +/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ +#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) +#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_S 10 +/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ +#define HINF_SDCLK_STOP_THRES 0x000007FFU +#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) +#define HINF_SDCLK_STOP_THRES_V 0x000007FFU +#define HINF_SDCLK_STOP_THRES_S 16 +/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ +#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) +#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_S 28 + +/** HINF_CFG_UPDATE_REG register + * update sdio configurations + */ +#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) +/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ +#define HINF_CONF_UPDATE (BIT(0)) +#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) +#define HINF_CONF_UPDATE_V 0x00000001U +#define HINF_CONF_UPDATE_S 0 + +/** HINF_CFG_DATA7_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) +/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ +#define HINF_PIN_STATE 0x000000FFU +#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) +#define HINF_PIN_STATE_V 0x000000FFU +#define HINF_PIN_STATE_S 0 +/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ +#define HINF_CHIP_STATE 0x000000FFU +#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) +#define HINF_CHIP_STATE_V 0x000000FFU +#define HINF_CHIP_STATE_S 8 +/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) +#define HINF_SDIO_RST_V 0x00000001U +#define HINF_SDIO_RST_S 16 +/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) +#define HINF_SDIO_IOREADY0_V 0x00000001U +#define HINF_SDIO_IOREADY0_S 17 +/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ +#define HINF_SDIO_MEM_PD (BIT(18)) +#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) +#define HINF_SDIO_MEM_PD_V 0x00000001U +#define HINF_SDIO_MEM_PD_S 18 +/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ +#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) +#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) +#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U +#define HINF_ESDIO_DATA1_INT_EN_S 19 +/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ +#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) +#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) +#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_SW_S 20 +/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ +#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) +#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) +#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U +#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 +/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ +#define HINF_CLK_EN (BIT(22)) +#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) +#define HINF_CLK_EN_V 0x00000001U +#define HINF_CLK_EN_S 22 +/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ +#define HINF_SDDR50 (BIT(23)) +#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) +#define HINF_SDDR50_V 0x00000001U +#define HINF_SDDR50_S 23 +/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ +#define HINF_SSDR104 (BIT(24)) +#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) +#define HINF_SSDR104_V 0x00000001U +#define HINF_SSDR104_S 24 +/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ +#define HINF_SSDR50 (BIT(25)) +#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) +#define HINF_SSDR50_V 0x00000001U +#define HINF_SSDR50_S 25 +/** HINF_SDTD : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ +#define HINF_SDTD (BIT(26)) +#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) +#define HINF_SDTD_V 0x00000001U +#define HINF_SDTD_S 26 +/** HINF_SDTA : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ +#define HINF_SDTA (BIT(27)) +#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) +#define HINF_SDTA_V 0x00000001U +#define HINF_SDTA_S 27 +/** HINF_SDTC : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ +#define HINF_SDTC (BIT(28)) +#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) +#define HINF_SDTC_V 0x00000001U +#define HINF_SDTC_S 28 +/** HINF_SAI : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ +#define HINF_SAI (BIT(29)) +#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) +#define HINF_SAI_V 0x00000001U +#define HINF_SAI_S 29 +/** HINF_SDIO_WAKEUP_CLR : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ +#define HINF_SDIO_WAKEUP_CLR (BIT(30)) +#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) +#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U +#define HINF_SDIO_WAKEUP_CLR_S 30 + +/** HINF_CIS_CONF_W0_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) +/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ +#define HINF_CIS_CONF_W0 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_S 0 + +/** HINF_CIS_CONF_W1_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) +/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ +#define HINF_CIS_CONF_W1 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_S 0 + +/** HINF_CIS_CONF_W2_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) +/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ +#define HINF_CIS_CONF_W2 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_S 0 + +/** HINF_CIS_CONF_W3_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) +/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ +#define HINF_CIS_CONF_W3 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_S 0 + +/** HINF_CIS_CONF_W4_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) +/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ +#define HINF_CIS_CONF_W4 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_S 0 + +/** HINF_CIS_CONF_W5_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) +/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ +#define HINF_CIS_CONF_W5 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_S 0 + +/** HINF_CIS_CONF_W6_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) +/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ +#define HINF_CIS_CONF_W6 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_S 0 + +/** HINF_CIS_CONF_W7_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) +/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ +#define HINF_CIS_CONF_W7 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_S 0 + +/** HINF_CFG_DATA16_REG register + * SDIO cis configuration register + */ +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ +#define HINF_DEVICE_ID_FN2 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) +#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_S 0 +/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ +#define HINF_USER_ID_FN2 0x0000FFFFU +#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) +#define HINF_USER_ID_FN2_V 0x0000FFFFU +#define HINF_USER_ID_FN2_S 16 + +/** HINF_CFG_UHS1_INT_MODE_REG register + * configure int to start and end ahead of time in uhs1 mode + */ +#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) +/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_END_AHEAD_MODE 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) +#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_S 0 +/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_END_AHEAD_MODE 0x00000003U +#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) +#define HINF_INT_END_AHEAD_MODE_V 0x00000003U +#define HINF_INT_END_AHEAD_MODE_S 2 +/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) +#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_S 4 +/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_ST_AHEAD_MODE 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) +#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_S 6 + +/** HINF_CONF_STATUS_REG register + * func0 config0 status + */ +#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) +/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ +#define HINF_FUNC0_CONFIG0 0x000000FFU +#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) +#define HINF_FUNC0_CONFIG0_V 0x000000FFU +#define HINF_FUNC0_CONFIG0_S 0 +/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; + * sdr25 status + */ +#define HINF_SDR25_ST (BIT(8)) +#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) +#define HINF_SDR25_ST_V 0x00000001U +#define HINF_SDR25_ST_S 8 +/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; + * sdr50 status + */ +#define HINF_SDR50_ST (BIT(9)) +#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) +#define HINF_SDR50_ST_V 0x00000001U +#define HINF_SDR50_ST_S 9 +/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; + * sdr104 status + */ +#define HINF_SDR104_ST (BIT(10)) +#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) +#define HINF_SDR104_ST_V 0x00000001U +#define HINF_SDR104_ST_S 10 +/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; + * ddr50 status + */ +#define HINF_DDR50_ST (BIT(11)) +#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) +#define HINF_DDR50_ST_V 0x00000001U +#define HINF_DDR50_ST_S 11 +/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ +#define HINF_TUNE_ST 0x00000007U +#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) +#define HINF_TUNE_ST_V 0x00000007U +#define HINF_TUNE_ST_S 12 +/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ +#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) +#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) +#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_ST_S 15 +/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ +#define HINF_SDIO_SWITCH_END (BIT(16)) +#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) +#define HINF_SDIO_SWITCH_END_V 0x00000001U +#define HINF_SDIO_SWITCH_END_S 16 + +/** HINF_SDIO_SLAVE_LDO_CONF_REG register + * sdio slave ldo control register + */ +#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) +/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ +#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) +#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) +#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U +#define HINF_LDO_READY_CTL_IN_EN_S 0 +/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ +#define HINF_LDO_READY_THRES 0x0000001FU +#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) +#define HINF_LDO_READY_THRES_V 0x0000001FU +#define HINF_LDO_READY_THRES_S 1 +/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ +#define HINF_LDO_READY_IGNORE_EN (BIT(6)) +#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) +#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U +#define HINF_LDO_READY_IGNORE_EN_S 6 + +/** HINF_SDIO_DATE_REG register + * ******* Description *********** + */ +#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) +/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ +#define HINF_SDIO_DATE 0xFFFFFFFFU +#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) +#define HINF_SDIO_DATE_V 0xFFFFFFFFU +#define HINF_SDIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sdio_hinf_struct.h b/components/soc/esp32c5/register/soc/sdio_hinf_struct.h new file mode 100644 index 0000000000..8b03a91781 --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_hinf_struct.h @@ -0,0 +1,492 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of cfg_data0 register + * Configure sdio cis content + */ +typedef union { + struct { + /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ + uint32_t device_id_fn1:16; + /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ + uint32_t user_id_fn1:16; + }; + uint32_t val; +} hinf_cfg_data0_reg_t; + +/** Type of cfg_data1 register + * SDIO configuration register + */ +typedef union { + struct { + /** sdio_enable : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ + uint32_t sdio_enable:1; + /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready1:1; + /** highspeed_enable : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ + uint32_t highspeed_enable:1; + /** highspeed_mode : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ + uint32_t highspeed_mode:1; + /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ + uint32_t sdio_cd_enable:1; + /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready2:1; + /** sdio_int_mask : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ + uint32_t sdio_int_mask:1; + /** ioenable2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ + uint32_t ioenable2:1; + /** cd_disable : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ + uint32_t cd_disable:1; + /** func1_eps : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ + uint32_t func1_eps:1; + /** emp : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ + uint32_t emp:1; + /** ioenable1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ + uint32_t ioenable1:1; + /** sdio_ver : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ + uint32_t sdio_ver:12; + /** func2_eps : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ + uint32_t func2_eps:1; + /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ + uint32_t sdio20_conf:7; + }; + uint32_t val; +} hinf_cfg_data1_reg_t; + +/** Type of cfg_timing register + * Timing configuration registers + */ +typedef union { + struct { + /** ncrc : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ + uint32_t ncrc:3; + /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ + uint32_t pst_end_cmd_low_value:7; + /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ + uint32_t pst_end_data_low_value:6; + /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ + uint32_t sdclk_stop_thres:11; + uint32_t reserved_27:1; + /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ + uint32_t sample_clk_divider:4; + }; + uint32_t val; +} hinf_cfg_timing_reg_t; + +/** Type of cfg_update register + * update sdio configurations + */ +typedef union { + struct { + /** conf_update : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ + uint32_t conf_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hinf_cfg_update_reg_t; + +/** Type of cfg_data7 register + * SDIO configuration register + */ +typedef union { + struct { + /** pin_state : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ + uint32_t pin_state:8; + /** chip_state : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ + uint32_t chip_state:8; + /** sdio_rst : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ + uint32_t sdio_rst:1; + /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ + uint32_t sdio_ioready0:1; + /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ + uint32_t sdio_mem_pd:1; + /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ + uint32_t esdio_data1_int_en:1; + /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ + uint32_t sdio_switch_volt_sw:1; + /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ + uint32_t ddr50_blk_len_fix_en:1; + /** clk_en : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ + uint32_t clk_en:1; + /** sddr50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ + uint32_t sddr50:1; + /** ssdr104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ + uint32_t ssdr104:1; + /** ssdr50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ + uint32_t ssdr50:1; + /** sdtd : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ + uint32_t sdtd:1; + /** sdta : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ + uint32_t sdta:1; + /** sdtc : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ + uint32_t sdtc:1; + /** sai : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ + uint32_t sai:1; + /** sdio_wakeup_clr : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ + uint32_t sdio_wakeup_clr:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} hinf_cfg_data7_reg_t; + +/** Type of cis_conf_w0 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ + uint32_t cis_conf_w0:32; + }; + uint32_t val; +} hinf_cis_conf_w0_reg_t; + +/** Type of cis_conf_w1 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ + uint32_t cis_conf_w1:32; + }; + uint32_t val; +} hinf_cis_conf_w1_reg_t; + +/** Type of cis_conf_w2 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ + uint32_t cis_conf_w2:32; + }; + uint32_t val; +} hinf_cis_conf_w2_reg_t; + +/** Type of cis_conf_w3 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ + uint32_t cis_conf_w3:32; + }; + uint32_t val; +} hinf_cis_conf_w3_reg_t; + +/** Type of cis_conf_w4 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ + uint32_t cis_conf_w4:32; + }; + uint32_t val; +} hinf_cis_conf_w4_reg_t; + +/** Type of cis_conf_w5 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ + uint32_t cis_conf_w5:32; + }; + uint32_t val; +} hinf_cis_conf_w5_reg_t; + +/** Type of cis_conf_w6 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ + uint32_t cis_conf_w6:32; + }; + uint32_t val; +} hinf_cis_conf_w6_reg_t; + +/** Type of cis_conf_w7 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ + uint32_t cis_conf_w7:32; + }; + uint32_t val; +} hinf_cis_conf_w7_reg_t; + +/** Type of cfg_data16 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ + uint32_t device_id_fn2:16; + /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ + uint32_t user_id_fn2:16; + }; + uint32_t val; +} hinf_cfg_data16_reg_t; + +/** Type of cfg_uhs1_int_mode register + * configure int to start and end ahead of time in uhs1 mode + */ +typedef union { + struct { + /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_end_ahead_mode:2; + /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_end_ahead_mode:2; + /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_st_ahead_mode:2; + /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_st_ahead_mode:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hinf_cfg_uhs1_int_mode_reg_t; + +/** Type of sdio_slave_ldo_conf register + * sdio slave ldo control register + */ +typedef union { + struct { + /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ + uint32_t ldo_ready_ctl_in_en:1; + /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ + uint32_t ldo_ready_thres:5; + /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ + uint32_t ldo_ready_ignore_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} hinf_sdio_slave_ldo_conf_reg_t; + + +/** Group: Status registers */ +/** Type of conf_status register + * func0 config0 status + */ +typedef union { + struct { + /** func0_config0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ + uint32_t func0_config0:8; + /** sdr25_st : RO; bitpos: [8]; default: 0; + * sdr25 status + */ + uint32_t sdr25_st:1; + /** sdr50_st : RO; bitpos: [9]; default: 0; + * sdr50 status + */ + uint32_t sdr50_st:1; + /** sdr104_st : RO; bitpos: [10]; default: 0; + * sdr104 status + */ + uint32_t sdr104_st:1; + /** ddr50_st : RO; bitpos: [11]; default: 0; + * ddr50 status + */ + uint32_t ddr50_st:1; + /** tune_st : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ + uint32_t tune_st:3; + /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ + uint32_t sdio_switch_volt_st:1; + /** sdio_switch_end : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ + uint32_t sdio_switch_end:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hinf_conf_status_reg_t; + + +/** Group: Version register */ +/** Type of sdio_date register + * ******* Description *********** + */ +typedef union { + struct { + /** sdio_date : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ + uint32_t sdio_date:32; + }; + uint32_t val; +} hinf_sdio_date_reg_t; + + +typedef struct { + volatile hinf_cfg_data0_reg_t cfg_data0; + volatile hinf_cfg_data1_reg_t cfg_data1; + volatile hinf_cfg_timing_reg_t cfg_timing; + volatile hinf_cfg_update_reg_t cfg_update; + uint32_t reserved_010[3]; + volatile hinf_cfg_data7_reg_t cfg_data7; + volatile hinf_cis_conf_w0_reg_t cis_conf_w0; + volatile hinf_cis_conf_w1_reg_t cis_conf_w1; + volatile hinf_cis_conf_w2_reg_t cis_conf_w2; + volatile hinf_cis_conf_w3_reg_t cis_conf_w3; + volatile hinf_cis_conf_w4_reg_t cis_conf_w4; + volatile hinf_cis_conf_w5_reg_t cis_conf_w5; + volatile hinf_cis_conf_w6_reg_t cis_conf_w6; + volatile hinf_cis_conf_w7_reg_t cis_conf_w7; + volatile hinf_cfg_data16_reg_t cfg_data16; + volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; + uint32_t reserved_048[3]; + volatile hinf_conf_status_reg_t conf_status; + uint32_t reserved_058[22]; + volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; + uint32_t reserved_0b4[18]; + volatile hinf_sdio_date_reg_t sdio_date; +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifndef __cplusplus +_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sdio_slc_host_reg.h b/components/soc/esp32c5/register/soc/sdio_slc_host_reg.h new file mode 100644 index 0000000000..1649577009 --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_slc_host_reg.h @@ -0,0 +1,3883 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_HOST_FUNC2_0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x10) +/** SDIO_SLC_HOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_FUNC2_INT (BIT(24)) +#define SDIO_SLC_HOST_SLC_FUNC2_INT_M (SDIO_SLC_HOST_SLC_FUNC2_INT_V << SDIO_SLC_HOST_SLC_FUNC2_INT_S) +#define SDIO_SLC_HOST_SLC_FUNC2_INT_V 0x00000001U +#define SDIO_SLC_HOST_SLC_FUNC2_INT_S 24 + +/** SDIO_SLC_HOST_FUNC2_1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x14) +/** SDIO_SLC_HOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_FUNC2_INT_EN (BIT(0)) +#define SDIO_SLC_HOST_SLC_FUNC2_INT_EN_M (SDIO_SLC_HOST_SLC_FUNC2_INT_EN_V << SDIO_SLC_HOST_SLC_FUNC2_INT_EN_S) +#define SDIO_SLC_HOST_SLC_FUNC2_INT_EN_V 0x00000001U +#define SDIO_SLC_HOST_SLC_FUNC2_INT_EN_S 0 + +/** SDIO_SLC_HOST_FUNC2_2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x20) +/** SDIO_SLC_HOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define SDIO_SLC_HOST_SLC_FUNC1_MDSTAT_M (SDIO_SLC_HOST_SLC_FUNC1_MDSTAT_V << SDIO_SLC_HOST_SLC_FUNC1_MDSTAT_S) +#define SDIO_SLC_HOST_SLC_FUNC1_MDSTAT_V 0x00000001U +#define SDIO_SLC_HOST_SLC_FUNC1_MDSTAT_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x34) +/** SDIO_SLC_HOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT0 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_INT0_M (SDIO_SLC_HOST_GPIO_SDIO_INT0_V << SDIO_SLC_HOST_GPIO_SDIO_INT0_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_INT0_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x38) +/** SDIO_SLC_HOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT1 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_INT1_M (SDIO_SLC_HOST_GPIO_SDIO_INT1_V << SDIO_SLC_HOST_GPIO_SDIO_INT1_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_INT1_S 0 + +/** SDIO_SLC_HOST_GPIO_IN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x3c) +/** SDIO_SLC_HOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_IN0 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_IN0_M (SDIO_SLC_HOST_GPIO_SDIO_IN0_V << SDIO_SLC_HOST_GPIO_SDIO_IN0_S) +#define SDIO_SLC_HOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_IN0_S 0 + +/** SDIO_SLC_HOST_GPIO_IN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x40) +/** SDIO_SLC_HOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_IN1 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_IN1_M (SDIO_SLC_HOST_GPIO_SDIO_IN1_V << SDIO_SLC_HOST_GPIO_SDIO_IN1_S) +#define SDIO_SLC_HOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_GPIO_SDIO_IN1_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x44) +/** SDIO_SLC_HOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC_HOST_SLC0_TOKEN0_M (SDIO_SLC_HOST_SLC0_TOKEN0_V << SDIO_SLC_HOST_SLC0_TOKEN0_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC0_TOKEN0_S 0 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID (BIT(12)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_S 12 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 +/** SDIO_SLC_HOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_EOF 0x0000000FU +#define SDIO_SLC_HOST_SLC0_RX_PF_EOF_M (SDIO_SLC_HOST_SLC0_RX_PF_EOF_V << SDIO_SLC_HOST_SLC0_RX_PF_EOF_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLC_HOST_SLC0_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_PF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x48) +/** SDIO_SLC_HOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_PF_DATA 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC0_PF_DATA_M (SDIO_SLC_HOST_SLC0_PF_DATA_V << SDIO_SLC_HOST_SLC0_PF_DATA_S) +#define SDIO_SLC_HOST_SLC0_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC0_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC1_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_PF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x4c) +/** SDIO_SLC_HOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_PF_DATA 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC1_PF_DATA_M (SDIO_SLC_HOST_SLC1_PF_DATA_V << SDIO_SLC_HOST_SLC1_PF_DATA_S) +#define SDIO_SLC_HOST_SLC1_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC1_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x50) +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW_M (SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW_V << SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW_M (SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW_V << SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW_M (SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW_V << SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW_M (SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW_V << SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_RAW_S 16 +/** SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_RAW_S 17 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW_M (SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW_V << SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW_M (SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW_V << SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW_M (SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW_V << SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW_M (SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW_V << SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLC_HOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_RAW_M (SDIO_SLC_HOST_GPIO_SDIO_INT_RAW_V << SDIO_SLC_HOST_GPIO_SDIO_INT_RAW_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_GPIO_SDIO_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x54) +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW_M (SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW_V << SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW_M (SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW_V << SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW_M (SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW_V << SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW_M (SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW_V << SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_RAW_S 16 +/** SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_RAW_S 17 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW_M (SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW_V << SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW_M (SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW_V << SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW_M (SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW_V << SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW_M (SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW_V << SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x58) +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST_M (SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST_V << SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST_M (SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST_V << SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST_M (SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST_V << SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST_M (SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST_V << SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST_M (SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST_V << SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ST_S 14 +/** SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST_M (SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST_V << SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST_S) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ST_S 15 +/** SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST_M (SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST_V << SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ST_S 16 +/** SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST_M (SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST_V << SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ST_S 17 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST_M (SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST_V << SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST_M (SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST_V << SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST_M (SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST_V << SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST_M (SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST_V << SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST_M (SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST_V << SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST_M (SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST_V << SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLC_HOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ST (BIT(25)) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ST_M (SDIO_SLC_HOST_GPIO_SDIO_INT_ST_V << SDIO_SLC_HOST_GPIO_SDIO_INT_ST_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ST_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x5c) +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST_M (SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST_V << SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST_M (SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST_V << SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST_M (SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST_V << SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST_M (SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST_V << SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST_M (SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST_V << SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ST_S 14 +/** SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST_M (SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST_V << SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST_S) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ST_S 15 +/** SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST_M (SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST_V << SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ST_S 16 +/** SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST_M (SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST_V << SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ST_S 17 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST_M (SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST_V << SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST_M (SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST_V << SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST_M (SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST_V << SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST_M (SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST_V << SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST_M (SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST_V << SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 + +/** SDIO_SLC_HOST_PKT_LEN_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x60) +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_S 0 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 + +/** SDIO_SLC_HOST_STATE_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x64) +/** SDIO_SLC_HOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE0 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE0_M (SDIO_SLC_HOST_SLCHOST_STATE0_V << SDIO_SLC_HOST_SLCHOST_STATE0_S) +#define SDIO_SLC_HOST_SLCHOST_STATE0_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE0_S 0 +/** SDIO_SLC_HOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE1 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE1_M (SDIO_SLC_HOST_SLCHOST_STATE1_V << SDIO_SLC_HOST_SLCHOST_STATE1_S) +#define SDIO_SLC_HOST_SLCHOST_STATE1_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE1_S 8 +/** SDIO_SLC_HOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE2 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE2_M (SDIO_SLC_HOST_SLCHOST_STATE2_V << SDIO_SLC_HOST_SLCHOST_STATE2_S) +#define SDIO_SLC_HOST_SLCHOST_STATE2_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE2_S 16 +/** SDIO_SLC_HOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE3 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE3_M (SDIO_SLC_HOST_SLCHOST_STATE3_V << SDIO_SLC_HOST_SLCHOST_STATE3_S) +#define SDIO_SLC_HOST_SLCHOST_STATE3_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE3_S 24 + +/** SDIO_SLC_HOST_STATE_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x68) +/** SDIO_SLC_HOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE4 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE4_M (SDIO_SLC_HOST_SLCHOST_STATE4_V << SDIO_SLC_HOST_SLCHOST_STATE4_S) +#define SDIO_SLC_HOST_SLCHOST_STATE4_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE4_S 0 +/** SDIO_SLC_HOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE5 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE5_M (SDIO_SLC_HOST_SLCHOST_STATE5_V << SDIO_SLC_HOST_SLCHOST_STATE5_S) +#define SDIO_SLC_HOST_SLCHOST_STATE5_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE5_S 8 +/** SDIO_SLC_HOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE6 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE6_M (SDIO_SLC_HOST_SLCHOST_STATE6_V << SDIO_SLC_HOST_SLCHOST_STATE6_S) +#define SDIO_SLC_HOST_SLCHOST_STATE6_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE6_S 16 +/** SDIO_SLC_HOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_STATE7 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE7_M (SDIO_SLC_HOST_SLCHOST_STATE7_V << SDIO_SLC_HOST_SLCHOST_STATE7_S) +#define SDIO_SLC_HOST_SLCHOST_STATE7_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_STATE7_S 24 + +/** SDIO_SLC_HOST_CONF_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x6c) +/** SDIO_SLC_HOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF0 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF0_M (SDIO_SLC_HOST_SLCHOST_CONF0_V << SDIO_SLC_HOST_SLCHOST_CONF0_S) +#define SDIO_SLC_HOST_SLCHOST_CONF0_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF0_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF1 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF1_M (SDIO_SLC_HOST_SLCHOST_CONF1_V << SDIO_SLC_HOST_SLCHOST_CONF1_S) +#define SDIO_SLC_HOST_SLCHOST_CONF1_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF1_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF2 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF2_M (SDIO_SLC_HOST_SLCHOST_CONF2_V << SDIO_SLC_HOST_SLCHOST_CONF2_S) +#define SDIO_SLC_HOST_SLCHOST_CONF2_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF2_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF3 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF3_M (SDIO_SLC_HOST_SLCHOST_CONF3_V << SDIO_SLC_HOST_SLCHOST_CONF3_S) +#define SDIO_SLC_HOST_SLCHOST_CONF3_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF3_S 24 + +/** SDIO_SLC_HOST_CONF_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x70) +/** SDIO_SLC_HOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF4 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF4_M (SDIO_SLC_HOST_SLCHOST_CONF4_V << SDIO_SLC_HOST_SLCHOST_CONF4_S) +#define SDIO_SLC_HOST_SLCHOST_CONF4_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF4_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF5 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF5_M (SDIO_SLC_HOST_SLCHOST_CONF5_V << SDIO_SLC_HOST_SLCHOST_CONF5_S) +#define SDIO_SLC_HOST_SLCHOST_CONF5_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF5_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF6 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF6_M (SDIO_SLC_HOST_SLCHOST_CONF6_V << SDIO_SLC_HOST_SLCHOST_CONF6_S) +#define SDIO_SLC_HOST_SLCHOST_CONF6_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF6_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF7 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF7_M (SDIO_SLC_HOST_SLCHOST_CONF7_V << SDIO_SLC_HOST_SLCHOST_CONF7_S) +#define SDIO_SLC_HOST_SLCHOST_CONF7_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF7_S 24 + +/** SDIO_SLC_HOST_CONF_W2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x74) +/** SDIO_SLC_HOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF8 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF8_M (SDIO_SLC_HOST_SLCHOST_CONF8_V << SDIO_SLC_HOST_SLCHOST_CONF8_S) +#define SDIO_SLC_HOST_SLCHOST_CONF8_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF8_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF9 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF9_M (SDIO_SLC_HOST_SLCHOST_CONF9_V << SDIO_SLC_HOST_SLCHOST_CONF9_S) +#define SDIO_SLC_HOST_SLCHOST_CONF9_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF9_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF10 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF10_M (SDIO_SLC_HOST_SLCHOST_CONF10_V << SDIO_SLC_HOST_SLCHOST_CONF10_S) +#define SDIO_SLC_HOST_SLCHOST_CONF10_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF10_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF11 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF11_M (SDIO_SLC_HOST_SLCHOST_CONF11_V << SDIO_SLC_HOST_SLCHOST_CONF11_S) +#define SDIO_SLC_HOST_SLCHOST_CONF11_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF11_S 24 + +/** SDIO_SLC_HOST_CONF_W3_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W3_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x78) +/** SDIO_SLC_HOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF12 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF12_M (SDIO_SLC_HOST_SLCHOST_CONF12_V << SDIO_SLC_HOST_SLCHOST_CONF12_S) +#define SDIO_SLC_HOST_SLCHOST_CONF12_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF12_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF13 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF13_M (SDIO_SLC_HOST_SLCHOST_CONF13_V << SDIO_SLC_HOST_SLCHOST_CONF13_S) +#define SDIO_SLC_HOST_SLCHOST_CONF13_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF13_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF14 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF14_M (SDIO_SLC_HOST_SLCHOST_CONF14_V << SDIO_SLC_HOST_SLCHOST_CONF14_S) +#define SDIO_SLC_HOST_SLCHOST_CONF14_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF14_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF15 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF15_M (SDIO_SLC_HOST_SLCHOST_CONF15_V << SDIO_SLC_HOST_SLCHOST_CONF15_S) +#define SDIO_SLC_HOST_SLCHOST_CONF15_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF15_S 24 + +/** SDIO_SLC_HOST_CONF_W4_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W4_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x7c) +/** SDIO_SLC_HOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF16 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF16_M (SDIO_SLC_HOST_SLCHOST_CONF16_V << SDIO_SLC_HOST_SLCHOST_CONF16_S) +#define SDIO_SLC_HOST_SLCHOST_CONF16_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF16_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF17 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF17_M (SDIO_SLC_HOST_SLCHOST_CONF17_V << SDIO_SLC_HOST_SLCHOST_CONF17_S) +#define SDIO_SLC_HOST_SLCHOST_CONF17_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF17_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF18 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF18_M (SDIO_SLC_HOST_SLCHOST_CONF18_V << SDIO_SLC_HOST_SLCHOST_CONF18_S) +#define SDIO_SLC_HOST_SLCHOST_CONF18_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF18_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF19 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF19_M (SDIO_SLC_HOST_SLCHOST_CONF19_V << SDIO_SLC_HOST_SLCHOST_CONF19_S) +#define SDIO_SLC_HOST_SLCHOST_CONF19_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF19_S 24 + +/** SDIO_SLC_HOST_CONF_W5_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W5_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x80) +/** SDIO_SLC_HOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF20 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF20_M (SDIO_SLC_HOST_SLCHOST_CONF20_V << SDIO_SLC_HOST_SLCHOST_CONF20_S) +#define SDIO_SLC_HOST_SLCHOST_CONF20_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF20_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF21 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF21_M (SDIO_SLC_HOST_SLCHOST_CONF21_V << SDIO_SLC_HOST_SLCHOST_CONF21_S) +#define SDIO_SLC_HOST_SLCHOST_CONF21_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF21_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF22 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF22_M (SDIO_SLC_HOST_SLCHOST_CONF22_V << SDIO_SLC_HOST_SLCHOST_CONF22_S) +#define SDIO_SLC_HOST_SLCHOST_CONF22_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF22_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF23 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF23_M (SDIO_SLC_HOST_SLCHOST_CONF23_V << SDIO_SLC_HOST_SLCHOST_CONF23_S) +#define SDIO_SLC_HOST_SLCHOST_CONF23_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF23_S 24 + +/** SDIO_SLC_HOST_WIN_CMD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_WIN_CMD_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x84) +/** SDIO_SLC_HOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_WIN_CMD 0x0000FFFFU +#define SDIO_SLC_HOST_SLCHOST_WIN_CMD_M (SDIO_SLC_HOST_SLCHOST_WIN_CMD_V << SDIO_SLC_HOST_SLCHOST_WIN_CMD_S) +#define SDIO_SLC_HOST_SLCHOST_WIN_CMD_V 0x0000FFFFU +#define SDIO_SLC_HOST_SLCHOST_WIN_CMD_S 0 + +/** SDIO_SLC_HOST_CONF_W6_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W6_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x88) +/** SDIO_SLC_HOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF24 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF24_M (SDIO_SLC_HOST_SLCHOST_CONF24_V << SDIO_SLC_HOST_SLCHOST_CONF24_S) +#define SDIO_SLC_HOST_SLCHOST_CONF24_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF24_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF25 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF25_M (SDIO_SLC_HOST_SLCHOST_CONF25_V << SDIO_SLC_HOST_SLCHOST_CONF25_S) +#define SDIO_SLC_HOST_SLCHOST_CONF25_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF25_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF26 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF26_M (SDIO_SLC_HOST_SLCHOST_CONF26_V << SDIO_SLC_HOST_SLCHOST_CONF26_S) +#define SDIO_SLC_HOST_SLCHOST_CONF26_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF26_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF27 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF27_M (SDIO_SLC_HOST_SLCHOST_CONF27_V << SDIO_SLC_HOST_SLCHOST_CONF27_S) +#define SDIO_SLC_HOST_SLCHOST_CONF27_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF27_S 24 + +/** SDIO_SLC_HOST_CONF_W7_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W7_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x8c) +/** SDIO_SLC_HOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF28 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF28_M (SDIO_SLC_HOST_SLCHOST_CONF28_V << SDIO_SLC_HOST_SLCHOST_CONF28_S) +#define SDIO_SLC_HOST_SLCHOST_CONF28_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF28_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF29 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF29_M (SDIO_SLC_HOST_SLCHOST_CONF29_V << SDIO_SLC_HOST_SLCHOST_CONF29_S) +#define SDIO_SLC_HOST_SLCHOST_CONF29_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF29_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF30 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF30_M (SDIO_SLC_HOST_SLCHOST_CONF30_V << SDIO_SLC_HOST_SLCHOST_CONF30_S) +#define SDIO_SLC_HOST_SLCHOST_CONF30_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF30_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF31 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF31_M (SDIO_SLC_HOST_SLCHOST_CONF31_V << SDIO_SLC_HOST_SLCHOST_CONF31_S) +#define SDIO_SLC_HOST_SLCHOST_CONF31_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF31_S 24 + +/** SDIO_SLC_HOST_PKT_LEN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x90) +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_S 0 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x94) +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_S 0 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x98) +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_S 0 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 + +/** SDIO_SLC_HOST_CONF_W8_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W8_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x9c) +/** SDIO_SLC_HOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF32 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF32_M (SDIO_SLC_HOST_SLCHOST_CONF32_V << SDIO_SLC_HOST_SLCHOST_CONF32_S) +#define SDIO_SLC_HOST_SLCHOST_CONF32_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF32_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF33 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF33_M (SDIO_SLC_HOST_SLCHOST_CONF33_V << SDIO_SLC_HOST_SLCHOST_CONF33_S) +#define SDIO_SLC_HOST_SLCHOST_CONF33_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF33_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF34 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF34_M (SDIO_SLC_HOST_SLCHOST_CONF34_V << SDIO_SLC_HOST_SLCHOST_CONF34_S) +#define SDIO_SLC_HOST_SLCHOST_CONF34_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF34_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF35 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF35_M (SDIO_SLC_HOST_SLCHOST_CONF35_V << SDIO_SLC_HOST_SLCHOST_CONF35_S) +#define SDIO_SLC_HOST_SLCHOST_CONF35_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF35_S 24 + +/** SDIO_SLC_HOST_CONF_W9_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W9_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa0) +/** SDIO_SLC_HOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF36 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF36_M (SDIO_SLC_HOST_SLCHOST_CONF36_V << SDIO_SLC_HOST_SLCHOST_CONF36_S) +#define SDIO_SLC_HOST_SLCHOST_CONF36_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF36_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF37 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF37_M (SDIO_SLC_HOST_SLCHOST_CONF37_V << SDIO_SLC_HOST_SLCHOST_CONF37_S) +#define SDIO_SLC_HOST_SLCHOST_CONF37_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF37_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF38 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF38_M (SDIO_SLC_HOST_SLCHOST_CONF38_V << SDIO_SLC_HOST_SLCHOST_CONF38_S) +#define SDIO_SLC_HOST_SLCHOST_CONF38_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF38_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF39 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF39_M (SDIO_SLC_HOST_SLCHOST_CONF39_V << SDIO_SLC_HOST_SLCHOST_CONF39_S) +#define SDIO_SLC_HOST_SLCHOST_CONF39_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF39_S 24 + +/** SDIO_SLC_HOST_CONF_W10_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W10_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa4) +/** SDIO_SLC_HOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF40 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF40_M (SDIO_SLC_HOST_SLCHOST_CONF40_V << SDIO_SLC_HOST_SLCHOST_CONF40_S) +#define SDIO_SLC_HOST_SLCHOST_CONF40_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF40_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF41 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF41_M (SDIO_SLC_HOST_SLCHOST_CONF41_V << SDIO_SLC_HOST_SLCHOST_CONF41_S) +#define SDIO_SLC_HOST_SLCHOST_CONF41_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF41_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF42 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF42_M (SDIO_SLC_HOST_SLCHOST_CONF42_V << SDIO_SLC_HOST_SLCHOST_CONF42_S) +#define SDIO_SLC_HOST_SLCHOST_CONF42_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF42_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF43 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF43_M (SDIO_SLC_HOST_SLCHOST_CONF43_V << SDIO_SLC_HOST_SLCHOST_CONF43_S) +#define SDIO_SLC_HOST_SLCHOST_CONF43_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF43_S 24 + +/** SDIO_SLC_HOST_CONF_W11_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W11_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa8) +/** SDIO_SLC_HOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF44 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF44_M (SDIO_SLC_HOST_SLCHOST_CONF44_V << SDIO_SLC_HOST_SLCHOST_CONF44_S) +#define SDIO_SLC_HOST_SLCHOST_CONF44_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF44_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF45 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF45_M (SDIO_SLC_HOST_SLCHOST_CONF45_V << SDIO_SLC_HOST_SLCHOST_CONF45_S) +#define SDIO_SLC_HOST_SLCHOST_CONF45_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF45_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF46 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF46_M (SDIO_SLC_HOST_SLCHOST_CONF46_V << SDIO_SLC_HOST_SLCHOST_CONF46_S) +#define SDIO_SLC_HOST_SLCHOST_CONF46_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF46_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF47 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF47_M (SDIO_SLC_HOST_SLCHOST_CONF47_V << SDIO_SLC_HOST_SLCHOST_CONF47_S) +#define SDIO_SLC_HOST_SLCHOST_CONF47_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF47_S 24 + +/** SDIO_SLC_HOST_CONF_W12_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W12_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xac) +/** SDIO_SLC_HOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF48 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF48_M (SDIO_SLC_HOST_SLCHOST_CONF48_V << SDIO_SLC_HOST_SLCHOST_CONF48_S) +#define SDIO_SLC_HOST_SLCHOST_CONF48_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF48_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF49 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF49_M (SDIO_SLC_HOST_SLCHOST_CONF49_V << SDIO_SLC_HOST_SLCHOST_CONF49_S) +#define SDIO_SLC_HOST_SLCHOST_CONF49_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF49_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF50 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF50_M (SDIO_SLC_HOST_SLCHOST_CONF50_V << SDIO_SLC_HOST_SLCHOST_CONF50_S) +#define SDIO_SLC_HOST_SLCHOST_CONF50_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF50_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF51 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF51_M (SDIO_SLC_HOST_SLCHOST_CONF51_V << SDIO_SLC_HOST_SLCHOST_CONF51_S) +#define SDIO_SLC_HOST_SLCHOST_CONF51_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF51_S 24 + +/** SDIO_SLC_HOST_CONF_W13_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W13_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb0) +/** SDIO_SLC_HOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF52 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF52_M (SDIO_SLC_HOST_SLCHOST_CONF52_V << SDIO_SLC_HOST_SLCHOST_CONF52_S) +#define SDIO_SLC_HOST_SLCHOST_CONF52_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF52_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF53 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF53_M (SDIO_SLC_HOST_SLCHOST_CONF53_V << SDIO_SLC_HOST_SLCHOST_CONF53_S) +#define SDIO_SLC_HOST_SLCHOST_CONF53_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF53_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF54 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF54_M (SDIO_SLC_HOST_SLCHOST_CONF54_V << SDIO_SLC_HOST_SLCHOST_CONF54_S) +#define SDIO_SLC_HOST_SLCHOST_CONF54_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF54_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF55 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF55_M (SDIO_SLC_HOST_SLCHOST_CONF55_V << SDIO_SLC_HOST_SLCHOST_CONF55_S) +#define SDIO_SLC_HOST_SLCHOST_CONF55_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF55_S 24 + +/** SDIO_SLC_HOST_CONF_W14_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W14_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb4) +/** SDIO_SLC_HOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF56 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF56_M (SDIO_SLC_HOST_SLCHOST_CONF56_V << SDIO_SLC_HOST_SLCHOST_CONF56_S) +#define SDIO_SLC_HOST_SLCHOST_CONF56_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF56_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF57 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF57_M (SDIO_SLC_HOST_SLCHOST_CONF57_V << SDIO_SLC_HOST_SLCHOST_CONF57_S) +#define SDIO_SLC_HOST_SLCHOST_CONF57_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF57_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF58 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF58_M (SDIO_SLC_HOST_SLCHOST_CONF58_V << SDIO_SLC_HOST_SLCHOST_CONF58_S) +#define SDIO_SLC_HOST_SLCHOST_CONF58_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF58_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF59 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF59_M (SDIO_SLC_HOST_SLCHOST_CONF59_V << SDIO_SLC_HOST_SLCHOST_CONF59_S) +#define SDIO_SLC_HOST_SLCHOST_CONF59_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF59_S 24 + +/** SDIO_SLC_HOST_CONF_W15_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W15_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb8) +/** SDIO_SLC_HOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF60 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF60_M (SDIO_SLC_HOST_SLCHOST_CONF60_V << SDIO_SLC_HOST_SLCHOST_CONF60_S) +#define SDIO_SLC_HOST_SLCHOST_CONF60_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF60_S 0 +/** SDIO_SLC_HOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF61 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF61_M (SDIO_SLC_HOST_SLCHOST_CONF61_V << SDIO_SLC_HOST_SLCHOST_CONF61_S) +#define SDIO_SLC_HOST_SLCHOST_CONF61_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF61_S 8 +/** SDIO_SLC_HOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CONF62 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF62_M (SDIO_SLC_HOST_SLCHOST_CONF62_V << SDIO_SLC_HOST_SLCHOST_CONF62_S) +#define SDIO_SLC_HOST_SLCHOST_CONF62_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF62_S 16 +/** SDIO_SLC_HOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ +#define SDIO_SLC_HOST_SLCHOST_CONF63 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF63_M (SDIO_SLC_HOST_SLCHOST_CONF63_V << SDIO_SLC_HOST_SLCHOST_CONF63_S) +#define SDIO_SLC_HOST_SLCHOST_CONF63_V 0x000000FFU +#define SDIO_SLC_HOST_SLCHOST_CONF63_S 24 + +/** SDIO_SLC_HOST_CHECK_SUM0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xbc) +/** SDIO_SLC_HOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM0_M (SDIO_SLC_HOST_SLCHOST_CHECK_SUM0_V << SDIO_SLC_HOST_SLCHOST_CHECK_SUM0_S) +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM0_S 0 + +/** SDIO_SLC_HOST_CHECK_SUM1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc0) +/** SDIO_SLC_HOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM1_M (SDIO_SLC_HOST_SLCHOST_CHECK_SUM1_V << SDIO_SLC_HOST_SLCHOST_CHECK_SUM1_S) +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_CHECK_SUM1_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc4) +/** SDIO_SLC_HOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC_HOST_SLC1_TOKEN0_M (SDIO_SLC_HOST_SLC1_TOKEN0_V << SDIO_SLC_HOST_SLC1_TOKEN0_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC1_TOKEN0_S 0 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID (BIT(12)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_S 12 +/** SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1_M (SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1_V << SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1_S) +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC_HOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 +/** SDIO_SLC_HOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_EOF 0x0000000FU +#define SDIO_SLC_HOST_SLC1_RX_PF_EOF_M (SDIO_SLC_HOST_SLC1_RX_PF_EOF_V << SDIO_SLC_HOST_SLC1_RX_PF_EOF_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLC_HOST_SLC1_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc8) +/** SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD_M (SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD_V << SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD_S 0 +/** SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD_M (SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD_V << SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xcc) +/** SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD_M (SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD_V << SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD_S 0 +/** SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD_M (SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD_V << SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_TOKEN_CON_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_TOKEN_CON_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd0) +/** SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC_M (SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC_V << SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC_S 0 +/** SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC_M (SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC_V << SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_DEC_S 1 +/** SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR_M (SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR_V << SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TOKEN0_WR_S 2 +/** SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR_M (SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR_V << SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR_S) +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TOKEN1_WR_S 3 +/** SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC_M (SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC_V << SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_DEC_S 4 +/** SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC_M (SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC_V << SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_DEC_S 5 +/** SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR_M (SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR_V << SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TOKEN0_WR_S 6 +/** SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR_M (SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR_V << SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR_S) +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TOKEN1_WR_S 7 +/** SDIO_SLC_HOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_LEN_WR (BIT(8)) +#define SDIO_SLC_HOST_SLC0HOST_LEN_WR_M (SDIO_SLC_HOST_SLC0HOST_LEN_WR_V << SDIO_SLC_HOST_SLC0HOST_LEN_WR_S) +#define SDIO_SLC_HOST_SLC0HOST_LEN_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_LEN_WR_S 8 + +/** SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd4) +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR_M (SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR_V << SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR_M (SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR_V << SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR_M (SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR_V << SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR_M (SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR_V << SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_CLR_S 16 +/** SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_CLR_S 17 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR_M (SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR_V << SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR_M (SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR_V << SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR_M (SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR_V << SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR_M (SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR_V << SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLC_HOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_CLR_M (SDIO_SLC_HOST_GPIO_SDIO_INT_CLR_V << SDIO_SLC_HOST_GPIO_SDIO_INT_CLR_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_GPIO_SDIO_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd8) +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR_M (SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR_V << SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR_M (SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR_V << SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR_M (SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR_V << SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR_M (SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR_V << SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_CLR_S 16 +/** SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_CLR_S 17 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR_M (SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR_V << SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR_M (SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR_V << SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR_M (SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR_V << SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR_M (SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR_V << SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xdc) +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA_M (SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA_V << SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe0) +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe4) +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA_M (SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA_V << SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe8) +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xec) +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA_M (SDIO_SLC_HOST_GPIO_SDIO_INT_ENA_V << SDIO_SLC_HOST_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf0) +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf4) +/** SDIO_SLC_HOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_M (SDIO_SLC_HOST_SLC0HOST_RX_INFOR_V << SDIO_SLC_HOST_SLC0HOST_RX_INFOR_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf8) +/** SDIO_SLC_HOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_M (SDIO_SLC_HOST_SLC1HOST_RX_INFOR_V << SDIO_SLC_HOST_SLC1HOST_RX_INFOR_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xfc) +/** SDIO_SLC_HOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_M (SDIO_SLC_HOST_SLC0HOST_LEN_WD_V << SDIO_SLC_HOST_SLC0HOST_LEN_WD_S) +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x100) +/** SDIO_SLC_HOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_M (SDIO_SLC_HOST_SLC_APBWIN_WDATA_V << SDIO_SLC_HOST_SLC_APBWIN_WDATA_S) +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_CONF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x104) +/** SDIO_SLC_HOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_ADDR 0x0FFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_ADDR_M (SDIO_SLC_HOST_SLC_APBWIN_ADDR_V << SDIO_SLC_HOST_SLC_APBWIN_ADDR_S) +#define SDIO_SLC_HOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_ADDR_S 0 +/** SDIO_SLC_HOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_WR (BIT(28)) +#define SDIO_SLC_HOST_SLC_APBWIN_WR_M (SDIO_SLC_HOST_SLC_APBWIN_WR_V << SDIO_SLC_HOST_SLC_APBWIN_WR_S) +#define SDIO_SLC_HOST_SLC_APBWIN_WR_V 0x00000001U +#define SDIO_SLC_HOST_SLC_APBWIN_WR_S 28 +/** SDIO_SLC_HOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_START (BIT(29)) +#define SDIO_SLC_HOST_SLC_APBWIN_START_M (SDIO_SLC_HOST_SLC_APBWIN_START_V << SDIO_SLC_HOST_SLC_APBWIN_START_S) +#define SDIO_SLC_HOST_SLC_APBWIN_START_V 0x00000001U +#define SDIO_SLC_HOST_SLC_APBWIN_START_S 29 + +/** SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x108) +/** SDIO_SLC_HOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_M (SDIO_SLC_HOST_SLC_APBWIN_RDATA_V << SDIO_SLC_HOST_SLC_APBWIN_RDATA_S) +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_S 0 + +/** SDIO_SLC_HOST_RDCLR0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x10c) +/** SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR_S) +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 +/** SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR_S) +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_RDCLR1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x110) +/** SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR_S) +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 +/** SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR_S) +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLC_HOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x114) +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1_M (SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1_V << SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1_M (SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1_V << SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1_M (SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1_V << SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1_M (SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1_V << SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1_M (SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1_V << SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1_M (SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1_V << SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1_M (SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1_V << SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1_M (SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1_V << SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1_M (SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1_V << SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1_M (SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1_V << SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1_S) +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_GPIO_SDIO_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x118) +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1_M (SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1_V << SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1_M (SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1_V << SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1_M (SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1_V << SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1_M (SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1_V << SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1_M (SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1_V << SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1_M (SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1_V << SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1_M (SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1_V << SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1_M (SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1_V << SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1_M (SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1_V << SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLC_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_DATE_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_DATE_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x178) +/** SDIO_SLC_HOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_DATE 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_DATE_M (SDIO_SLC_HOST_SLCHOST_DATE_V << SDIO_SLC_HOST_SLCHOST_DATE_S) +#define SDIO_SLC_HOST_SLCHOST_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_DATE_S 0 + +/** SDIO_SLC_HOST_ID_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_ID_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x17c) +/** SDIO_SLC_HOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLCHOST_ID 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_ID_M (SDIO_SLC_HOST_SLCHOST_ID_V << SDIO_SLC_HOST_SLCHOST_ID_S) +#define SDIO_SLC_HOST_SLCHOST_ID_V 0xFFFFFFFFU +#define SDIO_SLC_HOST_SLCHOST_ID_S 0 + +/** SDIO_SLC_HOST_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x1f0) +/** SDIO_SLC_HOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FRC_SDIO11 0x0000001FU +#define SDIO_SLC_HOST_FRC_SDIO11_M (SDIO_SLC_HOST_FRC_SDIO11_V << SDIO_SLC_HOST_FRC_SDIO11_S) +#define SDIO_SLC_HOST_FRC_SDIO11_V 0x0000001FU +#define SDIO_SLC_HOST_FRC_SDIO11_S 0 +/** SDIO_SLC_HOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FRC_SDIO20 0x0000001FU +#define SDIO_SLC_HOST_FRC_SDIO20_M (SDIO_SLC_HOST_FRC_SDIO20_V << SDIO_SLC_HOST_FRC_SDIO20_S) +#define SDIO_SLC_HOST_FRC_SDIO20_V 0x0000001FU +#define SDIO_SLC_HOST_FRC_SDIO20_S 5 +/** SDIO_SLC_HOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FRC_NEG_SAMP 0x0000001FU +#define SDIO_SLC_HOST_FRC_NEG_SAMP_M (SDIO_SLC_HOST_FRC_NEG_SAMP_V << SDIO_SLC_HOST_FRC_NEG_SAMP_S) +#define SDIO_SLC_HOST_FRC_NEG_SAMP_V 0x0000001FU +#define SDIO_SLC_HOST_FRC_NEG_SAMP_S 10 +/** SDIO_SLC_HOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FRC_POS_SAMP 0x0000001FU +#define SDIO_SLC_HOST_FRC_POS_SAMP_M (SDIO_SLC_HOST_FRC_POS_SAMP_V << SDIO_SLC_HOST_FRC_POS_SAMP_S) +#define SDIO_SLC_HOST_FRC_POS_SAMP_V 0x0000001FU +#define SDIO_SLC_HOST_FRC_POS_SAMP_S 15 +/** SDIO_SLC_HOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_FRC_QUICK_IN 0x0000001FU +#define SDIO_SLC_HOST_FRC_QUICK_IN_M (SDIO_SLC_HOST_FRC_QUICK_IN_V << SDIO_SLC_HOST_FRC_QUICK_IN_S) +#define SDIO_SLC_HOST_FRC_QUICK_IN_V 0x0000001FU +#define SDIO_SLC_HOST_FRC_QUICK_IN_S 20 +/** SDIO_SLC_HOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SDIO20_INT_DELAY (BIT(25)) +#define SDIO_SLC_HOST_SDIO20_INT_DELAY_M (SDIO_SLC_HOST_SDIO20_INT_DELAY_V << SDIO_SLC_HOST_SDIO20_INT_DELAY_S) +#define SDIO_SLC_HOST_SDIO20_INT_DELAY_V 0x00000001U +#define SDIO_SLC_HOST_SDIO20_INT_DELAY_S 25 +/** SDIO_SLC_HOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SDIO_PAD_PULLUP (BIT(26)) +#define SDIO_SLC_HOST_SDIO_PAD_PULLUP_M (SDIO_SLC_HOST_SDIO_PAD_PULLUP_V << SDIO_SLC_HOST_SDIO_PAD_PULLUP_S) +#define SDIO_SLC_HOST_SDIO_PAD_PULLUP_V 0x00000001U +#define SDIO_SLC_HOST_SDIO_PAD_PULLUP_S 26 +/** SDIO_SLC_HOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_HSPEED_CON_EN (BIT(27)) +#define SDIO_SLC_HOST_HSPEED_CON_EN_M (SDIO_SLC_HOST_HSPEED_CON_EN_V << SDIO_SLC_HOST_HSPEED_CON_EN_S) +#define SDIO_SLC_HOST_HSPEED_CON_EN_V 0x00000001U +#define SDIO_SLC_HOST_HSPEED_CON_EN_S 27 + +/** SDIO_SLC_HOST_INF_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_INF_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x1f4) +/** SDIO_SLC_HOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SDIO20_MODE 0x0000001FU +#define SDIO_SLC_HOST_SDIO20_MODE_M (SDIO_SLC_HOST_SDIO20_MODE_V << SDIO_SLC_HOST_SDIO20_MODE_S) +#define SDIO_SLC_HOST_SDIO20_MODE_V 0x0000001FU +#define SDIO_SLC_HOST_SDIO20_MODE_S 0 +/** SDIO_SLC_HOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SDIO_NEG_SAMP 0x0000001FU +#define SDIO_SLC_HOST_SDIO_NEG_SAMP_M (SDIO_SLC_HOST_SDIO_NEG_SAMP_V << SDIO_SLC_HOST_SDIO_NEG_SAMP_S) +#define SDIO_SLC_HOST_SDIO_NEG_SAMP_V 0x0000001FU +#define SDIO_SLC_HOST_SDIO_NEG_SAMP_S 5 +/** SDIO_SLC_HOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLC_HOST_SDIO_QUICK_IN 0x0000001FU +#define SDIO_SLC_HOST_SDIO_QUICK_IN_M (SDIO_SLC_HOST_SDIO_QUICK_IN_V << SDIO_SLC_HOST_SDIO_QUICK_IN_S) +#define SDIO_SLC_HOST_SDIO_QUICK_IN_V 0x0000001FU +#define SDIO_SLC_HOST_SDIO_QUICK_IN_S 10 +/** SDIO_SLC_HOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ +#define SDIO_SLC_HOST_DLL_ON_SW (BIT(15)) +#define SDIO_SLC_HOST_DLL_ON_SW_M (SDIO_SLC_HOST_DLL_ON_SW_V << SDIO_SLC_HOST_DLL_ON_SW_S) +#define SDIO_SLC_HOST_DLL_ON_SW_V 0x00000001U +#define SDIO_SLC_HOST_DLL_ON_SW_S 15 +/** SDIO_SLC_HOST_DLL_ON : R/W; bitpos: [16]; default: 0; + * Software dll on + */ +#define SDIO_SLC_HOST_DLL_ON (BIT(16)) +#define SDIO_SLC_HOST_DLL_ON_M (SDIO_SLC_HOST_DLL_ON_V << SDIO_SLC_HOST_DLL_ON_S) +#define SDIO_SLC_HOST_DLL_ON_V 0x00000001U +#define SDIO_SLC_HOST_DLL_ON_S 16 +/** SDIO_SLC_HOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ +#define SDIO_SLC_HOST_CLK_MODE_SW (BIT(17)) +#define SDIO_SLC_HOST_CLK_MODE_SW_M (SDIO_SLC_HOST_CLK_MODE_SW_V << SDIO_SLC_HOST_CLK_MODE_SW_S) +#define SDIO_SLC_HOST_CLK_MODE_SW_V 0x00000001U +#define SDIO_SLC_HOST_CLK_MODE_SW_S 17 +/** SDIO_SLC_HOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ +#define SDIO_SLC_HOST_CLK_MODE 0x00000003U +#define SDIO_SLC_HOST_CLK_MODE_M (SDIO_SLC_HOST_CLK_MODE_V << SDIO_SLC_HOST_CLK_MODE_S) +#define SDIO_SLC_HOST_CLK_MODE_V 0x00000003U +#define SDIO_SLC_HOST_CLK_MODE_S 18 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sdio_slc_host_struct.h b/components/soc/esp32c5/register/soc/sdio_slc_host_struct.h new file mode 100644 index 0000000000..cb1290fca4 --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_slc_host_struct.h @@ -0,0 +1,2738 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ********Registers */ +/** Type of func2_0 register + * *******Description*********** + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slc_func2_int : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_host_func2_0_reg_t; + +/** Type of func2_1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func2_int_en : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_1_reg_t; + +/** Type of func2_2 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ + uint32_t slc_func1_mdstat:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_2_reg_t; + +/** Type of gpio_status0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status0_reg_t; + +/** Type of gpio_status1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status1_reg_t; + +/** Type of gpio_in0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in0_reg_t; + +/** Type of gpio_in1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in1_reg_t; + +/** Type of slc0host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0:12; + /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_token1:12; + /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_rdata_reg_t; + +/** Type of slc0_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc0_host_pf_reg_t; + +/** Type of slc1_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc1_host_pf_reg_t; + +/** Type of slc0host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_raw:1; + /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_raw:1; + /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_raw:1; + /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_raw:1; + /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_raw:1; + /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_raw:1; + /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_raw:1; + /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_raw:1; + /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_raw:1; + /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_raw:1; + /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_raw:1; + /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_raw:1; + /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_raw:1; + /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_raw:1; + /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_raw:1; + /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_raw:1; + /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_raw:1; + /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_raw:1; + /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_raw:1; + /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_raw_reg_t; + +/** Type of slc1host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_raw:1; + /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_raw:1; + /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_raw:1; + /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_raw:1; + /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_raw:1; + /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_raw:1; + /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_raw:1; + /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_raw:1; + /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_raw:1; + /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_raw:1; + /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_raw:1; + /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_raw:1; + /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_raw:1; + /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_raw:1; + /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_raw:1; + /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_raw:1; + /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_raw:1; + /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_raw:1; + /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_raw:1; + /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_raw_reg_t; + +/** Type of slc0host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_st:1; + /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_st:1; + /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_st:1; + /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_st:1; + /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_st:1; + /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_st:1; + /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_st:1; + /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_st:1; + /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_st:1; + /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_st:1; + /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_st:1; + /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_st:1; + /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_st:1; + /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_st:1; + /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_st:1; + /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_st:1; + /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_st:1; + /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_st:1; + /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_st:1; + /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_st_reg_t; + +/** Type of slc1host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_st:1; + /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_st:1; + /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_st:1; + /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_st:1; + /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_st:1; + /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_st:1; + /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_st:1; + /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_st:1; + /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_st:1; + /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_st:1; + /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_st:1; + /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_st:1; + /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_st:1; + /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_st:1; + /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_st:1; + /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_st:1; + /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_st:1; + /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_st:1; + /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_st:1; + /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_st_reg_t; + +/** Type of pkt_len register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len:20; + /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len_reg_t; + +/** Type of state_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state0:8; + /** slchost_state1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state1:8; + /** slchost_state2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state2:8; + /** slchost_state3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state3:8; + }; + uint32_t val; +} sdio_slc_host_state_w0_reg_t; + +/** Type of state_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state4:8; + /** slchost_state5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state5:8; + /** slchost_state6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state6:8; + /** slchost_state7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state7:8; + }; + uint32_t val; +} sdio_slc_host_state_w1_reg_t; + +/** Type of conf_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf0:8; + /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf1:8; + /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf2:8; + /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf3:8; + }; + uint32_t val; +} sdio_slc_host_conf_w0_reg_t; + +/** Type of conf_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf4:8; + /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf5:8; + /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf6:8; + /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf7:8; + }; + uint32_t val; +} sdio_slc_host_conf_w1_reg_t; + +/** Type of conf_w2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf8:8; + /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf9:8; + /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf10:8; + /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf11:8; + }; + uint32_t val; +} sdio_slc_host_conf_w2_reg_t; + +/** Type of conf_w3 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ + uint32_t slchost_conf12:8; + /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf13:8; + /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf14:8; + /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf15:8; + }; + uint32_t val; +} sdio_slc_host_conf_w3_reg_t; + +/** Type of conf_w4 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ + uint32_t slchost_conf16:8; + /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ + uint32_t slchost_conf17:8; + /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf18:8; + /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf19:8; + }; + uint32_t val; +} sdio_slc_host_conf_w4_reg_t; + +/** Type of conf_w5 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf20:8; + /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf21:8; + /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf22:8; + /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf23:8; + }; + uint32_t val; +} sdio_slc_host_conf_w5_reg_t; + +/** Type of win_cmd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_win_cmd:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_host_win_cmd_reg_t; + +/** Type of conf_w6 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf24:8; + /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf25:8; + /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf26:8; + /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf27:8; + }; + uint32_t val; +} sdio_slc_host_conf_w6_reg_t; + +/** Type of conf_w7 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf28:8; + /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf29:8; + /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf30:8; + /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf31:8; + }; + uint32_t val; +} sdio_slc_host_conf_w7_reg_t; + +/** Type of pkt_len0 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0:20; + /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len0_reg_t; + +/** Type of pkt_len1 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1:20; + /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len1_reg_t; + +/** Type of pkt_len2 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2:20; + /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len2_reg_t; + +/** Type of conf_w8 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf32:8; + /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf33:8; + /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf34:8; + /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf35:8; + }; + uint32_t val; +} sdio_slc_host_conf_w8_reg_t; + +/** Type of conf_w9 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf36:8; + /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf37:8; + /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf38:8; + /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf39:8; + }; + uint32_t val; +} sdio_slc_host_conf_w9_reg_t; + +/** Type of conf_w10 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf40:8; + /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf41:8; + /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf42:8; + /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf43:8; + }; + uint32_t val; +} sdio_slc_host_conf_w10_reg_t; + +/** Type of conf_w11 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf44:8; + /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf45:8; + /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf46:8; + /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf47:8; + }; + uint32_t val; +} sdio_slc_host_conf_w11_reg_t; + +/** Type of conf_w12 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf48:8; + /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf49:8; + /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf50:8; + /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf51:8; + }; + uint32_t val; +} sdio_slc_host_conf_w12_reg_t; + +/** Type of conf_w13 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf52:8; + /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf53:8; + /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf54:8; + /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf55:8; + }; + uint32_t val; +} sdio_slc_host_conf_w13_reg_t; + +/** Type of conf_w14 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf56:8; + /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf57:8; + /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf58:8; + /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf59:8; + }; + uint32_t val; +} sdio_slc_host_conf_w14_reg_t; + +/** Type of conf_w15 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf60:8; + /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf61:8; + /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf62:8; + /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ + uint32_t slchost_conf63:8; + }; + uint32_t val; +} sdio_slc_host_conf_w15_reg_t; + +/** Type of check_sum0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_check_sum0:32; + }; + uint32_t val; +} sdio_slc_host_check_sum0_reg_t; + +/** Type of check_sum1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ + uint32_t slchost_check_sum1:32; + }; + uint32_t val; +} sdio_slc_host_check_sum1_reg_t; + +/** Type of slc1host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0:12; + /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc1_token1:12; + /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_rdata_reg_t; + +/** Type of slc0host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wd:12; + uint32_t reserved_12:4; + /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_wdata_reg_t; + +/** Type of slc1host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wd:12; + uint32_t reserved_12:4; + /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_wdata_reg_t; + +/** Type of token_con register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_dec : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_dec:1; + /** slc0host_token1_dec : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_dec:1; + /** slc0host_token0_wr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wr:1; + /** slc0host_token1_wr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wr:1; + /** slc1host_token0_dec : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_dec:1; + /** slc1host_token1_dec : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_dec:1; + /** slc1host_token0_wr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wr:1; + /** slc1host_token1_wr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wr:1; + /** slc0host_len_wr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} sdio_slc_host_token_con_reg_t; + +/** Type of slc0host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_clr:1; + /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_clr:1; + /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_clr:1; + /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_clr:1; + /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_clr:1; + /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_clr:1; + /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_clr:1; + /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_clr:1; + /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_clr:1; + /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_clr:1; + /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_clr:1; + /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_clr:1; + /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_clr:1; + /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_clr:1; + /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_clr:1; + /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_clr:1; + /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_clr:1; + /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_clr:1; + /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_clr:1; + /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_clr_reg_t; + +/** Type of slc1host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_clr:1; + /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_clr:1; + /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_clr:1; + /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_clr:1; + /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_clr:1; + /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_clr:1; + /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_clr:1; + /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_clr:1; + /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_clr:1; + /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_clr:1; + /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_clr:1; + /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_clr:1; + /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_clr:1; + /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_clr:1; + /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_clr:1; + /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_clr:1; + /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_clr:1; + /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_clr:1; + /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_clr:1; + /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_clr_reg_t; + +/** Type of slc0host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit0_int_ena:1; + /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit1_int_ena:1; + /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit2_int_ena:1; + /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit3_int_ena:1; + /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit4_int_ena:1; + /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit5_int_ena:1; + /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit6_int_ena:1; + /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit7_int_ena:1; + /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_1to0_int_ena:1; + /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_1to0_int_ena:1; + /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_0to1_int_ena:1; + /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_0to1_int_ena:1; + /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_sof_int_ena:1; + /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_eof_int_ena:1; + /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_start_int_ena:1; + /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_tx_start_int_ena:1; + /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_udf_int_ena:1; + /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tx_ovf_int_ena:1; + /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_pf_valid_int_ena:1; + /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit0_int_ena:1; + /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit1_int_ena:1; + /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit2_int_ena:1; + /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit3_int_ena:1; + /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_new_packet_int_ena:1; + /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_host_rd_retry_int_ena:1; + /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func1_int_ena_reg_t; + +/** Type of slc1host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit0_int_ena:1; + /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit1_int_ena:1; + /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit2_int_ena:1; + /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit3_int_ena:1; + /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit4_int_ena:1; + /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit5_int_ena:1; + /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit6_int_ena:1; + /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit7_int_ena:1; + /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_1to0_int_ena:1; + /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_1to0_int_ena:1; + /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_0to1_int_ena:1; + /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_0to1_int_ena:1; + /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_sof_int_ena:1; + /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_eof_int_ena:1; + /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_start_int_ena:1; + /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_tx_start_int_ena:1; + /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_udf_int_ena:1; + /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tx_ovf_int_ena:1; + /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_pf_valid_int_ena:1; + /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit0_int_ena:1; + /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit1_int_ena:1; + /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit2_int_ena:1; + /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit3_int_ena:1; + /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1; + /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_host_rd_retry_int_ena:1; + /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func1_int_ena_reg_t; + +/** Type of slc0host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit0_int_ena:1; + /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit1_int_ena:1; + /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit2_int_ena:1; + /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit3_int_ena:1; + /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit4_int_ena:1; + /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit5_int_ena:1; + /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit6_int_ena:1; + /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit7_int_ena:1; + /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_1to0_int_ena:1; + /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_1to0_int_ena:1; + /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_0to1_int_ena:1; + /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_0to1_int_ena:1; + /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_sof_int_ena:1; + /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_eof_int_ena:1; + /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_start_int_ena:1; + /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_tx_start_int_ena:1; + /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_udf_int_ena:1; + /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tx_ovf_int_ena:1; + /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_pf_valid_int_ena:1; + /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit0_int_ena:1; + /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit1_int_ena:1; + /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit2_int_ena:1; + /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit3_int_ena:1; + /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_new_packet_int_ena:1; + /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_host_rd_retry_int_ena:1; + /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func2_int_ena_reg_t; + +/** Type of slc1host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit0_int_ena:1; + /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit1_int_ena:1; + /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit2_int_ena:1; + /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit3_int_ena:1; + /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit4_int_ena:1; + /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit5_int_ena:1; + /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit6_int_ena:1; + /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit7_int_ena:1; + /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_1to0_int_ena:1; + /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_1to0_int_ena:1; + /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_0to1_int_ena:1; + /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_0to1_int_ena:1; + /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_sof_int_ena:1; + /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_eof_int_ena:1; + /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_start_int_ena:1; + /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_tx_start_int_ena:1; + /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_udf_int_ena:1; + /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tx_ovf_int_ena:1; + /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_pf_valid_int_ena:1; + /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit0_int_ena:1; + /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit1_int_ena:1; + /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit2_int_ena:1; + /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit3_int_ena:1; + /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1; + /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_host_rd_retry_int_ena:1; + /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func2_int_ena_reg_t; + +/** Type of slc0host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena:1; + /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena:1; + /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena:1; + /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena:1; + /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena:1; + /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena:1; + /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena:1; + /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena:1; + /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena:1; + /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena:1; + /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena:1; + /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena:1; + /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena:1; + /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena:1; + /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena:1; + /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena:1; + /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena:1; + /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena:1; + /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena:1; + /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena_reg_t; + +/** Type of slc1host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena:1; + /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena:1; + /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena:1; + /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena:1; + /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena:1; + /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena:1; + /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena:1; + /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena:1; + /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena:1; + /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena:1; + /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena:1; + /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena:1; + /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena:1; + /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena:1; + /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena:1; + /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena:1; + /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena:1; + /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena:1; + /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena:1; + /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena_reg_t; + +/** Type of slc0host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc0host_rx_infor_reg_t; + +/** Type of slc1host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc1host_rx_infor_reg_t; + +/** Type of slc0host_len_wd register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wd:32; + }; + uint32_t val; +} sdio_slc_host_slc0host_len_wd_reg_t; + +/** Type of slc_apbwin_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_wdata_reg_t; + +/** Type of slc_apbwin_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_addr:28; + /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wr:1; + /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_start:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_conf_reg_t; + +/** Type of slc_apbwin_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_rdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_rdata_reg_t; + +/** Type of rdclr0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ + uint32_t slchost_slc0_bit7_clraddr:9; + /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc0_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr0_reg_t; + +/** Type of rdclr1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit7_clraddr:9; + /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr1_reg_t; + +/** Type of slc0host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena1:1; + /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena1:1; + /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena1:1; + /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena1:1; + /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena1:1; + /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena1:1; + /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena1:1; + /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena1:1; + /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena1:1; + /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena1:1; + /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena1:1; + /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena1:1; + /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena1:1; + /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena1:1; + /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena1:1; + /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena1:1; + /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena1:1; + /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena1:1; + /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena1:1; + /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena1_reg_t; + +/** Type of slc1host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena1:1; + /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena1:1; + /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena1:1; + /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena1:1; + /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena1:1; + /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena1:1; + /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena1:1; + /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena1:1; + /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena1:1; + /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena1:1; + /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena1:1; + /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena1:1; + /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena1:1; + /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena1:1; + /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena1:1; + /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena1:1; + /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena1:1; + /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena1:1; + /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena1:1; + /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena1_reg_t; + +/** Type of date register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_date : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ + uint32_t slchost_date:32; + }; + uint32_t val; +} sdio_slc_host_date_reg_t; + +/** Type of id register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_id : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ + uint32_t slchost_id:32; + }; + uint32_t val; +} sdio_slc_host_id_reg_t; + +/** Type of conf register + * *******Description*********** + */ +typedef union { + struct { + /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio11:5; + /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio20:5; + /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t frc_neg_samp:5; + /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ + uint32_t frc_pos_samp:5; + /** frc_quick_in : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ + uint32_t frc_quick_in:5; + /** sdio20_int_delay : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_int_delay:1; + /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ + uint32_t sdio_pad_pullup:1; + /** hspeed_con_en : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ + uint32_t hspeed_con_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_conf_reg_t; + +/** Type of inf_st register + * *******Description*********** + */ +typedef union { + struct { + /** sdio20_mode : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_mode:5; + /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t sdio_neg_samp:5; + /** sdio_quick_in : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t sdio_quick_in:5; + /** dll_on_sw : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ + uint32_t dll_on_sw:1; + /** dll_on : R/W; bitpos: [16]; default: 0; + * Software dll on + */ + uint32_t dll_on:1; + /** clk_mode_sw : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ + uint32_t clk_mode_sw:1; + /** clk_mode : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ + uint32_t clk_mode:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_inf_st_reg_t; + + +typedef struct { + uint32_t reserved_000[4]; + volatile sdio_slc_host_func2_0_reg_t func2_0; + volatile sdio_slc_host_func2_1_reg_t func2_1; + uint32_t reserved_018[2]; + volatile sdio_slc_host_func2_2_reg_t func2_2; + uint32_t reserved_024[4]; + volatile sdio_slc_host_gpio_status0_reg_t gpio_status0; + volatile sdio_slc_host_gpio_status1_reg_t gpio_status1; + volatile sdio_slc_host_gpio_in0_reg_t gpio_in0; + volatile sdio_slc_host_gpio_in1_reg_t gpio_in1; + volatile sdio_slc_host_slc0host_token_rdata_reg_t slc0host_token_rdata; + volatile sdio_slc_host_slc0_host_pf_reg_t slc0_host_pf; + volatile sdio_slc_host_slc1_host_pf_reg_t slc1_host_pf; + volatile sdio_slc_host_slc0host_int_raw_reg_t slc0host_int_raw; + volatile sdio_slc_host_slc1host_int_raw_reg_t slc1host_int_raw; + volatile sdio_slc_host_slc0host_int_st_reg_t slc0host_int_st; + volatile sdio_slc_host_slc1host_int_st_reg_t slc1host_int_st; + volatile sdio_slc_host_pkt_len_reg_t pkt_len; + volatile sdio_slc_host_state_w0_reg_t state_w0; + volatile sdio_slc_host_state_w1_reg_t state_w1; + volatile sdio_slc_host_conf_w0_reg_t conf_w0; + volatile sdio_slc_host_conf_w1_reg_t conf_w1; + volatile sdio_slc_host_conf_w2_reg_t conf_w2; + volatile sdio_slc_host_conf_w3_reg_t conf_w3; + volatile sdio_slc_host_conf_w4_reg_t conf_w4; + volatile sdio_slc_host_conf_w5_reg_t conf_w5; + volatile sdio_slc_host_win_cmd_reg_t win_cmd; + volatile sdio_slc_host_conf_w6_reg_t conf_w6; + volatile sdio_slc_host_conf_w7_reg_t conf_w7; + volatile sdio_slc_host_pkt_len0_reg_t pkt_len0; + volatile sdio_slc_host_pkt_len1_reg_t pkt_len1; + volatile sdio_slc_host_pkt_len2_reg_t pkt_len2; + volatile sdio_slc_host_conf_w8_reg_t conf_w8; + volatile sdio_slc_host_conf_w9_reg_t conf_w9; + volatile sdio_slc_host_conf_w10_reg_t conf_w10; + volatile sdio_slc_host_conf_w11_reg_t conf_w11; + volatile sdio_slc_host_conf_w12_reg_t conf_w12; + volatile sdio_slc_host_conf_w13_reg_t conf_w13; + volatile sdio_slc_host_conf_w14_reg_t conf_w14; + volatile sdio_slc_host_conf_w15_reg_t conf_w15; + volatile sdio_slc_host_check_sum0_reg_t check_sum0; + volatile sdio_slc_host_check_sum1_reg_t check_sum1; + volatile sdio_slc_host_slc1host_token_rdata_reg_t slc1host_token_rdata; + volatile sdio_slc_host_slc0host_token_wdata_reg_t slc0host_token_wdata; + volatile sdio_slc_host_slc1host_token_wdata_reg_t slc1host_token_wdata; + volatile sdio_slc_host_token_con_reg_t token_con; + volatile sdio_slc_host_slc0host_int_clr_reg_t slc0host_int_clr; + volatile sdio_slc_host_slc1host_int_clr_reg_t slc1host_int_clr; + volatile sdio_slc_host_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena; + volatile sdio_slc_host_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena; + volatile sdio_slc_host_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena; + volatile sdio_slc_host_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena; + volatile sdio_slc_host_slc0host_int_ena_reg_t slc0host_int_ena; + volatile sdio_slc_host_slc1host_int_ena_reg_t slc1host_int_ena; + volatile sdio_slc_host_slc0host_rx_infor_reg_t slc0host_rx_infor; + volatile sdio_slc_host_slc1host_rx_infor_reg_t slc1host_rx_infor; + volatile sdio_slc_host_slc0host_len_wd_reg_t slc0host_len_wd; + volatile sdio_slc_host_slc_apbwin_wdata_reg_t slc_apbwin_wdata; + volatile sdio_slc_host_slc_apbwin_conf_reg_t slc_apbwin_conf; + volatile sdio_slc_host_slc_apbwin_rdata_reg_t slc_apbwin_rdata; + volatile sdio_slc_host_rdclr0_reg_t rdclr0; + volatile sdio_slc_host_rdclr1_reg_t rdclr1; + volatile sdio_slc_host_slc0host_int_ena1_reg_t slc0host_int_ena1; + volatile sdio_slc_host_slc1host_int_ena1_reg_t slc1host_int_ena1; + uint32_t reserved_11c[23]; + volatile sdio_slc_host_date_reg_t date; + volatile sdio_slc_host_id_reg_t id; + uint32_t reserved_180[28]; + volatile sdio_slc_host_conf_reg_t conf; + volatile sdio_slc_host_inf_st_reg_t inf_st; +} host_dev_t; + +extern host_dev_t HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sdio_slc_reg.h b/components/soc/esp32c5/register/soc/sdio_slc_reg.h new file mode 100644 index 0000000000..77ba56bd63 --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_slc_reg.h @@ -0,0 +1,4382 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_CONF0_REG register + * Sdio slave DMA configuration register. + */ +#define SDIO_SLC_CONF0_REG (DR_REG_SDIO_BASE + 0x0) +/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ +#define SDIO_SLC0_TX_RST (BIT(0)) +#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) +#define SDIO_SLC0_TX_RST_V 0x00000001U +#define SDIO_SLC0_TX_RST_S 0 +/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ +#define SDIO_SLC0_RX_RST (BIT(1)) +#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) +#define SDIO_SLC0_RX_RST_V 0x00000001U +#define SDIO_SLC0_RX_RST_S 1 +/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) +#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) +#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U +#define SDIO_SLC_AHBM_FIFO_RST_S 2 +/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_RST (BIT(3)) +#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) +#define SDIO_SLC_AHBM_RST_V 0x00000001U +#define SDIO_SLC_AHBM_RST_S 3 +/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) +#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) +#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_TX_LOOP_TEST_S 4 +/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) +#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) +#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_RX_LOOP_TEST_S 5 +/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) +#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 +/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ +#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) +#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 +/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) +#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 +/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) +#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_EN_S 9 +/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) +#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 +/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) +#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 +/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) +#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 +/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) +#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_EN_S 13 +/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ +#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) +#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 +/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ +#define SDIO_SLC0_TOKEN_SEL (BIT(15)) +#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) +#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC0_TOKEN_SEL_S 15 +/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ +#define SDIO_SLC1_TX_RST (BIT(16)) +#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) +#define SDIO_SLC1_TX_RST_V 0x00000001U +#define SDIO_SLC1_TX_RST_S 16 +/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ +#define SDIO_SLC1_RX_RST (BIT(17)) +#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) +#define SDIO_SLC1_RX_RST_V 0x00000001U +#define SDIO_SLC1_RX_RST_S 17 +/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) +#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 +/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) +#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 +/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) +#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) +#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_TX_LOOP_TEST_S 20 +/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) +#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) +#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_RX_LOOP_TEST_S 21 +/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ +#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) +#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 +/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ +#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) +#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 +/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ +#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) +#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 +/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ +#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) +#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_EN_S 25 +/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) +#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 +/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) +#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 +/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ +#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) +#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 +/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ +#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) +#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_EN_S 29 +/** SDIO_SLC_1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC_1_TOKEN_SEL (BIT(31)) +#define SDIO_SLC_1_TOKEN_SEL_M (SDIO_SLC_1_TOKEN_SEL_V << SDIO_SLC_1_TOKEN_SEL_S) +#define SDIO_SLC_1_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC_1_TOKEN_SEL_S 31 + +/** SDIO_SLC_SLC0INT_RAW_REG register + * Sdio slave DMA channel0 raw interrupt status register. + */ +#define SDIO_SLC_SLC0INT_RAW_REG (DR_REG_SDIO_BASE + 0x4) +/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ +#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) +#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_RAW_S 8 +/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ +#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) +#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_RAW_S 9 +/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ +#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ +#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ +#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) +#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ +#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) +#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ +#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) +#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_RAW_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ +#define SDIO_CMD_DTC_INT_RAW (BIT(25)) +#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) +#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U +#define SDIO_CMD_DTC_INT_RAW_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ +#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) +#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 + +/** SDIO_SLC_SLC0INT_ST_REG register + * Sdio slave DMA channel0 masked interrupt status register. + */ +#define SDIO_SLC_SLC0INT_ST_REG (DR_REG_SDIO_BASE + 0x8) +/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) +#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST_S 8 +/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) +#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) +#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) +#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) +#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST_S 17 +/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) +#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 +/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST (BIT(25)) +#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) +#define SDIO_CMD_DTC_INT_ST_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) +#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST_S 28 + +/** SDIO_SLC_SLC0INT_ENA_REG register + * Sdio slave DMA channel0 interrupt enable register. + */ +#define SDIO_SLC_SLC0INT_ENA_REG (DR_REG_SDIO_BASE + 0xc) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) +#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA_S 8 +/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) +#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) +#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) +#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) +#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) +#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) +#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 + +/** SDIO_SLC_SLC0INT_CLR_REG register + * Sdio slave DMA channel0 interrupt clear register. + */ +#define SDIO_SLC_SLC0INT_CLR_REG (DR_REG_SDIO_BASE + 0x10) +/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) +#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_CLR_S 8 +/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) +#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_CLR_S 9 +/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) +#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) +#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) +#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_CLR_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_CLR (BIT(25)) +#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) +#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U +#define SDIO_CMD_DTC_INT_CLR_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) +#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 + +/** SDIO_SLC_SLC1INT_RAW_REG register + * Sdio slave DMA channel1 raw interrupt status register. + */ +#define SDIO_SLC_SLC1INT_RAW_REG (DR_REG_SDIO_BASE + 0x14) +/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 +/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ +#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) +#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_RAW_S 8 +/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ +#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) +#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_RAW_S 9 +/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ +#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ +#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ +#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) +#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ +#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) +#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ +#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) +#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) +#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_RAW_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 + +/** SDIO_SLC_SLC1INT_ST_REG register + * Sdio slave DMA channel1 masked interrupt status register. + */ +#define SDIO_SLC_SLC1INT_ST_REG (DR_REG_SDIO_BASE + 0x18) +/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 +/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) +#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST_S 8 +/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) +#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) +#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) +#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) +#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST_S 17 +/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) +#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 + +/** SDIO_SLC_SLC1INT_ENA_REG register + * Sdio slave DMA channel1 interrupt enable register. + */ +#define SDIO_SLC_SLC1INT_ENA_REG (DR_REG_SDIO_BASE + 0x1c) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 +/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) +#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA_S 8 +/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) +#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) +#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) +#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) +#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) +#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 + +/** SDIO_SLC_SLC1INT_CLR_REG register + * Sdio slave DMA channel1 interrupt clear register. + */ +#define SDIO_SLC_SLC1INT_CLR_REG (DR_REG_SDIO_BASE + 0x20) +/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 +/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) +#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_CLR_S 8 +/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) +#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_CLR_S 9 +/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) +#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) +#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) +#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) +#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_CLR_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 + +/** SDIO_SLC_RX_STATUS_REG register + * Sdio slave DMA rxfifo status register. + */ +#define SDIO_SLC_RX_STATUS_REG (DR_REG_SDIO_BASE + 0x24) +/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_FULL (BIT(0)) +#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) +#define SDIO_SLC0_RX_FULL_V 0x00000001U +#define SDIO_SLC0_RX_FULL_S 0 +/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_EMPTY (BIT(1)) +#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) +#define SDIO_SLC0_RX_EMPTY_V 0x00000001U +#define SDIO_SLC0_RX_EMPTY_S 1 +/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ +#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) +#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_S 2 +/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_FULL (BIT(16)) +#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) +#define SDIO_SLC1_RX_FULL_V 0x00000001U +#define SDIO_SLC1_RX_FULL_S 16 +/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_EMPTY (BIT(17)) +#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) +#define SDIO_SLC1_RX_EMPTY_V 0x00000001U +#define SDIO_SLC1_RX_EMPTY_S 17 +/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ +#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) +#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_S 18 + +/** SDIO_SLC_SLC0RXFIFO_PUSH_REG register + * Sdio slave DMA channel0 rxfifo debug register. + */ +#define SDIO_SLC_SLC0RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x28) +/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) +#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_S 0 +/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) +#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC0_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_SLC1RXFIFO_PUSH_REG register + * Sdio slave DMA channel1 rxfifo debug register. + */ +#define SDIO_SLC_SLC1RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x2c) +/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) +#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_S 0 +/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) +#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC1_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_TX_STATUS_REG register + * Sdio slave DMA txfifo status register. + */ +#define SDIO_SLC_TX_STATUS_REG (DR_REG_SDIO_BASE + 0x30) +/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_FULL (BIT(0)) +#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) +#define SDIO_SLC0_TX_FULL_V 0x00000001U +#define SDIO_SLC0_TX_FULL_S 0 +/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_EMPTY (BIT(1)) +#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) +#define SDIO_SLC0_TX_EMPTY_V 0x00000001U +#define SDIO_SLC0_TX_EMPTY_S 1 +/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_FULL (BIT(16)) +#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) +#define SDIO_SLC1_TX_FULL_V 0x00000001U +#define SDIO_SLC1_TX_FULL_S 16 +/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_EMPTY (BIT(17)) +#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) +#define SDIO_SLC1_TX_EMPTY_V 0x00000001U +#define SDIO_SLC1_TX_EMPTY_S 17 + +/** SDIO_SLC_SLC0TXFIFO_POP_REG register + * Sdio slave DMA channel0 txfifo debug register. + */ +#define SDIO_SLC_SLC0TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x34) +/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) +#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_S 0 +/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ +#define SDIO_SLC0_TXFIFO_POP (BIT(16)) +#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) +#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC0_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC1TXFIFO_POP_REG register + * Sdio slave DMA channel1 txfifo debug register. + */ +#define SDIO_SLC_SLC1TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x38) +/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) +#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_S 0 +/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ +#define SDIO_SLC1_TXFIFO_POP (BIT(16)) +#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) +#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC1_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC0RX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC0RX_LINK_REG (DR_REG_SDIO_BASE + 0x3c) +/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ +#define SDIO_SLC0_RXLINK_STOP (BIT(28)) +#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) +#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_RXLINK_STOP_S 28 +/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC0_RXLINK_START (BIT(29)) +#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) +#define SDIO_SLC0_RXLINK_START_V 0x00000001U +#define SDIO_SLC0_RXLINK_START_S 29 +/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ +#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) +#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_RXLINK_RESTART_S 30 +/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_RXLINK_PARK (BIT(31)) +#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) +#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0RX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC0RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x40) +/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ +#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) +#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC0TX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC0TX_LINK_REG (DR_REG_SDIO_BASE + 0x44) +/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ +#define SDIO_SLC0_TXLINK_STOP (BIT(28)) +#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) +#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_TXLINK_STOP_S 28 +/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC0_TXLINK_START (BIT(29)) +#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) +#define SDIO_SLC0_TXLINK_START_V 0x00000001U +#define SDIO_SLC0_TXLINK_START_S 29 +/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ +#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) +#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_TXLINK_RESTART_S 30 +/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_TXLINK_PARK (BIT(31)) +#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) +#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0TX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC0TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x48) +/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ +#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) +#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1RX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC1RX_LINK_REG (DR_REG_SDIO_BASE + 0x4c) +/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ +#define SDIO_SLC1_BT_PACKET (BIT(20)) +#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) +#define SDIO_SLC1_BT_PACKET_V 0x00000001U +#define SDIO_SLC1_BT_PACKET_S 20 +/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ +#define SDIO_SLC1_RXLINK_STOP (BIT(28)) +#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) +#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_RXLINK_STOP_S 28 +/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC1_RXLINK_START (BIT(29)) +#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) +#define SDIO_SLC1_RXLINK_START_V 0x00000001U +#define SDIO_SLC1_RXLINK_START_S 29 +/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ +#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) +#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_RXLINK_RESTART_S 30 +/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_RXLINK_PARK (BIT(31)) +#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) +#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1RX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC1RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x50) +/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ +#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) +#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1TX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC1TX_LINK_REG (DR_REG_SDIO_BASE + 0x54) +/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ +#define SDIO_SLC1_TXLINK_STOP (BIT(28)) +#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) +#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_TXLINK_STOP_S 28 +/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC1_TXLINK_START (BIT(29)) +#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) +#define SDIO_SLC1_TXLINK_START_V 0x00000001U +#define SDIO_SLC1_TXLINK_START_S 29 +/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ +#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) +#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_TXLINK_RESTART_S 30 +/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_TXLINK_PARK (BIT(31)) +#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) +#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1TX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC1TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x58) +/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ +#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) +#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLCINTVEC_TOHOST_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLCINTVEC_TOHOST_REG (DR_REG_SDIO_BASE + 0x5c) +/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ +#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) +#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_S 0 +/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ +#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) +#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_S 16 + +/** SDIO_SLC_SLC0TOKEN0_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC0TOKEN0_REG (DR_REG_SDIO_BASE + 0x60) +/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) +#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_S 0 +/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ +#define SDIO_SLC0_TOKEN0_WR (BIT(12)) +#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) +#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_WR_S 12 +/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ +#define SDIO_SLC0_TOKEN0_INC (BIT(13)) +#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) +#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_S 13 +/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ +#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) +#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) +#define SDIO_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_S 16 + +/** SDIO_SLC_SLC0TOKEN1_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC0TOKEN1_REG (DR_REG_SDIO_BASE + 0x64) +/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) +#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_S 0 +/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ +#define SDIO_SLC0_TOKEN1_WR (BIT(12)) +#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) +#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_WR_S 12 +/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC (BIT(13)) +#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) +#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_S 13 +/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ +#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) +#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) +#define SDIO_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_S 16 + +/** SDIO_SLC_SLC1TOKEN0_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC1TOKEN0_REG (DR_REG_SDIO_BASE + 0x68) +/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) +#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_S 0 +/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ +#define SDIO_SLC1_TOKEN0_WR (BIT(12)) +#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) +#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_WR_S 12 +/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ +#define SDIO_SLC1_TOKEN0_INC (BIT(13)) +#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) +#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_S 13 +/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ +#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) +#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) +#define SDIO_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_S 16 + +/** SDIO_SLC_SLC1TOKEN1_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC1TOKEN1_REG (DR_REG_SDIO_BASE + 0x6c) +/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) +#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_S 0 +/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ +#define SDIO_SLC1_TOKEN1_WR (BIT(12)) +#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) +#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_WR_S 12 +/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ +#define SDIO_SLC1_TOKEN1_INC (BIT(13)) +#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) +#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_S 13 +/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ +#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) +#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) +#define SDIO_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_S 16 + +/** SDIO_SLC_CONF1_REG register + * Sdio slave DMA configuration1 register. + */ +#define SDIO_SLC_CONF1_REG (DR_REG_SDIO_BASE + 0x70) +/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ +#define SDIO_SLC0_CHECK_OWNER (BIT(0)) +#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) +#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC0_CHECK_OWNER_S 0 +/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ +#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) +#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 +/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ +#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) +#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 +/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ +#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) +#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) +#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U +#define SDIO_SDIO_CMD_HOLD_EN_S 3 +/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ +#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) +#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_LEN_AUTO_CLR_S 4 +/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ +#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) +#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) +#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_TX_STITCH_EN_S 5 +/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ +#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) +#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) +#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_RX_STITCH_EN_S 6 +/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ +#define SDIO_SLC1_CHECK_OWNER (BIT(16)) +#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) +#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC1_CHECK_OWNER_S 16 +/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ +#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) +#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 +/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ +#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) +#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 +/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ +#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) +#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) +#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U +#define SDIO_HOST_INT_LEVEL_SEL_S 19 +/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ +#define SDIO_SDIO_CLK_EN (BIT(22)) +#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) +#define SDIO_SDIO_CLK_EN_V 0x00000001U +#define SDIO_SDIO_CLK_EN_S 22 + +/** SDIO_SLC_SLC0_STATE0_REG register + * Sdio slave DMA channel0 status register. + */ +#define SDIO_SLC_SLC0_STATE0_REG (DR_REG_SDIO_BASE + 0x74) +/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC0_STATE0 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) +#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_S 0 + +/** SDIO_SLC_SLC0_STATE1_REG register + * Sdio slave DMA channel0 status1 register. + */ +#define SDIO_SLC_SLC0_STATE1_REG (DR_REG_SDIO_BASE + 0x78) +/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC0_STATE1 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) +#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_S 0 + +/** SDIO_SLC_SLC1_STATE0_REG register + * Sdio slave DMA channel1 status register. + */ +#define SDIO_SLC_SLC1_STATE0_REG (DR_REG_SDIO_BASE + 0x7c) +/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC1_STATE0 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) +#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_S 0 + +/** SDIO_SLC_SLC1_STATE1_REG register + * Sdio slave DMA channel1 status1 register. + */ +#define SDIO_SLC_SLC1_STATE1_REG (DR_REG_SDIO_BASE + 0x80) +/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC1_STATE1 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) +#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_S 0 + +/** SDIO_SLC_BRIDGE_CONF_REG register + * Sdio slave DMA bridge configuration register. + */ +#define SDIO_SLC_BRIDGE_CONF_REG (DR_REG_SDIO_BASE + 0x84) +/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ +#define SDIO_SLC_TXEOF_ENA 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) +#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_S 0 +/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ +#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) +#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_S 8 +/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ +#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) +#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC0_TX_DUMMY_MODE_S 12 +/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ +#define SDIO_SLC_HDA_MAP_128K (BIT(13)) +#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) +#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U +#define SDIO_SLC_HDA_MAP_128K_S 13 +/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ +#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) +#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC1_TX_DUMMY_MODE_S 14 +/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; + * reserved + */ +#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) +#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 + +/** SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x88) +/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 receiving packet status register. + */ +#define SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x8c) +/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x90) +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x94) +/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 receiving packet status register. + */ +#define SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x98) +/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x9c) +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_AHB_TEST_REG register + * Sdio slave AHB test register. + */ +#define SDIO_SLC_AHB_TEST_REG (DR_REG_SDIO_BASE + 0xa0) +/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ +#define SDIO_SLC_AHB_TESTMODE 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) +#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_S 0 +/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ +#define SDIO_SLC_AHB_TESTADDR 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) +#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_S 4 + +/** SDIO_SLC_SDIO_ST_REG register + * Sdio slave function status register. + */ +#define SDIO_SLC_SDIO_ST_REG (DR_REG_SDIO_BASE + 0xa4) +/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ +#define SDIO_CMD_ST 0x00000007U +#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) +#define SDIO_CMD_ST_V 0x00000007U +#define SDIO_CMD_ST_S 0 +/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ +#define SDIO_FUNC_ST 0x0000000FU +#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) +#define SDIO_FUNC_ST_V 0x0000000FU +#define SDIO_FUNC_ST_S 4 +/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SDIO_WAKEUP (BIT(8)) +#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) +#define SDIO_SDIO_WAKEUP_V 0x00000001U +#define SDIO_SDIO_WAKEUP_S 8 +/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ +#define SDIO_BUS_ST 0x00000007U +#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) +#define SDIO_BUS_ST_V 0x00000007U +#define SDIO_BUS_ST_S 12 +/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ +#define SDIO_FUNC1_ACC_STATE 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) +#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_S 16 +/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ +#define SDIO_FUNC2_ACC_STATE 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) +#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_S 24 + +/** SDIO_SLC_RX_DSCR_CONF_REG register + * Sdio slave sending descriptor configuration register. + */ +#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xa8) +/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) +#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 +/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) +#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 +/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) +#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) +#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC0_RX_FILL_MODE_S 2 +/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ +#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) +#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) +#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC0_RX_EOF_MODE_S 3 +/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_FILL_EN (BIT(4)) +#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) +#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC0_RX_FILL_EN_S 4 +/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; + * reserved + */ +#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 +/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) +#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 +/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) +#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 +/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) +#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) +#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC1_RX_FILL_MODE_S 18 +/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ +#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) +#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) +#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC1_RX_EOF_MODE_S 19 +/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_FILL_EN (BIT(20)) +#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) +#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC1_RX_FILL_EN_S 20 +/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; + * reserved + */ +#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xac) +/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) +#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xb0) +/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) +#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xb4) +/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) +#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xb8) +/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) +#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xbc) +/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) +#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xc0) +/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) +#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xc4) +/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) +#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xc8) +/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) +#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xcc) +/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) +#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xd0) +/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) +#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xd4) +/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) +#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xd8) +/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) +#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xdc) +/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xe0) +/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_TOKEN_LAT_REG register + * reserved + */ +#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SDIO_BASE + 0xe4) +/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN 0x00000FFFU +#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) +#define SDIO_SLC0_TOKEN_V 0x00000FFFU +#define SDIO_SLC0_TOKEN_S 0 +/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN 0x00000FFFU +#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) +#define SDIO_SLC1_TOKEN_V 0x00000FFFU +#define SDIO_SLC1_TOKEN_S 16 + +/** SDIO_SLC_TX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xe8) +/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; + * reserved + */ +#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) +#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 + +/** SDIO_SLC_CMD_INFOR0_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SDIO_BASE + 0xec) +/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT0 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) +#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_S 0 + +/** SDIO_SLC_CMD_INFOR1_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SDIO_BASE + 0xf0) +/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT1 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) +#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_S 0 + +/** SDIO_SLC_SLC0_LEN_CONF_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LEN_CONF_REG (DR_REG_SDIO_BASE + 0xf4) +/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ +#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) +#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_S 0 +/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ +#define SDIO_SLC0_LEN_WR (BIT(20)) +#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) +#define SDIO_SLC0_LEN_WR_V 0x00000001U +#define SDIO_SLC0_LEN_WR_S 20 +/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC (BIT(21)) +#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) +#define SDIO_SLC0_LEN_INC_V 0x00000001U +#define SDIO_SLC0_LEN_INC_S 21 +/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) +#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) +#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U +#define SDIO_SLC0_LEN_INC_MORE_S 22 +/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 +/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 +/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ +#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) +#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 +/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ +#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) +#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 +/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ +#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) +#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 +/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ +#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) +#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 +/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 +/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 + +/** SDIO_SLC_SLC0_LENGTH_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LENGTH_REG (DR_REG_SDIO_BASE + 0xf8) +/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ +#define SDIO_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) +#define SDIO_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC0_LEN_S 0 + +/** SDIO_SLC_SLC0_TXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0xfc) +/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x100) +/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0x104) +/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x108) +/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x10c) +/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x110) +/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x114) +/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x118) +/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SEQ_POSITION_REG register + * The position of receiving packet configuration register. + */ +#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SDIO_BASE + 0x11c) +/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ +#define SDIO_SLC0_SEQ_POSITION 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) +#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_S 0 +/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ +#define SDIO_SLC1_SEQ_POSITION 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) +#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_S 8 + +/** SDIO_SLC_SLC0_DSCR_REC_CONF_REG register + * Sdio slave DMA sending linked list limit configuration register. + */ +#define SDIO_SLC_SLC0_DSCR_REC_CONF_REG (DR_REG_SDIO_BASE + 0x120) +/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ +#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) +#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 + +/** SDIO_SLC_SDIO_CRC_ST0_REG register + * Sdio slave receiving packet data crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SDIO_BASE + 0x124) +/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ +#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) +#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_S 0 +/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ +#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) +#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_S 8 +/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ +#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) +#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_S 16 +/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ +#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) +#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_S 24 + +/** SDIO_SLC_SDIO_CRC_ST1_REG register + * Sdio slave receiving command crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SDIO_BASE + 0x128) +/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ +#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) +#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_S 0 +/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ +#define SDIO_ERR_CNT_CLR (BIT(31)) +#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) +#define SDIO_ERR_CNT_CLR_V 0x00000001U +#define SDIO_ERR_CNT_CLR_S 31 + +/** SDIO_SLC_SLC0_EOF_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_EOF_START_DES_REG (DR_REG_SDIO_BASE + 0x12c) +/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) +#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x130) +/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +#define SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x134) +/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ +#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_SUB_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_SUB_START_DES_REG (DR_REG_SDIO_BASE + 0x138) +/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DSCR_CNT_REG register + * Sdio slave DMA channel0 descriptor status register. + */ +#define SDIO_SLC_SLC0_DSCR_CNT_REG (DR_REG_SDIO_BASE + 0x13c) +/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ +#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) +#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 +/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ +#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) +#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U +#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 + +/** SDIO_SLC_SLC0_LEN_LIM_CONF_REG register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +#define SDIO_SLC_SLC0_LEN_LIM_CONF_REG (DR_REG_SDIO_BASE + 0x140) +/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ +#define SDIO_SLC0_LEN_LIM 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) +#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_S 0 + +/** SDIO_SLC_SLC0INT_ST1_REG register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +#define SDIO_SLC_SLC0INT_ST1_REG (DR_REG_SDIO_BASE + 0x144) +/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 +/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) +#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST1_S 8 +/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) +#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) +#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) +#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) +#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) +#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) +#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) +#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) +#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 + +/** SDIO_SLC_SLC0INT_ENA1_REG register + * Sdio slave DMA channel0 interrupt enable register1. + */ +#define SDIO_SLC_SLC0INT_ENA1_REG (DR_REG_SDIO_BASE + 0x148) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) +#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA1_S 8 +/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) +#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) +#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) +#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) +#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) +#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) +#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 + +/** SDIO_SLC_SLC1INT_ST1_REG register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +#define SDIO_SLC_SLC1INT_ST1_REG (DR_REG_SDIO_BASE + 0x14c) +/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 +/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) +#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST1_S 8 +/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) +#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) +#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) +#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) +#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) +#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) +#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) +#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 + +/** SDIO_SLC_SLC1INT_ENA1_REG register + * Sdio slave DMA channel1 interrupt enable register1. + */ +#define SDIO_SLC_SLC1INT_ENA1_REG (DR_REG_SDIO_BASE + 0x150) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 +/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) +#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA1_S 8 +/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) +#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) +#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) +#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) +#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) +#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x154) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x158) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x15c) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x160) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x164) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x168) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x16c) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x170) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_HDA_TX_SHAREMEM_START_REG register + * Sdio slave HAD receiving address range register. + */ +#define SDIO_SLC_HDA_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x174) +/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_HDA_RX_SHAREMEM_START_REG register + * Sdio slave HAD sending address range register. + */ +#define SDIO_SLC_HDA_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x178) +/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_BURST_LEN_REG register + * Sdio slave AHB burst type configuration register. + */ +#define SDIO_SLC_BURST_LEN_REG (DR_REG_SDIO_BASE + 0x17c) +/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) +#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) +#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 +/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) +#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) +#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 +/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) +#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) +#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 +/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) +#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) +#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 + +/** SDIO_SLC_DATE_REG register + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE_REG (DR_REG_SDIO_BASE + 0x1f8) +/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE 0xFFFFFFFFU +#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) +#define SDIO_SLC_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_DATE_S 0 + +/** SDIO_SLC_ID_REG register + * Sdio slave ID register. + */ +#define SDIO_SLC_ID_REG (DR_REG_SDIO_BASE + 0x1fc) +/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; + * reserved + */ +#define SDIO_SLC_ID 0xFFFFFFFFU +#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) +#define SDIO_SLC_ID_V 0xFFFFFFFFU +#define SDIO_SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sdio_slc_struct.h b/components/soc/esp32c5/register/soc/sdio_slc_struct.h new file mode 100644 index 0000000000..85ee76e355 --- /dev/null +++ b/components/soc/esp32c5/register/soc/sdio_slc_struct.h @@ -0,0 +1,3345 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of slc_conf0 register + * Sdio slave DMA configuration register. + */ +typedef union { + struct { + /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ + uint32_t slc0_tx_rst:1; + /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ + uint32_t slc0_rx_rst:1; + /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ + uint32_t slc_ahbm_fifo_rst:1; + /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ + uint32_t slc_ahbm_rst:1; + /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ + uint32_t slc0_tx_loop_test:1; + /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ + uint32_t slc0_rx_loop_test:1; + /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc0_rx_auto_wrback:1; + /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ + uint32_t slc0_rx_no_restart_clr:1; + /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ + uint32_t slc0_rxdscr_burst_en:1; + /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc0_rxdata_burst_en:1; + /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_rxlink_auto_ret:1; + /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_txlink_auto_ret:1; + /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ + uint32_t slc0_txdscr_burst_en:1; + /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc0_txdata_burst_en:1; + /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ + uint32_t slc0_token_auto_clr:1; + /** slc0_token_sel : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ + uint32_t slc0_token_sel:1; + /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ + uint32_t slc1_tx_rst:1; + /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ + uint32_t slc1_rx_rst:1; + /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc0_wr_retry_mask_en:1; + /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc1_wr_retry_mask_en:1; + /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_tx_loop_test:1; + /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_rx_loop_test:1; + /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ + uint32_t slc1_rx_auto_wrback:1; + /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ + uint32_t slc1_rx_no_restart_clr:1; + /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ + uint32_t slc1_rxdscr_burst_en:1; + /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ + uint32_t slc1_rxdata_burst_en:1; + /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_rxlink_auto_ret:1; + /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_txlink_auto_ret:1; + /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ + uint32_t slc1_txdscr_burst_en:1; + /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ + uint32_t slc1_txdata_burst_en:1; + uint32_t reserved_30:1; + /** slc_1_token_sel : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc_1_token_sel:1; + }; + uint32_t val; +} sdio_slc_conf0_reg_t; + +/** Type of slc_slc0rxfifo_push register + * Sdio slave DMA channel0 rxfifo debug register. + */ +typedef union { + struct { + /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc0_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ + uint32_t slc0_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0rxfifo_push_reg_t; + +/** Type of slc_slc1rxfifo_push register + * Sdio slave DMA channel1 rxfifo debug register. + */ +typedef union { + struct { + /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc1_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ + uint32_t slc1_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1rxfifo_push_reg_t; + +/** Type of slc_slc0rx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ + uint32_t slc0_rxlink_stop:1; + /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc0_rxlink_start:1; + /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ + uint32_t slc0_rxlink_restart:1; + /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ + uint32_t slc0_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0rx_link_reg_t; + +/** Type of slc_slc0rx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ + uint32_t slc0_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0rx_link_addr_reg_t; + +/** Type of slc_slc0tx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ + uint32_t slc0_txlink_stop:1; + /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc0_txlink_start:1; + /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ + uint32_t slc0_txlink_restart:1; + /** slc0_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ + uint32_t slc0_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0tx_link_reg_t; + +/** Type of slc_slc0tx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ + uint32_t slc0_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0tx_link_addr_reg_t; + +/** Type of slc_slc1rx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ + uint32_t slc1_bt_packet:1; + uint32_t reserved_21:7; + /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ + uint32_t slc1_rxlink_stop:1; + /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc1_rxlink_start:1; + /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ + uint32_t slc1_rxlink_restart:1; + /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ + uint32_t slc1_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1rx_link_reg_t; + +/** Type of slc_slc1rx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ + uint32_t slc1_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1rx_link_addr_reg_t; + +/** Type of slc_slc1tx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ + uint32_t slc1_txlink_stop:1; + /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc1_txlink_start:1; + /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ + uint32_t slc1_txlink_restart:1; + /** slc1_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ + uint32_t slc1_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1tx_link_reg_t; + +/** Type of slc_slc1tx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ + uint32_t slc1_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1tx_link_addr_reg_t; + +/** Type of slc_slcintvec_tohost register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ + uint32_t slc0_tohost_intvec:8; + uint32_t reserved_8:8; + /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ + uint32_t slc1_tohost_intvec:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdio_slc_slcintvec_tohost_reg_t; + +/** Type of slc_slc0token0 register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token0_wdata:12; + /** slc0_token0_wr : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ + uint32_t slc0_token0_wr:1; + /** slc0_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ + uint32_t slc0_token0_inc:1; + /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ + uint32_t slc0_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token0_reg_t; + +/** Type of slc_slc0token1 register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token1_wdata:12; + /** slc0_token1_wr : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ + uint32_t slc0_token1_wr:1; + /** slc0_token1_inc : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ + uint32_t slc0_token1_inc:1; + /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ + uint32_t slc0_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token1_reg_t; + +/** Type of slc_slc1token0 register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token0_wdata:12; + /** slc1_token0_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ + uint32_t slc1_token0_wr:1; + /** slc1_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ + uint32_t slc1_token0_inc:1; + /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ + uint32_t slc1_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token0_reg_t; + +/** Type of slc_slc1token1 register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token1_wdata:12; + /** slc1_token1_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ + uint32_t slc1_token1_wr:1; + /** slc1_token1_inc : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ + uint32_t slc1_token1_inc:1; + /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ + uint32_t slc1_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token1_reg_t; + +/** Type of slc_conf1 register + * Sdio slave DMA configuration1 register. + */ +typedef union { + struct { + /** slc0_check_owner : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ + uint32_t slc0_check_owner:1; + /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ + uint32_t slc0_tx_check_sum_en:1; + /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ + uint32_t slc0_rx_check_sum_en:1; + /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ + uint32_t sdio_cmd_hold_en:1; + /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ + uint32_t slc0_len_auto_clr:1; + /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ + uint32_t slc0_tx_stitch_en:1; + /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ + uint32_t slc0_rx_stitch_en:1; + uint32_t reserved_7:9; + /** slc1_check_owner : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ + uint32_t slc1_check_owner:1; + /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ + uint32_t slc1_tx_check_sum_en:1; + /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ + uint32_t slc1_rx_check_sum_en:1; + /** host_int_level_sel : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ + uint32_t host_int_level_sel:1; + uint32_t reserved_20:2; + /** sdio_clk_en : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ + uint32_t sdio_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} sdio_slc_conf1_reg_t; + +/** Type of slc_bridge_conf register + * Sdio slave DMA bridge configuration register. + */ +typedef union { + struct { + /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ + uint32_t slc_txeof_ena:6; + uint32_t reserved_6:2; + /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ + uint32_t slc_fifo_map_ena:4; + /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ + uint32_t slc0_tx_dummy_mode:1; + /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ + uint32_t slc_hda_map_128k:1; + /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ + uint32_t slc1_tx_dummy_mode:1; + uint32_t reserved_15:1; + /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; + * reserved + */ + uint32_t slc_tx_push_idle_num:16; + }; + uint32_t val; +} sdio_slc_bridge_conf_reg_t; + +/** Type of slc_slc0_to_eof_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ + uint32_t slc0_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_des_addr_reg_t; + +/** Type of slc_slc0_tx_eof_des_addr register + * Sdio slave DMA channel0 receiving packet status register. + */ +typedef union { + struct { + /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ + uint32_t slc0_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_eof_des_addr_reg_t; + +/** Type of slc_slc0_to_eof_bfr_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ + uint32_t slc0_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ + uint32_t slc1_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_des_addr_reg_t; + +/** Type of slc_slc1_tx_eof_des_addr register + * Sdio slave DMA channel1 receiving packet status register. + */ +typedef union { + struct { + /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ + uint32_t slc1_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_eof_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_bfr_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ + uint32_t slc1_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_rx_dscr_conf register + * Sdio slave sending descriptor configuration register. + */ +typedef union { + struct { + /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_token_no_replace:1; + /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_infor_no_replace:1; + /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc0_rx_fill_mode:1; + /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ + uint32_t slc0_rx_eof_mode:1; + /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_rx_fill_en:1; + /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; + * reserved + */ + uint32_t slc0_rd_retry_threshold:11; + /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; + * reserved + */ + uint32_t slc1_token_no_replace:1; + /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_infor_no_replace:1; + /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc1_rx_fill_mode:1; + /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ + uint32_t slc1_rx_eof_mode:1; + /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_rx_fill_en:1; + /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; + * reserved + */ + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; +} sdio_slc_rx_dscr_conf_reg_t; + +/** Type of slc_tx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; + * reserved + */ + uint32_t slc_wr_retry_threshold:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdio_slc_tx_dscr_conf_reg_t; + +/** Type of slc_slc0_len_conf register + * reserved + */ +typedef union { + struct { + /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ + uint32_t slc0_len_wdata:20; + /** slc0_len_wr : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ + uint32_t slc0_len_wr:1; + /** slc0_len_inc : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ + uint32_t slc0_len_inc:1; + /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ + uint32_t slc0_len_inc_more:1; + /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ + uint32_t slc0_rx_packet_load_en:1; + /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ + uint32_t slc0_tx_packet_load_en:1; + /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ + uint32_t slc0_rx_get_used_dscr:1; + /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ + uint32_t slc0_tx_get_used_dscr:1; + /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ + uint32_t slc0_rx_new_pkt_ind:1; + /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ + uint32_t slc0_tx_new_pkt_ind:1; + /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_rx_packet_load_en_st:1; + /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_tx_packet_load_en_st:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdio_slc_slc0_len_conf_reg_t; + +/** Type of slc_slc0_txpkt_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_tx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_h_dscr_reg_t; + +/** Type of slc_slc0_txpkt_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ + uint32_t slc0_tx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_e_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_h_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_e_dscr_reg_t; + +/** Type of slc_slc0_txpktu_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ + uint32_t slc0_tx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_h_dscr_reg_t; + +/** Type of slc_slc0_txpktu_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ + uint32_t slc0_tx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_e_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_h_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_e_dscr_reg_t; + +/** Type of slc_seq_position register + * The position of receiving packet configuration register. + */ +typedef union { + struct { + /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ + uint32_t slc0_seq_position:8; + /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ + uint32_t slc1_seq_position:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_seq_position_reg_t; + +/** Type of slc_slc0_dscr_rec_conf register + * Sdio slave DMA sending linked list limit configuration register. + */ +typedef union { + struct { + /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ + uint32_t slc0_rx_dscr_rec_lim:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdio_slc_slc0_dscr_rec_conf_reg_t; + +/** Type of slc_sdio_crc_st1 register + * Sdio slave receiving command crc status register. + */ +typedef union { + struct { + /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ + uint32_t cmd_crc_err_cnt:8; + uint32_t reserved_8:23; + /** err_cnt_clr : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ + uint32_t err_cnt_clr:1; + }; + uint32_t val; +} sdio_slc_sdio_crc_st1_reg_t; + +/** Type of slc_slc0_len_lim_conf register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +typedef union { + struct { + /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ + uint32_t slc0_len_lim:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_len_lim_conf_reg_t; + +/** Type of slc_slc0_tx_sharemem_start register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_start_reg_t; + +/** Type of slc_slc0_tx_sharemem_end register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_end_reg_t; + +/** Type of slc_slc0_rx_sharemem_start register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_start_reg_t; + +/** Type of slc_slc0_rx_sharemem_end register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_end_reg_t; + +/** Type of slc_slc1_tx_sharemem_start register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_start_reg_t; + +/** Type of slc_slc1_tx_sharemem_end register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_end_reg_t; + +/** Type of slc_slc1_rx_sharemem_start register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_start_reg_t; + +/** Type of slc_slc1_rx_sharemem_end register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_end_reg_t; + +/** Type of slc_hda_tx_sharemem_start register + * Sdio slave HAD receiving address range register. + */ +typedef union { + struct { + /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ + uint32_t sdio_hda_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_tx_sharemem_start_reg_t; + +/** Type of slc_hda_rx_sharemem_start register + * Sdio slave HAD sending address range register. + */ +typedef union { + struct { + /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ + uint32_t sdio_hda_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_rx_sharemem_start_reg_t; + +/** Type of slc_burst_len register + * Sdio slave AHB burst type configuration register. + */ +typedef union { + struct { + /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_txdata_burst_len:1; + /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_rxdata_burst_len:1; + /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_txdata_burst_len:1; + /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_rxdata_burst_len:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdio_slc_burst_len_reg_t; + + +/** Group: Interrupt registers */ +/** Type of slc_slc0int_raw register + * Sdio slave DMA channel0 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ + uint32_t slc_frhost_bit0_int_raw:1; + /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ + uint32_t slc_frhost_bit1_int_raw:1; + /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ + uint32_t slc_frhost_bit2_int_raw:1; + /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ + uint32_t slc_frhost_bit3_int_raw:1; + /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ + uint32_t slc_frhost_bit4_int_raw:1; + /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ + uint32_t slc_frhost_bit5_int_raw:1; + /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ + uint32_t slc_frhost_bit6_int_raw:1; + /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ + uint32_t slc_frhost_bit7_int_raw:1; + /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ + uint32_t slc0_rx_start_int_raw:1; + /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ + uint32_t slc0_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ + uint32_t slc0_tx_done_int_raw:1; + /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ + uint32_t slc0_tx_suc_eof_int_raw:1; + /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ + uint32_t slc0_rx_done_int_raw:1; + /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ + uint32_t slc0_rx_eof_int_raw:1; + /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc0_tohost_int_raw:1; + /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ + uint32_t slc0_tx_dscr_err_int_raw:1; + /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ + uint32_t slc0_rx_dscr_err_int_raw:1; + /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ + uint32_t slc0_tx_dscr_empty_int_raw:1; + /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ + uint32_t slc0_host_rd_ack_int_raw:1; + /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ + uint32_t slc0_wr_retry_done_int_raw:1; + /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ + uint32_t slc0_tx_err_eof_int_raw:1; + /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ + uint32_t cmd_dtc_int_raw:1; + /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ + uint32_t slc0_rx_quick_eof_int_raw:1; + /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ + uint32_t slc0_host_pop_eof_err_int_raw:1; + /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ + uint32_t hda_recv_done_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_raw_reg_t; + +/** Type of slc_slc0int_st register + * Sdio slave DMA channel0 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st:1; + /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st:1; + /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st:1; + /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st:1; + /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st:1; + /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st:1; + /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st:1; + /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st:1; + /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st:1; + /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st:1; + /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st:1; + /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st:1; + /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st:1; + /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st:1; + /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st:1; + /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st:1; + /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st:1; + /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st:1; + /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st:1; + /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st:1; + /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st:1; + /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st:1; + /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st:1; + /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st_reg_t; + +/** Type of slc_slc0int_ena register + * Sdio slave DMA channel0 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena:1; + /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena:1; + /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena:1; + /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena:1; + /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena:1; + /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena:1; + /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena:1; + /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena:1; + /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena:1; + /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena:1; + /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena:1; + /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena:1; + /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena:1; + /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena:1; + /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena:1; + /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena:1; + /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena:1; + /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena:1; + /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena:1; + /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena:1; + /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena:1; + /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena:1; + /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena:1; + /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena_reg_t; + +/** Type of slc_slc0int_clr register + * Sdio slave DMA channel0 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_clr:1; + /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_clr:1; + /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_clr:1; + /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_clr:1; + /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_clr:1; + /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_clr:1; + /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_clr:1; + /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_clr:1; + /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_clr:1; + /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_clr:1; + /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_clr:1; + /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_clr:1; + /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_clr:1; + /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_clr:1; + /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_clr:1; + /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_clr:1; + /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_clr:1; + /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_clr:1; + /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_clr:1; + /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_clr:1; + /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_clr:1; + /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_clr:1; + /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_clr:1; + /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_clr_reg_t; + +/** Type of slc_slc1int_raw register + * Sdio slave DMA channel1 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ + uint32_t slc_frhost_bit8_int_raw:1; + /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ + uint32_t slc_frhost_bit9_int_raw:1; + /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ + uint32_t slc_frhost_bit10_int_raw:1; + /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ + uint32_t slc_frhost_bit11_int_raw:1; + /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ + uint32_t slc_frhost_bit12_int_raw:1; + /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ + uint32_t slc_frhost_bit13_int_raw:1; + /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ + uint32_t slc_frhost_bit14_int_raw:1; + /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ + uint32_t slc_frhost_bit15_int_raw:1; + /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ + uint32_t slc1_rx_start_int_raw:1; + /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ + uint32_t slc1_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ + uint32_t slc1_tx_done_int_raw:1; + /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ + uint32_t slc1_tx_suc_eof_int_raw:1; + /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ + uint32_t slc1_rx_done_int_raw:1; + /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ + uint32_t slc1_rx_eof_int_raw:1; + /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc1_tohost_int_raw:1; + /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ + uint32_t slc1_tx_dscr_err_int_raw:1; + /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ + uint32_t slc1_rx_dscr_err_int_raw:1; + /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ + uint32_t slc1_tx_dscr_empty_int_raw:1; + /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ + uint32_t slc1_host_rd_ack_int_raw:1; + /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ + uint32_t slc1_wr_retry_done_int_raw:1; + /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ + uint32_t slc1_tx_err_eof_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_raw_reg_t; + +/** Type of slc_slc1int_st register + * Sdio slave DMA channel1 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st:1; + /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st:1; + /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st:1; + /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st:1; + /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st:1; + /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st:1; + /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st:1; + /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st:1; + /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st:1; + /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st:1; + /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st:1; + /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st:1; + /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st:1; + /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st:1; + /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st:1; + /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st:1; + /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st:1; + /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st:1; + /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st:1; + /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st_reg_t; + +/** Type of slc_slc1int_ena register + * Sdio slave DMA channel1 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena:1; + /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena:1; + /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena:1; + /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena:1; + /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena:1; + /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena:1; + /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena:1; + /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena:1; + /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena:1; + /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena:1; + /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena:1; + /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena:1; + /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena:1; + /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena:1; + /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena:1; + /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena:1; + /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena:1; + /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena:1; + /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena:1; + /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena_reg_t; + +/** Type of slc_slc1int_clr register + * Sdio slave DMA channel1 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_clr:1; + /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_clr:1; + /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_clr:1; + /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_clr:1; + /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_clr:1; + /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_clr:1; + /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_clr:1; + /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_clr:1; + /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_clr:1; + /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_clr:1; + /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_clr:1; + /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_clr:1; + /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_clr:1; + /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_clr:1; + /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_clr:1; + /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_clr:1; + /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_clr:1; + /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_clr:1; + /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_clr:1; + /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_clr_reg_t; + +/** Type of slc_slc0int_st1 register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st1:1; + /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st1:1; + /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st1:1; + /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st1:1; + /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st1:1; + /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st1:1; + /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st1:1; + /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st1:1; + /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st1:1; + /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st1:1; + /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st1:1; + /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st1:1; + /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st1:1; + /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st1:1; + /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st1:1; + /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st1:1; + /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st1:1; + /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st1:1; + /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st1:1; + /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st1:1; + /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st1:1; + /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st1:1; + /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st1:1; + /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st1:1; + /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st1:1; + /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st1:1; + /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st1:1; + /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st1:1; + /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st1_reg_t; + +/** Type of slc_slc0int_ena1 register + * Sdio slave DMA channel0 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena1:1; + /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena1:1; + /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena1:1; + /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena1:1; + /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena1:1; + /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena1:1; + /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena1:1; + /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena1:1; + /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena1:1; + /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena1:1; + /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena1:1; + /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena1:1; + /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena1:1; + /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena1:1; + /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena1:1; + /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena1:1; + /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena1:1; + /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena1:1; + /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena1:1; + /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena1:1; + /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena1:1; + /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena1:1; + /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena1:1; + /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena1_reg_t; + +/** Type of slc_slc1int_st1 register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st1:1; + /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st1:1; + /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st1:1; + /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st1:1; + /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st1:1; + /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st1:1; + /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st1:1; + /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st1:1; + /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st1:1; + /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st1:1; + /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st1:1; + /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st1:1; + /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st1:1; + /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st1:1; + /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st1:1; + /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st1:1; + /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st1:1; + /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st1:1; + /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st1:1; + /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st1:1; + /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st1:1; + /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st1:1; + /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st1:1; + /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st1:1; + /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st1_reg_t; + +/** Type of slc_slc1int_ena1 register + * Sdio slave DMA channel1 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena1:1; + /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena1:1; + /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena1:1; + /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena1:1; + /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena1:1; + /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena1:1; + /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena1:1; + /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena1:1; + /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena1:1; + /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena1:1; + /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena1:1; + /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena1:1; + /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena1:1; + /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena1:1; + /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena1:1; + /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena1:1; + /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena1:1; + /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena1:1; + /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena1:1; + /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena1_reg_t; + + +/** Group: Status registers */ +/** Type of slc_rx_status register + * Sdio slave DMA rxfifo status register. + */ +typedef union { + struct { + /** slc0_rx_full : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_full:1; + /** slc0_rx_empty : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_empty:1; + /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ + uint32_t slc0_rx_buf_len:14; + /** slc1_rx_full : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_full:1; + /** slc1_rx_empty : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_empty:1; + /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ + uint32_t slc1_rx_buf_len:14; + }; + uint32_t val; +} sdio_slc_rx_status_reg_t; + +/** Type of slc_tx_status register + * Sdio slave DMA txfifo status register. + */ +typedef union { + struct { + /** slc0_tx_full : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_full:1; + /** slc0_tx_empty : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_empty:1; + uint32_t reserved_2:14; + /** slc1_tx_full : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_full:1; + /** slc1_tx_empty : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_empty:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_tx_status_reg_t; + +/** Type of slc_slc0_state0 register + * Sdio slave DMA channel0 status register. + */ +typedef union { + struct { + /** slc0_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc0_state0:32; + }; + uint32_t val; +} sdio_slc_slc0_state0_reg_t; + +/** Type of slc_slc0_state1 register + * Sdio slave DMA channel0 status1 register. + */ +typedef union { + struct { + /** slc0_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc0_state1:32; + }; + uint32_t val; +} sdio_slc_slc0_state1_reg_t; + +/** Type of slc_slc1_state0 register + * Sdio slave DMA channel1 status register. + */ +typedef union { + struct { + /** slc1_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc1_state0:32; + }; + uint32_t val; +} sdio_slc_slc1_state0_reg_t; + +/** Type of slc_slc1_state1 register + * Sdio slave DMA channel1 status1 register. + */ +typedef union { + struct { + /** slc1_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc1_state1:32; + }; + uint32_t val; +} sdio_slc_slc1_state1_reg_t; + +/** Type of slc_sdio_st register + * Sdio slave function status register. + */ +typedef union { + struct { + /** cmd_st : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ + uint32_t cmd_st:3; + uint32_t reserved_3:1; + /** func_st : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ + uint32_t func_st:4; + /** sdio_wakeup : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t sdio_wakeup:1; + uint32_t reserved_9:3; + /** bus_st : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ + uint32_t bus_st:3; + uint32_t reserved_15:1; + /** func1_acc_state : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ + uint32_t func1_acc_state:5; + uint32_t reserved_21:3; + /** func2_acc_state : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ + uint32_t func2_acc_state:5; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_sdio_st_reg_t; + +/** Type of slc_slc0_txlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ + uint32_t slc0_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_txlink_dscr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf0 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ + uint32_t slc1_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_erreof_des_addr_reg_t; + +/** Type of slc_slc1_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_erreof_des_addr_reg_t; + +/** Type of slc_token_lat register + * reserved + */ +typedef union { + struct { + /** slc0_token : RO; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token:12; + uint32_t reserved_12:4; + /** slc1_token : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_token_lat_reg_t; + +/** Type of slc_cmd_infor0 register + * reserved + */ +typedef union { + struct { + /** cmd_content0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content0:32; + }; + uint32_t val; +} sdio_slc_cmd_infor0_reg_t; + +/** Type of slc_cmd_infor1 register + * reserved + */ +typedef union { + struct { + /** cmd_content1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content1:32; + }; + uint32_t val; +} sdio_slc_cmd_infor1_reg_t; + +/** Type of slc_slc0_length register + * reserved + */ +typedef union { + struct { + /** slc0_len : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ + uint32_t slc0_len:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_length_reg_t; + +/** Type of slc_sdio_crc_st0 register + * Sdio slave receiving packet data crc status register. + */ +typedef union { + struct { + /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ + uint32_t dat0_crc_err_cnt:8; + /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ + uint32_t dat1_crc_err_cnt:8; + /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ + uint32_t dat2_crc_err_cnt:8; + /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ + uint32_t dat3_crc_err_cnt:8; + }; + uint32_t val; +} sdio_slc_sdio_crc_st0_reg_t; + +/** Type of slc_slc0_eof_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_eof_start_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_eof_start_des_reg_t; + +/** Type of slc_slc0_push_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_rx_push_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_push_dscr_addr_reg_t; + +/** Type of slc_slc0_done_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +typedef union { + struct { + /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ + uint32_t slc0_rx_done_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_done_dscr_addr_reg_t; + +/** Type of slc_slc0_sub_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_sub_pac_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_sub_start_des_reg_t; + +/** Type of slc_slc0_dscr_cnt register + * Sdio slave DMA channel0 descriptor status register. + */ +typedef union { + struct { + /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ + uint32_t slc0_rx_dscr_cnt_lat:10; + uint32_t reserved_10:6; + /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ + uint32_t slc0_rx_get_eof_occ:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0_dscr_cnt_reg_t; + + +/** Group: Debud registers */ +/** Type of slc_slc0txfifo_pop register + * Sdio slave DMA channel0 txfifo debug register. + */ +typedef union { + struct { + /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc0_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ + uint32_t slc0_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0txfifo_pop_reg_t; + +/** Type of slc_slc1txfifo_pop register + * Sdio slave DMA channel1 txfifo debug register. + */ +typedef union { + struct { + /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc1_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ + uint32_t slc1_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1txfifo_pop_reg_t; + +/** Type of slc_ahb_test register + * Sdio slave AHB test register. + */ +typedef union { + struct { + /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ + uint32_t slc_ahb_testmode:3; + uint32_t reserved_3:1; + /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ + uint32_t slc_ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} sdio_slc_ahb_test_reg_t; + + +/** Group: Version registers */ +/** Type of slc_date register + * Sdio slave DMA version register. + */ +typedef union { + struct { + /** slc_date : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ + uint32_t slc_date:32; + }; + uint32_t val; +} sdio_slc_date_reg_t; + +/** Type of slc_id register + * Sdio slave ID register. + */ +typedef union { + struct { + /** slc_id : R/W; bitpos: [31:0]; default: 256; + * reserved + */ + uint32_t slc_id:32; + }; + uint32_t val; +} sdio_slc_id_reg_t; + + +typedef struct { + volatile sdio_slc_conf0_reg_t slc_conf0; + volatile sdio_slc_slc0int_raw_reg_t slc_slc0int_raw; + volatile sdio_slc_slc0int_st_reg_t slc_slc0int_st; + volatile sdio_slc_slc0int_ena_reg_t slc_slc0int_ena; + volatile sdio_slc_slc0int_clr_reg_t slc_slc0int_clr; + volatile sdio_slc_slc1int_raw_reg_t slc_slc1int_raw; + volatile sdio_slc_slc1int_st_reg_t slc_slc1int_st; + volatile sdio_slc_slc1int_ena_reg_t slc_slc1int_ena; + volatile sdio_slc_slc1int_clr_reg_t slc_slc1int_clr; + volatile sdio_slc_rx_status_reg_t slc_rx_status; + volatile sdio_slc_slc0rxfifo_push_reg_t slc_slc0rxfifo_push; + volatile sdio_slc_slc1rxfifo_push_reg_t slc_slc1rxfifo_push; + volatile sdio_slc_tx_status_reg_t slc_tx_status; + volatile sdio_slc_slc0txfifo_pop_reg_t slc_slc0txfifo_pop; + volatile sdio_slc_slc1txfifo_pop_reg_t slc_slc1txfifo_pop; + volatile sdio_slc_slc0rx_link_reg_t slc_slc0rx_link; + volatile sdio_slc_slc0rx_link_addr_reg_t slc_slc0rx_link_addr; + volatile sdio_slc_slc0tx_link_reg_t slc_slc0tx_link; + volatile sdio_slc_slc0tx_link_addr_reg_t slc_slc0tx_link_addr; + volatile sdio_slc_slc1rx_link_reg_t slc_slc1rx_link; + volatile sdio_slc_slc1rx_link_addr_reg_t slc_slc1rx_link_addr; + volatile sdio_slc_slc1tx_link_reg_t slc_slc1tx_link; + volatile sdio_slc_slc1tx_link_addr_reg_t slc_slc1tx_link_addr; + volatile sdio_slc_slcintvec_tohost_reg_t slc_slcintvec_tohost; + volatile sdio_slc_slc0token0_reg_t slc_slc0token0; + volatile sdio_slc_slc0token1_reg_t slc_slc0token1; + volatile sdio_slc_slc1token0_reg_t slc_slc1token0; + volatile sdio_slc_slc1token1_reg_t slc_slc1token1; + volatile sdio_slc_conf1_reg_t slc_conf1; + volatile sdio_slc_slc0_state0_reg_t slc_slc0_state0; + volatile sdio_slc_slc0_state1_reg_t slc_slc0_state1; + volatile sdio_slc_slc1_state0_reg_t slc_slc1_state0; + volatile sdio_slc_slc1_state1_reg_t slc_slc1_state1; + volatile sdio_slc_bridge_conf_reg_t slc_bridge_conf; + volatile sdio_slc_slc0_to_eof_des_addr_reg_t slc_slc0_to_eof_des_addr; + volatile sdio_slc_slc0_tx_eof_des_addr_reg_t slc_slc0_tx_eof_des_addr; + volatile sdio_slc_slc0_to_eof_bfr_des_addr_reg_t slc_slc0_to_eof_bfr_des_addr; + volatile sdio_slc_slc1_to_eof_des_addr_reg_t slc_slc1_to_eof_des_addr; + volatile sdio_slc_slc1_tx_eof_des_addr_reg_t slc_slc1_tx_eof_des_addr; + volatile sdio_slc_slc1_to_eof_bfr_des_addr_reg_t slc_slc1_to_eof_bfr_des_addr; + volatile sdio_slc_ahb_test_reg_t slc_ahb_test; + volatile sdio_slc_sdio_st_reg_t slc_sdio_st; + volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; + volatile sdio_slc_slc0_txlink_dscr_reg_t slc_slc0_txlink_dscr; + volatile sdio_slc_slc0_txlink_dscr_bf0_reg_t slc_slc0_txlink_dscr_bf0; + volatile sdio_slc_slc0_txlink_dscr_bf1_reg_t slc_slc0_txlink_dscr_bf1; + volatile sdio_slc_slc0_rxlink_dscr_reg_t slc_slc0_rxlink_dscr; + volatile sdio_slc_slc0_rxlink_dscr_bf0_reg_t slc_slc0_rxlink_dscr_bf0; + volatile sdio_slc_slc0_rxlink_dscr_bf1_reg_t slc_slc0_rxlink_dscr_bf1; + volatile sdio_slc_slc1_txlink_dscr_reg_t slc_slc1_txlink_dscr; + volatile sdio_slc_slc1_txlink_dscr_bf0_reg_t slc_slc1_txlink_dscr_bf0; + volatile sdio_slc_slc1_txlink_dscr_bf1_reg_t slc_slc1_txlink_dscr_bf1; + volatile sdio_slc_slc1_rxlink_dscr_reg_t slc_slc1_rxlink_dscr; + volatile sdio_slc_slc1_rxlink_dscr_bf0_reg_t slc_slc1_rxlink_dscr_bf0; + volatile sdio_slc_slc1_rxlink_dscr_bf1_reg_t slc_slc1_rxlink_dscr_bf1; + volatile sdio_slc_slc0_tx_erreof_des_addr_reg_t slc_slc0_tx_erreof_des_addr; + volatile sdio_slc_slc1_tx_erreof_des_addr_reg_t slc_slc1_tx_erreof_des_addr; + volatile sdio_slc_token_lat_reg_t slc_token_lat; + volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; + volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; + volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; + volatile sdio_slc_slc0_len_conf_reg_t slc_slc0_len_conf; + volatile sdio_slc_slc0_length_reg_t slc_slc0_length; + volatile sdio_slc_slc0_txpkt_h_dscr_reg_t slc_slc0_txpkt_h_dscr; + volatile sdio_slc_slc0_txpkt_e_dscr_reg_t slc_slc0_txpkt_e_dscr; + volatile sdio_slc_slc0_rxpkt_h_dscr_reg_t slc_slc0_rxpkt_h_dscr; + volatile sdio_slc_slc0_rxpkt_e_dscr_reg_t slc_slc0_rxpkt_e_dscr; + volatile sdio_slc_slc0_txpktu_h_dscr_reg_t slc_slc0_txpktu_h_dscr; + volatile sdio_slc_slc0_txpktu_e_dscr_reg_t slc_slc0_txpktu_e_dscr; + volatile sdio_slc_slc0_rxpktu_h_dscr_reg_t slc_slc0_rxpktu_h_dscr; + volatile sdio_slc_slc0_rxpktu_e_dscr_reg_t slc_slc0_rxpktu_e_dscr; + volatile sdio_slc_seq_position_reg_t slc_seq_position; + volatile sdio_slc_slc0_dscr_rec_conf_reg_t slc_slc0_dscr_rec_conf; + volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; + volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; + volatile sdio_slc_slc0_eof_start_des_reg_t slc_slc0_eof_start_des; + volatile sdio_slc_slc0_push_dscr_addr_reg_t slc_slc0_push_dscr_addr; + volatile sdio_slc_slc0_done_dscr_addr_reg_t slc_slc0_done_dscr_addr; + volatile sdio_slc_slc0_sub_start_des_reg_t slc_slc0_sub_start_des; + volatile sdio_slc_slc0_dscr_cnt_reg_t slc_slc0_dscr_cnt; + volatile sdio_slc_slc0_len_lim_conf_reg_t slc_slc0_len_lim_conf; + volatile sdio_slc_slc0int_st1_reg_t slc_slc0int_st1; + volatile sdio_slc_slc0int_ena1_reg_t slc_slc0int_ena1; + volatile sdio_slc_slc1int_st1_reg_t slc_slc1int_st1; + volatile sdio_slc_slc1int_ena1_reg_t slc_slc1int_ena1; + volatile sdio_slc_slc0_tx_sharemem_start_reg_t slc_slc0_tx_sharemem_start; + volatile sdio_slc_slc0_tx_sharemem_end_reg_t slc_slc0_tx_sharemem_end; + volatile sdio_slc_slc0_rx_sharemem_start_reg_t slc_slc0_rx_sharemem_start; + volatile sdio_slc_slc0_rx_sharemem_end_reg_t slc_slc0_rx_sharemem_end; + volatile sdio_slc_slc1_tx_sharemem_start_reg_t slc_slc1_tx_sharemem_start; + volatile sdio_slc_slc1_tx_sharemem_end_reg_t slc_slc1_tx_sharemem_end; + volatile sdio_slc_slc1_rx_sharemem_start_reg_t slc_slc1_rx_sharemem_start; + volatile sdio_slc_slc1_rx_sharemem_end_reg_t slc_slc1_rx_sharemem_end; + volatile sdio_slc_hda_tx_sharemem_start_reg_t slc_hda_tx_sharemem_start; + volatile sdio_slc_hda_rx_sharemem_start_reg_t slc_hda_rx_sharemem_start; + volatile sdio_slc_burst_len_reg_t slc_burst_len; + uint32_t reserved_180[30]; + volatile sdio_slc_date_reg_t slc_date; + volatile sdio_slc_id_reg_t slc_id; +} slc_dev_t; + +extern slc_dev_t SLC; + +#ifndef __cplusplus +_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/sha_reg.h b/components/soc/esp32c5/register/soc/sha_reg.h index 4dd7f4a2d9..4ebd8859b4 100644 --- a/components/soc/esp32c5/register/soc/sha_reg.h +++ b/components/soc/esp32c5/register/soc/sha_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,23 +15,26 @@ extern "C" { * Configures SHA algorithm */ #define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) -/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; - * Configures the SHA algorithm. \\ - * 0: SHA-1\\ - * 1: SHA-224\\ - * 2: SHA-256\\ +/** SHA_MODE : R/W; bitpos: [3:0]; default: 2; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA2-224 + * 2: SHA2-256 */ -#define SHA_MODE 0x00000007U +#define SHA_MODE 0x0000000FU #define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) -#define SHA_MODE_V 0x00000007U +#define SHA_MODE_V 0x0000000FU #define SHA_MODE_S 0 /** SHA_T_STRING_REG register * SHA 512/t configuration register 0. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) /** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; * Sha t_string (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SHA_T_STRING 0xFFFFFFFFU #define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) @@ -40,60 +43,63 @@ extern "C" { /** SHA_T_LENGTH_REG register * SHA 512/t configuration register 1. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) -/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; +/** SHA_T_LENGTH : R/W; bitpos: [6:0]; default: 0; * Sha t_length (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define SHA_T_LENGTH 0x0000003FU +#define SHA_T_LENGTH 0x0000007FU #define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) -#define SHA_T_LENGTH_V 0x0000003FU +#define SHA_T_LENGTH_V 0x0000007FU #define SHA_T_LENGTH_S 0 /** SHA_DMA_BLOCK_NUM_REG register * Block number register (only effective for DMA-SHA) */ #define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) -/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0; * Configures the DMA-SHA block number. */ -#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM 0x0000FFFFU #define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) -#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU #define SHA_DMA_BLOCK_NUM_S 0 /** SHA_START_REG register * Starts the SHA accelerator for Typical SHA operation */ #define SHA_START_REG (DR_REG_SHA_BASE + 0x10) -/** SHA_START : RO; bitpos: [31:1]; default: 0; - * Write 1 to start Typical SHA calculation. +/** SHA_START : WO; bitpos: [0]; default: 0; + * Start typical sha. */ -#define SHA_START 0x7FFFFFFFU +#define SHA_START (BIT(0)) #define SHA_START_M (SHA_START_V << SHA_START_S) -#define SHA_START_V 0x7FFFFFFFU -#define SHA_START_S 1 +#define SHA_START_V 0x00000001U +#define SHA_START_S 0 /** SHA_CONTINUE_REG register * Continues SHA operation (only effective in Typical SHA mode) */ #define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) -/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; - * Write 1 to continue Typical SHA calculation. +/** SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue typical sha. */ -#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE (BIT(0)) #define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) -#define SHA_CONTINUE_V 0x7FFFFFFFU -#define SHA_CONTINUE_S 1 +#define SHA_CONTINUE_V 0x00000001U +#define SHA_CONTINUE_S 0 /** SHA_BUSY_REG register * Represents if SHA Accelerator is busy or not */ #define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) /** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; - * Represents the states of SHA accelerator. \\ - * 0: idle\\ - * 1: busy\\ + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy */ #define SHA_BUSY_STATE (BIT(0)) #define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) @@ -152,7 +158,7 @@ extern "C" { * Version control register */ #define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) -/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; +/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291; * Version control register. */ #define SHA_DATE 0x3FFFFFFFU @@ -160,17 +166,33 @@ extern "C" { #define SHA_DATE_V 0x3FFFFFFFU #define SHA_DATE_S 0 +/** SHA_DMA_RX_RESET_REG register + * DMA RX FIFO Reset Signal + */ +#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30) +/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ +#define SHA_DMA_RX_RESET (BIT(0)) +#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S) +#define SHA_DMA_RX_RESET_V 0x00000001U +#define SHA_DMA_RX_RESET_S 0 + /** SHA_H_MEM register - * Sha H memory which contains intermediate hash or final hash. + * SHA1, SHA2-256, SM3 H memory which contains intermediate hash or final hash. + * SHA1, SHA2-256, SM3 : 0x00~0x20 (R/W) + * SHA2-512 : 0x00~0x40 (R/W) */ #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) #define SHA_H_MEM_SIZE_BYTES 64 /** SHA_M_MEM register - * Sha M memory which contains message. + * SHA1, SHA2-256, SM3 M memory which contains message. + * SHA1, SHA2-256, SM3 : 0x00~0x40 + * SHA2-512 : 0x00~0x80 */ #define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) -#define SHA_M_MEM_SIZE_BYTES 64 +#define SHA_M_MEM_SIZE_BYTES 128 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/register/soc/sha_struct.h b/components/soc/esp32c5/register/soc/sha_struct.h index bc2cd2cef2..1400394f3c 100644 --- a/components/soc/esp32c5/register/soc/sha_struct.h +++ b/components/soc/esp32c5/register/soc/sha_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,14 +16,14 @@ extern "C" { */ typedef union { struct { - /** mode : R/W; bitpos: [2:0]; default: 0; - * Configures the SHA algorithm. \\ - * 0: SHA-1\\ - * 1: SHA-224\\ - * 2: SHA-256\\ + /** mode : R/W; bitpos: [3:0]; default: 2; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA2-224 + * 2: SHA2-256 */ - uint32_t mode:3; - uint32_t reserved_3:29; + uint32_t mode:4; + uint32_t reserved_4:28; }; uint32_t val; } sha_mode_reg_t; @@ -33,11 +33,11 @@ typedef union { */ typedef union { struct { - /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + /** dma_block_num : R/W; bitpos: [15:0]; default: 0; * Configures the DMA-SHA block number. */ - uint32_t dma_block_num:6; - uint32_t reserved_6:26; + uint32_t dma_block_num:16; + uint32_t reserved_16:16; }; uint32_t val; } sha_dma_block_num_reg_t; @@ -47,11 +47,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:1; - /** start : RO; bitpos: [31:1]; default: 0; - * Write 1 to start Typical SHA calculation. + /** start : WO; bitpos: [0]; default: 0; + * Start typical sha. */ - uint32_t start:31; + uint32_t start:1; + uint32_t reserved_1:31; }; uint32_t val; } sha_start_reg_t; @@ -61,11 +61,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:1; - /** conti : RO; bitpos: [31:1]; default: 0; - * Write 1 to continue Typical SHA calculation. + /** conti : WO; bitpos: [0]; default: 0; + * Continue typical sha. */ - uint32_t conti:31; + uint32_t conti:1; + uint32_t reserved_1:31; }; uint32_t val; } sha_continue_reg_t; @@ -98,6 +98,20 @@ typedef union { uint32_t val; } sha_dma_continue_reg_t; +/** Type of dma_rx_reset register + * DMA RX FIFO Reset Signal + */ +typedef union { + struct { + /** dma_rx_reset : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ + uint32_t dma_rx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_rx_reset_reg_t; + /** Group: Configuration Register */ /** Type of t_string register @@ -107,6 +121,7 @@ typedef union { struct { /** t_string : R/W; bitpos: [31:0]; default: 0; * Sha t_string (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t t_string:32; }; @@ -118,11 +133,12 @@ typedef union { */ typedef union { struct { - /** t_length : R/W; bitpos: [5:0]; default: 0; + /** t_length : R/W; bitpos: [6:0]; default: 0; * Sha t_length (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t t_length:6; - uint32_t reserved_6:26; + uint32_t t_length:7; + uint32_t reserved_7:25; }; uint32_t val; } sha_t_length_reg_t; @@ -135,9 +151,9 @@ typedef union { typedef union { struct { /** busy_state : RO; bitpos: [0]; default: 0; - * Represents the states of SHA accelerator. \\ - * 0: idle\\ - * 1: busy\\ + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy */ uint32_t busy_state:1; uint32_t reserved_1:31; @@ -182,7 +198,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [29:0]; default: 538972713; + /** date : R/W; bitpos: [29:0]; default: 539232291; * Version control register. */ uint32_t date:30; @@ -207,15 +223,16 @@ typedef struct { volatile sha_clear_irq_reg_t clear_irq; volatile sha_irq_ena_reg_t irq_ena; volatile sha_date_reg_t date; - uint32_t reserved_030[4]; + volatile sha_dma_rx_reset_reg_t dma_rx_reset; + uint32_t reserved_034[3]; volatile uint32_t h[16]; - volatile uint32_t m[16]; + volatile uint32_t m[32]; } sha_dev_t; extern sha_dev_t SHA; #ifndef __cplusplus -_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); +_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h new file mode 100644 index 0000000000..e247e8d6ef --- /dev/null +++ b/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h @@ -0,0 +1,3988 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_MST_ST 0x0000000FU +#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) +#define SPI_MEM_MST_ST_V 0x0000000FU +#define SPI_MEM_MST_ST_S 0 +/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_SLV_ST 0x0000000FU +#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) +#define SPI_MEM_SLV_ST_V 0x0000000FU +#define SPI_MEM_SLV_ST_S 4 +/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) +#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_S 18 + +/** SPI_MEM_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) +#define SPI_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_FDUMMY_RIN_S 2 +/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) +#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_FDUMMY_WOUT_S 3 +/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) +#define SPI_MEM_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_FDOUT_OCT_S 4 +/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) +#define SPI_MEM_FDIN_OCT_V 0x00000001U +#define SPI_MEM_FDIN_OCT_S 5 +/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) +#define SPI_MEM_FADDR_OCT_V 0x00000001U +#define SPI_MEM_FADDR_OCT_S 6 +/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) +#define SPI_MEM_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_FCMD_QUAD_S 8 +/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) +#define SPI_MEM_FCMD_OCT_V 0x00000001U +#define SPI_MEM_FCMD_OCT_S 9 +/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) +#define SPI_MEM_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_FASTRD_MODE_S 13 +/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) +#define SPI_MEM_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_FREAD_DUAL_S 14 +/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) +#define SPI_MEM_Q_POL_V 0x00000001U +#define SPI_MEM_Q_POL_S 18 +/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) +#define SPI_MEM_D_POL_V 0x00000001U +#define SPI_MEM_D_POL_S 19 +/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) +#define SPI_MEM_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_FREAD_QUAD_S 20 +/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) +#define SPI_MEM_WP_REG_V 0x00000001U +#define SPI_MEM_WP_REG_S 21 +/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) +#define SPI_MEM_FREAD_DIO_V 0x00000001U +#define SPI_MEM_FREAD_DIO_S 23 +/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) +#define SPI_MEM_FREAD_QIO_V 0x00000001U +#define SPI_MEM_FREAD_QIO_S 24 +/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI_MEM_CLK_MODE 0x00000003U +#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) +#define SPI_MEM_CLK_MODE_V 0x00000003U +#define SPI_MEM_CLK_MODE_S 0 +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) +#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 +/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) +#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AR_SPLICE_EN_S 25 +/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) +#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AW_SPLICE_EN_S 26 +/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) +#define SPI_MEM_RAM0_EN_V 0x00000001U +#define SPI_MEM_RAM0_EN_S 27 +/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) +#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_DUAL_RAM_EN_S 28 +/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) +#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_FAST_WRITE_EN_S 29 +/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) +#define SPI_MEM_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_RXFIFO_RST_S 30 +/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) +#define SPI_MEM_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_TXFIFO_RST_S 31 + +/** SPI_MEM_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ +#define SPI_MEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) +#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_S 0 +/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ +#define SPI_MEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) +#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_S 5 +/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) +#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) +#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_S 31 + +/** SPI_MEM_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. + */ +#define SPI_MEM_CLKCNT_L 0x000000FFU +#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) +#define SPI_MEM_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_CLKCNT_L_S 0 +/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). + */ +#define SPI_MEM_CLKCNT_H 0x000000FFU +#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) +#define SPI_MEM_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_CLKCNT_H_S 8 +/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_CLKCNT_N+1) + */ +#define SPI_MEM_CLKCNT_N 0x000000FFU +#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) +#define SPI_MEM_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_CLKCNT_N_S 16 +/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) +#define SPI_MEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_CS_HOLD_S 6 +/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) +#define SPI_MEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_CS_SETUP_S 7 +/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) +#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_CK_OUT_EDGE_S 9 +/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) +#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_S 29 + +/** SPI_MEM_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_USR_DBYTELEN 0x0000003FU +#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) +#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU +#define SPI_MEM_USR_DBYTELEN_S 6 +/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) +#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_RD_STATUS_REG register + * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_BASE + 0x2c) +/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE 0x000000FFU +#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) +#define SPI_MEM_WB_MODE_V 0x000000FFU +#define SPI_MEM_WB_MODE_S 16 +/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) +#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_EN (BIT(27)) +#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) +#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_S 27 + +/** SPI_MEM_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) +#define SPI_MEM_FSUB_PIN_V 0x00000001U +#define SPI_MEM_FSUB_PIN_S 7 +/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) +#define SPI_MEM_SSUB_PIN_V 0x00000001U +#define SPI_MEM_SSUB_PIN_S 8 +/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) +#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_MEM_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (SPI_MEM_AXI_REQ_EN_V << SPI_MEM_AXI_REQ_EN_S) +#define SPI_MEM_AXI_REQ_EN_V 0x00000001U +#define SPI_MEM_AXI_REQ_EN_S 0 +/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (SPI_MEM_CACHE_FLASH_USR_CMD_V << SPI_MEM_CACHE_FLASH_USR_CMD_S) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x00000001U +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) +#define SPI_MEM_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_FDIN_DUAL_S 3 +/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) +#define SPI_MEM_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_FDOUT_DUAL_S 4 +/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) +#define SPI_MEM_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_FADDR_DUAL_S 5 +/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) +#define SPI_MEM_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_FDIN_QUAD_S 6 +/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) +#define SPI_MEM_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_FDOUT_QUAD_S 7 +/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) +#define SPI_MEM_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_FADDR_QUAD_S 8 +/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_CACHE_SCTRL_REG register + * SPI0 external RAM control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_CACHE_SCTRL_REG (DR_REG_SPI_BASE + 0x40) +/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 +/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) +#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U +#define SPI_MEM_USR_SRAM_DIO_S 1 +/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) +#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U +#define SPI_MEM_USR_SRAM_QIO_S 2 +/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) +#define SPI_MEM_SRAM_OCT_V 0x00000001U +#define SPI_MEM_SRAM_OCT_S 21 +/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 + +/** SPI_MEM_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCLK_MODE 0x00000003U +#define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) +#define SPI_MEM_SCLK_MODE_V 0x00000003U +#define SPI_MEM_SCLK_MODE_S 0 +/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SWB_MODE 0x000000FFU +#define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) +#define SPI_MEM_SWB_MODE_V 0x000000FFU +#define SPI_MEM_SWB_MODE_S 2 +/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) +#define SPI_MEM_SDIN_DUAL_V 0x00000001U +#define SPI_MEM_SDIN_DUAL_S 10 +/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) +#define SPI_MEM_SDOUT_DUAL_V 0x00000001U +#define SPI_MEM_SDOUT_DUAL_S 11 +/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) +#define SPI_MEM_SADDR_DUAL_V 0x00000001U +#define SPI_MEM_SADDR_DUAL_S 12 +/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) +#define SPI_MEM_SDIN_QUAD_V 0x00000001U +#define SPI_MEM_SDIN_QUAD_S 14 +/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) +#define SPI_MEM_SDOUT_QUAD_V 0x00000001U +#define SPI_MEM_SDOUT_QUAD_S 15 +/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) +#define SPI_MEM_SADDR_QUAD_V 0x00000001U +#define SPI_MEM_SADDR_QUAD_S 16 +/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) +#define SPI_MEM_SCMD_QUAD_V 0x00000001U +#define SPI_MEM_SCMD_QUAD_S 17 +/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) +#define SPI_MEM_SDIN_OCT_V 0x00000001U +#define SPI_MEM_SDIN_OCT_S 18 +/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) +#define SPI_MEM_SDOUT_OCT_V 0x00000001U +#define SPI_MEM_SDOUT_OCT_S 19 +/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) +#define SPI_MEM_SADDR_OCT_V 0x00000001U +#define SPI_MEM_SADDR_OCT_S 20 +/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (SPI_MEM_SCMD_OCT_V << SPI_MEM_SCMD_OCT_S) +#define SPI_MEM_SCMD_OCT_V 0x00000001U +#define SPI_MEM_SCMD_OCT_S 21 +/** SPI_MEM_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) +#define SPI_MEM_SDUMMY_RIN_V 0x00000001U +#define SPI_MEM_SDUMMY_RIN_S 22 +/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) +#define SPI_MEM_SDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_SDUMMY_WOUT_S 23 +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_MEM_SDIN_HEX : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDIN_HEX (BIT(26)) +#define SPI_MEM_SDIN_HEX_M (SPI_MEM_SDIN_HEX_V << SPI_MEM_SDIN_HEX_S) +#define SPI_MEM_SDIN_HEX_V 0x00000001U +#define SPI_MEM_SDIN_HEX_S 26 +/** SPI_MEM_SDOUT_HEX : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SDOUT_HEX (BIT(27)) +#define SPI_MEM_SDOUT_HEX_M (SPI_MEM_SDOUT_HEX_V << SPI_MEM_SDOUT_HEX_S) +#define SPI_MEM_SDOUT_HEX_V 0x00000001U +#define SPI_MEM_SDOUT_HEX_S 27 +/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ +#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_SRAM_DRD_CMD_REG register + * SPI0 external RAM DDR read command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_SRAM_DRD_CMD_REG (DR_REG_SPI_BASE + 0x48) +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/** SPI_MEM_SRAM_DWR_CMD_REG register + * SPI0 external RAM DDR write command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_SRAM_DWR_CMD_REG (DR_REG_SPI_BASE + 0x4c) +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/** SPI_MEM_SRAM_CLK_REG register + * SPI0 external RAM clock control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_SRAM_CLK_REG (DR_REG_SPI_BASE + 0x50) +/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCLKCNT_L 0x000000FFU +#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) +#define SPI_MEM_SCLKCNT_L_V 0x000000FFU +#define SPI_MEM_SCLKCNT_L_S 0 +/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCLKCNT_H 0x000000FFU +#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) +#define SPI_MEM_SCLKCNT_H_V 0x000000FFU +#define SPI_MEM_SCLKCNT_H_S 8 +/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCLKCNT_N 0x000000FFU +#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) +#define SPI_MEM_SCLKCNT_N_V 0x000000FFU +#define SPI_MEM_SCLKCNT_N_S 16 +/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU +#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU +#define SPI_MEM_LOCK_DELAY_TIME_S 7 +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) +#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) +#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U +#define SPI_MEM_FLASH_LOCK_EN_S 19 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) +#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) +#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U +#define SPI_MEM_SRAM_LOCK_EN_S 20 + +/** SPI_MEM_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 + +/** SPI_MEM_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 + +/** SPI_MEM_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 + +/** SPI_MEM_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 + +/** SPI_MEM_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) +#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) +#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 + +/** SPI_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) +/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) +#define SPI_SMEM_DDR_EN_V 0x00000001U +#define SPI_SMEM_DDR_EN_S 0 +/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) +#define SPI_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_SMEM_VAR_DUMMY_S 1 +/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) +#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) +#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) +#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_SMEM_DDR_CMD_DIS_S 4 +/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) +#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_S 5 +/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) +#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) +#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) +#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) +#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) +#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_EN_S 24 +/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) +#define SPI_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_SMEM_DQS_CA_IN_S 26 +/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) +#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_INV_S 28 +/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) +#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) +#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_SMEM_HYPERBUS_CA_S 30 + +/** SPI_FMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section 0 attribute register + */ +#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) +/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) +#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) +#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and + * SPI_FMEM_PMS0_SIZE_REG. + */ +#define SPI_FMEM_PMS0_ECC (BIT(2)) +#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) +#define SPI_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_FMEM_PMS0_ECC_S 2 + +/** SPI_FMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section 1 attribute register + */ +#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) +/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) +#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) +#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and + * SPI_FMEM_PMS1_SIZE_REG. + */ +#define SPI_FMEM_PMS1_ECC (BIT(2)) +#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) +#define SPI_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_FMEM_PMS1_ECC_S 2 + +/** SPI_FMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section 2 attribute register + */ +#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) +/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) +#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) +#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and + * SPI_FMEM_PMS2_SIZE_REG. + */ +#define SPI_FMEM_PMS2_ECC (BIT(2)) +#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) +#define SPI_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_FMEM_PMS2_ECC_S 2 + +/** SPI_FMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section 3 attribute register + */ +#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) +/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) +#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) +#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and + * SPI_FMEM_PMS3_SIZE_REG. + */ +#define SPI_FMEM_PMS3_ECC (BIT(2)) +#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) +#define SPI_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_FMEM_PMS3_ECC_S 2 + +/** SPI_FMEM_PMS0_ADDR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 0 start address value + */ +#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) +#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_S 0 + +/** SPI_FMEM_PMS1_ADDR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 1 start address value + */ +#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) +#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_S 0 + +/** SPI_FMEM_PMS2_ADDR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 2 start address value + */ +#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) +#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_S 0 + +/** SPI_FMEM_PMS3_ADDR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 3 start address value + */ +#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) +#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_S 0 + +/** SPI_FMEM_PMS0_SIZE_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, + * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) + */ +#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) +#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS0_SIZE_S 0 + +/** SPI_FMEM_PMS1_SIZE_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, + * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) + */ +#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) +#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS1_SIZE_S 0 + +/** SPI_FMEM_PMS2_SIZE_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, + * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) + */ +#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) +#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS2_SIZE_S 0 + +/** SPI_FMEM_PMS3_SIZE_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, + * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) + */ +#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) +#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS3_SIZE_S 0 + +/** SPI_SMEM_PMS0_ATTR_REG register + * SPI1 external RAM PMS section 0 attribute register + */ +#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) +/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) +#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) +#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and + * SPI_SMEM_PMS0_SIZE_REG. + */ +#define SPI_SMEM_PMS0_ECC (BIT(2)) +#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) +#define SPI_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_SMEM_PMS0_ECC_S 2 + +/** SPI_SMEM_PMS1_ATTR_REG register + * SPI1 external RAM PMS section 1 attribute register + */ +#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) +/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) +#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) +#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and + * SPI_SMEM_PMS1_SIZE_REG. + */ +#define SPI_SMEM_PMS1_ECC (BIT(2)) +#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) +#define SPI_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_SMEM_PMS1_ECC_S 2 + +/** SPI_SMEM_PMS2_ATTR_REG register + * SPI1 external RAM PMS section 2 attribute register + */ +#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) +/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) +#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) +#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and + * SPI_SMEM_PMS2_SIZE_REG. + */ +#define SPI_SMEM_PMS2_ECC (BIT(2)) +#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) +#define SPI_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_SMEM_PMS2_ECC_S 2 + +/** SPI_SMEM_PMS3_ATTR_REG register + * SPI1 external RAM PMS section 3 attribute register + */ +#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) +/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) +#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) +#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and + * SPI_SMEM_PMS3_SIZE_REG. + */ +#define SPI_SMEM_PMS3_ECC (BIT(2)) +#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) +#define SPI_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_SMEM_PMS3_ECC_S 2 + +/** SPI_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 0 start address value + */ +#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) +#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value + */ +#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) +#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value + */ +#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) +#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value + */ +#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) +#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, + * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) + */ +#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) +#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS0_SIZE_S 0 + +/** SPI_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, + * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) + */ +#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) +#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS1_SIZE_S 0 + +/** SPI_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, + * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) + */ +#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) +#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS2_SIZE_S 0 + +/** SPI_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, + * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) + */ +#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) +#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x160) +/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) +#define SPI_MEM_PM_EN_V 0x00000001U +#define SPI_MEM_PM_EN_S 27 +/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) +#define SPI_MEM_PMS_LD_V 0x00000001U +#define SPI_MEM_PMS_LD_S 28 +/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) +#define SPI_MEM_PMS_ST_V 0x00000001U +#define SPI_MEM_PMS_ST_S 29 +/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) +#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) +#define SPI_MEM_PMS_IVD_V 0x00000001U +#define SPI_MEM_PMS_IVD_S 31 + +/** SPI_MEM_PMS_REJECT_ADDR_REG register + * SPI1 access reject addr register + */ +#define SPI_MEM_PMS_REJECT_ADDR_REG (DR_REG_SPI_BASE + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 + +/** SPI_MEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) +/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) +#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_S 5 +/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) +#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_FMEM_PAGE_SIZE 0x00000003U +#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) +#define SPI_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_FMEM_PAGE_SIZE_S 18 +/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) +#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) +#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_FMEM_ECC_ADDR_EN_S 21 +/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_USR_ECC_ADDR_EN_S 22 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) +#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_S 25 + +/** SPI_MEM_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) +/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) +#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) +#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +/** SPI_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) +/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) +#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_SMEM_PAGE_SIZE 0x00000003U +#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) +#define SPI_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_SMEM_PAGE_SIZE_S 18 +/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) +#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) +/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) +#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_RDATA_AFIFO_REMPTY_S 27 +/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) +#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_RADDR_AFIFO_REMPTY_S 28 +/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) +#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_WDATA_AFIFO_REMPTY_S 29 +/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) +#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) +/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) +/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) +#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) +#define SPI_MEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_TIMING_CALI_S 1 +/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) +#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) +/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN0_MODE 0x00000007U +#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) +#define SPI_MEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_DIN0_MODE_S 0 +/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN1_MODE 0x00000007U +#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) +#define SPI_MEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_DIN1_MODE_S 3 +/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN2_MODE 0x00000007U +#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) +#define SPI_MEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_DIN2_MODE_S 6 +/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN3_MODE 0x00000007U +#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) +#define SPI_MEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_DIN3_MODE_S 9 +/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN4_MODE 0x00000007U +#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) +#define SPI_MEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_DIN4_MODE_S 12 +/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN5_MODE 0x00000007U +#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) +#define SPI_MEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_DIN5_MODE_S 15 +/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN6_MODE 0x00000007U +#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) +#define SPI_MEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_DIN6_MODE_S 18 +/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN7_MODE 0x00000007U +#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) +#define SPI_MEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_DIN7_MODE_S 21 +/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DINS_MODE 0x00000007U +#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) +#define SPI_MEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_DINS_MODE_S 24 + +/** SPI_MEM_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) +/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN0_NUM 0x00000003U +#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) +#define SPI_MEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_DIN0_NUM_S 0 +/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN1_NUM 0x00000003U +#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) +#define SPI_MEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_DIN1_NUM_S 2 +/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN2_NUM 0x00000003U +#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) +#define SPI_MEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_DIN2_NUM_S 4 +/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN3_NUM 0x00000003U +#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) +#define SPI_MEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_DIN3_NUM_S 6 +/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN4_NUM 0x00000003U +#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) +#define SPI_MEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_DIN4_NUM_S 8 +/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN5_NUM 0x00000003U +#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) +#define SPI_MEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_DIN5_NUM_S 10 +/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN6_NUM 0x00000003U +#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) +#define SPI_MEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_DIN6_NUM_S 12 +/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN7_NUM 0x00000003U +#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) +#define SPI_MEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_DIN7_NUM_S 14 +/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DINS_NUM 0x00000003U +#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) +#define SPI_MEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_DINS_NUM_S 16 + +/** SPI_MEM_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) +/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) +#define SPI_MEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_DOUT0_MODE_S 0 +/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) +#define SPI_MEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_DOUT1_MODE_S 1 +/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) +#define SPI_MEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_DOUT2_MODE_S 2 +/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) +#define SPI_MEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_DOUT3_MODE_S 3 +/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) +#define SPI_MEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_DOUT4_MODE_S 4 +/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) +#define SPI_MEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_DOUT5_MODE_S 5 +/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) +#define SPI_MEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_DOUT6_MODE_S 6 +/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) +#define SPI_MEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_DOUT7_MODE_S 7 +/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) +#define SPI_MEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) +/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) +#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) +#define SPI_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_TIMING_CALI_S 1 +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) +#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_DLL_TIMING_CALI_S 5 +/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_270_SEL 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) +#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_S 7 +/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_90_SEL 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) +#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_S 9 +/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_270_SEL 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S) +#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_S 11 +/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_90_SEL 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S) +#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_S 13 + +/** SPI_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) +/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN0_MODE 0x00000007U +#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) +#define SPI_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_SMEM_DIN0_MODE_S 0 +/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN1_MODE 0x00000007U +#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) +#define SPI_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_SMEM_DIN1_MODE_S 3 +/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN2_MODE 0x00000007U +#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) +#define SPI_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_SMEM_DIN2_MODE_S 6 +/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN3_MODE 0x00000007U +#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) +#define SPI_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_SMEM_DIN3_MODE_S 9 +/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN4_MODE 0x00000007U +#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) +#define SPI_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_SMEM_DIN4_MODE_S 12 +/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN5_MODE 0x00000007U +#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) +#define SPI_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_SMEM_DIN5_MODE_S 15 +/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN6_MODE 0x00000007U +#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) +#define SPI_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_SMEM_DIN6_MODE_S 18 +/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN7_MODE 0x00000007U +#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) +#define SPI_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_SMEM_DIN7_MODE_S 21 +/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_MODE 0x00000007U +#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) +#define SPI_SMEM_DINS_MODE_V 0x00000007U +#define SPI_SMEM_DINS_MODE_S 24 + +/** SPI_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) +/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN0_NUM 0x00000003U +#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) +#define SPI_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_SMEM_DIN0_NUM_S 0 +/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN1_NUM 0x00000003U +#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) +#define SPI_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_SMEM_DIN1_NUM_S 2 +/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN2_NUM 0x00000003U +#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) +#define SPI_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_SMEM_DIN2_NUM_S 4 +/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN3_NUM 0x00000003U +#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) +#define SPI_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_SMEM_DIN3_NUM_S 6 +/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN4_NUM 0x00000003U +#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) +#define SPI_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_SMEM_DIN4_NUM_S 8 +/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN5_NUM 0x00000003U +#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) +#define SPI_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_SMEM_DIN5_NUM_S 10 +/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN6_NUM 0x00000003U +#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) +#define SPI_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_SMEM_DIN6_NUM_S 12 +/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN7_NUM 0x00000003U +#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) +#define SPI_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_SMEM_DIN7_NUM_S 14 +/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_NUM 0x00000003U +#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) +#define SPI_SMEM_DINS_NUM_V 0x00000003U +#define SPI_SMEM_DINS_NUM_S 16 + +/** SPI_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) +/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) +#define SPI_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_SMEM_DOUT0_MODE_S 0 +/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) +#define SPI_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_SMEM_DOUT1_MODE_S 1 +/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) +#define SPI_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_SMEM_DOUT2_MODE_S 2 +/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) +#define SPI_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_SMEM_DOUT3_MODE_S 3 +/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) +#define SPI_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_SMEM_DOUT4_MODE_S 4 +/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) +#define SPI_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_SMEM_DOUT5_MODE_S 5 +/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) +#define SPI_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_SMEM_DOUT6_MODE_S 6 +/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) +#define SPI_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_SMEM_DOUT7_MODE_S 7 +/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) +#define SPI_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) +/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) +#define SPI_SMEM_CS_SETUP_V 0x00000001U +#define SPI_SMEM_CS_SETUP_S 0 +/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) +#define SPI_SMEM_CS_HOLD_V 0x00000001U +#define SPI_SMEM_CS_HOLD_S 1 +/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) +#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_S 2 +/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) +#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_S 7 +/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) +#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) +#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_SMEM_DIN_HEX_MODE_REG register + * MSPI 16x external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1a4) +/** SPI_SMEM_DIN08_MODE : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN08_MODE 0x00000007U +#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) +#define SPI_SMEM_DIN08_MODE_V 0x00000007U +#define SPI_SMEM_DIN08_MODE_S 0 +/** SPI_SMEM_DIN09_MODE : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN09_MODE 0x00000007U +#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) +#define SPI_SMEM_DIN09_MODE_V 0x00000007U +#define SPI_SMEM_DIN09_MODE_S 3 +/** SPI_SMEM_DIN10_MODE : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN10_MODE 0x00000007U +#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) +#define SPI_SMEM_DIN10_MODE_V 0x00000007U +#define SPI_SMEM_DIN10_MODE_S 6 +/** SPI_SMEM_DIN11_MODE : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN11_MODE 0x00000007U +#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) +#define SPI_SMEM_DIN11_MODE_V 0x00000007U +#define SPI_SMEM_DIN11_MODE_S 9 +/** SPI_SMEM_DIN12_MODE : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN12_MODE 0x00000007U +#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) +#define SPI_SMEM_DIN12_MODE_V 0x00000007U +#define SPI_SMEM_DIN12_MODE_S 12 +/** SPI_SMEM_DIN13_MODE : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN13_MODE 0x00000007U +#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) +#define SPI_SMEM_DIN13_MODE_V 0x00000007U +#define SPI_SMEM_DIN13_MODE_S 15 +/** SPI_SMEM_DIN14_MODE : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN14_MODE 0x00000007U +#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) +#define SPI_SMEM_DIN14_MODE_V 0x00000007U +#define SPI_SMEM_DIN14_MODE_S 18 +/** SPI_SMEM_DIN15_MODE : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN15_MODE 0x00000007U +#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) +#define SPI_SMEM_DIN15_MODE_V 0x00000007U +#define SPI_SMEM_DIN15_MODE_S 21 +/** SPI_SMEM_DINS_HEX_MODE : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_HEX_MODE 0x00000007U +#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) +#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U +#define SPI_SMEM_DINS_HEX_MODE_S 24 + +/** SPI_SMEM_DIN_HEX_NUM_REG register + * MSPI 16x external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_SPI_BASE + 0x1a8) +/** SPI_SMEM_DIN08_NUM : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN08_NUM 0x00000003U +#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) +#define SPI_SMEM_DIN08_NUM_V 0x00000003U +#define SPI_SMEM_DIN08_NUM_S 0 +/** SPI_SMEM_DIN09_NUM : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN09_NUM 0x00000003U +#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) +#define SPI_SMEM_DIN09_NUM_V 0x00000003U +#define SPI_SMEM_DIN09_NUM_S 2 +/** SPI_SMEM_DIN10_NUM : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN10_NUM 0x00000003U +#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) +#define SPI_SMEM_DIN10_NUM_V 0x00000003U +#define SPI_SMEM_DIN10_NUM_S 4 +/** SPI_SMEM_DIN11_NUM : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN11_NUM 0x00000003U +#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) +#define SPI_SMEM_DIN11_NUM_V 0x00000003U +#define SPI_SMEM_DIN11_NUM_S 6 +/** SPI_SMEM_DIN12_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN12_NUM 0x00000003U +#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) +#define SPI_SMEM_DIN12_NUM_V 0x00000003U +#define SPI_SMEM_DIN12_NUM_S 8 +/** SPI_SMEM_DIN13_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN13_NUM 0x00000003U +#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) +#define SPI_SMEM_DIN13_NUM_V 0x00000003U +#define SPI_SMEM_DIN13_NUM_S 10 +/** SPI_SMEM_DIN14_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN14_NUM 0x00000003U +#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) +#define SPI_SMEM_DIN14_NUM_V 0x00000003U +#define SPI_SMEM_DIN14_NUM_S 12 +/** SPI_SMEM_DIN15_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN15_NUM 0x00000003U +#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) +#define SPI_SMEM_DIN15_NUM_V 0x00000003U +#define SPI_SMEM_DIN15_NUM_S 14 +/** SPI_SMEM_DINS_HEX_NUM : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_HEX_NUM 0x00000003U +#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) +#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U +#define SPI_SMEM_DINS_HEX_NUM_S 16 + +/** SPI_SMEM_DOUT_HEX_MODE_REG register + * MSPI 16x external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1ac) +/** SPI_SMEM_DOUT08_MODE : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) +#define SPI_SMEM_DOUT08_MODE_V 0x00000001U +#define SPI_SMEM_DOUT08_MODE_S 0 +/** SPI_SMEM_DOUT09_MODE : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) +#define SPI_SMEM_DOUT09_MODE_V 0x00000001U +#define SPI_SMEM_DOUT09_MODE_S 1 +/** SPI_SMEM_DOUT10_MODE : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) +#define SPI_SMEM_DOUT10_MODE_V 0x00000001U +#define SPI_SMEM_DOUT10_MODE_S 2 +/** SPI_SMEM_DOUT11_MODE : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) +#define SPI_SMEM_DOUT11_MODE_V 0x00000001U +#define SPI_SMEM_DOUT11_MODE_S 3 +/** SPI_SMEM_DOUT12_MODE : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) +#define SPI_SMEM_DOUT12_MODE_V 0x00000001U +#define SPI_SMEM_DOUT12_MODE_S 4 +/** SPI_SMEM_DOUT13_MODE : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) +#define SPI_SMEM_DOUT13_MODE_V 0x00000001U +#define SPI_SMEM_DOUT13_MODE_S 5 +/** SPI_SMEM_DOUT14_MODE : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) +#define SPI_SMEM_DOUT14_MODE_V 0x00000001U +#define SPI_SMEM_DOUT14_MODE_S 6 +/** SPI_SMEM_DOUT15_MODE : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) +#define SPI_SMEM_DOUT15_MODE_V 0x00000001U +#define SPI_SMEM_DOUT15_MODE_S 7 +/** SPI_SMEM_DOUTS_HEX_MODE : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) +#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_HEX_MODE_S 8 + +/** SPI_MEM_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ +#define SPI_MSPI_CLK_FORCE_ON (BIT(1)) +#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S) +#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U +#define SPI_MSPI_CLK_FORCE_ON_S 1 + +/** SPI_MEM_NAND_FLASH_EN_REG register + * NAND FLASH control register + */ +#define SPI_MEM_NAND_FLASH_EN_REG (DR_REG_SPI_BASE + 0x204) +/** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; + * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: + * Disable NAND FLASH, Enable NOR FLASH. + */ +#define SPI_MEM_NAND_FLASH_EN (BIT(0)) +#define SPI_MEM_NAND_FLASH_EN_M (SPI_MEM_NAND_FLASH_EN_V << SPI_MEM_NAND_FLASH_EN_S) +#define SPI_MEM_NAND_FLASH_EN_V 0x00000001U +#define SPI_MEM_NAND_FLASH_EN_S 0 +/** SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO; bitpos: [15:1]; default: 32767; + * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st + * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. + */ +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFFU +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M (SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V << SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S) +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x00007FFFU +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 +/** SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO; bitpos: [16]; default: 0; + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V << SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 +/** SPI_MEM_NAND_FLASH_LUT_EN : HRO; bitpos: [17]; default: 0; + * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) +#define SPI_MEM_NAND_FLASH_LUT_EN_M (SPI_MEM_NAND_FLASH_LUT_EN_V << SPI_MEM_NAND_FLASH_LUT_EN_S) +#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x00000001U +#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 +/** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0; + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to + * execute page execute. 1: write end 0: write in a page size. + */ +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND (BIT(18)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S) +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S 18 + +/** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG (DR_REG_SPI_BASE + 0x208) +/** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR0_M (SPI_MEM_NAND_FLASH_SR_ADDR0_V << SPI_MEM_NAND_FLASH_SR_ADDR0_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 +/** SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO; bitpos: [15:8]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR1_M (SPI_MEM_NAND_FLASH_SR_ADDR1_V << SPI_MEM_NAND_FLASH_SR_ADDR1_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 +/** SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO; bitpos: [23:16]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR2_M (SPI_MEM_NAND_FLASH_SR_ADDR2_V << SPI_MEM_NAND_FLASH_SR_ADDR2_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 +/** SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO; bitpos: [31:24]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR3_M (SPI_MEM_NAND_FLASH_SR_ADDR3_V << SPI_MEM_NAND_FLASH_SR_ADDR3_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR3_S 24 + +/** SPI_MEM_NAND_FLASH_SR_DIN0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SR_DIN0_REG (DR_REG_SPI_BASE + 0x20c) +/** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN0_M (SPI_MEM_NAND_FLASH_SR_DIN0_V << SPI_MEM_NAND_FLASH_SR_DIN0_S) +#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 +/** SPI_MEM_NAND_FLASH_SR_DIN1 : RO; bitpos: [15:8]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN1_M (SPI_MEM_NAND_FLASH_SR_DIN1_V << SPI_MEM_NAND_FLASH_SR_DIN1_S) +#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 +/** SPI_MEM_NAND_FLASH_SR_DIN2 : RO; bitpos: [23:16]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN2_M (SPI_MEM_NAND_FLASH_SR_DIN2_V << SPI_MEM_NAND_FLASH_SR_DIN2_S) +#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 +/** SPI_MEM_NAND_FLASH_SR_DIN3 : RO; bitpos: [31:24]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN3_M (SPI_MEM_NAND_FLASH_SR_DIN3_V << SPI_MEM_NAND_FLASH_SR_DIN3_S) +#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN3_S 24 + +/** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG (DR_REG_SPI_BASE + 0x210) +/** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA0_M (SPI_MEM_NAND_FLASH_CFG_DATA0_V << SPI_MEM_NAND_FLASH_CFG_DATA0_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA1_M (SPI_MEM_NAND_FLASH_CFG_DATA1_V << SPI_MEM_NAND_FLASH_CFG_DATA1_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA1_S 16 + +/** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG (DR_REG_SPI_BASE + 0x214) +/** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA2_M (SPI_MEM_NAND_FLASH_CFG_DATA2_V << SPI_MEM_NAND_FLASH_CFG_DATA2_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA3_M (SPI_MEM_NAND_FLASH_CFG_DATA3_V << SPI_MEM_NAND_FLASH_CFG_DATA3_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA3_S 16 + +/** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG (DR_REG_SPI_BASE + 0x218) +/** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA4_M (SPI_MEM_NAND_FLASH_CFG_DATA4_V << SPI_MEM_NAND_FLASH_CFG_DATA4_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA5_M (SPI_MEM_NAND_FLASH_CFG_DATA5_V << SPI_MEM_NAND_FLASH_CFG_DATA5_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA5_S 16 + +/** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register + * MSPI NAND FLASH CMD LUT control register + */ +#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG (DR_REG_SPI_BASE + 0x240) +/** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; + * MSPI NAND FLASH config cmd value at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M (SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V << SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S) +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 +/** SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO; bitpos: [19:16]; default: 0; + * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; + * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. + */ +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M (SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V << SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S) +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 +/** SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO; bitpos: [23:20]; default: 0; + * MSPI NAND FLASH config cmd length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M (SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V << SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 +/** SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO; bitpos: [27:24]; default: 0; + * MSPI NAND FLASH config address length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M (SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V << SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 +/** SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO; bitpos: [29:28]; default: 0; + * MSPI NAND FLASH config data length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003U +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M (SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V << SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x00000003U +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 +/** SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO; bitpos: [30]; default: 0; + * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode + * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's + * field. The number of CMD LUT entries can be defined by the user, but cannot exceed + * 16 ) + */ +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0 (BIT(30)) +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V << SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S) +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S 30 + +/** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG (DR_REG_SPI_BASE + 0x280) +/** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; + * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for + * sequence. 0: Not the last index. + */ +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V << SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 +/** SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO; bitpos: [1]; default: 0; + * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (SPI_MEM_NAND_FLASH_SR_CHK_EN0_V << SPI_MEM_NAND_FLASH_SR_CHK_EN0_S) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 +/** SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO; bitpos: [5:2]; default: 0; + * MSPI NAND FLASH config din_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_CFG_DATA + */ +#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M (SPI_MEM_NAND_FLASH_DIN_INDEX0_V << SPI_MEM_NAND_FLASH_DIN_INDEX0_S) +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 +/** SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO; bitpos: [9:6]; default: 0; + * MSPI NAND FLASH config addr_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_SR_ADDR + */ +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M (SPI_MEM_NAND_FLASH_ADDR_INDEX0_V << SPI_MEM_NAND_FLASH_ADDR_INDEX0_S) +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 +/** SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO; bitpos: [10]; default: 0; + * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI + * SEQ configuration. + */ +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V << SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 +/** SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO; bitpos: [14:11]; default: 0; + * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in + * CMD LUT.(Note these registers are described to indicate the + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * by the user, but cannot exceed 16 ) + */ +#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M (SPI_MEM_NAND_FLASH_CMD_INDEX0_V << SPI_MEM_NAND_FLASH_CMD_INDEX0_S) +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_S 11 + +/** SPI_MEM_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) +/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_XTS_PLAIN 0xFFFFFFFFU +#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_XTS_PLAIN_S 0 + +/** SPI_MEM_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) +/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_XTS_LINESIZE 0x00000003U +#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_XTS_LINESIZE_V 0x00000003U +#define SPI_XTS_LINESIZE_S 0 + +/** SPI_MEM_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) +/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_XTS_DESTINATION (BIT(0)) +#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_XTS_DESTINATION_V 0x00000001U +#define SPI_XTS_DESTINATION_S 0 + +/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) +/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) +/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_XTS_TRIGGER (BIT(0)) +#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_XTS_TRIGGER_V 0x00000001U +#define SPI_XTS_TRIGGER_S 0 + +/** SPI_MEM_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) +/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_XTS_RELEASE (BIT(0)) +#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_XTS_RELEASE_V 0x00000001U +#define SPI_XTS_RELEASE_S 0 + +/** SPI_MEM_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) +/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_XTS_DESTROY (BIT(0)) +#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_XTS_DESTROY_V 0x00000001U +#define SPI_XTS_DESTROY_S 0 + +/** SPI_MEM_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) +/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_XTS_STATE 0x00000003U +#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_XTS_STATE_V 0x00000003U +#define SPI_XTS_STATE_S 0 + +/** SPI_MEM_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) +/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_XTS_DATE 0x3FFFFFFFU +#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_XTS_DATE_V 0x3FFFFFFFU +#define SPI_XTS_DATE_S 0 + +/** SPI_MEM_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) +/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) +/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) +/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MMU_MEM_FORCE_ON_S 0 +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PD_S 1 +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PU_S 2 +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MMU_PAGE_SIZE 0x00000003U +#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MMU_PAGE_SIZE_S 3 +/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_AUX_CTRL 0x00003FFFU +#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) +#define SPI_MEM_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_AUX_CTRL_S 16 +/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) +#define SPI_MEM_RDN_ENA_V 0x00000001U +#define SPI_MEM_RDN_ENA_S 30 +/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_RDN_RESULT (BIT(31)) +#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) +#define SPI_MEM_RDN_RESULT_V 0x00000001U +#define SPI_MEM_RDN_RESULT_S 31 + +/** SPI_MEM_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) +/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_SPI_BASE + 0x38c) +/** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_MODE_PSEUDO 0x00000003U +#define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) +#define SPI_MEM_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_MODE_PSEUDO_S 0 +/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) +#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) +#define SPI_MEM_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_PSEUDO_BASE_S 5 +/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_PSEUDO_INC 0x00000003U +#define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) +#define SPI_MEM_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_PSEUDO_INC_S 9 + +/** SPI_MEM_REGISTERRND_ECO_HIGH_REG register + * MSPI ECO high register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_SPI_BASE + 0x3f0) +/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_HIGH_M (SPI_MEM_REGISTERRND_ECO_HIGH_V << SPI_MEM_REGISTERRND_ECO_HIGH_S) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 + +/** SPI_MEM_REGISTERRND_ECO_LOW_REG register + * MSPI ECO low register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_SPI_BASE + 0x3f4) +/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_LOW_M (SPI_MEM_REGISTERRND_ECO_LOW_V << SPI_MEM_REGISTERRND_ECO_LOW_S) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 + +/** SPI_MEM_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; + * SPI0 register version. + */ +#define SPI_MEM_DATE 0x0FFFFFFFU +#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) +#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h new file mode 100644 index 0000000000..220deaf10b --- /dev/null +++ b/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h @@ -0,0 +1,2982 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of mem_cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mem_mst_st:4; + /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t mem_slv_st:4; + uint32_t reserved_8:10; + /** mem_usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t mem_usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_cmd_reg_t; + +/** Type of mem_axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t mem_axi_err_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of mem_ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t mem_wdummy_dqs_always_out:1; + /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t mem_wdummy_always_out:1; + /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t mem_fdummy_rin:1; + /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t mem_fdummy_wout:1; + /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t mem_fdout_oct:1; + /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t mem_fdin_oct:1; + /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t mem_faddr_oct:1; + uint32_t reserved_7:1; + /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_quad:1; + /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_oct:1; + uint32_t reserved_10:3; + /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t mem_fastrd_mode:1; + /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_dual:1; + uint32_t reserved_15:3; + /** mem_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t mem_q_pol:1; + /** mem_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t mem_d_pol:1; + /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_quad:1; + /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t mem_wp_reg:1; + uint32_t reserved_22:1; + /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_dio:1; + /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_qio:1; + uint32_t reserved_25:5; + /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t mem_dqs_ie_always_on:1; + /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t mem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_ctrl_reg_t; + +/** Type of mem_ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t mem_clk_mode:2; + uint32_t reserved_2:20; + /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ + uint32_t mem_rresp_ecc_err_en:1; + /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t mem_ar_splice_en:1; + /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t mem_aw_splice_en:1; + /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t mem_ram0_en:1; + /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t mem_dual_ram_en:1; + /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t mem_fast_write_en:1; + /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_rxfifo_rst:1; + /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_txfifo_rst:1; + }; + uint32_t val; +} spi_mem_ctrl1_reg_t; + +/** Type of mem_ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ + uint32_t mem_cs_setup_time:5; + /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ + uint32_t mem_cs_hold_time:5; + /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t mem_ecc_cs_hold_time:3; + /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t mem_ecc_skip_page_corner:1; + /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t mem_ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** mem_split_trans_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t mem_split_trans_en:1; + /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t mem_cs_hold_delay:6; + /** mem_sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t mem_sync_reset:1; + }; + uint32_t val; +} spi_mem_ctrl2_reg_t; + +/** Type of mem_misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t mem_fsub_pin:1; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t mem_ssub_pin:1; + /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t mem_ck_idle_edge:1; + /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t mem_cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_misc_reg_t; + +/** Type of mem_cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_axi_req_en:1; + /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_usr_addr_4byte:1; + /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_flash_usr_cmd:1; + /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_fdin_dual:1; + /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_fdout_dual:1; + /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_faddr_dual:1; + /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_fdin_quad:1; + /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_fdout_quad:1; + /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_faddr_quad:1; + uint32_t reserved_9:21; + /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_cache_fctrl_reg_t; + +/** Type of mem_ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of mem_clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. + */ + uint32_t mem_clkcnt_l:8; + /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). + */ + uint32_t mem_clkcnt_h:8; + /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_CLKCNT_N+1) + */ + uint32_t mem_clkcnt_n:8; + uint32_t reserved_24:7; + /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t mem_clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_clock_reg_t; + +/** Type of mem_sram_clk register + * SPI0 external RAM clock control register + */ +typedef union { + struct { + /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sclkcnt_l:8; + /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sclkcnt_h:8; + /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sclkcnt_n:8; + uint32_t reserved_24:7; + /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sclk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_sram_clk_reg_t; + +/** Type of mem_clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + /** mspi_clk_force_on : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ + uint32_t mspi_clk_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of mem_user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t mem_cs_hold:1; + /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t mem_cs_setup:1; + uint32_t reserved_8:1; + /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t mem_ck_out_edge:1; + uint32_t reserved_10:16; + /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t mem_usr_dummy_idle:1; + uint32_t reserved_27:2; + /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t mem_usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_user_reg_t; + +/** Type of mem_user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t mem_usr_dummy_cyclelen:6; + /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t mem_usr_dbytelen:6; + uint32_t reserved_12:14; + /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t mem_usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_user1_reg_t; + +/** Type of mem_user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t mem_usr_command_value:16; + uint32_t reserved_16:12; + /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t mem_usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_user2_reg_t; + +/** Type of mem_rd_status register + * SPI0 read control register. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode:8; + /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_bitlen:3; + /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_rd_status_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of mem_cache_sctrl register + * SPI0 external RAM control register + */ +typedef union { + struct { + /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_usr_saddr_4byte:1; + /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_usr_sram_dio:1; + /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_usr_sram_qio:1; + /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_usr_wr_sram_dummy:1; + /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_usr_rd_sram_dummy:1; + /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_rcmd:1; + /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sram_rdummy_cyclelen:6; + uint32_t reserved_12:2; + /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sram_addr_bitlen:6; + /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_wcmd:1; + /** mem_sram_oct : R/W; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sram_oct:1; + /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sram_wdummy_cyclelen:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_cache_sctrl_reg_t; + +/** Type of mem_sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sclk_mode:2; + /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_swb_mode:8; + /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_dual:1; + /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_dual:1; + /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_saddr_dual:1; + uint32_t reserved_13:1; + /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_quad:1; + /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_quad:1; + /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_saddr_quad:1; + /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_scmd_quad:1; + /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_oct:1; + /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_oct:1; + /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_saddr_oct:1; + /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_scmd_oct:1; + /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdummy_rin:1; + /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdummy_wout:1; + /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_hex:1; + /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_hex:1; + uint32_t reserved_28:2; + /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_sram_cmd_reg_t; + +/** Type of mem_sram_drd_cmd register + * SPI0 external RAM DDR read command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_rd_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_sram_drd_cmd_reg_t; + +/** Type of mem_sram_dwr_cmd register + * SPI0 external RAM DDR write command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_wr_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_sram_dwr_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of mem_fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t mem_lock_delay_time:12; + /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_flash_lock_en:1; + /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_sram_lock_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_mem_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of mem_int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_ena:1; + /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_ena:1; + /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_ena:1; + /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_ena:1; + /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_ena:1; + /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_ena:1; + /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_ena:1; + /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_ena:1; + /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_ena:1; + /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_ena:1; + }; + uint32_t val; +} spi_mem_int_ena_reg_t; + +/** Type of mem_int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_clr:1; + /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_clr:1; + /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_clr:1; + /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_clr:1; + /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_clr:1; + /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_clr:1; + /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_clr:1; + /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_clr:1; + /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_clr:1; + /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_clr:1; + }; + uint32_t val; +} spi_mem_int_clr_reg_t; + +/** Type of mem_int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t mem_slv_st_end_int_raw:1; + /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mem_mst_st_end_int_raw:1; + /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t mem_ecc_err_int_raw:1; + /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t mem_pms_reject_int_raw:1; + /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_raddr_err_int_raw:1; + /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t mem_axi_wr_flash_err_int_raw:1; + /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ + uint32_t mem_dqs0_afifo_ovf_int_raw:1; + /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ + uint32_t mem_dqs1_afifo_ovf_int_raw:1; + /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo1_udf_int_raw:1; + /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo0_udf_int_raw:1; + }; + uint32_t val; +} spi_mem_int_raw_reg_t; + +/** Type of mem_int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_st:1; + /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_st:1; + /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_st:1; + /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_st:1; + /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_st:1; + /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_st:1; + /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_st:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_st:1; + /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_st:1; + /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_st:1; + /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_st:1; + }; + uint32_t val; +} spi_mem_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * SPI1 flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section n start address value + */ + uint32_t fmem_pmsn_addr_s:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) + */ + uint32_t fmem_pmsn_size:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 external RAM PMS section n attribute register + */ +typedef union { + struct { + /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_rd_attr:1; + /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_wr_attr:1; + /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section n start address value + */ + uint32_t smem_pmsn_addr_s:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) + */ + uint32_t smem_pmsn_size:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_smem_pmsn_size_reg_t; + +/** Type of mem_pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** mem_pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t mem_pm_en:1; + /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ld:1; + /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_st:1; + /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_multi_hit:1; + /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ivd:1; + }; + uint32_t val; +} spi_mem_pms_reject_reg_t; + +/** Type of mem_pms_reject_addr register + * SPI1 access reject addr register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_pms_reject_addr_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of mem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_cnt:6; + /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + uint32_t reserved_20:1; + /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t mem_usr_ecc_addr_en:1; + uint32_t reserved_23:1; + /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t mem_ecc_continue_record_err_en:1; + /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t mem_ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_ecc_ctrl_reg_t; + +/** Type of mem_ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t mem_all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_smem_axi_addr_ctrl_reg_t; + +/** Type of mem_axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_vld:1; + /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_gid:1; + /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_size:1; + /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_flash:1; + /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_ecc:1; + /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_sens:1; + /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_wstrb:1; + /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_vld:1; + /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_gid:1; + /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_ecc:1; + /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t mem_ar_resp_en_mmu_sens:1; + /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t mem_ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of mem_timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t mem_timing_clk_ena:1; + /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t mem_timing_cali:1; + /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t mem_extra_dummy_cyclelen:3; + /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t mem_dll_timing_cali:1; + /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t mem_timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_timing_cali_reg_t; + +/** Type of mem_din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din0_mode:3; + /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din1_mode:3; + /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din2_mode:3; + /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din3_mode:3; + /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din4_mode:3; + /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din5_mode:3; + /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din6_mode:3; + /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din7_mode:3; + /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_din_mode_reg_t; + +/** Type of mem_din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din0_num:2; + /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din1_num:2; + /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din2_num:2; + /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din3_num:2; + /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din4_num:2; + /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din5_num:2; + /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din6_num:2; + /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din7_num:2; + /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_din_num_reg_t; + +/** Type of mem_dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout0_mode:1; + /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout1_mode:1; + /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout2_mode:1; + /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout3_mode:1; + /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout4_mode:1; + /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout5_mode:1; + /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout6_mode:1; + /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout7_mode:1; + /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:1; + /** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_270_sel:2; + /** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_90_sel:2; + /** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_270_sel:2; + /** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_90_sel:2; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_mode_reg_t; + +/** Type of smem_din_hex_mode register + * MSPI 16x external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din08_mode : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din08_mode:3; + /** smem_din09_mode : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din09_mode:3; + /** smem_din10_mode : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din10_mode:3; + /** smem_din11_mode : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din11_mode:3; + /** smem_din12_mode : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din12_mode:3; + /** smem_din13_mode : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din13_mode:3; + /** smem_din14_mode : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din14_mode:3; + /** smem_din15_mode : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din15_mode:3; + /** smem_dins_hex_mode : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_hex_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_hex_mode_reg_t; + +/** Type of smem_din_hex_num register + * MSPI 16x external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din08_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din08_num:2; + /** smem_din09_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din09_num:2; + /** smem_din10_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din10_num:2; + /** smem_din11_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din11_num:2; + /** smem_din12_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din12_num:2; + /** smem_din13_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din13_num:2; + /** smem_din14_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din14_num:2; + /** smem_din15_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din15_num:2; + /** smem_dins_hex_num : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_hex_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_hex_num_reg_t; + +/** Type of smem_dout_hex_mode register + * MSPI 16x external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout08_mode : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout08_mode:1; + /** smem_dout09_mode : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout09_mode:1; + /** smem_dout10_mode : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout10_mode:1; + /** smem_dout11_mode : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout11_mode:1; + /** smem_dout12_mode : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout12_mode:1; + /** smem_dout13_mode : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout13_mode:1; + /** smem_dout14_mode : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout14_mode:1; + /** smem_dout15_mode : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout15_mode:1; + /** smem_douts_hex_mode : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_hex_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_hex_mode_reg_t; + + +/** Group: NAND FLASH control and status registers */ +/** Type of mem_nand_flash_en register + * NAND FLASH control register + */ +typedef union { + struct { + /** mem_nand_flash_en : HRO; bitpos: [0]; default: 0; + * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: + * Disable NAND FLASH, Enable NOR FLASH. + */ + uint32_t mem_nand_flash_en:1; + /** mem_nand_flash_seq_hd_index : HRO; bitpos: [15:1]; default: 32767; + * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st + * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. + */ + uint32_t mem_nand_flash_seq_hd_index:15; + /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + */ + uint32_t mem_nand_flash_seq_usr_trig:1; + /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; + * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. + */ + uint32_t mem_nand_flash_lut_en:1; + /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to + * execute page execute. 1: write end 0: write in a page size. + */ + uint32_t mem_nand_flash_seq_usr_wend:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_nand_flash_en_reg_t; + +/** Type of mem_nand_flash_sr_addr0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_sr_addr0 : HRO; bitpos: [7:0]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr0:8; + /** mem_nand_flash_sr_addr1 : HRO; bitpos: [15:8]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr1:8; + /** mem_nand_flash_sr_addr2 : HRO; bitpos: [23:16]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr2:8; + /** mem_nand_flash_sr_addr3 : HRO; bitpos: [31:24]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr3:8; + }; + uint32_t val; +} spi_mem_nand_flash_sr_addr0_reg_t; + +/** Type of mem_nand_flash_sr_din0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din0:8; + /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din1:8; + /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din2:8; + /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din3:8; + }; + uint32_t val; +} spi_mem_nand_flash_sr_din0_reg_t; + +/** Type of mem_nand_flash_cfg_data0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data0 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data0:16; + /** mem_nand_flash_cfg_data1 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data1:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data0_reg_t; + +/** Type of mem_nand_flash_cfg_data1 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data2 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data2:16; + /** mem_nand_flash_cfg_data3 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data3:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data1_reg_t; + +/** Type of mem_nand_flash_cfg_data2 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data4 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data4:16; + /** mem_nand_flash_cfg_data5 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data5:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data2_reg_t; + +/** Type of mem_nand_flash_cmd_lut0 register + * MSPI NAND FLASH CMD LUT control register + */ +typedef union { + struct { + /** mem_nand_flash_lut_cmd_value0 : HRO; bitpos: [15:0]; default: 0; + * MSPI NAND FLASH config cmd value at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_cmd_value0:16; + /** mem_nand_flash_lut_sfsm_st_en0 : HRO; bitpos: [19:16]; default: 0; + * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; + * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. + */ + uint32_t mem_nand_flash_lut_sfsm_st_en0:4; + /** mem_nand_flash_lut_cmd_len0 : HRO; bitpos: [23:20]; default: 0; + * MSPI NAND FLASH config cmd length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_cmd_len0:4; + /** mem_nand_flash_lut_addr_len0 : HRO; bitpos: [27:24]; default: 0; + * MSPI NAND FLASH config address length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_addr_len0:4; + /** mem_nand_flash_lut_data_len0 : HRO; bitpos: [29:28]; default: 0; + * MSPI NAND FLASH config data length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_data_len0:2; + /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; + * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode + * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's + * field. The number of CMD LUT entries can be defined by the user, but cannot exceed + * 16 ) + */ + uint32_t mem_nand_flash_lut_bus_en0:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_nand_flash_cmd_lut0_reg_t; + +/** Type of mem_nand_flash_spi_seq0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_seq_tail_flg0 : HRO; bitpos: [0]; default: 0; + * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for + * sequence. 0: Not the last index. + */ + uint32_t mem_nand_flash_seq_tail_flg0:1; + /** mem_nand_flash_sr_chk_en0 : HRO; bitpos: [1]; default: 0; + * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. + */ + uint32_t mem_nand_flash_sr_chk_en0:1; + /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; + * MSPI NAND FLASH config din_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_CFG_DATA + */ + uint32_t mem_nand_flash_din_index0:4; + /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; + * MSPI NAND FLASH config addr_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_SR_ADDR + */ + uint32_t mem_nand_flash_addr_index0:4; + /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; + * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI + * SEQ configuration. + */ + uint32_t mem_nand_flash_req_or_cfg0:1; + /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; + * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in + * CMD LUT.(Note these registers are described to indicate the + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * by the user, but cannot exceed 16 ) + */ + uint32_t mem_nand_flash_cmd_index0:4; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_nand_flash_spi_seq0_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of mem_xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of mem_xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_linesize_reg_t; + +/** Type of mem_xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destination_reg_t; + +/** Type of mem_xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of mem_xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_trigger_reg_t; + +/** Type of mem_xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_release_reg_t; + +/** Type of mem_xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destroy_reg_t; + +/** Type of mem_xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of mem_xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mem_mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_mmu_item_content_reg_t; + +/** Type of mem_mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mem_mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; + /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t mem_aux_ctrl:14; + /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_rdn_ena:1; + /** mem_rdn_result : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_rdn_result:1; + }; + uint32_t val; +} spi_mem_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of mem_dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_dpa_ctrl_reg_t; + + +/** Group: External mem cryption PSEUDO registers */ +/** Type of mem_xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mem_mode_pseudo:2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_base:4; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ + uint32_t mem_pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_xts_pseudo_round_conf_reg_t; + + +/** Group: ECO registers */ +/** Type of mem_registerrnd_eco_high register + * MSPI ECO high register + */ +typedef union { + struct { + /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_registerrnd_eco_high:32; + }; + uint32_t val; +} spi_mem_registerrnd_eco_high_reg_t; + +/** Type of mem_registerrnd_eco_low register + * MSPI ECO low register + */ +typedef union { + struct { + /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_registerrnd_eco_low:32; + }; + uint32_t val; +} spi_mem_registerrnd_eco_low_reg_t; + + +/** Group: Version control register */ +/** Type of mem_date register + * SPI0 version control register + */ +typedef union { + struct { + /** mem_date : R/W; bitpos: [27:0]; default: 37822512; + * SPI0 register version. + */ + uint32_t mem_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_date_reg_t; + + +typedef struct { + volatile spi_mem_cmd_reg_t mem_cmd; + uint32_t reserved_004; + volatile spi_mem_ctrl_reg_t mem_ctrl; + volatile spi_mem_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_clock_reg_t mem_clock; + volatile spi_mem_user_reg_t mem_user; + volatile spi_mem_user1_reg_t mem_user1; + volatile spi_mem_user2_reg_t mem_user2; + uint32_t reserved_024[2]; + volatile spi_mem_rd_status_reg_t mem_rd_status; + uint32_t reserved_030; + volatile spi_mem_misc_reg_t mem_misc; + uint32_t reserved_038; + volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; + volatile spi_mem_cache_sctrl_reg_t mem_cache_sctrl; + volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; + volatile spi_mem_sram_drd_cmd_reg_t mem_sram_drd_cmd; + volatile spi_mem_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; + volatile spi_mem_sram_clk_reg_t mem_sram_clk; + volatile spi_mem_fsm_reg_t mem_fsm; + uint32_t reserved_058[26]; + volatile spi_mem_int_ena_reg_t mem_int_ena; + volatile spi_mem_int_clr_reg_t mem_int_clr; + volatile spi_mem_int_raw_reg_t mem_int_raw; + volatile spi_mem_int_st_reg_t mem_int_st; + uint32_t reserved_0d0; + volatile spi_mem_ddr_reg_t mem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; + volatile spi_mem_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_pms_reject_addr_reg_t mem_pms_reject_addr; + volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_din_mode_reg_t mem_din_mode; + volatile spi_mem_din_num_reg_t mem_din_num; + volatile spi_mem_dout_mode_reg_t mem_dout_mode; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; + volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; + volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; + volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; + uint32_t reserved_1b0[20]; + volatile spi_mem_clock_gate_reg_t mem_clock_gate; + volatile spi_mem_nand_flash_en_reg_t mem_nand_flash_en; + volatile spi_mem_nand_flash_sr_addr0_reg_t mem_nand_flash_sr_addr0; + volatile spi_mem_nand_flash_sr_din0_reg_t mem_nand_flash_sr_din0; + volatile spi_mem_nand_flash_cfg_data0_reg_t mem_nand_flash_cfg_data0; + volatile spi_mem_nand_flash_cfg_data1_reg_t mem_nand_flash_cfg_data1; + volatile spi_mem_nand_flash_cfg_data2_reg_t mem_nand_flash_cfg_data2; + uint32_t reserved_21c[9]; + volatile spi_mem_nand_flash_cmd_lut0_reg_t mem_nand_flash_cmd_lut0; + uint32_t reserved_244[15]; + volatile spi_mem_nand_flash_spi_seq0_reg_t mem_nand_flash_spi_seq0; + uint32_t reserved_284[31]; + volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_xts_release_reg_t mem_xts_release; + volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_xts_state_reg_t mem_xts_state; + volatile spi_mem_xts_date_reg_t mem_xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; + volatile spi_mem_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; + uint32_t reserved_390[24]; + volatile spi_mem_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; + volatile spi_mem_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; + uint32_t reserved_3f8; + volatile spi_mem_date_reg_t mem_date; +} spi_dev_t; + +extern spi_dev_t SPIMEM0; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/register/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h index a0be766c73..48caf26c3d 100644 --- a/components/soc/esp32c5/register/soc/tee_reg.h +++ b/components/soc/esp32c5/register/soc/tee_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,11 @@ extern "C" { */ #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) /** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M0 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M0 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M0_MODE 0x00000003U #define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) @@ -39,11 +39,11 @@ extern "C" { */ #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) /** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M1 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M1 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M1_MODE 0x00000003U #define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) @@ -62,11 +62,11 @@ extern "C" { */ #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) /** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M2 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M2 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M2_MODE 0x00000003U #define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) @@ -85,11 +85,11 @@ extern "C" { */ #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) /** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M3 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M3 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M3_MODE 0x00000003U #define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) @@ -108,11 +108,11 @@ extern "C" { */ #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) /** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M4 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M4 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M4_MODE 0x00000003U #define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) @@ -131,11 +131,11 @@ extern "C" { */ #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) /** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M5 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M5 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M5_MODE 0x00000003U #define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) @@ -154,11 +154,11 @@ extern "C" { */ #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) /** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M6 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M6 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M6_MODE 0x00000003U #define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) @@ -177,11 +177,11 @@ extern "C" { */ #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) /** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M7 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M7 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M7_MODE 0x00000003U #define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) @@ -200,11 +200,11 @@ extern "C" { */ #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) /** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M8 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M8 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M8_MODE 0x00000003U #define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) @@ -223,11 +223,11 @@ extern "C" { */ #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) /** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M9 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M9 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M9_MODE 0x00000003U #define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) @@ -246,11 +246,11 @@ extern "C" { */ #define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) /** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M10 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M10 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M10_MODE 0x00000003U #define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) @@ -269,11 +269,11 @@ extern "C" { */ #define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) /** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M11 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M11 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M11_MODE 0x00000003U #define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) @@ -292,11 +292,11 @@ extern "C" { */ #define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) /** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M12 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M12 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M12_MODE 0x00000003U #define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) @@ -315,11 +315,11 @@ extern "C" { */ #define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) /** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M13 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M13 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M13_MODE 0x00000003U #define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) @@ -338,11 +338,11 @@ extern "C" { */ #define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) /** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M14 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M14 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M14_MODE 0x00000003U #define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) @@ -361,11 +361,11 @@ extern "C" { */ #define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) /** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M15 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M15 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M15_MODE 0x00000003U #define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) @@ -384,11 +384,11 @@ extern "C" { */ #define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) /** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M16 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M16 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M16_MODE 0x00000003U #define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) @@ -407,11 +407,11 @@ extern "C" { */ #define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) /** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M17 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M17 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M17_MODE 0x00000003U #define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) @@ -430,11 +430,11 @@ extern "C" { */ #define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) /** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M18 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M18 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M18_MODE 0x00000003U #define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) @@ -453,11 +453,11 @@ extern "C" { */ #define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) /** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M19 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M19 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M19_MODE 0x00000003U #define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) @@ -476,11 +476,11 @@ extern "C" { */ #define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) /** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M20 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M20 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M20_MODE 0x00000003U #define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) @@ -499,11 +499,11 @@ extern "C" { */ #define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) /** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M21 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M21 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M21_MODE 0x00000003U #define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) @@ -522,11 +522,11 @@ extern "C" { */ #define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) /** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M22 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M22 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M22_MODE 0x00000003U #define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) @@ -545,11 +545,11 @@ extern "C" { */ #define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) /** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M23 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M23 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M23_MODE 0x00000003U #define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) @@ -568,11 +568,11 @@ extern "C" { */ #define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) /** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M24 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M24 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M24_MODE 0x00000003U #define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) @@ -591,11 +591,11 @@ extern "C" { */ #define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) /** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M25 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M25 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M25_MODE 0x00000003U #define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) @@ -614,11 +614,11 @@ extern "C" { */ #define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) /** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M26 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M26 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M26_MODE 0x00000003U #define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) @@ -637,11 +637,11 @@ extern "C" { */ #define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) /** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M27 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M27 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M27_MODE 0x00000003U #define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) @@ -660,11 +660,11 @@ extern "C" { */ #define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) /** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M28 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M28 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M28_MODE 0x00000003U #define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) @@ -683,11 +683,11 @@ extern "C" { */ #define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) /** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M29 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M29 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M29_MODE 0x00000003U #define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) @@ -706,11 +706,11 @@ extern "C" { */ #define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) /** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M30 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M30 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M30_MODE 0x00000003U #define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) @@ -729,11 +729,11 @@ extern "C" { */ #define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) /** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M31 security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures M31 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ #define TEE_M31_MODE 0x00000003U #define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) @@ -747,14 +747,3493 @@ extern "C" { #define TEE_M31_LOCK_V 0x00000001U #define TEE_M31_LOCK_S 2 +/** TEE_UART0_CTRL_REG register + * uart0 read/write control register + */ +#define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) +/** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART0 (BIT(0)) +#define TEE_READ_TEE_UART0_M (TEE_READ_TEE_UART0_V << TEE_READ_TEE_UART0_S) +#define TEE_READ_TEE_UART0_V 0x00000001U +#define TEE_READ_TEE_UART0_S 0 +/** TEE_READ_REE0_UART0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART0 (BIT(1)) +#define TEE_READ_REE0_UART0_M (TEE_READ_REE0_UART0_V << TEE_READ_REE0_UART0_S) +#define TEE_READ_REE0_UART0_V 0x00000001U +#define TEE_READ_REE0_UART0_S 1 +/** TEE_READ_REE1_UART0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART0 (BIT(2)) +#define TEE_READ_REE1_UART0_M (TEE_READ_REE1_UART0_V << TEE_READ_REE1_UART0_S) +#define TEE_READ_REE1_UART0_V 0x00000001U +#define TEE_READ_REE1_UART0_S 2 +/** TEE_READ_REE2_UART0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART0 (BIT(3)) +#define TEE_READ_REE2_UART0_M (TEE_READ_REE2_UART0_V << TEE_READ_REE2_UART0_S) +#define TEE_READ_REE2_UART0_V 0x00000001U +#define TEE_READ_REE2_UART0_S 3 +/** TEE_WRITE_TEE_UART0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART0 (BIT(4)) +#define TEE_WRITE_TEE_UART0_M (TEE_WRITE_TEE_UART0_V << TEE_WRITE_TEE_UART0_S) +#define TEE_WRITE_TEE_UART0_V 0x00000001U +#define TEE_WRITE_TEE_UART0_S 4 +/** TEE_WRITE_REE0_UART0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART0 (BIT(5)) +#define TEE_WRITE_REE0_UART0_M (TEE_WRITE_REE0_UART0_V << TEE_WRITE_REE0_UART0_S) +#define TEE_WRITE_REE0_UART0_V 0x00000001U +#define TEE_WRITE_REE0_UART0_S 5 +/** TEE_WRITE_REE1_UART0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART0 (BIT(6)) +#define TEE_WRITE_REE1_UART0_M (TEE_WRITE_REE1_UART0_V << TEE_WRITE_REE1_UART0_S) +#define TEE_WRITE_REE1_UART0_V 0x00000001U +#define TEE_WRITE_REE1_UART0_S 6 +/** TEE_WRITE_REE2_UART0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART0 (BIT(7)) +#define TEE_WRITE_REE2_UART0_M (TEE_WRITE_REE2_UART0_V << TEE_WRITE_REE2_UART0_S) +#define TEE_WRITE_REE2_UART0_V 0x00000001U +#define TEE_WRITE_REE2_UART0_S 7 + +/** TEE_UART1_CTRL_REG register + * uart1 read/write control register + */ +#define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) +/** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART1 (BIT(0)) +#define TEE_READ_TEE_UART1_M (TEE_READ_TEE_UART1_V << TEE_READ_TEE_UART1_S) +#define TEE_READ_TEE_UART1_V 0x00000001U +#define TEE_READ_TEE_UART1_S 0 +/** TEE_READ_REE0_UART1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART1 (BIT(1)) +#define TEE_READ_REE0_UART1_M (TEE_READ_REE0_UART1_V << TEE_READ_REE0_UART1_S) +#define TEE_READ_REE0_UART1_V 0x00000001U +#define TEE_READ_REE0_UART1_S 1 +/** TEE_READ_REE1_UART1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART1 (BIT(2)) +#define TEE_READ_REE1_UART1_M (TEE_READ_REE1_UART1_V << TEE_READ_REE1_UART1_S) +#define TEE_READ_REE1_UART1_V 0x00000001U +#define TEE_READ_REE1_UART1_S 2 +/** TEE_READ_REE2_UART1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART1 (BIT(3)) +#define TEE_READ_REE2_UART1_M (TEE_READ_REE2_UART1_V << TEE_READ_REE2_UART1_S) +#define TEE_READ_REE2_UART1_V 0x00000001U +#define TEE_READ_REE2_UART1_S 3 +/** TEE_WRITE_TEE_UART1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART1 (BIT(4)) +#define TEE_WRITE_TEE_UART1_M (TEE_WRITE_TEE_UART1_V << TEE_WRITE_TEE_UART1_S) +#define TEE_WRITE_TEE_UART1_V 0x00000001U +#define TEE_WRITE_TEE_UART1_S 4 +/** TEE_WRITE_REE0_UART1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART1 (BIT(5)) +#define TEE_WRITE_REE0_UART1_M (TEE_WRITE_REE0_UART1_V << TEE_WRITE_REE0_UART1_S) +#define TEE_WRITE_REE0_UART1_V 0x00000001U +#define TEE_WRITE_REE0_UART1_S 5 +/** TEE_WRITE_REE1_UART1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART1 (BIT(6)) +#define TEE_WRITE_REE1_UART1_M (TEE_WRITE_REE1_UART1_V << TEE_WRITE_REE1_UART1_S) +#define TEE_WRITE_REE1_UART1_V 0x00000001U +#define TEE_WRITE_REE1_UART1_S 6 +/** TEE_WRITE_REE2_UART1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART1 (BIT(7)) +#define TEE_WRITE_REE2_UART1_M (TEE_WRITE_REE2_UART1_V << TEE_WRITE_REE2_UART1_S) +#define TEE_WRITE_REE2_UART1_V 0x00000001U +#define TEE_WRITE_REE2_UART1_S 7 + +/** TEE_UHCI0_CTRL_REG register + * uhci0 read/write control register + */ +#define TEE_UHCI0_CTRL_REG (DR_REG_TEE_BASE + 0x90) +/** TEE_READ_TEE_UHCI0 : R/W; bitpos: [0]; default: 1; + * Configures uhci0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UHCI0 (BIT(0)) +#define TEE_READ_TEE_UHCI0_M (TEE_READ_TEE_UHCI0_V << TEE_READ_TEE_UHCI0_S) +#define TEE_READ_TEE_UHCI0_V 0x00000001U +#define TEE_READ_TEE_UHCI0_S 0 +/** TEE_READ_REE0_UHCI0 : R/W; bitpos: [1]; default: 0; + * Configures uhci0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UHCI0 (BIT(1)) +#define TEE_READ_REE0_UHCI0_M (TEE_READ_REE0_UHCI0_V << TEE_READ_REE0_UHCI0_S) +#define TEE_READ_REE0_UHCI0_V 0x00000001U +#define TEE_READ_REE0_UHCI0_S 1 +/** TEE_READ_REE1_UHCI0 : R/W; bitpos: [2]; default: 0; + * Configures uhci0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UHCI0 (BIT(2)) +#define TEE_READ_REE1_UHCI0_M (TEE_READ_REE1_UHCI0_V << TEE_READ_REE1_UHCI0_S) +#define TEE_READ_REE1_UHCI0_V 0x00000001U +#define TEE_READ_REE1_UHCI0_S 2 +/** TEE_READ_REE2_UHCI0 : R/W; bitpos: [3]; default: 0; + * Configures uhci0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UHCI0 (BIT(3)) +#define TEE_READ_REE2_UHCI0_M (TEE_READ_REE2_UHCI0_V << TEE_READ_REE2_UHCI0_S) +#define TEE_READ_REE2_UHCI0_V 0x00000001U +#define TEE_READ_REE2_UHCI0_S 3 +/** TEE_WRITE_TEE_UHCI0 : R/W; bitpos: [4]; default: 1; + * Configures uhci0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UHCI0 (BIT(4)) +#define TEE_WRITE_TEE_UHCI0_M (TEE_WRITE_TEE_UHCI0_V << TEE_WRITE_TEE_UHCI0_S) +#define TEE_WRITE_TEE_UHCI0_V 0x00000001U +#define TEE_WRITE_TEE_UHCI0_S 4 +/** TEE_WRITE_REE0_UHCI0 : R/W; bitpos: [5]; default: 0; + * Configures uhci0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UHCI0 (BIT(5)) +#define TEE_WRITE_REE0_UHCI0_M (TEE_WRITE_REE0_UHCI0_V << TEE_WRITE_REE0_UHCI0_S) +#define TEE_WRITE_REE0_UHCI0_V 0x00000001U +#define TEE_WRITE_REE0_UHCI0_S 5 +/** TEE_WRITE_REE1_UHCI0 : R/W; bitpos: [6]; default: 0; + * Configures uhci0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UHCI0 (BIT(6)) +#define TEE_WRITE_REE1_UHCI0_M (TEE_WRITE_REE1_UHCI0_V << TEE_WRITE_REE1_UHCI0_S) +#define TEE_WRITE_REE1_UHCI0_V 0x00000001U +#define TEE_WRITE_REE1_UHCI0_S 6 +/** TEE_WRITE_REE2_UHCI0 : R/W; bitpos: [7]; default: 0; + * Configures uhci0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UHCI0 (BIT(7)) +#define TEE_WRITE_REE2_UHCI0_M (TEE_WRITE_REE2_UHCI0_V << TEE_WRITE_REE2_UHCI0_S) +#define TEE_WRITE_REE2_UHCI0_V 0x00000001U +#define TEE_WRITE_REE2_UHCI0_S 7 + +/** TEE_I2C_EXT0_CTRL_REG register + * i2c_ext0 read/write control register + */ +#define TEE_I2C_EXT0_CTRL_REG (DR_REG_TEE_BASE + 0x94) +/** TEE_READ_TEE_I2C_EXT0 : R/W; bitpos: [0]; default: 1; + * Configures i2c_ext0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2C_EXT0 (BIT(0)) +#define TEE_READ_TEE_I2C_EXT0_M (TEE_READ_TEE_I2C_EXT0_V << TEE_READ_TEE_I2C_EXT0_S) +#define TEE_READ_TEE_I2C_EXT0_V 0x00000001U +#define TEE_READ_TEE_I2C_EXT0_S 0 +/** TEE_READ_REE0_I2C_EXT0 : R/W; bitpos: [1]; default: 0; + * Configures i2c_ext0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2C_EXT0 (BIT(1)) +#define TEE_READ_REE0_I2C_EXT0_M (TEE_READ_REE0_I2C_EXT0_V << TEE_READ_REE0_I2C_EXT0_S) +#define TEE_READ_REE0_I2C_EXT0_V 0x00000001U +#define TEE_READ_REE0_I2C_EXT0_S 1 +/** TEE_READ_REE1_I2C_EXT0 : R/W; bitpos: [2]; default: 0; + * Configures i2c_ext0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2C_EXT0 (BIT(2)) +#define TEE_READ_REE1_I2C_EXT0_M (TEE_READ_REE1_I2C_EXT0_V << TEE_READ_REE1_I2C_EXT0_S) +#define TEE_READ_REE1_I2C_EXT0_V 0x00000001U +#define TEE_READ_REE1_I2C_EXT0_S 2 +/** TEE_READ_REE2_I2C_EXT0 : R/W; bitpos: [3]; default: 0; + * Configures i2c_ext0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2C_EXT0 (BIT(3)) +#define TEE_READ_REE2_I2C_EXT0_M (TEE_READ_REE2_I2C_EXT0_V << TEE_READ_REE2_I2C_EXT0_S) +#define TEE_READ_REE2_I2C_EXT0_V 0x00000001U +#define TEE_READ_REE2_I2C_EXT0_S 3 +/** TEE_WRITE_TEE_I2C_EXT0 : R/W; bitpos: [4]; default: 1; + * Configures i2c_ext0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2C_EXT0 (BIT(4)) +#define TEE_WRITE_TEE_I2C_EXT0_M (TEE_WRITE_TEE_I2C_EXT0_V << TEE_WRITE_TEE_I2C_EXT0_S) +#define TEE_WRITE_TEE_I2C_EXT0_V 0x00000001U +#define TEE_WRITE_TEE_I2C_EXT0_S 4 +/** TEE_WRITE_REE0_I2C_EXT0 : R/W; bitpos: [5]; default: 0; + * Configures i2c_ext0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2C_EXT0 (BIT(5)) +#define TEE_WRITE_REE0_I2C_EXT0_M (TEE_WRITE_REE0_I2C_EXT0_V << TEE_WRITE_REE0_I2C_EXT0_S) +#define TEE_WRITE_REE0_I2C_EXT0_V 0x00000001U +#define TEE_WRITE_REE0_I2C_EXT0_S 5 +/** TEE_WRITE_REE1_I2C_EXT0 : R/W; bitpos: [6]; default: 0; + * Configures i2c_ext0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2C_EXT0 (BIT(6)) +#define TEE_WRITE_REE1_I2C_EXT0_M (TEE_WRITE_REE1_I2C_EXT0_V << TEE_WRITE_REE1_I2C_EXT0_S) +#define TEE_WRITE_REE1_I2C_EXT0_V 0x00000001U +#define TEE_WRITE_REE1_I2C_EXT0_S 6 +/** TEE_WRITE_REE2_I2C_EXT0 : R/W; bitpos: [7]; default: 0; + * Configures i2c_ext0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2C_EXT0 (BIT(7)) +#define TEE_WRITE_REE2_I2C_EXT0_M (TEE_WRITE_REE2_I2C_EXT0_V << TEE_WRITE_REE2_I2C_EXT0_S) +#define TEE_WRITE_REE2_I2C_EXT0_V 0x00000001U +#define TEE_WRITE_REE2_I2C_EXT0_S 7 + +/** TEE_I2S_CTRL_REG register + * i2s read/write control register + */ +#define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) +/** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2S (BIT(0)) +#define TEE_READ_TEE_I2S_M (TEE_READ_TEE_I2S_V << TEE_READ_TEE_I2S_S) +#define TEE_READ_TEE_I2S_V 0x00000001U +#define TEE_READ_TEE_I2S_S 0 +/** TEE_READ_REE0_I2S : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2S (BIT(1)) +#define TEE_READ_REE0_I2S_M (TEE_READ_REE0_I2S_V << TEE_READ_REE0_I2S_S) +#define TEE_READ_REE0_I2S_V 0x00000001U +#define TEE_READ_REE0_I2S_S 1 +/** TEE_READ_REE1_I2S : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2S (BIT(2)) +#define TEE_READ_REE1_I2S_M (TEE_READ_REE1_I2S_V << TEE_READ_REE1_I2S_S) +#define TEE_READ_REE1_I2S_V 0x00000001U +#define TEE_READ_REE1_I2S_S 2 +/** TEE_READ_REE2_I2S : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2S (BIT(3)) +#define TEE_READ_REE2_I2S_M (TEE_READ_REE2_I2S_V << TEE_READ_REE2_I2S_S) +#define TEE_READ_REE2_I2S_V 0x00000001U +#define TEE_READ_REE2_I2S_S 3 +/** TEE_WRITE_TEE_I2S : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2S (BIT(4)) +#define TEE_WRITE_TEE_I2S_M (TEE_WRITE_TEE_I2S_V << TEE_WRITE_TEE_I2S_S) +#define TEE_WRITE_TEE_I2S_V 0x00000001U +#define TEE_WRITE_TEE_I2S_S 4 +/** TEE_WRITE_REE0_I2S : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2S (BIT(5)) +#define TEE_WRITE_REE0_I2S_M (TEE_WRITE_REE0_I2S_V << TEE_WRITE_REE0_I2S_S) +#define TEE_WRITE_REE0_I2S_V 0x00000001U +#define TEE_WRITE_REE0_I2S_S 5 +/** TEE_WRITE_REE1_I2S : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2S (BIT(6)) +#define TEE_WRITE_REE1_I2S_M (TEE_WRITE_REE1_I2S_V << TEE_WRITE_REE1_I2S_S) +#define TEE_WRITE_REE1_I2S_V 0x00000001U +#define TEE_WRITE_REE1_I2S_S 6 +/** TEE_WRITE_REE2_I2S : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2S (BIT(7)) +#define TEE_WRITE_REE2_I2S_M (TEE_WRITE_REE2_I2S_V << TEE_WRITE_REE2_I2S_S) +#define TEE_WRITE_REE2_I2S_V 0x00000001U +#define TEE_WRITE_REE2_I2S_S 7 + +/** TEE_PARL_IO_CTRL_REG register + * parl_io read/write control register + */ +#define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) +/** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PARL_IO (BIT(0)) +#define TEE_READ_TEE_PARL_IO_M (TEE_READ_TEE_PARL_IO_V << TEE_READ_TEE_PARL_IO_S) +#define TEE_READ_TEE_PARL_IO_V 0x00000001U +#define TEE_READ_TEE_PARL_IO_S 0 +/** TEE_READ_REE0_PARL_IO : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PARL_IO (BIT(1)) +#define TEE_READ_REE0_PARL_IO_M (TEE_READ_REE0_PARL_IO_V << TEE_READ_REE0_PARL_IO_S) +#define TEE_READ_REE0_PARL_IO_V 0x00000001U +#define TEE_READ_REE0_PARL_IO_S 1 +/** TEE_READ_REE1_PARL_IO : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PARL_IO (BIT(2)) +#define TEE_READ_REE1_PARL_IO_M (TEE_READ_REE1_PARL_IO_V << TEE_READ_REE1_PARL_IO_S) +#define TEE_READ_REE1_PARL_IO_V 0x00000001U +#define TEE_READ_REE1_PARL_IO_S 2 +/** TEE_READ_REE2_PARL_IO : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PARL_IO (BIT(3)) +#define TEE_READ_REE2_PARL_IO_M (TEE_READ_REE2_PARL_IO_V << TEE_READ_REE2_PARL_IO_S) +#define TEE_READ_REE2_PARL_IO_V 0x00000001U +#define TEE_READ_REE2_PARL_IO_S 3 +/** TEE_WRITE_TEE_PARL_IO : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PARL_IO (BIT(4)) +#define TEE_WRITE_TEE_PARL_IO_M (TEE_WRITE_TEE_PARL_IO_V << TEE_WRITE_TEE_PARL_IO_S) +#define TEE_WRITE_TEE_PARL_IO_V 0x00000001U +#define TEE_WRITE_TEE_PARL_IO_S 4 +/** TEE_WRITE_REE0_PARL_IO : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PARL_IO (BIT(5)) +#define TEE_WRITE_REE0_PARL_IO_M (TEE_WRITE_REE0_PARL_IO_V << TEE_WRITE_REE0_PARL_IO_S) +#define TEE_WRITE_REE0_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE0_PARL_IO_S 5 +/** TEE_WRITE_REE1_PARL_IO : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PARL_IO (BIT(6)) +#define TEE_WRITE_REE1_PARL_IO_M (TEE_WRITE_REE1_PARL_IO_V << TEE_WRITE_REE1_PARL_IO_S) +#define TEE_WRITE_REE1_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE1_PARL_IO_S 6 +/** TEE_WRITE_REE2_PARL_IO : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PARL_IO (BIT(7)) +#define TEE_WRITE_REE2_PARL_IO_M (TEE_WRITE_REE2_PARL_IO_V << TEE_WRITE_REE2_PARL_IO_S) +#define TEE_WRITE_REE2_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE2_PARL_IO_S 7 + +/** TEE_PWM_CTRL_REG register + * pwm read/write control register + */ +#define TEE_PWM_CTRL_REG (DR_REG_TEE_BASE + 0xa4) +/** TEE_READ_TEE_PWM : R/W; bitpos: [0]; default: 1; + * Configures pwm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PWM (BIT(0)) +#define TEE_READ_TEE_PWM_M (TEE_READ_TEE_PWM_V << TEE_READ_TEE_PWM_S) +#define TEE_READ_TEE_PWM_V 0x00000001U +#define TEE_READ_TEE_PWM_S 0 +/** TEE_READ_REE0_PWM : R/W; bitpos: [1]; default: 0; + * Configures pwm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PWM (BIT(1)) +#define TEE_READ_REE0_PWM_M (TEE_READ_REE0_PWM_V << TEE_READ_REE0_PWM_S) +#define TEE_READ_REE0_PWM_V 0x00000001U +#define TEE_READ_REE0_PWM_S 1 +/** TEE_READ_REE1_PWM : R/W; bitpos: [2]; default: 0; + * Configures pwm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PWM (BIT(2)) +#define TEE_READ_REE1_PWM_M (TEE_READ_REE1_PWM_V << TEE_READ_REE1_PWM_S) +#define TEE_READ_REE1_PWM_V 0x00000001U +#define TEE_READ_REE1_PWM_S 2 +/** TEE_READ_REE2_PWM : R/W; bitpos: [3]; default: 0; + * Configures pwm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PWM (BIT(3)) +#define TEE_READ_REE2_PWM_M (TEE_READ_REE2_PWM_V << TEE_READ_REE2_PWM_S) +#define TEE_READ_REE2_PWM_V 0x00000001U +#define TEE_READ_REE2_PWM_S 3 +/** TEE_WRITE_TEE_PWM : R/W; bitpos: [4]; default: 1; + * Configures pwm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PWM (BIT(4)) +#define TEE_WRITE_TEE_PWM_M (TEE_WRITE_TEE_PWM_V << TEE_WRITE_TEE_PWM_S) +#define TEE_WRITE_TEE_PWM_V 0x00000001U +#define TEE_WRITE_TEE_PWM_S 4 +/** TEE_WRITE_REE0_PWM : R/W; bitpos: [5]; default: 0; + * Configures pwm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PWM (BIT(5)) +#define TEE_WRITE_REE0_PWM_M (TEE_WRITE_REE0_PWM_V << TEE_WRITE_REE0_PWM_S) +#define TEE_WRITE_REE0_PWM_V 0x00000001U +#define TEE_WRITE_REE0_PWM_S 5 +/** TEE_WRITE_REE1_PWM : R/W; bitpos: [6]; default: 0; + * Configures pwm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PWM (BIT(6)) +#define TEE_WRITE_REE1_PWM_M (TEE_WRITE_REE1_PWM_V << TEE_WRITE_REE1_PWM_S) +#define TEE_WRITE_REE1_PWM_V 0x00000001U +#define TEE_WRITE_REE1_PWM_S 6 +/** TEE_WRITE_REE2_PWM : R/W; bitpos: [7]; default: 0; + * Configures pwm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PWM (BIT(7)) +#define TEE_WRITE_REE2_PWM_M (TEE_WRITE_REE2_PWM_V << TEE_WRITE_REE2_PWM_S) +#define TEE_WRITE_REE2_PWM_V 0x00000001U +#define TEE_WRITE_REE2_PWM_S 7 + +/** TEE_LEDC_CTRL_REG register + * ledc read/write control register + */ +#define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) +/** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_LEDC (BIT(0)) +#define TEE_READ_TEE_LEDC_M (TEE_READ_TEE_LEDC_V << TEE_READ_TEE_LEDC_S) +#define TEE_READ_TEE_LEDC_V 0x00000001U +#define TEE_READ_TEE_LEDC_S 0 +/** TEE_READ_REE0_LEDC : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_LEDC (BIT(1)) +#define TEE_READ_REE0_LEDC_M (TEE_READ_REE0_LEDC_V << TEE_READ_REE0_LEDC_S) +#define TEE_READ_REE0_LEDC_V 0x00000001U +#define TEE_READ_REE0_LEDC_S 1 +/** TEE_READ_REE1_LEDC : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_LEDC (BIT(2)) +#define TEE_READ_REE1_LEDC_M (TEE_READ_REE1_LEDC_V << TEE_READ_REE1_LEDC_S) +#define TEE_READ_REE1_LEDC_V 0x00000001U +#define TEE_READ_REE1_LEDC_S 2 +/** TEE_READ_REE2_LEDC : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_LEDC (BIT(3)) +#define TEE_READ_REE2_LEDC_M (TEE_READ_REE2_LEDC_V << TEE_READ_REE2_LEDC_S) +#define TEE_READ_REE2_LEDC_V 0x00000001U +#define TEE_READ_REE2_LEDC_S 3 +/** TEE_WRITE_TEE_LEDC : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_LEDC (BIT(4)) +#define TEE_WRITE_TEE_LEDC_M (TEE_WRITE_TEE_LEDC_V << TEE_WRITE_TEE_LEDC_S) +#define TEE_WRITE_TEE_LEDC_V 0x00000001U +#define TEE_WRITE_TEE_LEDC_S 4 +/** TEE_WRITE_REE0_LEDC : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_LEDC (BIT(5)) +#define TEE_WRITE_REE0_LEDC_M (TEE_WRITE_REE0_LEDC_V << TEE_WRITE_REE0_LEDC_S) +#define TEE_WRITE_REE0_LEDC_V 0x00000001U +#define TEE_WRITE_REE0_LEDC_S 5 +/** TEE_WRITE_REE1_LEDC : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_LEDC (BIT(6)) +#define TEE_WRITE_REE1_LEDC_M (TEE_WRITE_REE1_LEDC_V << TEE_WRITE_REE1_LEDC_S) +#define TEE_WRITE_REE1_LEDC_V 0x00000001U +#define TEE_WRITE_REE1_LEDC_S 6 +/** TEE_WRITE_REE2_LEDC : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_LEDC (BIT(7)) +#define TEE_WRITE_REE2_LEDC_M (TEE_WRITE_REE2_LEDC_V << TEE_WRITE_REE2_LEDC_S) +#define TEE_WRITE_REE2_LEDC_V 0x00000001U +#define TEE_WRITE_REE2_LEDC_S 7 + +/** TEE_CAN0_CTRL_REG register + * can read/write control register + */ +#define TEE_CAN0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_CAN0 : R/W; bitpos: [0]; default: 1; + * Configures can0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CAN0 (BIT(0)) +#define TEE_READ_TEE_CAN0_M (TEE_READ_TEE_CAN0_V << TEE_READ_TEE_CAN0_S) +#define TEE_READ_TEE_CAN0_V 0x00000001U +#define TEE_READ_TEE_CAN0_S 0 +/** TEE_READ_REE0_CAN0 : R/W; bitpos: [1]; default: 0; + * Configures can0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CAN0 (BIT(1)) +#define TEE_READ_REE0_CAN0_M (TEE_READ_REE0_CAN0_V << TEE_READ_REE0_CAN0_S) +#define TEE_READ_REE0_CAN0_V 0x00000001U +#define TEE_READ_REE0_CAN0_S 1 +/** TEE_READ_REE1_CAN0 : R/W; bitpos: [2]; default: 0; + * Configures can0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CAN0 (BIT(2)) +#define TEE_READ_REE1_CAN0_M (TEE_READ_REE1_CAN0_V << TEE_READ_REE1_CAN0_S) +#define TEE_READ_REE1_CAN0_V 0x00000001U +#define TEE_READ_REE1_CAN0_S 2 +/** TEE_READ_REE2_CAN0 : R/W; bitpos: [3]; default: 0; + * Configures can0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CAN0 (BIT(3)) +#define TEE_READ_REE2_CAN0_M (TEE_READ_REE2_CAN0_V << TEE_READ_REE2_CAN0_S) +#define TEE_READ_REE2_CAN0_V 0x00000001U +#define TEE_READ_REE2_CAN0_S 3 +/** TEE_WRITE_TEE_CAN0 : R/W; bitpos: [4]; default: 1; + * Configures can0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CAN0 (BIT(4)) +#define TEE_WRITE_TEE_CAN0_M (TEE_WRITE_TEE_CAN0_V << TEE_WRITE_TEE_CAN0_S) +#define TEE_WRITE_TEE_CAN0_V 0x00000001U +#define TEE_WRITE_TEE_CAN0_S 4 +/** TEE_WRITE_REE0_CAN0 : R/W; bitpos: [5]; default: 0; + * Configures can0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CAN0 (BIT(5)) +#define TEE_WRITE_REE0_CAN0_M (TEE_WRITE_REE0_CAN0_V << TEE_WRITE_REE0_CAN0_S) +#define TEE_WRITE_REE0_CAN0_V 0x00000001U +#define TEE_WRITE_REE0_CAN0_S 5 +/** TEE_WRITE_REE1_CAN0 : R/W; bitpos: [6]; default: 0; + * Configures can0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CAN0 (BIT(6)) +#define TEE_WRITE_REE1_CAN0_M (TEE_WRITE_REE1_CAN0_V << TEE_WRITE_REE1_CAN0_S) +#define TEE_WRITE_REE1_CAN0_V 0x00000001U +#define TEE_WRITE_REE1_CAN0_S 6 +/** TEE_WRITE_REE2_CAN0 : R/W; bitpos: [7]; default: 0; + * Configures can0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CAN0 (BIT(7)) +#define TEE_WRITE_REE2_CAN0_M (TEE_WRITE_REE2_CAN0_V << TEE_WRITE_REE2_CAN0_S) +#define TEE_WRITE_REE2_CAN0_V 0x00000001U +#define TEE_WRITE_REE2_CAN0_S 7 + +/** TEE_USB_DEVICE_CTRL_REG register + * usb_device read/write control register + */ +#define TEE_USB_DEVICE_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_DEVICE : R/W; bitpos: [0]; default: 1; + * Configures usb_device registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_DEVICE (BIT(0)) +#define TEE_READ_TEE_USB_DEVICE_M (TEE_READ_TEE_USB_DEVICE_V << TEE_READ_TEE_USB_DEVICE_S) +#define TEE_READ_TEE_USB_DEVICE_V 0x00000001U +#define TEE_READ_TEE_USB_DEVICE_S 0 +/** TEE_READ_REE0_USB_DEVICE : R/W; bitpos: [1]; default: 0; + * Configures usb_device registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_DEVICE (BIT(1)) +#define TEE_READ_REE0_USB_DEVICE_M (TEE_READ_REE0_USB_DEVICE_V << TEE_READ_REE0_USB_DEVICE_S) +#define TEE_READ_REE0_USB_DEVICE_V 0x00000001U +#define TEE_READ_REE0_USB_DEVICE_S 1 +/** TEE_READ_REE1_USB_DEVICE : R/W; bitpos: [2]; default: 0; + * Configures usb_device registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_DEVICE (BIT(2)) +#define TEE_READ_REE1_USB_DEVICE_M (TEE_READ_REE1_USB_DEVICE_V << TEE_READ_REE1_USB_DEVICE_S) +#define TEE_READ_REE1_USB_DEVICE_V 0x00000001U +#define TEE_READ_REE1_USB_DEVICE_S 2 +/** TEE_READ_REE2_USB_DEVICE : R/W; bitpos: [3]; default: 0; + * Configures usb_device registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_DEVICE (BIT(3)) +#define TEE_READ_REE2_USB_DEVICE_M (TEE_READ_REE2_USB_DEVICE_V << TEE_READ_REE2_USB_DEVICE_S) +#define TEE_READ_REE2_USB_DEVICE_V 0x00000001U +#define TEE_READ_REE2_USB_DEVICE_S 3 +/** TEE_WRITE_TEE_USB_DEVICE : R/W; bitpos: [4]; default: 1; + * Configures usb_device registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_DEVICE (BIT(4)) +#define TEE_WRITE_TEE_USB_DEVICE_M (TEE_WRITE_TEE_USB_DEVICE_V << TEE_WRITE_TEE_USB_DEVICE_S) +#define TEE_WRITE_TEE_USB_DEVICE_V 0x00000001U +#define TEE_WRITE_TEE_USB_DEVICE_S 4 +/** TEE_WRITE_REE0_USB_DEVICE : R/W; bitpos: [5]; default: 0; + * Configures usb_device registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_DEVICE (BIT(5)) +#define TEE_WRITE_REE0_USB_DEVICE_M (TEE_WRITE_REE0_USB_DEVICE_V << TEE_WRITE_REE0_USB_DEVICE_S) +#define TEE_WRITE_REE0_USB_DEVICE_V 0x00000001U +#define TEE_WRITE_REE0_USB_DEVICE_S 5 +/** TEE_WRITE_REE1_USB_DEVICE : R/W; bitpos: [6]; default: 0; + * Configures usb_device registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_DEVICE (BIT(6)) +#define TEE_WRITE_REE1_USB_DEVICE_M (TEE_WRITE_REE1_USB_DEVICE_V << TEE_WRITE_REE1_USB_DEVICE_S) +#define TEE_WRITE_REE1_USB_DEVICE_V 0x00000001U +#define TEE_WRITE_REE1_USB_DEVICE_S 6 +/** TEE_WRITE_REE2_USB_DEVICE : R/W; bitpos: [7]; default: 0; + * Configures usb_device registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_DEVICE (BIT(7)) +#define TEE_WRITE_REE2_USB_DEVICE_M (TEE_WRITE_REE2_USB_DEVICE_V << TEE_WRITE_REE2_USB_DEVICE_S) +#define TEE_WRITE_REE2_USB_DEVICE_V 0x00000001U +#define TEE_WRITE_REE2_USB_DEVICE_S 7 + +/** TEE_RMT_CTRL_REG register + * rmt read/write control register + */ +#define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) +/** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_RMT (BIT(0)) +#define TEE_READ_TEE_RMT_M (TEE_READ_TEE_RMT_V << TEE_READ_TEE_RMT_S) +#define TEE_READ_TEE_RMT_V 0x00000001U +#define TEE_READ_TEE_RMT_S 0 +/** TEE_READ_REE0_RMT : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_RMT (BIT(1)) +#define TEE_READ_REE0_RMT_M (TEE_READ_REE0_RMT_V << TEE_READ_REE0_RMT_S) +#define TEE_READ_REE0_RMT_V 0x00000001U +#define TEE_READ_REE0_RMT_S 1 +/** TEE_READ_REE1_RMT : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_RMT (BIT(2)) +#define TEE_READ_REE1_RMT_M (TEE_READ_REE1_RMT_V << TEE_READ_REE1_RMT_S) +#define TEE_READ_REE1_RMT_V 0x00000001U +#define TEE_READ_REE1_RMT_S 2 +/** TEE_READ_REE2_RMT : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_RMT (BIT(3)) +#define TEE_READ_REE2_RMT_M (TEE_READ_REE2_RMT_V << TEE_READ_REE2_RMT_S) +#define TEE_READ_REE2_RMT_V 0x00000001U +#define TEE_READ_REE2_RMT_S 3 +/** TEE_WRITE_TEE_RMT : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_RMT (BIT(4)) +#define TEE_WRITE_TEE_RMT_M (TEE_WRITE_TEE_RMT_V << TEE_WRITE_TEE_RMT_S) +#define TEE_WRITE_TEE_RMT_V 0x00000001U +#define TEE_WRITE_TEE_RMT_S 4 +/** TEE_WRITE_REE0_RMT : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_RMT (BIT(5)) +#define TEE_WRITE_REE0_RMT_M (TEE_WRITE_REE0_RMT_V << TEE_WRITE_REE0_RMT_S) +#define TEE_WRITE_REE0_RMT_V 0x00000001U +#define TEE_WRITE_REE0_RMT_S 5 +/** TEE_WRITE_REE1_RMT : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_RMT (BIT(6)) +#define TEE_WRITE_REE1_RMT_M (TEE_WRITE_REE1_RMT_V << TEE_WRITE_REE1_RMT_S) +#define TEE_WRITE_REE1_RMT_V 0x00000001U +#define TEE_WRITE_REE1_RMT_S 6 +/** TEE_WRITE_REE2_RMT : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_RMT (BIT(7)) +#define TEE_WRITE_REE2_RMT_M (TEE_WRITE_REE2_RMT_V << TEE_WRITE_REE2_RMT_S) +#define TEE_WRITE_REE2_RMT_V 0x00000001U +#define TEE_WRITE_REE2_RMT_S 7 + +/** TEE_GDMA_CTRL_REG register + * gdma read/write control register + */ +#define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) +/** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GDMA (BIT(0)) +#define TEE_READ_TEE_GDMA_M (TEE_READ_TEE_GDMA_V << TEE_READ_TEE_GDMA_S) +#define TEE_READ_TEE_GDMA_V 0x00000001U +#define TEE_READ_TEE_GDMA_S 0 +/** TEE_READ_REE0_GDMA : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GDMA (BIT(1)) +#define TEE_READ_REE0_GDMA_M (TEE_READ_REE0_GDMA_V << TEE_READ_REE0_GDMA_S) +#define TEE_READ_REE0_GDMA_V 0x00000001U +#define TEE_READ_REE0_GDMA_S 1 +/** TEE_READ_REE1_GDMA : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GDMA (BIT(2)) +#define TEE_READ_REE1_GDMA_M (TEE_READ_REE1_GDMA_V << TEE_READ_REE1_GDMA_S) +#define TEE_READ_REE1_GDMA_V 0x00000001U +#define TEE_READ_REE1_GDMA_S 2 +/** TEE_READ_REE2_GDMA : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GDMA (BIT(3)) +#define TEE_READ_REE2_GDMA_M (TEE_READ_REE2_GDMA_V << TEE_READ_REE2_GDMA_S) +#define TEE_READ_REE2_GDMA_V 0x00000001U +#define TEE_READ_REE2_GDMA_S 3 +/** TEE_WRITE_TEE_GDMA : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GDMA (BIT(4)) +#define TEE_WRITE_TEE_GDMA_M (TEE_WRITE_TEE_GDMA_V << TEE_WRITE_TEE_GDMA_S) +#define TEE_WRITE_TEE_GDMA_V 0x00000001U +#define TEE_WRITE_TEE_GDMA_S 4 +/** TEE_WRITE_REE0_GDMA : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GDMA (BIT(5)) +#define TEE_WRITE_REE0_GDMA_M (TEE_WRITE_REE0_GDMA_V << TEE_WRITE_REE0_GDMA_S) +#define TEE_WRITE_REE0_GDMA_V 0x00000001U +#define TEE_WRITE_REE0_GDMA_S 5 +/** TEE_WRITE_REE1_GDMA : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GDMA (BIT(6)) +#define TEE_WRITE_REE1_GDMA_M (TEE_WRITE_REE1_GDMA_V << TEE_WRITE_REE1_GDMA_S) +#define TEE_WRITE_REE1_GDMA_V 0x00000001U +#define TEE_WRITE_REE1_GDMA_S 6 +/** TEE_WRITE_REE2_GDMA : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GDMA (BIT(7)) +#define TEE_WRITE_REE2_GDMA_M (TEE_WRITE_REE2_GDMA_V << TEE_WRITE_REE2_GDMA_S) +#define TEE_WRITE_REE2_GDMA_V 0x00000001U +#define TEE_WRITE_REE2_GDMA_S 7 + +/** TEE_REGDMA_CTRL_REG register + * regdma read/write control register + */ +#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) +/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_REGDMA (BIT(0)) +#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) +#define TEE_READ_TEE_REGDMA_V 0x00000001U +#define TEE_READ_TEE_REGDMA_S 0 +/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_REGDMA (BIT(1)) +#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) +#define TEE_READ_REE0_REGDMA_V 0x00000001U +#define TEE_READ_REE0_REGDMA_S 1 +/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_REGDMA (BIT(2)) +#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) +#define TEE_READ_REE1_REGDMA_V 0x00000001U +#define TEE_READ_REE1_REGDMA_S 2 +/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_REGDMA (BIT(3)) +#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) +#define TEE_READ_REE2_REGDMA_V 0x00000001U +#define TEE_READ_REE2_REGDMA_S 3 +/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_REGDMA (BIT(4)) +#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) +#define TEE_WRITE_TEE_REGDMA_V 0x00000001U +#define TEE_WRITE_TEE_REGDMA_S 4 +/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_REGDMA (BIT(5)) +#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) +#define TEE_WRITE_REE0_REGDMA_V 0x00000001U +#define TEE_WRITE_REE0_REGDMA_S 5 +/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_REGDMA (BIT(6)) +#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) +#define TEE_WRITE_REE1_REGDMA_V 0x00000001U +#define TEE_WRITE_REE1_REGDMA_S 6 +/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_REGDMA (BIT(7)) +#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) +#define TEE_WRITE_REE2_REGDMA_V 0x00000001U +#define TEE_WRITE_REE2_REGDMA_S 7 + +/** TEE_ETM_CTRL_REG register + * etm read/write control register + */ +#define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) +/** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_ETM (BIT(0)) +#define TEE_READ_TEE_ETM_M (TEE_READ_TEE_ETM_V << TEE_READ_TEE_ETM_S) +#define TEE_READ_TEE_ETM_V 0x00000001U +#define TEE_READ_TEE_ETM_S 0 +/** TEE_READ_REE0_ETM : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_ETM (BIT(1)) +#define TEE_READ_REE0_ETM_M (TEE_READ_REE0_ETM_V << TEE_READ_REE0_ETM_S) +#define TEE_READ_REE0_ETM_V 0x00000001U +#define TEE_READ_REE0_ETM_S 1 +/** TEE_READ_REE1_ETM : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_ETM (BIT(2)) +#define TEE_READ_REE1_ETM_M (TEE_READ_REE1_ETM_V << TEE_READ_REE1_ETM_S) +#define TEE_READ_REE1_ETM_V 0x00000001U +#define TEE_READ_REE1_ETM_S 2 +/** TEE_READ_REE2_ETM : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_ETM (BIT(3)) +#define TEE_READ_REE2_ETM_M (TEE_READ_REE2_ETM_V << TEE_READ_REE2_ETM_S) +#define TEE_READ_REE2_ETM_V 0x00000001U +#define TEE_READ_REE2_ETM_S 3 +/** TEE_WRITE_TEE_ETM : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_ETM (BIT(4)) +#define TEE_WRITE_TEE_ETM_M (TEE_WRITE_TEE_ETM_V << TEE_WRITE_TEE_ETM_S) +#define TEE_WRITE_TEE_ETM_V 0x00000001U +#define TEE_WRITE_TEE_ETM_S 4 +/** TEE_WRITE_REE0_ETM : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_ETM (BIT(5)) +#define TEE_WRITE_REE0_ETM_M (TEE_WRITE_REE0_ETM_V << TEE_WRITE_REE0_ETM_S) +#define TEE_WRITE_REE0_ETM_V 0x00000001U +#define TEE_WRITE_REE0_ETM_S 5 +/** TEE_WRITE_REE1_ETM : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_ETM (BIT(6)) +#define TEE_WRITE_REE1_ETM_M (TEE_WRITE_REE1_ETM_V << TEE_WRITE_REE1_ETM_S) +#define TEE_WRITE_REE1_ETM_V 0x00000001U +#define TEE_WRITE_REE1_ETM_S 6 +/** TEE_WRITE_REE2_ETM : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_ETM (BIT(7)) +#define TEE_WRITE_REE2_ETM_M (TEE_WRITE_REE2_ETM_V << TEE_WRITE_REE2_ETM_S) +#define TEE_WRITE_REE2_ETM_V 0x00000001U +#define TEE_WRITE_REE2_ETM_S 7 + +/** TEE_INTMTX_CTRL_REG register + * intmtx read/write control register + */ +#define TEE_INTMTX_CTRL_REG (DR_REG_TEE_BASE + 0xc8) +/** TEE_READ_TEE_INTMTX_CORE : R/W; bitpos: [0]; default: 1; + * Configures intmtx registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTMTX_CORE (BIT(0)) +#define TEE_READ_TEE_INTMTX_CORE_M (TEE_READ_TEE_INTMTX_CORE_V << TEE_READ_TEE_INTMTX_CORE_S) +#define TEE_READ_TEE_INTMTX_CORE_V 0x00000001U +#define TEE_READ_TEE_INTMTX_CORE_S 0 +/** TEE_READ_REE0_INTMTX_CORE : R/W; bitpos: [1]; default: 0; + * Configures intmtx registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTMTX_CORE (BIT(1)) +#define TEE_READ_REE0_INTMTX_CORE_M (TEE_READ_REE0_INTMTX_CORE_V << TEE_READ_REE0_INTMTX_CORE_S) +#define TEE_READ_REE0_INTMTX_CORE_V 0x00000001U +#define TEE_READ_REE0_INTMTX_CORE_S 1 +/** TEE_READ_REE1_INTMTX_CORE : R/W; bitpos: [2]; default: 0; + * Configures intmtx registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTMTX_CORE (BIT(2)) +#define TEE_READ_REE1_INTMTX_CORE_M (TEE_READ_REE1_INTMTX_CORE_V << TEE_READ_REE1_INTMTX_CORE_S) +#define TEE_READ_REE1_INTMTX_CORE_V 0x00000001U +#define TEE_READ_REE1_INTMTX_CORE_S 2 +/** TEE_READ_REE2_INTMTX_CORE : R/W; bitpos: [3]; default: 0; + * Configures intmtx registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTMTX_CORE (BIT(3)) +#define TEE_READ_REE2_INTMTX_CORE_M (TEE_READ_REE2_INTMTX_CORE_V << TEE_READ_REE2_INTMTX_CORE_S) +#define TEE_READ_REE2_INTMTX_CORE_V 0x00000001U +#define TEE_READ_REE2_INTMTX_CORE_S 3 +/** TEE_WRITE_TEE_INTMTX_CORE : R/W; bitpos: [4]; default: 1; + * Configures intmtx registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTMTX_CORE (BIT(4)) +#define TEE_WRITE_TEE_INTMTX_CORE_M (TEE_WRITE_TEE_INTMTX_CORE_V << TEE_WRITE_TEE_INTMTX_CORE_S) +#define TEE_WRITE_TEE_INTMTX_CORE_V 0x00000001U +#define TEE_WRITE_TEE_INTMTX_CORE_S 4 +/** TEE_WRITE_REE0_INTMTX_CORE : R/W; bitpos: [5]; default: 0; + * Configures intmtx registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTMTX_CORE (BIT(5)) +#define TEE_WRITE_REE0_INTMTX_CORE_M (TEE_WRITE_REE0_INTMTX_CORE_V << TEE_WRITE_REE0_INTMTX_CORE_S) +#define TEE_WRITE_REE0_INTMTX_CORE_V 0x00000001U +#define TEE_WRITE_REE0_INTMTX_CORE_S 5 +/** TEE_WRITE_REE1_INTMTX_CORE : R/W; bitpos: [6]; default: 0; + * Configures intmtx registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTMTX_CORE (BIT(6)) +#define TEE_WRITE_REE1_INTMTX_CORE_M (TEE_WRITE_REE1_INTMTX_CORE_V << TEE_WRITE_REE1_INTMTX_CORE_S) +#define TEE_WRITE_REE1_INTMTX_CORE_V 0x00000001U +#define TEE_WRITE_REE1_INTMTX_CORE_S 6 +/** TEE_WRITE_REE2_INTMTX_CORE : R/W; bitpos: [7]; default: 0; + * Configures intmtx registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTMTX_CORE (BIT(7)) +#define TEE_WRITE_REE2_INTMTX_CORE_M (TEE_WRITE_REE2_INTMTX_CORE_V << TEE_WRITE_REE2_INTMTX_CORE_S) +#define TEE_WRITE_REE2_INTMTX_CORE_V 0x00000001U +#define TEE_WRITE_REE2_INTMTX_CORE_S 7 + +/** TEE_APB_ADC_CTRL_REG register + * apb_adc read/write control register + */ +#define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) +/** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_APB_ADC (BIT(0)) +#define TEE_READ_TEE_APB_ADC_M (TEE_READ_TEE_APB_ADC_V << TEE_READ_TEE_APB_ADC_S) +#define TEE_READ_TEE_APB_ADC_V 0x00000001U +#define TEE_READ_TEE_APB_ADC_S 0 +/** TEE_READ_REE0_APB_ADC : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_APB_ADC (BIT(1)) +#define TEE_READ_REE0_APB_ADC_M (TEE_READ_REE0_APB_ADC_V << TEE_READ_REE0_APB_ADC_S) +#define TEE_READ_REE0_APB_ADC_V 0x00000001U +#define TEE_READ_REE0_APB_ADC_S 1 +/** TEE_READ_REE1_APB_ADC : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_APB_ADC (BIT(2)) +#define TEE_READ_REE1_APB_ADC_M (TEE_READ_REE1_APB_ADC_V << TEE_READ_REE1_APB_ADC_S) +#define TEE_READ_REE1_APB_ADC_V 0x00000001U +#define TEE_READ_REE1_APB_ADC_S 2 +/** TEE_READ_REE2_APB_ADC : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_APB_ADC (BIT(3)) +#define TEE_READ_REE2_APB_ADC_M (TEE_READ_REE2_APB_ADC_V << TEE_READ_REE2_APB_ADC_S) +#define TEE_READ_REE2_APB_ADC_V 0x00000001U +#define TEE_READ_REE2_APB_ADC_S 3 +/** TEE_WRITE_TEE_APB_ADC : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_APB_ADC (BIT(4)) +#define TEE_WRITE_TEE_APB_ADC_M (TEE_WRITE_TEE_APB_ADC_V << TEE_WRITE_TEE_APB_ADC_S) +#define TEE_WRITE_TEE_APB_ADC_V 0x00000001U +#define TEE_WRITE_TEE_APB_ADC_S 4 +/** TEE_WRITE_REE0_APB_ADC : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_APB_ADC (BIT(5)) +#define TEE_WRITE_REE0_APB_ADC_M (TEE_WRITE_REE0_APB_ADC_V << TEE_WRITE_REE0_APB_ADC_S) +#define TEE_WRITE_REE0_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE0_APB_ADC_S 5 +/** TEE_WRITE_REE1_APB_ADC : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_APB_ADC (BIT(6)) +#define TEE_WRITE_REE1_APB_ADC_M (TEE_WRITE_REE1_APB_ADC_V << TEE_WRITE_REE1_APB_ADC_S) +#define TEE_WRITE_REE1_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE1_APB_ADC_S 6 +/** TEE_WRITE_REE2_APB_ADC : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_APB_ADC (BIT(7)) +#define TEE_WRITE_REE2_APB_ADC_M (TEE_WRITE_REE2_APB_ADC_V << TEE_WRITE_REE2_APB_ADC_S) +#define TEE_WRITE_REE2_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE2_APB_ADC_S 7 + +/** TEE_TIMERGROUP0_CTRL_REG register + * timergroup0 read/write control register + */ +#define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) +/** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP0 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP0_M (TEE_READ_TEE_TIMERGROUP0_V << TEE_READ_TEE_TIMERGROUP0_S) +#define TEE_READ_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP0_S 0 +/** TEE_READ_REE0_TIMERGROUP0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP0 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP0_M (TEE_READ_REE0_TIMERGROUP0_V << TEE_READ_REE0_TIMERGROUP0_S) +#define TEE_READ_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP0_S 1 +/** TEE_READ_REE1_TIMERGROUP0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP0 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP0_M (TEE_READ_REE1_TIMERGROUP0_V << TEE_READ_REE1_TIMERGROUP0_S) +#define TEE_READ_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP0_S 2 +/** TEE_READ_REE2_TIMERGROUP0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP0 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP0_M (TEE_READ_REE2_TIMERGROUP0_V << TEE_READ_REE2_TIMERGROUP0_S) +#define TEE_READ_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP0_S 3 +/** TEE_WRITE_TEE_TIMERGROUP0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP0 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP0_M (TEE_WRITE_TEE_TIMERGROUP0_V << TEE_WRITE_TEE_TIMERGROUP0_S) +#define TEE_WRITE_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP0_S 4 +/** TEE_WRITE_REE0_TIMERGROUP0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP0 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP0_M (TEE_WRITE_REE0_TIMERGROUP0_V << TEE_WRITE_REE0_TIMERGROUP0_S) +#define TEE_WRITE_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP0_S 5 +/** TEE_WRITE_REE1_TIMERGROUP0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP0 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP0_M (TEE_WRITE_REE1_TIMERGROUP0_V << TEE_WRITE_REE1_TIMERGROUP0_S) +#define TEE_WRITE_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP0_S 6 +/** TEE_WRITE_REE2_TIMERGROUP0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP0 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP0_M (TEE_WRITE_REE2_TIMERGROUP0_V << TEE_WRITE_REE2_TIMERGROUP0_S) +#define TEE_WRITE_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP0_S 7 + +/** TEE_TIMERGROUP1_CTRL_REG register + * timergroup1 read/write control register + */ +#define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) +/** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP1 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP1_M (TEE_READ_TEE_TIMERGROUP1_V << TEE_READ_TEE_TIMERGROUP1_S) +#define TEE_READ_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP1_S 0 +/** TEE_READ_REE0_TIMERGROUP1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP1 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP1_M (TEE_READ_REE0_TIMERGROUP1_V << TEE_READ_REE0_TIMERGROUP1_S) +#define TEE_READ_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP1_S 1 +/** TEE_READ_REE1_TIMERGROUP1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP1 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP1_M (TEE_READ_REE1_TIMERGROUP1_V << TEE_READ_REE1_TIMERGROUP1_S) +#define TEE_READ_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP1_S 2 +/** TEE_READ_REE2_TIMERGROUP1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP1 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP1_M (TEE_READ_REE2_TIMERGROUP1_V << TEE_READ_REE2_TIMERGROUP1_S) +#define TEE_READ_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP1_S 3 +/** TEE_WRITE_TEE_TIMERGROUP1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP1 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP1_M (TEE_WRITE_TEE_TIMERGROUP1_V << TEE_WRITE_TEE_TIMERGROUP1_S) +#define TEE_WRITE_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP1_S 4 +/** TEE_WRITE_REE0_TIMERGROUP1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP1 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP1_M (TEE_WRITE_REE0_TIMERGROUP1_V << TEE_WRITE_REE0_TIMERGROUP1_S) +#define TEE_WRITE_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP1_S 5 +/** TEE_WRITE_REE1_TIMERGROUP1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP1 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP1_M (TEE_WRITE_REE1_TIMERGROUP1_V << TEE_WRITE_REE1_TIMERGROUP1_S) +#define TEE_WRITE_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP1_S 6 +/** TEE_WRITE_REE2_TIMERGROUP1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP1 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP1_M (TEE_WRITE_REE2_TIMERGROUP1_V << TEE_WRITE_REE2_TIMERGROUP1_S) +#define TEE_WRITE_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP1_S 7 + +/** TEE_SYSTIMER_CTRL_REG register + * systimer read/write control register + */ +#define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) +/** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SYSTIMER (BIT(0)) +#define TEE_READ_TEE_SYSTIMER_M (TEE_READ_TEE_SYSTIMER_V << TEE_READ_TEE_SYSTIMER_S) +#define TEE_READ_TEE_SYSTIMER_V 0x00000001U +#define TEE_READ_TEE_SYSTIMER_S 0 +/** TEE_READ_REE0_SYSTIMER : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SYSTIMER (BIT(1)) +#define TEE_READ_REE0_SYSTIMER_M (TEE_READ_REE0_SYSTIMER_V << TEE_READ_REE0_SYSTIMER_S) +#define TEE_READ_REE0_SYSTIMER_V 0x00000001U +#define TEE_READ_REE0_SYSTIMER_S 1 +/** TEE_READ_REE1_SYSTIMER : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SYSTIMER (BIT(2)) +#define TEE_READ_REE1_SYSTIMER_M (TEE_READ_REE1_SYSTIMER_V << TEE_READ_REE1_SYSTIMER_S) +#define TEE_READ_REE1_SYSTIMER_V 0x00000001U +#define TEE_READ_REE1_SYSTIMER_S 2 +/** TEE_READ_REE2_SYSTIMER : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SYSTIMER (BIT(3)) +#define TEE_READ_REE2_SYSTIMER_M (TEE_READ_REE2_SYSTIMER_V << TEE_READ_REE2_SYSTIMER_S) +#define TEE_READ_REE2_SYSTIMER_V 0x00000001U +#define TEE_READ_REE2_SYSTIMER_S 3 +/** TEE_WRITE_TEE_SYSTIMER : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SYSTIMER (BIT(4)) +#define TEE_WRITE_TEE_SYSTIMER_M (TEE_WRITE_TEE_SYSTIMER_V << TEE_WRITE_TEE_SYSTIMER_S) +#define TEE_WRITE_TEE_SYSTIMER_V 0x00000001U +#define TEE_WRITE_TEE_SYSTIMER_S 4 +/** TEE_WRITE_REE0_SYSTIMER : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SYSTIMER (BIT(5)) +#define TEE_WRITE_REE0_SYSTIMER_M (TEE_WRITE_REE0_SYSTIMER_V << TEE_WRITE_REE0_SYSTIMER_S) +#define TEE_WRITE_REE0_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE0_SYSTIMER_S 5 +/** TEE_WRITE_REE1_SYSTIMER : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SYSTIMER (BIT(6)) +#define TEE_WRITE_REE1_SYSTIMER_M (TEE_WRITE_REE1_SYSTIMER_V << TEE_WRITE_REE1_SYSTIMER_S) +#define TEE_WRITE_REE1_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE1_SYSTIMER_S 6 +/** TEE_WRITE_REE2_SYSTIMER : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SYSTIMER (BIT(7)) +#define TEE_WRITE_REE2_SYSTIMER_M (TEE_WRITE_REE2_SYSTIMER_V << TEE_WRITE_REE2_SYSTIMER_S) +#define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE2_SYSTIMER_S 7 + +/** TEE_MISC_CTRL_REG register + * misc read/write control register + */ +#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) +/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MISC (BIT(0)) +#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) +#define TEE_READ_TEE_MISC_V 0x00000001U +#define TEE_READ_TEE_MISC_S 0 +/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MISC (BIT(1)) +#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) +#define TEE_READ_REE0_MISC_V 0x00000001U +#define TEE_READ_REE0_MISC_S 1 +/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MISC (BIT(2)) +#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) +#define TEE_READ_REE1_MISC_V 0x00000001U +#define TEE_READ_REE1_MISC_S 2 +/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MISC (BIT(3)) +#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) +#define TEE_READ_REE2_MISC_V 0x00000001U +#define TEE_READ_REE2_MISC_S 3 +/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MISC (BIT(4)) +#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) +#define TEE_WRITE_TEE_MISC_V 0x00000001U +#define TEE_WRITE_TEE_MISC_S 4 +/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MISC (BIT(5)) +#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) +#define TEE_WRITE_REE0_MISC_V 0x00000001U +#define TEE_WRITE_REE0_MISC_S 5 +/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MISC (BIT(6)) +#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) +#define TEE_WRITE_REE1_MISC_V 0x00000001U +#define TEE_WRITE_REE1_MISC_S 6 +/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MISC (BIT(7)) +#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) +#define TEE_WRITE_REE2_MISC_V 0x00000001U +#define TEE_WRITE_REE2_MISC_S 7 + +/** TEE_PVT_MONITOR_CTRL_REG register + * pvt_monitor read/write control register + */ +#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) +/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) +#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) +#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PVT_MONITOR_S 0 +/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) +#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) +#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PVT_MONITOR_S 1 +/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) +#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) +#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PVT_MONITOR_S 2 +/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) +#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) +#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PVT_MONITOR_S 3 +/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) +#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PVT_MONITOR_S 4 +/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) +#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PVT_MONITOR_S 5 +/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) +#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PVT_MONITOR_S 6 +/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) +#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PVT_MONITOR_S 7 + +/** TEE_PCNT_CTRL_REG register + * pcnt read/write control register + */ +#define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) +/** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCNT (BIT(0)) +#define TEE_READ_TEE_PCNT_M (TEE_READ_TEE_PCNT_V << TEE_READ_TEE_PCNT_S) +#define TEE_READ_TEE_PCNT_V 0x00000001U +#define TEE_READ_TEE_PCNT_S 0 +/** TEE_READ_REE0_PCNT : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCNT (BIT(1)) +#define TEE_READ_REE0_PCNT_M (TEE_READ_REE0_PCNT_V << TEE_READ_REE0_PCNT_S) +#define TEE_READ_REE0_PCNT_V 0x00000001U +#define TEE_READ_REE0_PCNT_S 1 +/** TEE_READ_REE1_PCNT : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCNT (BIT(2)) +#define TEE_READ_REE1_PCNT_M (TEE_READ_REE1_PCNT_V << TEE_READ_REE1_PCNT_S) +#define TEE_READ_REE1_PCNT_V 0x00000001U +#define TEE_READ_REE1_PCNT_S 2 +/** TEE_READ_REE2_PCNT : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCNT (BIT(3)) +#define TEE_READ_REE2_PCNT_M (TEE_READ_REE2_PCNT_V << TEE_READ_REE2_PCNT_S) +#define TEE_READ_REE2_PCNT_V 0x00000001U +#define TEE_READ_REE2_PCNT_S 3 +/** TEE_WRITE_TEE_PCNT : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCNT (BIT(4)) +#define TEE_WRITE_TEE_PCNT_M (TEE_WRITE_TEE_PCNT_V << TEE_WRITE_TEE_PCNT_S) +#define TEE_WRITE_TEE_PCNT_V 0x00000001U +#define TEE_WRITE_TEE_PCNT_S 4 +/** TEE_WRITE_REE0_PCNT : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCNT (BIT(5)) +#define TEE_WRITE_REE0_PCNT_M (TEE_WRITE_REE0_PCNT_V << TEE_WRITE_REE0_PCNT_S) +#define TEE_WRITE_REE0_PCNT_V 0x00000001U +#define TEE_WRITE_REE0_PCNT_S 5 +/** TEE_WRITE_REE1_PCNT : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCNT (BIT(6)) +#define TEE_WRITE_REE1_PCNT_M (TEE_WRITE_REE1_PCNT_V << TEE_WRITE_REE1_PCNT_S) +#define TEE_WRITE_REE1_PCNT_V 0x00000001U +#define TEE_WRITE_REE1_PCNT_S 6 +/** TEE_WRITE_REE2_PCNT : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCNT (BIT(7)) +#define TEE_WRITE_REE2_PCNT_M (TEE_WRITE_REE2_PCNT_V << TEE_WRITE_REE2_PCNT_S) +#define TEE_WRITE_REE2_PCNT_V 0x00000001U +#define TEE_WRITE_REE2_PCNT_S 7 + +/** TEE_IOMUX_CTRL_REG register + * iomux read/write control register + */ +#define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) +/** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_IOMUX (BIT(0)) +#define TEE_READ_TEE_IOMUX_M (TEE_READ_TEE_IOMUX_V << TEE_READ_TEE_IOMUX_S) +#define TEE_READ_TEE_IOMUX_V 0x00000001U +#define TEE_READ_TEE_IOMUX_S 0 +/** TEE_READ_REE0_IOMUX : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_IOMUX (BIT(1)) +#define TEE_READ_REE0_IOMUX_M (TEE_READ_REE0_IOMUX_V << TEE_READ_REE0_IOMUX_S) +#define TEE_READ_REE0_IOMUX_V 0x00000001U +#define TEE_READ_REE0_IOMUX_S 1 +/** TEE_READ_REE1_IOMUX : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_IOMUX (BIT(2)) +#define TEE_READ_REE1_IOMUX_M (TEE_READ_REE1_IOMUX_V << TEE_READ_REE1_IOMUX_S) +#define TEE_READ_REE1_IOMUX_V 0x00000001U +#define TEE_READ_REE1_IOMUX_S 2 +/** TEE_READ_REE2_IOMUX : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_IOMUX (BIT(3)) +#define TEE_READ_REE2_IOMUX_M (TEE_READ_REE2_IOMUX_V << TEE_READ_REE2_IOMUX_S) +#define TEE_READ_REE2_IOMUX_V 0x00000001U +#define TEE_READ_REE2_IOMUX_S 3 +/** TEE_WRITE_TEE_IOMUX : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_IOMUX (BIT(4)) +#define TEE_WRITE_TEE_IOMUX_M (TEE_WRITE_TEE_IOMUX_V << TEE_WRITE_TEE_IOMUX_S) +#define TEE_WRITE_TEE_IOMUX_V 0x00000001U +#define TEE_WRITE_TEE_IOMUX_S 4 +/** TEE_WRITE_REE0_IOMUX : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_IOMUX (BIT(5)) +#define TEE_WRITE_REE0_IOMUX_M (TEE_WRITE_REE0_IOMUX_V << TEE_WRITE_REE0_IOMUX_S) +#define TEE_WRITE_REE0_IOMUX_V 0x00000001U +#define TEE_WRITE_REE0_IOMUX_S 5 +/** TEE_WRITE_REE1_IOMUX : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_IOMUX (BIT(6)) +#define TEE_WRITE_REE1_IOMUX_M (TEE_WRITE_REE1_IOMUX_V << TEE_WRITE_REE1_IOMUX_S) +#define TEE_WRITE_REE1_IOMUX_V 0x00000001U +#define TEE_WRITE_REE1_IOMUX_S 6 +/** TEE_WRITE_REE2_IOMUX : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_IOMUX (BIT(7)) +#define TEE_WRITE_REE2_IOMUX_M (TEE_WRITE_REE2_IOMUX_V << TEE_WRITE_REE2_IOMUX_S) +#define TEE_WRITE_REE2_IOMUX_V 0x00000001U +#define TEE_WRITE_REE2_IOMUX_S 7 + +/** TEE_PSRAM_MEM_MONITOR_CTRL_REG register + * psram_mem_monitor read/write control register + */ +#define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) +/** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PSRAM_MEM_MONITOR (BIT(0)) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_M (TEE_READ_TEE_PSRAM_MEM_MONITOR_V << TEE_READ_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_S 0 +/** TEE_READ_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PSRAM_MEM_MONITOR (BIT(1)) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_M (TEE_READ_REE0_PSRAM_MEM_MONITOR_V << TEE_READ_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_S 1 +/** TEE_READ_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PSRAM_MEM_MONITOR (BIT(2)) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_M (TEE_READ_REE1_PSRAM_MEM_MONITOR_V << TEE_READ_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_S 2 +/** TEE_READ_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PSRAM_MEM_MONITOR (BIT(3)) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_M (TEE_READ_REE2_PSRAM_MEM_MONITOR_V << TEE_READ_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_S 3 +/** TEE_WRITE_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_M (TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V << TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S 4 +/** TEE_WRITE_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S 5 +/** TEE_WRITE_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S 6 +/** TEE_WRITE_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 + +/** TEE_MEM_ACS_MONITOR_CTRL_REG register + * mem_acs_monitor read/write control register + */ +#define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) +/** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MEM_ACS_MONITOR (BIT(0)) +#define TEE_READ_TEE_MEM_ACS_MONITOR_M (TEE_READ_TEE_MEM_ACS_MONITOR_V << TEE_READ_TEE_MEM_ACS_MONITOR_S) +#define TEE_READ_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_MEM_ACS_MONITOR_S 0 +/** TEE_READ_REE0_MEM_ACS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MEM_ACS_MONITOR (BIT(1)) +#define TEE_READ_REE0_MEM_ACS_MONITOR_M (TEE_READ_REE0_MEM_ACS_MONITOR_V << TEE_READ_REE0_MEM_ACS_MONITOR_S) +#define TEE_READ_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_MEM_ACS_MONITOR_S 1 +/** TEE_READ_REE1_MEM_ACS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MEM_ACS_MONITOR (BIT(2)) +#define TEE_READ_REE1_MEM_ACS_MONITOR_M (TEE_READ_REE1_MEM_ACS_MONITOR_V << TEE_READ_REE1_MEM_ACS_MONITOR_S) +#define TEE_READ_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_MEM_ACS_MONITOR_S 2 +/** TEE_READ_REE2_MEM_ACS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MEM_ACS_MONITOR (BIT(3)) +#define TEE_READ_REE2_MEM_ACS_MONITOR_M (TEE_READ_REE2_MEM_ACS_MONITOR_V << TEE_READ_REE2_MEM_ACS_MONITOR_S) +#define TEE_READ_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_MEM_ACS_MONITOR_S 3 +/** TEE_WRITE_TEE_MEM_ACS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MEM_ACS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_M (TEE_WRITE_TEE_MEM_ACS_MONITOR_V << TEE_WRITE_TEE_MEM_ACS_MONITOR_S) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_S 4 +/** TEE_WRITE_REE0_MEM_ACS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MEM_ACS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_M (TEE_WRITE_REE0_MEM_ACS_MONITOR_V << TEE_WRITE_REE0_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_S 5 +/** TEE_WRITE_REE1_MEM_ACS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MEM_ACS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_M (TEE_WRITE_REE1_MEM_ACS_MONITOR_V << TEE_WRITE_REE1_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_S 6 +/** TEE_WRITE_REE2_MEM_ACS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MEM_ACS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_M (TEE_WRITE_REE2_MEM_ACS_MONITOR_V << TEE_WRITE_REE2_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 + +/** TEE_HP_SYSTEM_REG_CTRL_REG register + * hp_system_reg read/write control register + */ +#define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) +/** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_SYSTEM_REG (BIT(0)) +#define TEE_READ_TEE_HP_SYSTEM_REG_M (TEE_READ_TEE_HP_SYSTEM_REG_V << TEE_READ_TEE_HP_SYSTEM_REG_S) +#define TEE_READ_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_TEE_HP_SYSTEM_REG_S 0 +/** TEE_READ_REE0_HP_SYSTEM_REG : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_SYSTEM_REG (BIT(1)) +#define TEE_READ_REE0_HP_SYSTEM_REG_M (TEE_READ_REE0_HP_SYSTEM_REG_V << TEE_READ_REE0_HP_SYSTEM_REG_S) +#define TEE_READ_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE0_HP_SYSTEM_REG_S 1 +/** TEE_READ_REE1_HP_SYSTEM_REG : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_SYSTEM_REG (BIT(2)) +#define TEE_READ_REE1_HP_SYSTEM_REG_M (TEE_READ_REE1_HP_SYSTEM_REG_V << TEE_READ_REE1_HP_SYSTEM_REG_S) +#define TEE_READ_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE1_HP_SYSTEM_REG_S 2 +/** TEE_READ_REE2_HP_SYSTEM_REG : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_SYSTEM_REG (BIT(3)) +#define TEE_READ_REE2_HP_SYSTEM_REG_M (TEE_READ_REE2_HP_SYSTEM_REG_V << TEE_READ_REE2_HP_SYSTEM_REG_S) +#define TEE_READ_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE2_HP_SYSTEM_REG_S 3 +/** TEE_WRITE_TEE_HP_SYSTEM_REG : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_SYSTEM_REG (BIT(4)) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_M (TEE_WRITE_TEE_HP_SYSTEM_REG_V << TEE_WRITE_TEE_HP_SYSTEM_REG_S) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_TEE_HP_SYSTEM_REG_S 4 +/** TEE_WRITE_REE0_HP_SYSTEM_REG : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_SYSTEM_REG (BIT(5)) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_M (TEE_WRITE_REE0_HP_SYSTEM_REG_V << TEE_WRITE_REE0_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE0_HP_SYSTEM_REG_S 5 +/** TEE_WRITE_REE1_HP_SYSTEM_REG : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_SYSTEM_REG (BIT(6)) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_M (TEE_WRITE_REE1_HP_SYSTEM_REG_V << TEE_WRITE_REE1_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE1_HP_SYSTEM_REG_S 6 +/** TEE_WRITE_REE2_HP_SYSTEM_REG : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_SYSTEM_REG (BIT(7)) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_M (TEE_WRITE_REE2_HP_SYSTEM_REG_V << TEE_WRITE_REE2_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 + +/** TEE_PCR_REG_CTRL_REG register + * pcr_reg read/write control register + */ +#define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) +/** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCR_REG (BIT(0)) +#define TEE_READ_TEE_PCR_REG_M (TEE_READ_TEE_PCR_REG_V << TEE_READ_TEE_PCR_REG_S) +#define TEE_READ_TEE_PCR_REG_V 0x00000001U +#define TEE_READ_TEE_PCR_REG_S 0 +/** TEE_READ_REE0_PCR_REG : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCR_REG (BIT(1)) +#define TEE_READ_REE0_PCR_REG_M (TEE_READ_REE0_PCR_REG_V << TEE_READ_REE0_PCR_REG_S) +#define TEE_READ_REE0_PCR_REG_V 0x00000001U +#define TEE_READ_REE0_PCR_REG_S 1 +/** TEE_READ_REE1_PCR_REG : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCR_REG (BIT(2)) +#define TEE_READ_REE1_PCR_REG_M (TEE_READ_REE1_PCR_REG_V << TEE_READ_REE1_PCR_REG_S) +#define TEE_READ_REE1_PCR_REG_V 0x00000001U +#define TEE_READ_REE1_PCR_REG_S 2 +/** TEE_READ_REE2_PCR_REG : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCR_REG (BIT(3)) +#define TEE_READ_REE2_PCR_REG_M (TEE_READ_REE2_PCR_REG_V << TEE_READ_REE2_PCR_REG_S) +#define TEE_READ_REE2_PCR_REG_V 0x00000001U +#define TEE_READ_REE2_PCR_REG_S 3 +/** TEE_WRITE_TEE_PCR_REG : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCR_REG (BIT(4)) +#define TEE_WRITE_TEE_PCR_REG_M (TEE_WRITE_TEE_PCR_REG_V << TEE_WRITE_TEE_PCR_REG_S) +#define TEE_WRITE_TEE_PCR_REG_V 0x00000001U +#define TEE_WRITE_TEE_PCR_REG_S 4 +/** TEE_WRITE_REE0_PCR_REG : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCR_REG (BIT(5)) +#define TEE_WRITE_REE0_PCR_REG_M (TEE_WRITE_REE0_PCR_REG_V << TEE_WRITE_REE0_PCR_REG_S) +#define TEE_WRITE_REE0_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE0_PCR_REG_S 5 +/** TEE_WRITE_REE1_PCR_REG : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCR_REG (BIT(6)) +#define TEE_WRITE_REE1_PCR_REG_M (TEE_WRITE_REE1_PCR_REG_V << TEE_WRITE_REE1_PCR_REG_S) +#define TEE_WRITE_REE1_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE1_PCR_REG_S 6 +/** TEE_WRITE_REE2_PCR_REG : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCR_REG (BIT(7)) +#define TEE_WRITE_REE2_PCR_REG_M (TEE_WRITE_REE2_PCR_REG_V << TEE_WRITE_REE2_PCR_REG_S) +#define TEE_WRITE_REE2_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE2_PCR_REG_S 7 + +/** TEE_MSPI_CTRL_REG register + * mspi read/write control register + */ +#define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) +/** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MSPI (BIT(0)) +#define TEE_READ_TEE_MSPI_M (TEE_READ_TEE_MSPI_V << TEE_READ_TEE_MSPI_S) +#define TEE_READ_TEE_MSPI_V 0x00000001U +#define TEE_READ_TEE_MSPI_S 0 +/** TEE_READ_REE0_MSPI : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MSPI (BIT(1)) +#define TEE_READ_REE0_MSPI_M (TEE_READ_REE0_MSPI_V << TEE_READ_REE0_MSPI_S) +#define TEE_READ_REE0_MSPI_V 0x00000001U +#define TEE_READ_REE0_MSPI_S 1 +/** TEE_READ_REE1_MSPI : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MSPI (BIT(2)) +#define TEE_READ_REE1_MSPI_M (TEE_READ_REE1_MSPI_V << TEE_READ_REE1_MSPI_S) +#define TEE_READ_REE1_MSPI_V 0x00000001U +#define TEE_READ_REE1_MSPI_S 2 +/** TEE_READ_REE2_MSPI : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MSPI (BIT(3)) +#define TEE_READ_REE2_MSPI_M (TEE_READ_REE2_MSPI_V << TEE_READ_REE2_MSPI_S) +#define TEE_READ_REE2_MSPI_V 0x00000001U +#define TEE_READ_REE2_MSPI_S 3 +/** TEE_WRITE_TEE_MSPI : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MSPI (BIT(4)) +#define TEE_WRITE_TEE_MSPI_M (TEE_WRITE_TEE_MSPI_V << TEE_WRITE_TEE_MSPI_S) +#define TEE_WRITE_TEE_MSPI_V 0x00000001U +#define TEE_WRITE_TEE_MSPI_S 4 +/** TEE_WRITE_REE0_MSPI : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MSPI (BIT(5)) +#define TEE_WRITE_REE0_MSPI_M (TEE_WRITE_REE0_MSPI_V << TEE_WRITE_REE0_MSPI_S) +#define TEE_WRITE_REE0_MSPI_V 0x00000001U +#define TEE_WRITE_REE0_MSPI_S 5 +/** TEE_WRITE_REE1_MSPI : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MSPI (BIT(6)) +#define TEE_WRITE_REE1_MSPI_M (TEE_WRITE_REE1_MSPI_V << TEE_WRITE_REE1_MSPI_S) +#define TEE_WRITE_REE1_MSPI_V 0x00000001U +#define TEE_WRITE_REE1_MSPI_S 6 +/** TEE_WRITE_REE2_MSPI : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MSPI (BIT(7)) +#define TEE_WRITE_REE2_MSPI_M (TEE_WRITE_REE2_MSPI_V << TEE_WRITE_REE2_MSPI_S) +#define TEE_WRITE_REE2_MSPI_V 0x00000001U +#define TEE_WRITE_REE2_MSPI_S 7 + +/** TEE_HP_APM_CTRL_REG register + * hp_apm read/write control register + */ +#define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) +/** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_APM (BIT(0)) +#define TEE_READ_TEE_HP_APM_M (TEE_READ_TEE_HP_APM_V << TEE_READ_TEE_HP_APM_S) +#define TEE_READ_TEE_HP_APM_V 0x00000001U +#define TEE_READ_TEE_HP_APM_S 0 +/** TEE_READ_REE0_HP_APM : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_APM (BIT(1)) +#define TEE_READ_REE0_HP_APM_M (TEE_READ_REE0_HP_APM_V << TEE_READ_REE0_HP_APM_S) +#define TEE_READ_REE0_HP_APM_V 0x00000001U +#define TEE_READ_REE0_HP_APM_S 1 +/** TEE_READ_REE1_HP_APM : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_APM (BIT(2)) +#define TEE_READ_REE1_HP_APM_M (TEE_READ_REE1_HP_APM_V << TEE_READ_REE1_HP_APM_S) +#define TEE_READ_REE1_HP_APM_V 0x00000001U +#define TEE_READ_REE1_HP_APM_S 2 +/** TEE_READ_REE2_HP_APM : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_APM (BIT(3)) +#define TEE_READ_REE2_HP_APM_M (TEE_READ_REE2_HP_APM_V << TEE_READ_REE2_HP_APM_S) +#define TEE_READ_REE2_HP_APM_V 0x00000001U +#define TEE_READ_REE2_HP_APM_S 3 +/** TEE_WRITE_TEE_HP_APM : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_APM (BIT(4)) +#define TEE_WRITE_TEE_HP_APM_M (TEE_WRITE_TEE_HP_APM_V << TEE_WRITE_TEE_HP_APM_S) +#define TEE_WRITE_TEE_HP_APM_V 0x00000001U +#define TEE_WRITE_TEE_HP_APM_S 4 +/** TEE_WRITE_REE0_HP_APM : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_APM (BIT(5)) +#define TEE_WRITE_REE0_HP_APM_M (TEE_WRITE_REE0_HP_APM_V << TEE_WRITE_REE0_HP_APM_S) +#define TEE_WRITE_REE0_HP_APM_V 0x00000001U +#define TEE_WRITE_REE0_HP_APM_S 5 +/** TEE_WRITE_REE1_HP_APM : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_APM (BIT(6)) +#define TEE_WRITE_REE1_HP_APM_M (TEE_WRITE_REE1_HP_APM_V << TEE_WRITE_REE1_HP_APM_S) +#define TEE_WRITE_REE1_HP_APM_V 0x00000001U +#define TEE_WRITE_REE1_HP_APM_S 6 +/** TEE_WRITE_REE2_HP_APM : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_APM (BIT(7)) +#define TEE_WRITE_REE2_HP_APM_M (TEE_WRITE_REE2_HP_APM_V << TEE_WRITE_REE2_HP_APM_S) +#define TEE_WRITE_REE2_HP_APM_V 0x00000001U +#define TEE_WRITE_REE2_HP_APM_S 7 + +/** TEE_CPU_APM_CTRL_REG register + * cpu_apm read/write control register + */ +#define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) +/** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_APM (BIT(0)) +#define TEE_READ_TEE_CPU_APM_M (TEE_READ_TEE_CPU_APM_V << TEE_READ_TEE_CPU_APM_S) +#define TEE_READ_TEE_CPU_APM_V 0x00000001U +#define TEE_READ_TEE_CPU_APM_S 0 +/** TEE_READ_REE0_CPU_APM : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_APM (BIT(1)) +#define TEE_READ_REE0_CPU_APM_M (TEE_READ_REE0_CPU_APM_V << TEE_READ_REE0_CPU_APM_S) +#define TEE_READ_REE0_CPU_APM_V 0x00000001U +#define TEE_READ_REE0_CPU_APM_S 1 +/** TEE_READ_REE1_CPU_APM : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_APM (BIT(2)) +#define TEE_READ_REE1_CPU_APM_M (TEE_READ_REE1_CPU_APM_V << TEE_READ_REE1_CPU_APM_S) +#define TEE_READ_REE1_CPU_APM_V 0x00000001U +#define TEE_READ_REE1_CPU_APM_S 2 +/** TEE_READ_REE2_CPU_APM : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_APM (BIT(3)) +#define TEE_READ_REE2_CPU_APM_M (TEE_READ_REE2_CPU_APM_V << TEE_READ_REE2_CPU_APM_S) +#define TEE_READ_REE2_CPU_APM_V 0x00000001U +#define TEE_READ_REE2_CPU_APM_S 3 +/** TEE_WRITE_TEE_CPU_APM : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_APM (BIT(4)) +#define TEE_WRITE_TEE_CPU_APM_M (TEE_WRITE_TEE_CPU_APM_V << TEE_WRITE_TEE_CPU_APM_S) +#define TEE_WRITE_TEE_CPU_APM_V 0x00000001U +#define TEE_WRITE_TEE_CPU_APM_S 4 +/** TEE_WRITE_REE0_CPU_APM : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_APM (BIT(5)) +#define TEE_WRITE_REE0_CPU_APM_M (TEE_WRITE_REE0_CPU_APM_V << TEE_WRITE_REE0_CPU_APM_S) +#define TEE_WRITE_REE0_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE0_CPU_APM_S 5 +/** TEE_WRITE_REE1_CPU_APM : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_APM (BIT(6)) +#define TEE_WRITE_REE1_CPU_APM_M (TEE_WRITE_REE1_CPU_APM_V << TEE_WRITE_REE1_CPU_APM_S) +#define TEE_WRITE_REE1_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE1_CPU_APM_S 6 +/** TEE_WRITE_REE2_CPU_APM : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_APM (BIT(7)) +#define TEE_WRITE_REE2_CPU_APM_M (TEE_WRITE_REE2_CPU_APM_V << TEE_WRITE_REE2_CPU_APM_S) +#define TEE_WRITE_REE2_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE2_CPU_APM_S 7 + +/** TEE_TEE_CTRL_REG register + * tee read/write control register + */ +#define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118) +/** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TEE (BIT(0)) +#define TEE_READ_TEE_TEE_M (TEE_READ_TEE_TEE_V << TEE_READ_TEE_TEE_S) +#define TEE_READ_TEE_TEE_V 0x00000001U +#define TEE_READ_TEE_TEE_S 0 +/** TEE_READ_REE0_TEE : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TEE (BIT(1)) +#define TEE_READ_REE0_TEE_M (TEE_READ_REE0_TEE_V << TEE_READ_REE0_TEE_S) +#define TEE_READ_REE0_TEE_V 0x00000001U +#define TEE_READ_REE0_TEE_S 1 +/** TEE_READ_REE1_TEE : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TEE (BIT(2)) +#define TEE_READ_REE1_TEE_M (TEE_READ_REE1_TEE_V << TEE_READ_REE1_TEE_S) +#define TEE_READ_REE1_TEE_V 0x00000001U +#define TEE_READ_REE1_TEE_S 2 +/** TEE_READ_REE2_TEE : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TEE (BIT(3)) +#define TEE_READ_REE2_TEE_M (TEE_READ_REE2_TEE_V << TEE_READ_REE2_TEE_S) +#define TEE_READ_REE2_TEE_V 0x00000001U +#define TEE_READ_REE2_TEE_S 3 +/** TEE_WRITE_TEE_TEE : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TEE (BIT(4)) +#define TEE_WRITE_TEE_TEE_M (TEE_WRITE_TEE_TEE_V << TEE_WRITE_TEE_TEE_S) +#define TEE_WRITE_TEE_TEE_V 0x00000001U +#define TEE_WRITE_TEE_TEE_S 4 +/** TEE_WRITE_REE0_TEE : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TEE (BIT(5)) +#define TEE_WRITE_REE0_TEE_M (TEE_WRITE_REE0_TEE_V << TEE_WRITE_REE0_TEE_S) +#define TEE_WRITE_REE0_TEE_V 0x00000001U +#define TEE_WRITE_REE0_TEE_S 5 +/** TEE_WRITE_REE1_TEE : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TEE (BIT(6)) +#define TEE_WRITE_REE1_TEE_M (TEE_WRITE_REE1_TEE_V << TEE_WRITE_REE1_TEE_S) +#define TEE_WRITE_REE1_TEE_V 0x00000001U +#define TEE_WRITE_REE1_TEE_S 6 +/** TEE_WRITE_REE2_TEE : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TEE (BIT(7)) +#define TEE_WRITE_REE2_TEE_M (TEE_WRITE_REE2_TEE_V << TEE_WRITE_REE2_TEE_S) +#define TEE_WRITE_REE2_TEE_V 0x00000001U +#define TEE_WRITE_REE2_TEE_S 7 + +/** TEE_CRYPT_CTRL_REG register + * crypt read/write control register + */ +#define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x11c) +/** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CRYPT (BIT(0)) +#define TEE_READ_TEE_CRYPT_M (TEE_READ_TEE_CRYPT_V << TEE_READ_TEE_CRYPT_S) +#define TEE_READ_TEE_CRYPT_V 0x00000001U +#define TEE_READ_TEE_CRYPT_S 0 +/** TEE_READ_REE0_CRYPT : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CRYPT (BIT(1)) +#define TEE_READ_REE0_CRYPT_M (TEE_READ_REE0_CRYPT_V << TEE_READ_REE0_CRYPT_S) +#define TEE_READ_REE0_CRYPT_V 0x00000001U +#define TEE_READ_REE0_CRYPT_S 1 +/** TEE_READ_REE1_CRYPT : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CRYPT (BIT(2)) +#define TEE_READ_REE1_CRYPT_M (TEE_READ_REE1_CRYPT_V << TEE_READ_REE1_CRYPT_S) +#define TEE_READ_REE1_CRYPT_V 0x00000001U +#define TEE_READ_REE1_CRYPT_S 2 +/** TEE_READ_REE2_CRYPT : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CRYPT (BIT(3)) +#define TEE_READ_REE2_CRYPT_M (TEE_READ_REE2_CRYPT_V << TEE_READ_REE2_CRYPT_S) +#define TEE_READ_REE2_CRYPT_V 0x00000001U +#define TEE_READ_REE2_CRYPT_S 3 +/** TEE_WRITE_TEE_CRYPT : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CRYPT (BIT(4)) +#define TEE_WRITE_TEE_CRYPT_M (TEE_WRITE_TEE_CRYPT_V << TEE_WRITE_TEE_CRYPT_S) +#define TEE_WRITE_TEE_CRYPT_V 0x00000001U +#define TEE_WRITE_TEE_CRYPT_S 4 +/** TEE_WRITE_REE0_CRYPT : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CRYPT (BIT(5)) +#define TEE_WRITE_REE0_CRYPT_M (TEE_WRITE_REE0_CRYPT_V << TEE_WRITE_REE0_CRYPT_S) +#define TEE_WRITE_REE0_CRYPT_V 0x00000001U +#define TEE_WRITE_REE0_CRYPT_S 5 +/** TEE_WRITE_REE1_CRYPT : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CRYPT (BIT(6)) +#define TEE_WRITE_REE1_CRYPT_M (TEE_WRITE_REE1_CRYPT_V << TEE_WRITE_REE1_CRYPT_S) +#define TEE_WRITE_REE1_CRYPT_V 0x00000001U +#define TEE_WRITE_REE1_CRYPT_S 6 +/** TEE_WRITE_REE2_CRYPT : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CRYPT (BIT(7)) +#define TEE_WRITE_REE2_CRYPT_M (TEE_WRITE_REE2_CRYPT_V << TEE_WRITE_REE2_CRYPT_S) +#define TEE_WRITE_REE2_CRYPT_V 0x00000001U +#define TEE_WRITE_REE2_CRYPT_S 7 + +/** TEE_TRACE_CTRL_REG register + * trace read/write control register + */ +#define TEE_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x120) +/** TEE_READ_TEE_TRACE : R/W; bitpos: [0]; default: 1; + * Configures trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TRACE (BIT(0)) +#define TEE_READ_TEE_TRACE_M (TEE_READ_TEE_TRACE_V << TEE_READ_TEE_TRACE_S) +#define TEE_READ_TEE_TRACE_V 0x00000001U +#define TEE_READ_TEE_TRACE_S 0 +/** TEE_READ_REE0_TRACE : R/W; bitpos: [1]; default: 0; + * Configures trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TRACE (BIT(1)) +#define TEE_READ_REE0_TRACE_M (TEE_READ_REE0_TRACE_V << TEE_READ_REE0_TRACE_S) +#define TEE_READ_REE0_TRACE_V 0x00000001U +#define TEE_READ_REE0_TRACE_S 1 +/** TEE_READ_REE1_TRACE : R/W; bitpos: [2]; default: 0; + * Configures trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TRACE (BIT(2)) +#define TEE_READ_REE1_TRACE_M (TEE_READ_REE1_TRACE_V << TEE_READ_REE1_TRACE_S) +#define TEE_READ_REE1_TRACE_V 0x00000001U +#define TEE_READ_REE1_TRACE_S 2 +/** TEE_READ_REE2_TRACE : R/W; bitpos: [3]; default: 0; + * Configures trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TRACE (BIT(3)) +#define TEE_READ_REE2_TRACE_M (TEE_READ_REE2_TRACE_V << TEE_READ_REE2_TRACE_S) +#define TEE_READ_REE2_TRACE_V 0x00000001U +#define TEE_READ_REE2_TRACE_S 3 +/** TEE_WRITE_TEE_TRACE : R/W; bitpos: [4]; default: 1; + * Configures trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TRACE (BIT(4)) +#define TEE_WRITE_TEE_TRACE_M (TEE_WRITE_TEE_TRACE_V << TEE_WRITE_TEE_TRACE_S) +#define TEE_WRITE_TEE_TRACE_V 0x00000001U +#define TEE_WRITE_TEE_TRACE_S 4 +/** TEE_WRITE_REE0_TRACE : R/W; bitpos: [5]; default: 0; + * Configures trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TRACE (BIT(5)) +#define TEE_WRITE_REE0_TRACE_M (TEE_WRITE_REE0_TRACE_V << TEE_WRITE_REE0_TRACE_S) +#define TEE_WRITE_REE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE0_TRACE_S 5 +/** TEE_WRITE_REE1_TRACE : R/W; bitpos: [6]; default: 0; + * Configures trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TRACE (BIT(6)) +#define TEE_WRITE_REE1_TRACE_M (TEE_WRITE_REE1_TRACE_V << TEE_WRITE_REE1_TRACE_S) +#define TEE_WRITE_REE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE1_TRACE_S 6 +/** TEE_WRITE_REE2_TRACE : R/W; bitpos: [7]; default: 0; + * Configures trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TRACE (BIT(7)) +#define TEE_WRITE_REE2_TRACE_M (TEE_WRITE_REE2_TRACE_V << TEE_WRITE_REE2_TRACE_S) +#define TEE_WRITE_REE2_TRACE_V 0x00000001U +#define TEE_WRITE_REE2_TRACE_S 7 + +/** TEE_CPU_BUS_MONITOR_CTRL_REG register + * cpu_bus_monitor read/write control register + */ +#define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x128) +/** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_BUS_MONITOR (BIT(0)) +#define TEE_READ_TEE_CPU_BUS_MONITOR_M (TEE_READ_TEE_CPU_BUS_MONITOR_V << TEE_READ_TEE_CPU_BUS_MONITOR_S) +#define TEE_READ_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_CPU_BUS_MONITOR_S 0 +/** TEE_READ_REE0_CPU_BUS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_BUS_MONITOR (BIT(1)) +#define TEE_READ_REE0_CPU_BUS_MONITOR_M (TEE_READ_REE0_CPU_BUS_MONITOR_V << TEE_READ_REE0_CPU_BUS_MONITOR_S) +#define TEE_READ_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_CPU_BUS_MONITOR_S 1 +/** TEE_READ_REE1_CPU_BUS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_BUS_MONITOR (BIT(2)) +#define TEE_READ_REE1_CPU_BUS_MONITOR_M (TEE_READ_REE1_CPU_BUS_MONITOR_V << TEE_READ_REE1_CPU_BUS_MONITOR_S) +#define TEE_READ_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_CPU_BUS_MONITOR_S 2 +/** TEE_READ_REE2_CPU_BUS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_BUS_MONITOR (BIT(3)) +#define TEE_READ_REE2_CPU_BUS_MONITOR_M (TEE_READ_REE2_CPU_BUS_MONITOR_V << TEE_READ_REE2_CPU_BUS_MONITOR_S) +#define TEE_READ_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_CPU_BUS_MONITOR_S 3 +/** TEE_WRITE_TEE_CPU_BUS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_BUS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_M (TEE_WRITE_TEE_CPU_BUS_MONITOR_V << TEE_WRITE_TEE_CPU_BUS_MONITOR_S) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_S 4 +/** TEE_WRITE_REE0_CPU_BUS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_BUS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_M (TEE_WRITE_REE0_CPU_BUS_MONITOR_V << TEE_WRITE_REE0_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_S 5 +/** TEE_WRITE_REE1_CPU_BUS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_BUS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_M (TEE_WRITE_REE1_CPU_BUS_MONITOR_V << TEE_WRITE_REE1_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_S 6 +/** TEE_WRITE_REE2_CPU_BUS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_BUS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_M (TEE_WRITE_REE2_CPU_BUS_MONITOR_V << TEE_WRITE_REE2_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 + +/** TEE_INTPRI_REG_CTRL_REG register + * intpri_reg read/write control register + */ +#define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x12c) +/** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTPRI_REG (BIT(0)) +#define TEE_READ_TEE_INTPRI_REG_M (TEE_READ_TEE_INTPRI_REG_V << TEE_READ_TEE_INTPRI_REG_S) +#define TEE_READ_TEE_INTPRI_REG_V 0x00000001U +#define TEE_READ_TEE_INTPRI_REG_S 0 +/** TEE_READ_REE0_INTPRI_REG : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTPRI_REG (BIT(1)) +#define TEE_READ_REE0_INTPRI_REG_M (TEE_READ_REE0_INTPRI_REG_V << TEE_READ_REE0_INTPRI_REG_S) +#define TEE_READ_REE0_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE0_INTPRI_REG_S 1 +/** TEE_READ_REE1_INTPRI_REG : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTPRI_REG (BIT(2)) +#define TEE_READ_REE1_INTPRI_REG_M (TEE_READ_REE1_INTPRI_REG_V << TEE_READ_REE1_INTPRI_REG_S) +#define TEE_READ_REE1_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE1_INTPRI_REG_S 2 +/** TEE_READ_REE2_INTPRI_REG : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTPRI_REG (BIT(3)) +#define TEE_READ_REE2_INTPRI_REG_M (TEE_READ_REE2_INTPRI_REG_V << TEE_READ_REE2_INTPRI_REG_S) +#define TEE_READ_REE2_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE2_INTPRI_REG_S 3 +/** TEE_WRITE_TEE_INTPRI_REG : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTPRI_REG (BIT(4)) +#define TEE_WRITE_TEE_INTPRI_REG_M (TEE_WRITE_TEE_INTPRI_REG_V << TEE_WRITE_TEE_INTPRI_REG_S) +#define TEE_WRITE_TEE_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_TEE_INTPRI_REG_S 4 +/** TEE_WRITE_REE0_INTPRI_REG : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTPRI_REG (BIT(5)) +#define TEE_WRITE_REE0_INTPRI_REG_M (TEE_WRITE_REE0_INTPRI_REG_V << TEE_WRITE_REE0_INTPRI_REG_S) +#define TEE_WRITE_REE0_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE0_INTPRI_REG_S 5 +/** TEE_WRITE_REE1_INTPRI_REG : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTPRI_REG (BIT(6)) +#define TEE_WRITE_REE1_INTPRI_REG_M (TEE_WRITE_REE1_INTPRI_REG_V << TEE_WRITE_REE1_INTPRI_REG_S) +#define TEE_WRITE_REE1_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE1_INTPRI_REG_S 6 +/** TEE_WRITE_REE2_INTPRI_REG : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTPRI_REG (BIT(7)) +#define TEE_WRITE_REE2_INTPRI_REG_M (TEE_WRITE_REE2_INTPRI_REG_V << TEE_WRITE_REE2_INTPRI_REG_S) +#define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE2_INTPRI_REG_S 7 + +/** TEE_CACHE_CFG_CTRL_REG register + * cache_cfg read/write control register + */ +#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x130) +/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CACHE_CFG (BIT(0)) +#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) +#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U +#define TEE_READ_TEE_CACHE_CFG_S 0 +/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CACHE_CFG (BIT(1)) +#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) +#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE0_CACHE_CFG_S 1 +/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CACHE_CFG (BIT(2)) +#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) +#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE1_CACHE_CFG_S 2 +/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CACHE_CFG (BIT(3)) +#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) +#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE2_CACHE_CFG_S 3 +/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) +#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) +#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_TEE_CACHE_CFG_S 4 +/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) +#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) +#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE0_CACHE_CFG_S 5 +/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) +#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) +#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE1_CACHE_CFG_S 6 +/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) +#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) +#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE2_CACHE_CFG_S 7 + +/** TEE_MODEM_CTRL_REG register + * modem read/write control register + */ +#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x134) +/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MODEM (BIT(0)) +#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) +#define TEE_READ_TEE_MODEM_V 0x00000001U +#define TEE_READ_TEE_MODEM_S 0 +/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MODEM (BIT(1)) +#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) +#define TEE_READ_REE0_MODEM_V 0x00000001U +#define TEE_READ_REE0_MODEM_S 1 +/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MODEM (BIT(2)) +#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) +#define TEE_READ_REE1_MODEM_V 0x00000001U +#define TEE_READ_REE1_MODEM_S 2 +/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MODEM (BIT(3)) +#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) +#define TEE_READ_REE2_MODEM_V 0x00000001U +#define TEE_READ_REE2_MODEM_S 3 +/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MODEM (BIT(4)) +#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) +#define TEE_WRITE_TEE_MODEM_V 0x00000001U +#define TEE_WRITE_TEE_MODEM_S 4 +/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MODEM (BIT(5)) +#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) +#define TEE_WRITE_REE0_MODEM_V 0x00000001U +#define TEE_WRITE_REE0_MODEM_S 5 +/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MODEM (BIT(6)) +#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) +#define TEE_WRITE_REE1_MODEM_V 0x00000001U +#define TEE_WRITE_REE1_MODEM_S 6 +/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MODEM (BIT(7)) +#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) +#define TEE_WRITE_REE2_MODEM_V 0x00000001U +#define TEE_WRITE_REE2_MODEM_S 7 + +/** TEE_CAN1_CTRL_REG register + * can1 read/write control register + */ +#define TEE_CAN1_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_CAN1 : R/W; bitpos: [0]; default: 1; + * Configures can1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CAN1 (BIT(0)) +#define TEE_READ_TEE_CAN1_M (TEE_READ_TEE_CAN1_V << TEE_READ_TEE_CAN1_S) +#define TEE_READ_TEE_CAN1_V 0x00000001U +#define TEE_READ_TEE_CAN1_S 0 +/** TEE_READ_REE0_CAN1 : R/W; bitpos: [1]; default: 0; + * Configures can1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CAN1 (BIT(1)) +#define TEE_READ_REE0_CAN1_M (TEE_READ_REE0_CAN1_V << TEE_READ_REE0_CAN1_S) +#define TEE_READ_REE0_CAN1_V 0x00000001U +#define TEE_READ_REE0_CAN1_S 1 +/** TEE_READ_REE1_CAN1 : R/W; bitpos: [2]; default: 0; + * Configures can1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CAN1 (BIT(2)) +#define TEE_READ_REE1_CAN1_M (TEE_READ_REE1_CAN1_V << TEE_READ_REE1_CAN1_S) +#define TEE_READ_REE1_CAN1_V 0x00000001U +#define TEE_READ_REE1_CAN1_S 2 +/** TEE_READ_REE2_CAN1 : R/W; bitpos: [3]; default: 0; + * Configures can1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CAN1 (BIT(3)) +#define TEE_READ_REE2_CAN1_M (TEE_READ_REE2_CAN1_V << TEE_READ_REE2_CAN1_S) +#define TEE_READ_REE2_CAN1_V 0x00000001U +#define TEE_READ_REE2_CAN1_S 3 +/** TEE_WRITE_TEE_CAN1 : R/W; bitpos: [4]; default: 1; + * Configures can1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CAN1 (BIT(4)) +#define TEE_WRITE_TEE_CAN1_M (TEE_WRITE_TEE_CAN1_V << TEE_WRITE_TEE_CAN1_S) +#define TEE_WRITE_TEE_CAN1_V 0x00000001U +#define TEE_WRITE_TEE_CAN1_S 4 +/** TEE_WRITE_REE0_CAN1 : R/W; bitpos: [5]; default: 0; + * Configures can1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CAN1 (BIT(5)) +#define TEE_WRITE_REE0_CAN1_M (TEE_WRITE_REE0_CAN1_V << TEE_WRITE_REE0_CAN1_S) +#define TEE_WRITE_REE0_CAN1_V 0x00000001U +#define TEE_WRITE_REE0_CAN1_S 5 +/** TEE_WRITE_REE1_CAN1 : R/W; bitpos: [6]; default: 0; + * Configures can1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CAN1 (BIT(6)) +#define TEE_WRITE_REE1_CAN1_M (TEE_WRITE_REE1_CAN1_V << TEE_WRITE_REE1_CAN1_S) +#define TEE_WRITE_REE1_CAN1_V 0x00000001U +#define TEE_WRITE_REE1_CAN1_S 6 +/** TEE_WRITE_REE2_CAN1 : R/W; bitpos: [7]; default: 0; + * Configures can1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CAN1 (BIT(7)) +#define TEE_WRITE_REE2_CAN1_M (TEE_WRITE_REE2_CAN1_V << TEE_WRITE_REE2_CAN1_S) +#define TEE_WRITE_REE2_CAN1_V 0x00000001U +#define TEE_WRITE_REE2_CAN1_S 7 + +/** TEE_SPI2_CTRL_REG register + * spi2 read/write control register + */ +#define TEE_SPI2_CTRL_REG (DR_REG_TEE_BASE + 0x13c) +/** TEE_READ_TEE_SPI2 : R/W; bitpos: [0]; default: 1; + * Configures spi2 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SPI2 (BIT(0)) +#define TEE_READ_TEE_SPI2_M (TEE_READ_TEE_SPI2_V << TEE_READ_TEE_SPI2_S) +#define TEE_READ_TEE_SPI2_V 0x00000001U +#define TEE_READ_TEE_SPI2_S 0 +/** TEE_READ_REE0_SPI2 : R/W; bitpos: [1]; default: 0; + * Configures spi2 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SPI2 (BIT(1)) +#define TEE_READ_REE0_SPI2_M (TEE_READ_REE0_SPI2_V << TEE_READ_REE0_SPI2_S) +#define TEE_READ_REE0_SPI2_V 0x00000001U +#define TEE_READ_REE0_SPI2_S 1 +/** TEE_READ_REE1_SPI2 : R/W; bitpos: [2]; default: 0; + * Configures spi2 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SPI2 (BIT(2)) +#define TEE_READ_REE1_SPI2_M (TEE_READ_REE1_SPI2_V << TEE_READ_REE1_SPI2_S) +#define TEE_READ_REE1_SPI2_V 0x00000001U +#define TEE_READ_REE1_SPI2_S 2 +/** TEE_READ_REE2_SPI2 : R/W; bitpos: [3]; default: 0; + * Configures spi2 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SPI2 (BIT(3)) +#define TEE_READ_REE2_SPI2_M (TEE_READ_REE2_SPI2_V << TEE_READ_REE2_SPI2_S) +#define TEE_READ_REE2_SPI2_V 0x00000001U +#define TEE_READ_REE2_SPI2_S 3 +/** TEE_WRITE_TEE_SPI2 : R/W; bitpos: [4]; default: 1; + * Configures spi2 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SPI2 (BIT(4)) +#define TEE_WRITE_TEE_SPI2_M (TEE_WRITE_TEE_SPI2_V << TEE_WRITE_TEE_SPI2_S) +#define TEE_WRITE_TEE_SPI2_V 0x00000001U +#define TEE_WRITE_TEE_SPI2_S 4 +/** TEE_WRITE_REE0_SPI2 : R/W; bitpos: [5]; default: 0; + * Configures spi2 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SPI2 (BIT(5)) +#define TEE_WRITE_REE0_SPI2_M (TEE_WRITE_REE0_SPI2_V << TEE_WRITE_REE0_SPI2_S) +#define TEE_WRITE_REE0_SPI2_V 0x00000001U +#define TEE_WRITE_REE0_SPI2_S 5 +/** TEE_WRITE_REE1_SPI2 : R/W; bitpos: [6]; default: 0; + * Configures spi2 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SPI2 (BIT(6)) +#define TEE_WRITE_REE1_SPI2_M (TEE_WRITE_REE1_SPI2_V << TEE_WRITE_REE1_SPI2_S) +#define TEE_WRITE_REE1_SPI2_V 0x00000001U +#define TEE_WRITE_REE1_SPI2_S 6 +/** TEE_WRITE_REE2_SPI2 : R/W; bitpos: [7]; default: 0; + * Configures spi2 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SPI2 (BIT(7)) +#define TEE_WRITE_REE2_SPI2_M (TEE_WRITE_REE2_SPI2_V << TEE_WRITE_REE2_SPI2_S) +#define TEE_WRITE_REE2_SPI2_V 0x00000001U +#define TEE_WRITE_REE2_SPI2_S 7 + +/** TEE_BS_CTRL_REG register + * bs read/write control register + */ +#define TEE_BS_CTRL_REG (DR_REG_TEE_BASE + 0x140) +/** TEE_READ_TEE_BS : R/W; bitpos: [0]; default: 1; + * Configures bs registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_BS (BIT(0)) +#define TEE_READ_TEE_BS_M (TEE_READ_TEE_BS_V << TEE_READ_TEE_BS_S) +#define TEE_READ_TEE_BS_V 0x00000001U +#define TEE_READ_TEE_BS_S 0 +/** TEE_READ_REE0_BS : R/W; bitpos: [1]; default: 0; + * Configures bs registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_BS (BIT(1)) +#define TEE_READ_REE0_BS_M (TEE_READ_REE0_BS_V << TEE_READ_REE0_BS_S) +#define TEE_READ_REE0_BS_V 0x00000001U +#define TEE_READ_REE0_BS_S 1 +/** TEE_READ_REE1_BS : R/W; bitpos: [2]; default: 0; + * Configures bs registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_BS (BIT(2)) +#define TEE_READ_REE1_BS_M (TEE_READ_REE1_BS_V << TEE_READ_REE1_BS_S) +#define TEE_READ_REE1_BS_V 0x00000001U +#define TEE_READ_REE1_BS_S 2 +/** TEE_READ_REE2_BS : R/W; bitpos: [3]; default: 0; + * Configures bs registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_BS (BIT(3)) +#define TEE_READ_REE2_BS_M (TEE_READ_REE2_BS_V << TEE_READ_REE2_BS_S) +#define TEE_READ_REE2_BS_V 0x00000001U +#define TEE_READ_REE2_BS_S 3 +/** TEE_WRITE_TEE_BS : R/W; bitpos: [4]; default: 1; + * Configures bs registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_BS (BIT(4)) +#define TEE_WRITE_TEE_BS_M (TEE_WRITE_TEE_BS_V << TEE_WRITE_TEE_BS_S) +#define TEE_WRITE_TEE_BS_V 0x00000001U +#define TEE_WRITE_TEE_BS_S 4 +/** TEE_WRITE_REE0_BS : R/W; bitpos: [5]; default: 0; + * Configures bs registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_BS (BIT(5)) +#define TEE_WRITE_REE0_BS_M (TEE_WRITE_REE0_BS_V << TEE_WRITE_REE0_BS_S) +#define TEE_WRITE_REE0_BS_V 0x00000001U +#define TEE_WRITE_REE0_BS_S 5 +/** TEE_WRITE_REE1_BS : R/W; bitpos: [6]; default: 0; + * Configures bs registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_BS (BIT(6)) +#define TEE_WRITE_REE1_BS_M (TEE_WRITE_REE1_BS_V << TEE_WRITE_REE1_BS_S) +#define TEE_WRITE_REE1_BS_V 0x00000001U +#define TEE_WRITE_REE1_BS_S 6 +/** TEE_WRITE_REE2_BS : R/W; bitpos: [7]; default: 0; + * Configures bs registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_BS (BIT(7)) +#define TEE_WRITE_REE2_BS_M (TEE_WRITE_REE2_BS_V << TEE_WRITE_REE2_BS_S) +#define TEE_WRITE_REE2_BS_V 0x00000001U +#define TEE_WRITE_REE2_BS_S 7 + +/** TEE_KM_CTRL_REG register + * km read/write control register + */ +#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x144) +/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_KM (BIT(0)) +#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) +#define TEE_READ_TEE_KM_V 0x00000001U +#define TEE_READ_TEE_KM_S 0 +/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_KM (BIT(1)) +#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) +#define TEE_READ_REE0_KM_V 0x00000001U +#define TEE_READ_REE0_KM_S 1 +/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_KM (BIT(2)) +#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) +#define TEE_READ_REE1_KM_V 0x00000001U +#define TEE_READ_REE1_KM_S 2 +/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_KM (BIT(3)) +#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) +#define TEE_READ_REE2_KM_V 0x00000001U +#define TEE_READ_REE2_KM_S 3 +/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_KM (BIT(4)) +#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) +#define TEE_WRITE_TEE_KM_V 0x00000001U +#define TEE_WRITE_TEE_KM_S 4 +/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_KM (BIT(5)) +#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) +#define TEE_WRITE_REE0_KM_V 0x00000001U +#define TEE_WRITE_REE0_KM_S 5 +/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_KM (BIT(6)) +#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) +#define TEE_WRITE_REE1_KM_V 0x00000001U +#define TEE_WRITE_REE1_KM_S 6 +/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_KM (BIT(7)) +#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) +#define TEE_WRITE_REE2_KM_V 0x00000001U +#define TEE_WRITE_REE2_KM_S 7 + +/** TEE_MODEM_PWR_CTRL_REG register + * modem_pwr read/write control register + */ +#define TEE_MODEM_PWR_CTRL_REG (DR_REG_TEE_BASE + 0x148) +/** TEE_READ_TEE_MODEM_PWR : R/W; bitpos: [0]; default: 1; + * Configures modem_pwr registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MODEM_PWR (BIT(0)) +#define TEE_READ_TEE_MODEM_PWR_M (TEE_READ_TEE_MODEM_PWR_V << TEE_READ_TEE_MODEM_PWR_S) +#define TEE_READ_TEE_MODEM_PWR_V 0x00000001U +#define TEE_READ_TEE_MODEM_PWR_S 0 +/** TEE_READ_REE0_MODEM_PWR : R/W; bitpos: [1]; default: 0; + * Configures modem_pwr registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MODEM_PWR (BIT(1)) +#define TEE_READ_REE0_MODEM_PWR_M (TEE_READ_REE0_MODEM_PWR_V << TEE_READ_REE0_MODEM_PWR_S) +#define TEE_READ_REE0_MODEM_PWR_V 0x00000001U +#define TEE_READ_REE0_MODEM_PWR_S 1 +/** TEE_READ_REE1_MODEM_PWR : R/W; bitpos: [2]; default: 0; + * Configures modem_pwr registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MODEM_PWR (BIT(2)) +#define TEE_READ_REE1_MODEM_PWR_M (TEE_READ_REE1_MODEM_PWR_V << TEE_READ_REE1_MODEM_PWR_S) +#define TEE_READ_REE1_MODEM_PWR_V 0x00000001U +#define TEE_READ_REE1_MODEM_PWR_S 2 +/** TEE_READ_REE2_MODEM_PWR : R/W; bitpos: [3]; default: 0; + * Configures modem_pwr registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MODEM_PWR (BIT(3)) +#define TEE_READ_REE2_MODEM_PWR_M (TEE_READ_REE2_MODEM_PWR_V << TEE_READ_REE2_MODEM_PWR_S) +#define TEE_READ_REE2_MODEM_PWR_V 0x00000001U +#define TEE_READ_REE2_MODEM_PWR_S 3 +/** TEE_WRITE_TEE_MODEM_PWR : R/W; bitpos: [4]; default: 1; + * Configures modem_pwr registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MODEM_PWR (BIT(4)) +#define TEE_WRITE_TEE_MODEM_PWR_M (TEE_WRITE_TEE_MODEM_PWR_V << TEE_WRITE_TEE_MODEM_PWR_S) +#define TEE_WRITE_TEE_MODEM_PWR_V 0x00000001U +#define TEE_WRITE_TEE_MODEM_PWR_S 4 +/** TEE_WRITE_REE0_MODEM_PWR : R/W; bitpos: [5]; default: 0; + * Configures modem_pwr registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MODEM_PWR (BIT(5)) +#define TEE_WRITE_REE0_MODEM_PWR_M (TEE_WRITE_REE0_MODEM_PWR_V << TEE_WRITE_REE0_MODEM_PWR_S) +#define TEE_WRITE_REE0_MODEM_PWR_V 0x00000001U +#define TEE_WRITE_REE0_MODEM_PWR_S 5 +/** TEE_WRITE_REE1_MODEM_PWR : R/W; bitpos: [6]; default: 0; + * Configures modem_pwr registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MODEM_PWR (BIT(6)) +#define TEE_WRITE_REE1_MODEM_PWR_M (TEE_WRITE_REE1_MODEM_PWR_V << TEE_WRITE_REE1_MODEM_PWR_S) +#define TEE_WRITE_REE1_MODEM_PWR_V 0x00000001U +#define TEE_WRITE_REE1_MODEM_PWR_S 6 +/** TEE_WRITE_REE2_MODEM_PWR : R/W; bitpos: [7]; default: 0; + * Configures modem_pwr registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MODEM_PWR (BIT(7)) +#define TEE_WRITE_REE2_MODEM_PWR_M (TEE_WRITE_REE2_MODEM_PWR_V << TEE_WRITE_REE2_MODEM_PWR_S) +#define TEE_WRITE_REE2_MODEM_PWR_V 0x00000001U +#define TEE_WRITE_REE2_MODEM_PWR_S 7 + +/** TEE_HINF_CTRL_REG register + * hinf read/write control register + */ +#define TEE_HINF_CTRL_REG (DR_REG_TEE_BASE + 0x14c) +/** TEE_READ_TEE_HINF : R/W; bitpos: [0]; default: 1; + * Configures hinf registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HINF (BIT(0)) +#define TEE_READ_TEE_HINF_M (TEE_READ_TEE_HINF_V << TEE_READ_TEE_HINF_S) +#define TEE_READ_TEE_HINF_V 0x00000001U +#define TEE_READ_TEE_HINF_S 0 +/** TEE_READ_REE0_HINF : R/W; bitpos: [1]; default: 0; + * Configures hinf registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HINF (BIT(1)) +#define TEE_READ_REE0_HINF_M (TEE_READ_REE0_HINF_V << TEE_READ_REE0_HINF_S) +#define TEE_READ_REE0_HINF_V 0x00000001U +#define TEE_READ_REE0_HINF_S 1 +/** TEE_READ_REE1_HINF : R/W; bitpos: [2]; default: 0; + * Configures hinf registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HINF (BIT(2)) +#define TEE_READ_REE1_HINF_M (TEE_READ_REE1_HINF_V << TEE_READ_REE1_HINF_S) +#define TEE_READ_REE1_HINF_V 0x00000001U +#define TEE_READ_REE1_HINF_S 2 +/** TEE_READ_REE2_HINF : R/W; bitpos: [3]; default: 0; + * Configures hinf registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HINF (BIT(3)) +#define TEE_READ_REE2_HINF_M (TEE_READ_REE2_HINF_V << TEE_READ_REE2_HINF_S) +#define TEE_READ_REE2_HINF_V 0x00000001U +#define TEE_READ_REE2_HINF_S 3 +/** TEE_WRITE_TEE_HINF : R/W; bitpos: [4]; default: 1; + * Configures hinf registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HINF (BIT(4)) +#define TEE_WRITE_TEE_HINF_M (TEE_WRITE_TEE_HINF_V << TEE_WRITE_TEE_HINF_S) +#define TEE_WRITE_TEE_HINF_V 0x00000001U +#define TEE_WRITE_TEE_HINF_S 4 +/** TEE_WRITE_REE0_HINF : R/W; bitpos: [5]; default: 0; + * Configures hinf registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HINF (BIT(5)) +#define TEE_WRITE_REE0_HINF_M (TEE_WRITE_REE0_HINF_V << TEE_WRITE_REE0_HINF_S) +#define TEE_WRITE_REE0_HINF_V 0x00000001U +#define TEE_WRITE_REE0_HINF_S 5 +/** TEE_WRITE_REE1_HINF : R/W; bitpos: [6]; default: 0; + * Configures hinf registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HINF (BIT(6)) +#define TEE_WRITE_REE1_HINF_M (TEE_WRITE_REE1_HINF_V << TEE_WRITE_REE1_HINF_S) +#define TEE_WRITE_REE1_HINF_V 0x00000001U +#define TEE_WRITE_REE1_HINF_S 6 +/** TEE_WRITE_REE2_HINF : R/W; bitpos: [7]; default: 0; + * Configures hinf registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HINF (BIT(7)) +#define TEE_WRITE_REE2_HINF_M (TEE_WRITE_REE2_HINF_V << TEE_WRITE_REE2_HINF_S) +#define TEE_WRITE_REE2_HINF_V 0x00000001U +#define TEE_WRITE_REE2_HINF_S 7 + +/** TEE_SLC_CTRL_REG register + * slc read/write control register + */ +#define TEE_SLC_CTRL_REG (DR_REG_TEE_BASE + 0x150) +/** TEE_READ_TEE_SLC : R/W; bitpos: [0]; default: 1; + * Configures slc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SLC (BIT(0)) +#define TEE_READ_TEE_SLC_M (TEE_READ_TEE_SLC_V << TEE_READ_TEE_SLC_S) +#define TEE_READ_TEE_SLC_V 0x00000001U +#define TEE_READ_TEE_SLC_S 0 +/** TEE_READ_REE0_SLC : R/W; bitpos: [1]; default: 0; + * Configures slc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SLC (BIT(1)) +#define TEE_READ_REE0_SLC_M (TEE_READ_REE0_SLC_V << TEE_READ_REE0_SLC_S) +#define TEE_READ_REE0_SLC_V 0x00000001U +#define TEE_READ_REE0_SLC_S 1 +/** TEE_READ_REE1_SLC : R/W; bitpos: [2]; default: 0; + * Configures slc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SLC (BIT(2)) +#define TEE_READ_REE1_SLC_M (TEE_READ_REE1_SLC_V << TEE_READ_REE1_SLC_S) +#define TEE_READ_REE1_SLC_V 0x00000001U +#define TEE_READ_REE1_SLC_S 2 +/** TEE_READ_REE2_SLC : R/W; bitpos: [3]; default: 0; + * Configures slc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SLC (BIT(3)) +#define TEE_READ_REE2_SLC_M (TEE_READ_REE2_SLC_V << TEE_READ_REE2_SLC_S) +#define TEE_READ_REE2_SLC_V 0x00000001U +#define TEE_READ_REE2_SLC_S 3 +/** TEE_WRITE_TEE_SLC : R/W; bitpos: [4]; default: 1; + * Configures slc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SLC (BIT(4)) +#define TEE_WRITE_TEE_SLC_M (TEE_WRITE_TEE_SLC_V << TEE_WRITE_TEE_SLC_S) +#define TEE_WRITE_TEE_SLC_V 0x00000001U +#define TEE_WRITE_TEE_SLC_S 4 +/** TEE_WRITE_REE0_SLC : R/W; bitpos: [5]; default: 0; + * Configures slc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SLC (BIT(5)) +#define TEE_WRITE_REE0_SLC_M (TEE_WRITE_REE0_SLC_V << TEE_WRITE_REE0_SLC_S) +#define TEE_WRITE_REE0_SLC_V 0x00000001U +#define TEE_WRITE_REE0_SLC_S 5 +/** TEE_WRITE_REE1_SLC : R/W; bitpos: [6]; default: 0; + * Configures slc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SLC (BIT(6)) +#define TEE_WRITE_REE1_SLC_M (TEE_WRITE_REE1_SLC_V << TEE_WRITE_REE1_SLC_S) +#define TEE_WRITE_REE1_SLC_V 0x00000001U +#define TEE_WRITE_REE1_SLC_S 6 +/** TEE_WRITE_REE2_SLC : R/W; bitpos: [7]; default: 0; + * Configures slc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SLC (BIT(7)) +#define TEE_WRITE_REE2_SLC_M (TEE_WRITE_REE2_SLC_V << TEE_WRITE_REE2_SLC_S) +#define TEE_WRITE_REE2_SLC_V 0x00000001U +#define TEE_WRITE_REE2_SLC_S 7 + +/** TEE_SLC_HOST_CTRL_REG register + * slc_host read/write control register + */ +#define TEE_SLC_HOST_CTRL_REG (DR_REG_TEE_BASE + 0x158) +/** TEE_READ_TEE_SLC_HOST : R/W; bitpos: [0]; default: 1; + * Configures slc_host registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SLC_HOST (BIT(0)) +#define TEE_READ_TEE_SLC_HOST_M (TEE_READ_TEE_SLC_HOST_V << TEE_READ_TEE_SLC_HOST_S) +#define TEE_READ_TEE_SLC_HOST_V 0x00000001U +#define TEE_READ_TEE_SLC_HOST_S 0 +/** TEE_READ_REE0_SLC_HOST : R/W; bitpos: [1]; default: 0; + * Configures slc_host registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SLC_HOST (BIT(1)) +#define TEE_READ_REE0_SLC_HOST_M (TEE_READ_REE0_SLC_HOST_V << TEE_READ_REE0_SLC_HOST_S) +#define TEE_READ_REE0_SLC_HOST_V 0x00000001U +#define TEE_READ_REE0_SLC_HOST_S 1 +/** TEE_READ_REE1_SLC_HOST : R/W; bitpos: [2]; default: 0; + * Configures slc_host registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SLC_HOST (BIT(2)) +#define TEE_READ_REE1_SLC_HOST_M (TEE_READ_REE1_SLC_HOST_V << TEE_READ_REE1_SLC_HOST_S) +#define TEE_READ_REE1_SLC_HOST_V 0x00000001U +#define TEE_READ_REE1_SLC_HOST_S 2 +/** TEE_READ_REE2_SLC_HOST : R/W; bitpos: [3]; default: 0; + * Configures slc_host registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SLC_HOST (BIT(3)) +#define TEE_READ_REE2_SLC_HOST_M (TEE_READ_REE2_SLC_HOST_V << TEE_READ_REE2_SLC_HOST_S) +#define TEE_READ_REE2_SLC_HOST_V 0x00000001U +#define TEE_READ_REE2_SLC_HOST_S 3 +/** TEE_WRITE_TEE_SLC_HOST : R/W; bitpos: [4]; default: 1; + * Configures slc_host registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SLC_HOST (BIT(4)) +#define TEE_WRITE_TEE_SLC_HOST_M (TEE_WRITE_TEE_SLC_HOST_V << TEE_WRITE_TEE_SLC_HOST_S) +#define TEE_WRITE_TEE_SLC_HOST_V 0x00000001U +#define TEE_WRITE_TEE_SLC_HOST_S 4 +/** TEE_WRITE_REE0_SLC_HOST : R/W; bitpos: [5]; default: 0; + * Configures slc_host registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SLC_HOST (BIT(5)) +#define TEE_WRITE_REE0_SLC_HOST_M (TEE_WRITE_REE0_SLC_HOST_V << TEE_WRITE_REE0_SLC_HOST_S) +#define TEE_WRITE_REE0_SLC_HOST_V 0x00000001U +#define TEE_WRITE_REE0_SLC_HOST_S 5 +/** TEE_WRITE_REE1_SLC_HOST : R/W; bitpos: [6]; default: 0; + * Configures slc_host registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SLC_HOST (BIT(6)) +#define TEE_WRITE_REE1_SLC_HOST_M (TEE_WRITE_REE1_SLC_HOST_V << TEE_WRITE_REE1_SLC_HOST_S) +#define TEE_WRITE_REE1_SLC_HOST_V 0x00000001U +#define TEE_WRITE_REE1_SLC_HOST_S 6 +/** TEE_WRITE_REE2_SLC_HOST : R/W; bitpos: [7]; default: 0; + * Configures slc_host registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SLC_HOST (BIT(7)) +#define TEE_WRITE_REE2_SLC_HOST_M (TEE_WRITE_REE2_SLC_HOST_V << TEE_WRITE_REE2_SLC_HOST_S) +#define TEE_WRITE_REE2_SLC_HOST_V 0x00000001U +#define TEE_WRITE_REE2_SLC_HOST_S 7 + +/** TEE_BUS_ERR_CONF_REG register + * Clock gating register + */ +#define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) +/** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ +#define TEE_BUS_ERR_RESP_EN (BIT(0)) +#define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) +#define TEE_BUS_ERR_RESP_EN_V 0x00000001U +#define TEE_BUS_ERR_RESP_EN_S 0 + /** TEE_CLOCK_GATE_REG register * Clock gating register */ -#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) /** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ #define TEE_CLK_EN (BIT(0)) #define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) @@ -765,7 +4244,7 @@ extern "C" { * Version control register */ #define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) -/** TEE_DATE : R/W; bitpos: [27:0]; default: 35725664; +/** TEE_DATE : R/W; bitpos: [27:0]; default: 37773824; * Version control register */ #define TEE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h index 2b9f8b48ba..13f9c99d53 100644 --- a/components/soc/esp32c5/register/soc/tee_struct.h +++ b/components/soc/esp32c5/register/soc/tee_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,11 +17,11 @@ extern "C" { typedef union { struct { /** mn_mode : R/W; bitpos: [1:0]; default: 0; - * Configures Mn security level mode.\\ - * 0: tee_mode \\ - * 1: ree_mode0 \\ - * 2: ree_mode1 \\ - * 3: ree_mode2 \\ + * Configures Mn security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 */ uint32_t mn_mode:2; /** mn_lock : R/W; bitpos: [2]; default: 0; @@ -34,6 +34,2636 @@ typedef union { } tee_mn_mode_ctrl_reg_t; +/** Group: read write control register */ +/** Type of uart0_ctrl register + * uart0 read/write control register + */ +typedef union { + struct { + /** read_tee_uart0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart0:1; + /** read_ree0_uart0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart0:1; + /** read_ree1_uart0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart0:1; + /** read_ree2_uart0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart0:1; + /** write_tee_uart0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart0:1; + /** write_ree0_uart0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart0:1; + /** write_ree1_uart0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart0:1; + /** write_ree2_uart0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart0_ctrl_reg_t; + +/** Type of uart1_ctrl register + * uart1 read/write control register + */ +typedef union { + struct { + /** read_tee_uart1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart1:1; + /** read_ree0_uart1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart1:1; + /** read_ree1_uart1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart1:1; + /** read_ree2_uart1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart1:1; + /** write_tee_uart1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart1:1; + /** write_ree0_uart1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart1:1; + /** write_ree1_uart1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart1:1; + /** write_ree2_uart1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart1_ctrl_reg_t; + +/** Type of uhci0_ctrl register + * uhci0 read/write control register + */ +typedef union { + struct { + /** read_tee_uhci0 : R/W; bitpos: [0]; default: 1; + * Configures uhci0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uhci0:1; + /** read_ree0_uhci0 : R/W; bitpos: [1]; default: 0; + * Configures uhci0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uhci0:1; + /** read_ree1_uhci0 : R/W; bitpos: [2]; default: 0; + * Configures uhci0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uhci0:1; + /** read_ree2_uhci0 : R/W; bitpos: [3]; default: 0; + * Configures uhci0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uhci0:1; + /** write_tee_uhci0 : R/W; bitpos: [4]; default: 1; + * Configures uhci0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uhci0:1; + /** write_ree0_uhci0 : R/W; bitpos: [5]; default: 0; + * Configures uhci0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uhci0:1; + /** write_ree1_uhci0 : R/W; bitpos: [6]; default: 0; + * Configures uhci0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uhci0:1; + /** write_ree2_uhci0 : R/W; bitpos: [7]; default: 0; + * Configures uhci0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uhci0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uhci0_ctrl_reg_t; + +/** Type of i2c_ext0_ctrl register + * i2c_ext0 read/write control register + */ +typedef union { + struct { + /** read_tee_i2c_ext0 : R/W; bitpos: [0]; default: 1; + * Configures i2c_ext0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c_ext0:1; + /** read_ree0_i2c_ext0 : R/W; bitpos: [1]; default: 0; + * Configures i2c_ext0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c_ext0:1; + /** read_ree1_i2c_ext0 : R/W; bitpos: [2]; default: 0; + * Configures i2c_ext0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c_ext0:1; + /** read_ree2_i2c_ext0 : R/W; bitpos: [3]; default: 0; + * Configures i2c_ext0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c_ext0:1; + /** write_tee_i2c_ext0 : R/W; bitpos: [4]; default: 1; + * Configures i2c_ext0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c_ext0:1; + /** write_ree0_i2c_ext0 : R/W; bitpos: [5]; default: 0; + * Configures i2c_ext0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c_ext0:1; + /** write_ree1_i2c_ext0 : R/W; bitpos: [6]; default: 0; + * Configures i2c_ext0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c_ext0:1; + /** write_ree2_i2c_ext0 : R/W; bitpos: [7]; default: 0; + * Configures i2c_ext0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c_ext0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2c_ext0_ctrl_reg_t; + +/** Type of i2s_ctrl register + * i2s read/write control register + */ +typedef union { + struct { + /** read_tee_i2s : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2s:1; + /** read_ree0_i2s : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2s:1; + /** read_ree1_i2s : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2s:1; + /** read_ree2_i2s : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2s:1; + /** write_tee_i2s : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2s:1; + /** write_ree0_i2s : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2s:1; + /** write_ree1_i2s : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2s:1; + /** write_ree2_i2s : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2s:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2s_ctrl_reg_t; + +/** Type of parl_io_ctrl register + * parl_io read/write control register + */ +typedef union { + struct { + /** read_tee_parl_io : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_parl_io:1; + /** read_ree0_parl_io : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_parl_io:1; + /** read_ree1_parl_io : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_parl_io:1; + /** read_ree2_parl_io : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_parl_io:1; + /** write_tee_parl_io : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_parl_io:1; + /** write_ree0_parl_io : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_parl_io:1; + /** write_ree1_parl_io : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_parl_io:1; + /** write_ree2_parl_io : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_parl_io:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_parl_io_ctrl_reg_t; + +/** Type of pwm_ctrl register + * pwm read/write control register + */ +typedef union { + struct { + /** read_tee_pwm : R/W; bitpos: [0]; default: 1; + * Configures pwm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pwm:1; + /** read_ree0_pwm : R/W; bitpos: [1]; default: 0; + * Configures pwm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pwm:1; + /** read_ree1_pwm : R/W; bitpos: [2]; default: 0; + * Configures pwm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pwm:1; + /** read_ree2_pwm : R/W; bitpos: [3]; default: 0; + * Configures pwm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pwm:1; + /** write_tee_pwm : R/W; bitpos: [4]; default: 1; + * Configures pwm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pwm:1; + /** write_ree0_pwm : R/W; bitpos: [5]; default: 0; + * Configures pwm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pwm:1; + /** write_ree1_pwm : R/W; bitpos: [6]; default: 0; + * Configures pwm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pwm:1; + /** write_ree2_pwm : R/W; bitpos: [7]; default: 0; + * Configures pwm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pwm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pwm_ctrl_reg_t; + +/** Type of ledc_ctrl register + * ledc read/write control register + */ +typedef union { + struct { + /** read_tee_ledc : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_ledc:1; + /** read_ree0_ledc : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_ledc:1; + /** read_ree1_ledc : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_ledc:1; + /** read_ree2_ledc : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_ledc:1; + /** write_tee_ledc : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_ledc:1; + /** write_ree0_ledc : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_ledc:1; + /** write_ree1_ledc : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_ledc:1; + /** write_ree2_ledc : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_ledc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_ledc_ctrl_reg_t; + +/** Type of can0_ctrl register + * can read/write control register + */ +typedef union { + struct { + /** read_tee_can0 : R/W; bitpos: [0]; default: 1; + * Configures can0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_can0:1; + /** read_ree0_can0 : R/W; bitpos: [1]; default: 0; + * Configures can0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_can0:1; + /** read_ree1_can0 : R/W; bitpos: [2]; default: 0; + * Configures can0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_can0:1; + /** read_ree2_can0 : R/W; bitpos: [3]; default: 0; + * Configures can0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_can0:1; + /** write_tee_can0 : R/W; bitpos: [4]; default: 1; + * Configures can0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_can0:1; + /** write_ree0_can0 : R/W; bitpos: [5]; default: 0; + * Configures can0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_can0:1; + /** write_ree1_can0 : R/W; bitpos: [6]; default: 0; + * Configures can0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_can0:1; + /** write_ree2_can0 : R/W; bitpos: [7]; default: 0; + * Configures can0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_can0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_can0_ctrl_reg_t; + +/** Type of usb_device_ctrl register + * usb_device read/write control register + */ +typedef union { + struct { + /** read_tee_usb_device : R/W; bitpos: [0]; default: 1; + * Configures usb_device registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_device:1; + /** read_ree0_usb_device : R/W; bitpos: [1]; default: 0; + * Configures usb_device registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_device:1; + /** read_ree1_usb_device : R/W; bitpos: [2]; default: 0; + * Configures usb_device registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_device:1; + /** read_ree2_usb_device : R/W; bitpos: [3]; default: 0; + * Configures usb_device registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_device:1; + /** write_tee_usb_device : R/W; bitpos: [4]; default: 1; + * Configures usb_device registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_device:1; + /** write_ree0_usb_device : R/W; bitpos: [5]; default: 0; + * Configures usb_device registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_device:1; + /** write_ree1_usb_device : R/W; bitpos: [6]; default: 0; + * Configures usb_device registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_device:1; + /** write_ree2_usb_device : R/W; bitpos: [7]; default: 0; + * Configures usb_device registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_device:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_device_ctrl_reg_t; + +/** Type of rmt_ctrl register + * rmt read/write control register + */ +typedef union { + struct { + /** read_tee_rmt : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_rmt:1; + /** read_ree0_rmt : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_rmt:1; + /** read_ree1_rmt : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_rmt:1; + /** read_ree2_rmt : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_rmt:1; + /** write_tee_rmt : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_rmt:1; + /** write_ree0_rmt : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_rmt:1; + /** write_ree1_rmt : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_rmt:1; + /** write_ree2_rmt : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_rmt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_rmt_ctrl_reg_t; + +/** Type of gdma_ctrl register + * gdma read/write control register + */ +typedef union { + struct { + /** read_tee_gdma : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gdma:1; + /** read_ree0_gdma : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gdma:1; + /** read_ree1_gdma : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gdma:1; + /** read_ree2_gdma : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gdma:1; + /** write_tee_gdma : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gdma:1; + /** write_ree0_gdma : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gdma:1; + /** write_ree1_gdma : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gdma:1; + /** write_ree2_gdma : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gdma_ctrl_reg_t; + +/** Type of regdma_ctrl register + * regdma read/write control register + */ +typedef union { + struct { + /** read_tee_regdma : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_regdma:1; + /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_regdma:1; + /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_regdma:1; + /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_regdma:1; + /** write_tee_regdma : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_regdma:1; + /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_regdma:1; + /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_regdma:1; + /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_regdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_regdma_ctrl_reg_t; + +/** Type of etm_ctrl register + * etm read/write control register + */ +typedef union { + struct { + /** read_tee_etm : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_etm:1; + /** read_ree0_etm : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_etm:1; + /** read_ree1_etm : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_etm:1; + /** read_ree2_etm : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_etm:1; + /** write_tee_etm : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_etm:1; + /** write_ree0_etm : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_etm:1; + /** write_ree1_etm : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_etm:1; + /** write_ree2_etm : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_etm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_etm_ctrl_reg_t; + +/** Type of intmtx_ctrl register + * intmtx read/write control register + */ +typedef union { + struct { + /** read_tee_intmtx_core : R/W; bitpos: [0]; default: 1; + * Configures intmtx registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intmtx_core:1; + /** read_ree0_intmtx_core : R/W; bitpos: [1]; default: 0; + * Configures intmtx registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intmtx_core:1; + /** read_ree1_intmtx_core : R/W; bitpos: [2]; default: 0; + * Configures intmtx registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intmtx_core:1; + /** read_ree2_intmtx_core : R/W; bitpos: [3]; default: 0; + * Configures intmtx registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intmtx_core:1; + /** write_tee_intmtx_core : R/W; bitpos: [4]; default: 1; + * Configures intmtx registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intmtx_core:1; + /** write_ree0_intmtx_core : R/W; bitpos: [5]; default: 0; + * Configures intmtx registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intmtx_core:1; + /** write_ree1_intmtx_core : R/W; bitpos: [6]; default: 0; + * Configures intmtx registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intmtx_core:1; + /** write_ree2_intmtx_core : R/W; bitpos: [7]; default: 0; + * Configures intmtx registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intmtx_core:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intmtx_ctrl_reg_t; + +/** Type of apb_adc_ctrl register + * apb_adc read/write control register + */ +typedef union { + struct { + /** read_tee_apb_adc : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_apb_adc:1; + /** read_ree0_apb_adc : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_apb_adc:1; + /** read_ree1_apb_adc : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_apb_adc:1; + /** read_ree2_apb_adc : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_apb_adc:1; + /** write_tee_apb_adc : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_apb_adc:1; + /** write_ree0_apb_adc : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_apb_adc:1; + /** write_ree1_apb_adc : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_apb_adc:1; + /** write_ree2_apb_adc : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_apb_adc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_apb_adc_ctrl_reg_t; + +/** Type of timergroup0_ctrl register + * timergroup0 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup0:1; + /** read_ree0_timergroup0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup0:1; + /** read_ree1_timergroup0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup0:1; + /** read_ree2_timergroup0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup0:1; + /** write_tee_timergroup0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup0:1; + /** write_ree0_timergroup0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup0:1; + /** write_ree1_timergroup0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup0:1; + /** write_ree2_timergroup0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup0_ctrl_reg_t; + +/** Type of timergroup1_ctrl register + * timergroup1 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup1:1; + /** read_ree0_timergroup1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup1:1; + /** read_ree1_timergroup1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup1:1; + /** read_ree2_timergroup1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup1:1; + /** write_tee_timergroup1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup1:1; + /** write_ree0_timergroup1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup1:1; + /** write_ree1_timergroup1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup1:1; + /** write_ree2_timergroup1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup1_ctrl_reg_t; + +/** Type of systimer_ctrl register + * systimer read/write control register + */ +typedef union { + struct { + /** read_tee_systimer : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_systimer:1; + /** read_ree0_systimer : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_systimer:1; + /** read_ree1_systimer : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_systimer:1; + /** read_ree2_systimer : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_systimer:1; + /** write_tee_systimer : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_systimer:1; + /** write_ree0_systimer : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_systimer:1; + /** write_ree1_systimer : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_systimer:1; + /** write_ree2_systimer : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_systimer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_systimer_ctrl_reg_t; + +/** Type of misc_ctrl register + * misc read/write control register + */ +typedef union { + struct { + /** read_tee_misc : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_misc:1; + /** read_ree0_misc : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_misc:1; + /** read_ree1_misc : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_misc:1; + /** read_ree2_misc : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_misc:1; + /** write_tee_misc : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_misc:1; + /** write_ree0_misc : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_misc:1; + /** write_ree1_misc : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_misc:1; + /** write_ree2_misc : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_misc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_misc_ctrl_reg_t; + +/** Type of pvt_monitor_ctrl register + * pvt_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pvt_monitor:1; + /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pvt_monitor:1; + /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pvt_monitor:1; + /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pvt_monitor:1; + /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pvt_monitor:1; + /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pvt_monitor:1; + /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pvt_monitor:1; + /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pvt_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pvt_monitor_ctrl_reg_t; + +/** Type of pcnt_ctrl register + * pcnt read/write control register + */ +typedef union { + struct { + /** read_tee_pcnt : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcnt:1; + /** read_ree0_pcnt : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcnt:1; + /** read_ree1_pcnt : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcnt:1; + /** read_ree2_pcnt : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcnt:1; + /** write_tee_pcnt : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcnt:1; + /** write_ree0_pcnt : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcnt:1; + /** write_ree1_pcnt : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcnt:1; + /** write_ree2_pcnt : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcnt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcnt_ctrl_reg_t; + +/** Type of iomux_ctrl register + * iomux read/write control register + */ +typedef union { + struct { + /** read_tee_iomux : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_iomux:1; + /** read_ree0_iomux : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_iomux:1; + /** read_ree1_iomux : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_iomux:1; + /** read_ree2_iomux : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_iomux:1; + /** write_tee_iomux : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_iomux:1; + /** write_ree0_iomux : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_iomux:1; + /** write_ree1_iomux : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_iomux:1; + /** write_ree2_iomux : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_iomux:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_iomux_ctrl_reg_t; + +/** Type of psram_mem_monitor_ctrl register + * psram_mem_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_psram_mem_monitor : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_psram_mem_monitor:1; + /** read_ree0_psram_mem_monitor : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_psram_mem_monitor:1; + /** read_ree1_psram_mem_monitor : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_psram_mem_monitor:1; + /** read_ree2_psram_mem_monitor : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_psram_mem_monitor:1; + /** write_tee_psram_mem_monitor : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_psram_mem_monitor:1; + /** write_ree0_psram_mem_monitor : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_psram_mem_monitor:1; + /** write_ree1_psram_mem_monitor : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_psram_mem_monitor:1; + /** write_ree2_psram_mem_monitor : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_psram_mem_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_psram_mem_monitor_ctrl_reg_t; + +/** Type of mem_acs_monitor_ctrl register + * mem_acs_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_mem_acs_monitor : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mem_acs_monitor:1; + /** read_ree0_mem_acs_monitor : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mem_acs_monitor:1; + /** read_ree1_mem_acs_monitor : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mem_acs_monitor:1; + /** read_ree2_mem_acs_monitor : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mem_acs_monitor:1; + /** write_tee_mem_acs_monitor : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mem_acs_monitor:1; + /** write_ree0_mem_acs_monitor : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mem_acs_monitor:1; + /** write_ree1_mem_acs_monitor : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mem_acs_monitor:1; + /** write_ree2_mem_acs_monitor : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mem_acs_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mem_acs_monitor_ctrl_reg_t; + +/** Type of hp_system_reg_ctrl register + * hp_system_reg read/write control register + */ +typedef union { + struct { + /** read_tee_hp_system_reg : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_system_reg:1; + /** read_ree0_hp_system_reg : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_system_reg:1; + /** read_ree1_hp_system_reg : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_system_reg:1; + /** read_ree2_hp_system_reg : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_system_reg:1; + /** write_tee_hp_system_reg : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_system_reg:1; + /** write_ree0_hp_system_reg : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_system_reg:1; + /** write_ree1_hp_system_reg : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_system_reg:1; + /** write_ree2_hp_system_reg : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_system_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_system_reg_ctrl_reg_t; + +/** Type of pcr_reg_ctrl register + * pcr_reg read/write control register + */ +typedef union { + struct { + /** read_tee_pcr_reg : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcr_reg:1; + /** read_ree0_pcr_reg : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcr_reg:1; + /** read_ree1_pcr_reg : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcr_reg:1; + /** read_ree2_pcr_reg : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcr_reg:1; + /** write_tee_pcr_reg : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcr_reg:1; + /** write_ree0_pcr_reg : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcr_reg:1; + /** write_ree1_pcr_reg : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcr_reg:1; + /** write_ree2_pcr_reg : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcr_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcr_reg_ctrl_reg_t; + +/** Type of mspi_ctrl register + * mspi read/write control register + */ +typedef union { + struct { + /** read_tee_mspi : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mspi:1; + /** read_ree0_mspi : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mspi:1; + /** read_ree1_mspi : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mspi:1; + /** read_ree2_mspi : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mspi:1; + /** write_tee_mspi : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mspi:1; + /** write_ree0_mspi : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mspi:1; + /** write_ree1_mspi : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mspi:1; + /** write_ree2_mspi : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mspi:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mspi_ctrl_reg_t; + +/** Type of hp_apm_ctrl register + * hp_apm read/write control register + */ +typedef union { + struct { + /** read_tee_hp_apm : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_apm:1; + /** read_ree0_hp_apm : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_apm:1; + /** read_ree1_hp_apm : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_apm:1; + /** read_ree2_hp_apm : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_apm:1; + /** write_tee_hp_apm : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_apm:1; + /** write_ree0_hp_apm : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_apm:1; + /** write_ree1_hp_apm : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_apm:1; + /** write_ree2_hp_apm : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_apm_ctrl_reg_t; + +/** Type of cpu_apm_ctrl register + * cpu_apm read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_apm : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_apm:1; + /** read_ree0_cpu_apm : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_apm:1; + /** read_ree1_cpu_apm : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_apm:1; + /** read_ree2_cpu_apm : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_apm:1; + /** write_tee_cpu_apm : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_apm:1; + /** write_ree0_cpu_apm : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_apm:1; + /** write_ree1_cpu_apm : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_apm:1; + /** write_ree2_cpu_apm : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_apm_ctrl_reg_t; + +/** Type of tee_ctrl register + * tee read/write control register + */ +typedef union { + struct { + /** read_tee_tee : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_tee:1; + /** read_ree0_tee : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_tee:1; + /** read_ree1_tee : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_tee:1; + /** read_ree2_tee : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_tee:1; + /** write_tee_tee : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_tee:1; + /** write_ree0_tee : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_tee:1; + /** write_ree1_tee : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_tee:1; + /** write_ree2_tee : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_tee:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_tee_ctrl_reg_t; + +/** Type of crypt_ctrl register + * crypt read/write control register + */ +typedef union { + struct { + /** read_tee_crypt : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_crypt:1; + /** read_ree0_crypt : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_crypt:1; + /** read_ree1_crypt : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_crypt:1; + /** read_ree2_crypt : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_crypt:1; + /** write_tee_crypt : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_crypt:1; + /** write_ree0_crypt : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_crypt:1; + /** write_ree1_crypt : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_crypt:1; + /** write_ree2_crypt : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_crypt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_crypt_ctrl_reg_t; + +/** Type of trace_ctrl register + * trace read/write control register + */ +typedef union { + struct { + /** read_tee_trace : R/W; bitpos: [0]; default: 1; + * Configures trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_trace:1; + /** read_ree0_trace : R/W; bitpos: [1]; default: 0; + * Configures trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_trace:1; + /** read_ree1_trace : R/W; bitpos: [2]; default: 0; + * Configures trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_trace:1; + /** read_ree2_trace : R/W; bitpos: [3]; default: 0; + * Configures trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_trace:1; + /** write_tee_trace : R/W; bitpos: [4]; default: 1; + * Configures trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_trace:1; + /** write_ree0_trace : R/W; bitpos: [5]; default: 0; + * Configures trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_trace:1; + /** write_ree1_trace : R/W; bitpos: [6]; default: 0; + * Configures trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_trace:1; + /** write_ree2_trace : R/W; bitpos: [7]; default: 0; + * Configures trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_trace:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_trace_ctrl_reg_t; + +/** Type of cpu_bus_monitor_ctrl register + * cpu_bus_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_bus_monitor : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_bus_monitor:1; + /** read_ree0_cpu_bus_monitor : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_bus_monitor:1; + /** read_ree1_cpu_bus_monitor : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_bus_monitor:1; + /** read_ree2_cpu_bus_monitor : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_bus_monitor:1; + /** write_tee_cpu_bus_monitor : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_bus_monitor:1; + /** write_ree0_cpu_bus_monitor : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_bus_monitor:1; + /** write_ree1_cpu_bus_monitor : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_bus_monitor:1; + /** write_ree2_cpu_bus_monitor : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_bus_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_bus_monitor_ctrl_reg_t; + +/** Type of intpri_reg_ctrl register + * intpri_reg read/write control register + */ +typedef union { + struct { + /** read_tee_intpri_reg : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intpri_reg:1; + /** read_ree0_intpri_reg : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intpri_reg:1; + /** read_ree1_intpri_reg : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intpri_reg:1; + /** read_ree2_intpri_reg : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intpri_reg:1; + /** write_tee_intpri_reg : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intpri_reg:1; + /** write_ree0_intpri_reg : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intpri_reg:1; + /** write_ree1_intpri_reg : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intpri_reg:1; + /** write_ree2_intpri_reg : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intpri_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intpri_reg_ctrl_reg_t; + +/** Type of cache_cfg_ctrl register + * cache_cfg read/write control register + */ +typedef union { + struct { + /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cache_cfg:1; + /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cache_cfg:1; + /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cache_cfg:1; + /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cache_cfg:1; + /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cache_cfg:1; + /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cache_cfg:1; + /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cache_cfg:1; + /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cache_cfg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cache_cfg_ctrl_reg_t; + +/** Type of modem_ctrl register + * modem read/write control register + */ +typedef union { + struct { + /** read_tee_modem : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_modem:1; + /** read_ree0_modem : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_modem:1; + /** read_ree1_modem : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_modem:1; + /** read_ree2_modem : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_modem:1; + /** write_tee_modem : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_modem:1; + /** write_ree0_modem : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_modem:1; + /** write_ree1_modem : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_modem:1; + /** write_ree2_modem : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_modem:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_modem_ctrl_reg_t; + +/** Type of can1_ctrl register + * can1 read/write control register + */ +typedef union { + struct { + /** read_tee_can1 : R/W; bitpos: [0]; default: 1; + * Configures can1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_can1:1; + /** read_ree0_can1 : R/W; bitpos: [1]; default: 0; + * Configures can1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_can1:1; + /** read_ree1_can1 : R/W; bitpos: [2]; default: 0; + * Configures can1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_can1:1; + /** read_ree2_can1 : R/W; bitpos: [3]; default: 0; + * Configures can1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_can1:1; + /** write_tee_can1 : R/W; bitpos: [4]; default: 1; + * Configures can1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_can1:1; + /** write_ree0_can1 : R/W; bitpos: [5]; default: 0; + * Configures can1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_can1:1; + /** write_ree1_can1 : R/W; bitpos: [6]; default: 0; + * Configures can1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_can1:1; + /** write_ree2_can1 : R/W; bitpos: [7]; default: 0; + * Configures can1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_can1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_can1_ctrl_reg_t; + +/** Type of spi2_ctrl register + * spi2 read/write control register + */ +typedef union { + struct { + /** read_tee_spi2 : R/W; bitpos: [0]; default: 1; + * Configures spi2 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_spi2:1; + /** read_ree0_spi2 : R/W; bitpos: [1]; default: 0; + * Configures spi2 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_spi2:1; + /** read_ree1_spi2 : R/W; bitpos: [2]; default: 0; + * Configures spi2 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_spi2:1; + /** read_ree2_spi2 : R/W; bitpos: [3]; default: 0; + * Configures spi2 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_spi2:1; + /** write_tee_spi2 : R/W; bitpos: [4]; default: 1; + * Configures spi2 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_spi2:1; + /** write_ree0_spi2 : R/W; bitpos: [5]; default: 0; + * Configures spi2 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_spi2:1; + /** write_ree1_spi2 : R/W; bitpos: [6]; default: 0; + * Configures spi2 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_spi2:1; + /** write_ree2_spi2 : R/W; bitpos: [7]; default: 0; + * Configures spi2 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_spi2:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_spi2_ctrl_reg_t; + +/** Type of bs_ctrl register + * bs read/write control register + */ +typedef union { + struct { + /** read_tee_bs : R/W; bitpos: [0]; default: 1; + * Configures bs registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_bs:1; + /** read_ree0_bs : R/W; bitpos: [1]; default: 0; + * Configures bs registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_bs:1; + /** read_ree1_bs : R/W; bitpos: [2]; default: 0; + * Configures bs registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_bs:1; + /** read_ree2_bs : R/W; bitpos: [3]; default: 0; + * Configures bs registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_bs:1; + /** write_tee_bs : R/W; bitpos: [4]; default: 1; + * Configures bs registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_bs:1; + /** write_ree0_bs : R/W; bitpos: [5]; default: 0; + * Configures bs registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_bs:1; + /** write_ree1_bs : R/W; bitpos: [6]; default: 0; + * Configures bs registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_bs:1; + /** write_ree2_bs : R/W; bitpos: [7]; default: 0; + * Configures bs registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_bs:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_bs_ctrl_reg_t; + +/** Type of km_ctrl register + * km read/write control register + */ +typedef union { + struct { + /** read_tee_km : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_km:1; + /** read_ree0_km : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_km:1; + /** read_ree1_km : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_km:1; + /** read_ree2_km : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_km:1; + /** write_tee_km : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_km:1; + /** write_ree0_km : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_km:1; + /** write_ree1_km : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_km:1; + /** write_ree2_km : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_km:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_km_ctrl_reg_t; + +/** Type of modem_pwr_ctrl register + * modem_pwr read/write control register + */ +typedef union { + struct { + /** read_tee_modem_pwr : R/W; bitpos: [0]; default: 1; + * Configures modem_pwr registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_modem_pwr:1; + /** read_ree0_modem_pwr : R/W; bitpos: [1]; default: 0; + * Configures modem_pwr registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_modem_pwr:1; + /** read_ree1_modem_pwr : R/W; bitpos: [2]; default: 0; + * Configures modem_pwr registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_modem_pwr:1; + /** read_ree2_modem_pwr : R/W; bitpos: [3]; default: 0; + * Configures modem_pwr registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_modem_pwr:1; + /** write_tee_modem_pwr : R/W; bitpos: [4]; default: 1; + * Configures modem_pwr registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_modem_pwr:1; + /** write_ree0_modem_pwr : R/W; bitpos: [5]; default: 0; + * Configures modem_pwr registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_modem_pwr:1; + /** write_ree1_modem_pwr : R/W; bitpos: [6]; default: 0; + * Configures modem_pwr registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_modem_pwr:1; + /** write_ree2_modem_pwr : R/W; bitpos: [7]; default: 0; + * Configures modem_pwr registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_modem_pwr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_modem_pwr_ctrl_reg_t; + +/** Type of hinf_ctrl register + * hinf read/write control register + */ +typedef union { + struct { + /** read_tee_hinf : R/W; bitpos: [0]; default: 1; + * Configures hinf registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hinf:1; + /** read_ree0_hinf : R/W; bitpos: [1]; default: 0; + * Configures hinf registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hinf:1; + /** read_ree1_hinf : R/W; bitpos: [2]; default: 0; + * Configures hinf registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hinf:1; + /** read_ree2_hinf : R/W; bitpos: [3]; default: 0; + * Configures hinf registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hinf:1; + /** write_tee_hinf : R/W; bitpos: [4]; default: 1; + * Configures hinf registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hinf:1; + /** write_ree0_hinf : R/W; bitpos: [5]; default: 0; + * Configures hinf registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hinf:1; + /** write_ree1_hinf : R/W; bitpos: [6]; default: 0; + * Configures hinf registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hinf:1; + /** write_ree2_hinf : R/W; bitpos: [7]; default: 0; + * Configures hinf registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hinf:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hinf_ctrl_reg_t; + +/** Type of slc_ctrl register + * slc read/write control register + */ +typedef union { + struct { + /** read_tee_slc : R/W; bitpos: [0]; default: 1; + * Configures slc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_slc:1; + /** read_ree0_slc : R/W; bitpos: [1]; default: 0; + * Configures slc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_slc:1; + /** read_ree1_slc : R/W; bitpos: [2]; default: 0; + * Configures slc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_slc:1; + /** read_ree2_slc : R/W; bitpos: [3]; default: 0; + * Configures slc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_slc:1; + /** write_tee_slc : R/W; bitpos: [4]; default: 1; + * Configures slc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_slc:1; + /** write_ree0_slc : R/W; bitpos: [5]; default: 0; + * Configures slc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_slc:1; + /** write_ree1_slc : R/W; bitpos: [6]; default: 0; + * Configures slc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_slc:1; + /** write_ree2_slc : R/W; bitpos: [7]; default: 0; + * Configures slc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_slc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_slc_ctrl_reg_t; + +/** Type of slc_host_ctrl register + * slc_host read/write control register + */ +typedef union { + struct { + /** read_tee_slc_host : R/W; bitpos: [0]; default: 1; + * Configures slc_host registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_slc_host:1; + /** read_ree0_slc_host : R/W; bitpos: [1]; default: 0; + * Configures slc_host registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_slc_host:1; + /** read_ree1_slc_host : R/W; bitpos: [2]; default: 0; + * Configures slc_host registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_slc_host:1; + /** read_ree2_slc_host : R/W; bitpos: [3]; default: 0; + * Configures slc_host registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_slc_host:1; + /** write_tee_slc_host : R/W; bitpos: [4]; default: 1; + * Configures slc_host registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_slc_host:1; + /** write_ree0_slc_host : R/W; bitpos: [5]; default: 0; + * Configures slc_host registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_slc_host:1; + /** write_ree1_slc_host : R/W; bitpos: [6]; default: 0; + * Configures slc_host registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_slc_host:1; + /** write_ree2_slc_host : R/W; bitpos: [7]; default: 0; + * Configures slc_host registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_slc_host:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_slc_host_ctrl_reg_t; + + +/** Group: config register */ +/** Type of bus_err_conf register + * Clock gating register + */ +typedef union { + struct { + /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ + uint32_t bus_err_resp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_bus_err_conf_reg_t; + + /** Group: clock gating register */ /** Type of clock_gate register * Clock gating register @@ -41,9 +2671,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -58,7 +2688,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35725664; + /** date : R/W; bitpos: [27:0]; default: 37773824; * Version control register */ uint32_t date:28; @@ -70,8 +2700,62 @@ typedef union { typedef struct { volatile tee_mn_mode_ctrl_reg_t mn_mode_ctrl[32]; + uint32_t reserved_080[2]; + volatile tee_uart0_ctrl_reg_t uart0_ctrl; + volatile tee_uart1_ctrl_reg_t uart1_ctrl; + volatile tee_uhci0_ctrl_reg_t uhci0_ctrl; + volatile tee_i2c_ext0_ctrl_reg_t i2c_ext0_ctrl; + uint32_t reserved_098; + volatile tee_i2s_ctrl_reg_t i2s_ctrl; + volatile tee_parl_io_ctrl_reg_t parl_io_ctrl; + volatile tee_pwm_ctrl_reg_t pwm_ctrl; + uint32_t reserved_0a8; + volatile tee_ledc_ctrl_reg_t ledc_ctrl; + volatile tee_can0_ctrl_reg_t can0_ctrl; + volatile tee_usb_device_ctrl_reg_t usb_device_ctrl; + volatile tee_rmt_ctrl_reg_t rmt_ctrl; + volatile tee_gdma_ctrl_reg_t gdma_ctrl; + volatile tee_regdma_ctrl_reg_t regdma_ctrl; + volatile tee_etm_ctrl_reg_t etm_ctrl; + volatile tee_intmtx_ctrl_reg_t intmtx_ctrl; + uint32_t reserved_0cc; + volatile tee_apb_adc_ctrl_reg_t apb_adc_ctrl; + volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; + volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; + volatile tee_systimer_ctrl_reg_t systimer_ctrl; + volatile tee_misc_ctrl_reg_t misc_ctrl; + uint32_t reserved_0e4[3]; + volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; + volatile tee_iomux_ctrl_reg_t iomux_ctrl; + volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; + volatile tee_mem_acs_monitor_ctrl_reg_t mem_acs_monitor_ctrl; + volatile tee_hp_system_reg_ctrl_reg_t hp_system_reg_ctrl; + volatile tee_pcr_reg_ctrl_reg_t pcr_reg_ctrl; + volatile tee_mspi_ctrl_reg_t mspi_ctrl; + volatile tee_hp_apm_ctrl_reg_t hp_apm_ctrl; + volatile tee_cpu_apm_ctrl_reg_t cpu_apm_ctrl; + volatile tee_tee_ctrl_reg_t tee_ctrl; + volatile tee_crypt_ctrl_reg_t crypt_ctrl; + volatile tee_trace_ctrl_reg_t trace_ctrl; + uint32_t reserved_124; + volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; + volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; + volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; + volatile tee_modem_ctrl_reg_t modem_ctrl; + volatile tee_can1_ctrl_reg_t can1_ctrl; + volatile tee_spi2_ctrl_reg_t spi2_ctrl; + volatile tee_bs_ctrl_reg_t bs_ctrl; + volatile tee_km_ctrl_reg_t km_ctrl; + volatile tee_modem_pwr_ctrl_reg_t modem_pwr_ctrl; + volatile tee_hinf_ctrl_reg_t hinf_ctrl; + volatile tee_slc_ctrl_reg_t slc_ctrl; + uint32_t reserved_154; + volatile tee_slc_host_ctrl_reg_t slc_host_ctrl; + uint32_t reserved_15c[933]; + volatile tee_bus_err_conf_reg_t bus_err_conf; + uint32_t reserved_ff4; volatile tee_clock_gate_reg_t clock_gate; - uint32_t reserved_084[990]; volatile tee_date_reg_t date; } tee_dev_t; diff --git a/components/soc/esp32c5/register/soc/timer_group_reg.h b/components/soc/esp32c5/register/soc/timer_group_reg.h index b00cdf705c..9c9f0da78d 100644 --- a/components/soc/esp32c5/register/soc/timer_group_reg.h +++ b/components/soc/esp32c5/register/soc/timer_group_reg.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -17,18 +17,18 @@ extern "C" { #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; * Configures whether or not to enable the timer 0 alarm function. This bit will be - * automatically cleared once an alarm occurs.\\ - * 0: Disable \\ - * 1: Enable \\ + * automatically cleared once an alarm occurs. + * 0: Disable + * 1: Enable */ #define TIMG_T0_ALARM_EN (BIT(10)) #define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) #define TIMG_T0_ALARM_EN_V 0x00000001U #define TIMG_T0_ALARM_EN_S 10 /** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; - * Configures whether or not to reset the timer 0 's clock divider counter. \\ - * 0: No effect \\ - * 1: Reset \\ + * Configures whether or not to reset the timer 0 's clock divider counter. + * 0: No effect + * 1: Reset */ #define TIMG_T0_DIVCNT_RST (BIT(12)) #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) @@ -43,28 +43,27 @@ extern "C" { #define TIMG_T0_DIVIDER_S 13 /** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; * Configures whether or not to enable the timer 0 auto-reload function at the time of - * alarm. \\ - * 0: No effect \\ - * 1: Enable \\ + * alarm. + * 0: No effect + * 1: Enable */ #define TIMG_T0_AUTORELOAD (BIT(29)) #define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) #define TIMG_T0_AUTORELOAD_V 0x00000001U #define TIMG_T0_AUTORELOAD_S 29 /** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; - * Configures the counting direction of the timer 0 time-base counter. \\ - * 0: Decrement \\ - * 1: Increment \\ - * + * Configures the counting direction of the timer 0 time-base counter. + * 0: Decrement + * 1: Increment */ #define TIMG_T0_INCREASE (BIT(30)) #define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) #define TIMG_T0_INCREASE_V 0x00000001U #define TIMG_T0_INCREASE_S 30 /** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; - * Configures whether or not to enable the timer 0 time-base counter. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the timer 0 time-base counter. + * 0: Disable + * 1: Enable */ #define TIMG_T0_EN (BIT(31)) #define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) @@ -77,8 +76,8 @@ extern "C" { #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; * Represents the low 32 bits of the time-base counter of timer 0. Valid only after - * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: T0_clk \\ + * writing to TIMG_T0UPDATE_REG. + * Measurement unit: T0_clk */ #define TIMG_T0_LO 0xFFFFFFFFU #define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) @@ -91,8 +90,8 @@ extern "C" { #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; * Represents the high 22 bits of the time-base counter of timer 0. Valid only after - * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: T0_clk \\ + * writing to TIMG_T0UPDATE_REG. + * Measurement unit: T0_clk */ #define TIMG_T0_HI 0x003FFFFFU #define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) @@ -104,9 +103,9 @@ extern "C" { */ #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; - * Configures to latch the counter value. \\ - * 0: Latch \\ - * 1: Latch \\ + * Configures to latch the counter value. + * 0: Latch + * 1: Latch */ #define TIMG_T0_UPDATE (BIT(31)) #define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) @@ -119,8 +118,8 @@ extern "C" { #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; * Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid - * only when TIMG_T0_ALARM_EN is 1. \\ - * Measurement unit: T0_clk \\ + * only when TIMG_T0_ALARM_EN is 1. + * Measurement unit: T0_clk */ #define TIMG_T0_ALARM_LO 0xFFFFFFFFU #define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) @@ -133,8 +132,8 @@ extern "C" { #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; * Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid - * only when TIMG_T0_ALARM_EN is 1. \\ - * Measurement unit: T0_clk \\ + * only when TIMG_T0_ALARM_EN is 1. + * Measurement unit: T0_clk */ #define TIMG_T0_ALARM_HI 0x003FFFFFU #define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) @@ -147,8 +146,8 @@ extern "C" { #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; * Configures low 32 bits of the value that a reload will load onto timer 0 time-base - * counter. \\ - * Measurement unit: T0_clk \\ + * counter. + * Measurement unit: T0_clk */ #define TIMG_T0_LOAD_LO 0xFFFFFFFFU #define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) @@ -161,8 +160,8 @@ extern "C" { #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; * Configures high 22 bits of the value that a reload will load onto timer 0 time-base - * counter. \\ - * Measurement unit: T0_clk \\ + * counter. + * Measurement unit: T0_clk */ #define TIMG_T0_LOAD_HI 0x003FFFFFU #define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) @@ -188,9 +187,9 @@ extern "C" { #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write - * protection is disabled. \\ - * 0: Mask \\ - * 1: Unmask \\ + * protection is disabled. + * 0: Mask + * 1: Unmask */ #define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) #define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) @@ -198,19 +197,18 @@ extern "C" { #define TIMG_WDT_APPCPU_RESET_EN_S 12 /** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write - * protection is disabled. \\ - * 0: Mask \\ - * 1: Unmask \\ - * + * protection is disabled. + * 0: Mask + * 1: Unmask */ #define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) #define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) #define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U #define TIMG_WDT_PROCPU_RESET_EN_S 13 /** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; - * Configures whether to enable flash boot protection.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable flash boot protection. + * 0: Disable + * 1: Enable */ #define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) #define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) @@ -218,17 +216,17 @@ extern "C" { #define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 /** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; * Configures the system reset signal length. Valid only when write protection is - * disabled. \\ + * disabled. * Measurement unit: mwdt_clk * \begin{multicols}{2} - * 0: 8 \\ - * 1: 16 \\ - * 2: 24 \\ - * 3: 32 \\ - * 4: 40 \\ - * 5: 64 \\ - * 6: 128 \\ - * 7: 256 \\ + * 0: 8 + * 1: 16 + * 2: 24 + * 3: 32 + * 4: 40 + * 5: 64 + * 6: 128 + * 7: 256 * \end{multicols} */ #define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U @@ -237,17 +235,17 @@ extern "C" { #define TIMG_WDT_SYS_RESET_LENGTH_S 15 /** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; * Configures the CPU reset signal length. Valid only when write protection is - * disabled.\\ - * Measurement unit: mwdt_clk \\ + * disabled. + * Measurement unit: mwdt_clk * \begin{multicols}{2} - * 0: 8 \\ - * 1: 16 \\ - * 2: 24 \\ - * 3: 32 \\ - * 4: 40 \\ - * 5: 64 \\ - * 6: 128 \\ - * 7: 256 \\ + * 0: 8 + * 1: 16 + * 2: 24 + * 3: 32 + * 4: 40 + * 5: 64 + * 6: 128 + * 7: 256 * \end{multicols} */ #define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U @@ -255,9 +253,9 @@ extern "C" { #define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U #define TIMG_WDT_CPU_RESET_LENGTH_S 18 /** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; - * Configures to update the WDT configuration registers.\\ - * 0: No effect \\ - * 1: Update \\ + * Configures to update the WDT configuration registers. + * 0: No effect + * 1: Update */ #define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) #define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) @@ -289,11 +287,11 @@ extern "C" { #define TIMG_WDT_STG1_S 27 /** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; * Configures the timeout action of stage 0. Valid only when write protection is - * disabled. \\ - * 0: No effect \\ - * 1: Interrupt \\ - * 2: Reset CPU \\ - * 3: Reset system \\ + * disabled. + * 0: No effect + * 1: Interrupt + * 2: Reset CPU + * 3: Reset system */ #define TIMG_WDT_STG0 0x00000003U #define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) @@ -301,9 +299,9 @@ extern "C" { #define TIMG_WDT_STG0_S 29 /** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; * Configures whether or not to enable the MWDT. Valid only when write protection is - * disabled. \\ - * 0: Disable \\ - * 1: Enable \\ + * disabled. + * 0: Disable + * 1: Enable */ #define TIMG_WDT_EN (BIT(31)) #define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) @@ -315,9 +313,9 @@ extern "C" { */ #define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; - * Configures whether to reset WDT 's clock divider counter. \\ - * 0: No effect \\ - * 1: Reset \\ + * Configures whether to reset WDT 's clock divider counter. + * 0: No effect + * 1: Reset */ #define TIMG_WDT_DIVCNT_RST (BIT(0)) #define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) @@ -325,8 +323,8 @@ extern "C" { #define TIMG_WDT_DIVCNT_RST_S 0 /** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; * Configures MWDT clock prescaler value. Valid only when write protection is - * disabled. \\ - * MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. \\ + * disabled. + * MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. */ #define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU #define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) @@ -339,8 +337,7 @@ extern "C" { #define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; * Configures the stage 0 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ #define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU #define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) @@ -352,9 +349,8 @@ extern "C" { */ #define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; - * Configures the stage 1 timeout value. Valid only when write protection is - * disabled.\\ - * Measurement unit: mwdt_clk \\ + * Configures the stage 1 timeout value. Valid only when write protection is disabled. + * Measurement unit: mwdt_clk */ #define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU #define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) @@ -367,8 +363,7 @@ extern "C" { #define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Configures the stage 2 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ #define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU #define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) @@ -381,8 +376,7 @@ extern "C" { #define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Configures the stage 3 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ #define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU #define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) @@ -418,35 +412,35 @@ extern "C" { */ #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; - * Configures the frequency calculation mode. \\ - * 0: one-shot frequency calculation \\ - * 1: periodic frequency calculation \\ + * Configures the frequency calculation mode. + * 0: one-shot frequency calculation + * 1: periodic frequency calculation */ #define TIMG_RTC_CALI_START_CYCLING (BIT(12)) #define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) #define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U #define TIMG_RTC_CALI_START_CYCLING_S 12 /** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; - * Represents whether one-shot frequency calculation is done.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether one-shot frequency calculation is done. + * 0: Not done + * 1: Done */ #define TIMG_RTC_CALI_RDY (BIT(15)) #define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) #define TIMG_RTC_CALI_RDY_V 0x00000001U #define TIMG_RTC_CALI_RDY_S 15 /** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; - * Configures the time to calculate RTC slow clock's frequency. \\ - * Measurement unit: XTAL_CLK \\ + * Configures the time to calculate RTC slow clock's frequency. + * Measurement unit: XTAL_CLK */ #define TIMG_RTC_CALI_MAX 0x00007FFFU #define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) #define TIMG_RTC_CALI_MAX_V 0x00007FFFU #define TIMG_RTC_CALI_MAX_S 16 /** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; - * Configures whether to enable one-shot frequency calculation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable one-shot frequency calculation. + * 0: Disable + * 1: Enable */ #define TIMG_RTC_CALI_START (BIT(31)) #define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) @@ -458,9 +452,9 @@ extern "C" { */ #define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; - * Represents whether periodic frequency calculation is done. \\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether periodic frequency calculation is done. + * 0: Not done + * 1: Done */ #define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) #define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) @@ -556,17 +550,17 @@ extern "C" { */ #define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; - * Represents whether RTC frequency calculation is timeout. \\ - * 0: No timeout \\ - * 1: Timeout \\ + * Represents whether RTC frequency calculation is timeout. + * 0: No timeout + * 1: Timeout */ #define TIMG_RTC_CALI_TIMEOUT (BIT(0)) #define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) #define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U #define TIMG_RTC_CALI_TIMEOUT_S 0 /** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; - * Configures the cycles that reset frequency calculation timeout. \\ - * Measurement unit: XTAL_CLK \\ + * Configures the cycles that reset frequency calculation timeout. + * Measurement unit: XTAL_CLK */ #define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU #define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) @@ -574,8 +568,8 @@ extern "C" { #define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 /** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; * Configures the threshold value for the RTC frequency calculation timer. If the - * timer's value exceeds this threshold, a timeout is triggered.\\ - * Measurement unit: XTAL_CLK \\ + * timer's value exceeds this threshold, a timeout is triggered. + * Measurement unit: XTAL_CLK */ #define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU #define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) @@ -599,18 +593,18 @@ extern "C" { */ #define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; - * Configures whether to enable timer's ETM task and event. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable timer's ETM task and event. + * 0: Disable + * 1: Enable */ #define TIMG_ETM_EN (BIT(28)) #define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) #define TIMG_ETM_EN_V 0x00000001U #define TIMG_ETM_EN_S 28 /** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether to enable gate clock signal for registers. \\ - * 0: Force clock on for registers \\ - * 1: Support clock only when registers are read or written to by software. \\ + * Configures whether to enable gate clock signal for registers. + * 0: Force clock on for registers + * 1: Support clock only when registers are read or written to by software. */ #define TIMG_CLK_EN (BIT(31)) #define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/timer_group_struct.h b/components/soc/esp32c5/register/soc/timer_group_struct.h index 90f04512bc..663f407d2c 100644 --- a/components/soc/esp32c5/register/soc/timer_group_struct.h +++ b/components/soc/esp32c5/register/soc/timer_group_struct.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,173 +10,173 @@ extern "C" { #endif -/** Group: Timer Control and configuration registers */ +/** Group: T0 Control and configuration registers */ /** Type of txconfig register - * Timer x configuration register + * Timer 0 configuration register */ typedef union { struct { - uint32_t reserved_0: 10; + uint32_t reserved_0:10; /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; - * Configures whether or not to enable the timer alarm function. This bit will be - * automatically cleared once an alarm occurs.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the timer 0 alarm function. This bit will be + * automatically cleared once an alarm occurs. + * 0: Disable + * 1: Enable */ - uint32_t tx_alarm_en: 1; - uint32_t reserved_11: 1; + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; - * Configures whether or not to reset the timer's clock divider counter. \\ - * 0: No effect \\ - * 1: Reset \\ + * Configures whether or not to reset the timer 0 's clock divider counter. + * 0: No effect + * 1: Reset */ - uint32_t tx_divcnt_rst: 1; + uint32_t tx_divcnt_rst:1; /** tx_divider : R/W; bitpos: [28:13]; default: 1; - * Represents the timer clock (Tx_clk) prescaler value. + * Represents the timer 0 clock (T0_clk) prescaler value. */ - uint32_t tx_divider: 16; + uint32_t tx_divider:16; /** tx_autoreload : R/W; bitpos: [29]; default: 1; - * Configures whether or not to enable the timer auto-reload function at the time of - * alarm. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures whether or not to enable the timer 0 auto-reload function at the time of + * alarm. + * 0: No effect + * 1: Enable */ - uint32_t tx_autoreload: 1; + uint32_t tx_autoreload:1; /** tx_increase : R/W; bitpos: [30]; default: 1; - * Configures the counting direction of the timer time-base counter. \\ - * 0: Decrement \\ - * 1: Increment \\ - * + * Configures the counting direction of the timer 0 time-base counter. + * 0: Decrement + * 1: Increment */ - uint32_t tx_increase: 1; + uint32_t tx_increase:1; /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; - * Configures whether or not to enable the timer time-base counter. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the timer 0 time-base counter. + * 0: Disable + * 1: Enable */ - uint32_t tx_en: 1; + uint32_t tx_en:1; }; uint32_t val; } timg_txconfig_reg_t; /** Type of txlo register - * Timer x current value, low 32 bits + * Timer 0 current value, low 32 bits */ typedef union { struct { /** tx_lo : RO; bitpos: [31:0]; default: 0; - * Represents the low 32 bits of the time-base counter of timer x. Valid only after - * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: Tx_clk \\ + * Represents the low 32 bits of the time-base counter of timer 0. Valid only after + * writing to TIMG_T0UPDATE_REG. + * Measurement unit: T0_clk */ - uint32_t tx_lo: 32; + uint32_t tx_lo:32; }; uint32_t val; } timg_txlo_reg_t; /** Type of txhi register - * Timer x current value, high 22 bits + * Timer 0 current value, high 22 bits */ typedef union { struct { /** tx_hi : RO; bitpos: [21:0]; default: 0; - * Represents the high 22 bits of the time-base counter of timer x. Valid only after - * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: Tx_clk \\ + * Represents the high 22 bits of the time-base counter of timer 0. Valid only after + * writing to TIMG_T0UPDATE_REG. + * Measurement unit: T0_clk */ - uint32_t tx_hi: 22; - uint32_t reserved_22: 10; + uint32_t tx_hi:22; + uint32_t reserved_22:10; }; uint32_t val; } timg_txhi_reg_t; /** Type of txupdate register - * Write to copy current timer value to TIMGn_TxLO_REG or TIMGn_TxHI_REG + * Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG */ typedef union { struct { - uint32_t reserved_0: 31; + uint32_t reserved_0:31; /** tx_update : R/W/SC; bitpos: [31]; default: 0; - * Configures to latch the counter value. \\ - * 0: Latch \\ - * 1: Latch \\ + * Configures to latch the counter value. + * 0: Latch + * 1: Latch */ - uint32_t tx_update: 1; + uint32_t tx_update:1; }; uint32_t val; } timg_txupdate_reg_t; /** Type of txalarmlo register - * Timer x alarm value, low 32 bits + * Timer 0 alarm value, low 32 bits */ typedef union { struct { /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; - * Configures the low 32 bits of timer x alarm trigger time-base counter value. Valid - * only when TIMG_Tx_ALARM_EN is 1. \\ - * Measurement unit: Tx_clk \\ + * Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid + * only when TIMG_T0_ALARM_EN is 1. + * Measurement unit: T0_clk */ - uint32_t tx_alarm_lo: 32; + uint32_t tx_alarm_lo:32; }; uint32_t val; } timg_txalarmlo_reg_t; /** Type of txalarmhi register - * Timer x alarm value, high bits + * Timer 0 alarm value, high bits */ typedef union { struct { /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; - * Configures the high 22 bits of timer x alarm trigger time-base counter value. Valid - * only when TIMG_Tx_ALARM_EN is 1. \\ - * Measurement unit: Tx_clk \\ + * Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid + * only when TIMG_T0_ALARM_EN is 1. + * Measurement unit: T0_clk */ - uint32_t tx_alarm_hi: 22; - uint32_t reserved_22: 10; + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; }; uint32_t val; } timg_txalarmhi_reg_t; /** Type of txloadlo register - * Timer x reload value, low 32 bits + * Timer 0 reload value, low 32 bits */ typedef union { struct { /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; - * Configures low 32 bits of the value that a reload will load onto timer x time-base - * counter. \\ - * Measurement unit: Tx_clk \\ + * Configures low 32 bits of the value that a reload will load onto timer 0 time-base + * counter. + * Measurement unit: T0_clk */ - uint32_t tx_load_lo: 32; + uint32_t tx_load_lo:32; }; uint32_t val; } timg_txloadlo_reg_t; /** Type of txloadhi register - * Timer x reload value, high 22 bits + * Timer 0 reload value, high 22 bits */ typedef union { struct { /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; - * Configures high 22 bits of the value that a reload will load onto timer x time-base - * counter. \\ - * Measurement unit: Tx_clk \\ + * Configures high 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + * Measurement unit: T0_clk */ - uint32_t tx_load_hi: 22; - uint32_t reserved_22: 10; + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; }; uint32_t val; } timg_txloadhi_reg_t; /** Type of txload register - * Write to reload timer from TIMG_TxLOADLO_REG or TIMG_TxLOADHI_REG + * Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG */ typedef union { struct { /** tx_load : WT; bitpos: [31:0]; default: 0; - * Write any value to trigger a timer x time-base counter reload. + * Write any value to trigger a timer 0 time-base counter reload. + * */ - uint32_t tx_load: 32; + uint32_t tx_load:32; }; uint32_t val; } timg_txload_reg_t; @@ -188,98 +188,97 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0: 12; + uint32_t reserved_0:12; /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write - * protection is disabled. \\ - * 0: Mask \\ - * 1: Unmask \\ + * protection is disabled. + * 0: Mask + * 1: Unmask */ - uint32_t wdt_appcpu_reset_en: 1; + uint32_t wdt_appcpu_reset_en:1; /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write - * protection is disabled. \\ - * 0: Mask \\ - * 1: Unmask \\ - * + * protection is disabled. + * 0: Mask + * 1: Unmask */ - uint32_t wdt_procpu_reset_en: 1; + uint32_t wdt_procpu_reset_en:1; /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; - * Configures whether to enable flash boot protection.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable flash boot protection. + * 0: Disable + * 1: Enable */ - uint32_t wdt_flashboot_mod_en: 1; + uint32_t wdt_flashboot_mod_en:1; /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; * Configures the system reset signal length. Valid only when write protection is - * disabled. \\ + * disabled. * Measurement unit: mwdt_clk * \begin{multicols}{2} - * 0: 8 \\ - * 1: 16 \\ - * 2: 24 \\ - * 3: 32 \\ - * 4: 40 \\ - * 5: 64 \\ - * 6: 128 \\ - * 7: 256 \\ + * 0: 8 + * 1: 16 + * 2: 24 + * 3: 32 + * 4: 40 + * 5: 64 + * 6: 128 + * 7: 256 * \end{multicols} */ - uint32_t wdt_sys_reset_length: 3; + uint32_t wdt_sys_reset_length:3; /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; * Configures the CPU reset signal length. Valid only when write protection is - * disabled.\\ - * Measurement unit: mwdt_clk \\ + * disabled. + * Measurement unit: mwdt_clk * \begin{multicols}{2} - * 0: 8 \\ - * 1: 16 \\ - * 2: 24 \\ - * 3: 32 \\ - * 4: 40 \\ - * 5: 64 \\ - * 6: 128 \\ - * 7: 256 \\ + * 0: 8 + * 1: 16 + * 2: 24 + * 3: 32 + * 4: 40 + * 5: 64 + * 6: 128 + * 7: 256 * \end{multicols} */ - uint32_t wdt_cpu_reset_length: 3; - uint32_t reserved_21: 1; + uint32_t wdt_cpu_reset_length:3; + uint32_t reserved_21:1; /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; - * Configures to update the WDT configuration registers.\\ - * 0: No effect \\ - * 1: Update \\ + * Configures to update the WDT configuration registers. + * 0: No effect + * 1: Update */ - uint32_t wdt_conf_update_en: 1; + uint32_t wdt_conf_update_en:1; /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; * Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg3: 2; + uint32_t wdt_stg3:2; /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; * Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg2: 2; + uint32_t wdt_stg2:2; /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; * Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg1: 2; + uint32_t wdt_stg1:2; /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; * Configures the timeout action of stage 0. Valid only when write protection is - * disabled. \\ - * 0: No effect \\ - * 1: Interrupt \\ - * 2: Reset CPU \\ - * 3: Reset system \\ + * disabled. + * 0: No effect + * 1: Interrupt + * 2: Reset CPU + * 3: Reset system */ - uint32_t wdt_stg0: 2; + uint32_t wdt_stg0:2; /** wdt_en : R/W; bitpos: [31]; default: 0; * Configures whether or not to enable the MWDT. Valid only when write protection is - * disabled. \\ - * 0: Disable \\ - * 1: Enable \\ + * disabled. + * 0: Disable + * 1: Enable */ - uint32_t wdt_en: 1; + uint32_t wdt_en:1; }; uint32_t val; } timg_wdtconfig0_reg_t; @@ -290,18 +289,18 @@ typedef union { typedef union { struct { /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; - * Configures whether to reset WDT 's clock divider counter. \\ - * 0: No effect \\ - * 1: Reset \\ + * Configures whether to reset WDT 's clock divider counter. + * 0: No effect + * 1: Reset */ - uint32_t wdt_divcnt_rst: 1; - uint32_t reserved_1: 15; + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; * Configures MWDT clock prescaler value. Valid only when write protection is - * disabled. \\ - * MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. \\ + * disabled. + * MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. */ - uint32_t wdt_clk_prescale: 16; + uint32_t wdt_clk_prescale:16; }; uint32_t val; } timg_wdtconfig1_reg_t; @@ -313,10 +312,9 @@ typedef union { struct { /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; * Configures the stage 0 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ - uint32_t wdt_stg0_hold: 32; + uint32_t wdt_stg0_hold:32; }; uint32_t val; } timg_wdtconfig2_reg_t; @@ -327,11 +325,10 @@ typedef union { typedef union { struct { /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; - * Configures the stage 1 timeout value. Valid only when write protection is - * disabled.\\ - * Measurement unit: mwdt_clk \\ + * Configures the stage 1 timeout value. Valid only when write protection is disabled. + * Measurement unit: mwdt_clk */ - uint32_t wdt_stg1_hold: 32; + uint32_t wdt_stg1_hold:32; }; uint32_t val; } timg_wdtconfig3_reg_t; @@ -343,10 +340,9 @@ typedef union { struct { /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; * Configures the stage 2 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ - uint32_t wdt_stg2_hold: 32; + uint32_t wdt_stg2_hold:32; }; uint32_t val; } timg_wdtconfig4_reg_t; @@ -358,10 +354,9 @@ typedef union { struct { /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; * Configures the stage 3 timeout value. Valid only when write protection is disabled. - * \\ - * Measurement unit: mwdt_clk \\ + * Measurement unit: mwdt_clk */ - uint32_t wdt_stg3_hold: 32; + uint32_t wdt_stg3_hold:32; }; uint32_t val; } timg_wdtconfig5_reg_t; @@ -374,7 +369,7 @@ typedef union { /** wdt_feed : WT; bitpos: [31:0]; default: 0; * Write any value to feed the MWDT. Valid only when write protection is disabled. */ - uint32_t wdt_feed: 32; + uint32_t wdt_feed:32; }; uint32_t val; } timg_wdtfeed_reg_t; @@ -387,7 +382,7 @@ typedef union { /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; * Configures a different value than its reset value to enable write protection. */ - uint32_t wdt_wkey: 32; + uint32_t wdt_wkey:32; }; uint32_t val; } timg_wdtwprotect_reg_t; @@ -399,31 +394,31 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0: 12; + uint32_t reserved_0:12; /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; - * Configures the frequency calculation mode. \\ - * 0: one-shot frequency calculation \\ - * 1: periodic frequency calculation \\ + * Configures the frequency calculation mode. + * 0: one-shot frequency calculation + * 1: periodic frequency calculation */ - uint32_t rtc_cali_start_cycling: 1; - uint32_t reserved_13: 2; + uint32_t rtc_cali_start_cycling:1; + uint32_t reserved_13:2; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; - * Represents whether one-shot frequency calculation is done.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether one-shot frequency calculation is done. + * 0: Not done + * 1: Done */ - uint32_t rtc_cali_rdy: 1; + uint32_t rtc_cali_rdy:1; /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; - * Configures the time to calculate RTC slow clock's frequency. \\ - * Measurement unit: XTAL_CLK \\ + * Configures the time to calculate RTC slow clock's frequency. + * Measurement unit: XTAL_CLK */ - uint32_t rtc_cali_max: 15; + uint32_t rtc_cali_max:15; /** rtc_cali_start : R/W; bitpos: [31]; default: 0; - * Configures whether to enable one-shot frequency calculation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable one-shot frequency calculation. + * 0: Disable + * 1: Enable */ - uint32_t rtc_cali_start: 1; + uint32_t rtc_cali_start:1; }; uint32_t val; } timg_rtccalicfg_reg_t; @@ -434,17 +429,17 @@ typedef union { typedef union { struct { /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; - * Represents whether periodic frequency calculation is done. \\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether periodic frequency calculation is done. + * 0: Not done + * 1: Done */ - uint32_t rtc_cali_cycling_data_vld: 1; - uint32_t reserved_1: 6; + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; * Represents the value countered by XTAL_CLK when one-shot or periodic frequency * calculation is done. It is used to calculate RTC slow clock's frequency. */ - uint32_t rtc_cali_value: 25; + uint32_t rtc_cali_value:25; }; uint32_t val; } timg_rtccalicfg1_reg_t; @@ -455,23 +450,23 @@ typedef union { typedef union { struct { /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; - * Represents whether RTC frequency calculation is timeout. \\ - * 0: No timeout \\ - * 1: Timeout \\ + * Represents whether RTC frequency calculation is timeout. + * 0: No timeout + * 1: Timeout */ - uint32_t rtc_cali_timeout: 1; - uint32_t reserved_1: 2; + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; - * Configures the cycles that reset frequency calculation timeout. \\ - * Measurement unit: XTAL_CLK \\ + * Configures the cycles that reset frequency calculation timeout. + * Measurement unit: XTAL_CLK */ - uint32_t rtc_cali_timeout_rst_cnt: 4; + uint32_t rtc_cali_timeout_rst_cnt:4; /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; * Configures the threshold value for the RTC frequency calculation timer. If the - * timer's value exceeds this threshold, a timeout is triggered.\\ - * Measurement unit: XTAL_CLK \\ + * timer's value exceeds this threshold, a timeout is triggered. + * Measurement unit: XTAL_CLK */ - uint32_t rtc_cali_timeout_thres: 25; + uint32_t rtc_cali_timeout_thres:25; }; uint32_t val; } timg_rtccalicfg2_reg_t; @@ -486,13 +481,13 @@ typedef union { /** t0_int_ena : R/W; bitpos: [0]; default: 0; * Write 1 to enable the TIMG_T0_INT interrupt. */ - uint32_t t0_int_ena: 1; - uint32_t reserved_1: 1; + uint32_t t0_int_ena:1; + uint32_t reserved_1:1; /** wdt_int_ena : R/W; bitpos: [2]; default: 0; * Write 1 to enable the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_ena: 1; - uint32_t reserved_3: 29; + uint32_t wdt_int_ena:1; + uint32_t reserved_3:29; }; uint32_t val; } timg_int_ena_timers_reg_t; @@ -505,13 +500,13 @@ typedef union { /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status bit of the TIMG_T0_INT interrupt. */ - uint32_t t0_int_raw: 1; - uint32_t reserved_1: 1; + uint32_t t0_int_raw:1; + uint32_t reserved_1:1; /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; * The raw interrupt status bit of the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_raw: 1; - uint32_t reserved_3: 29; + uint32_t wdt_int_raw:1; + uint32_t reserved_3:29; }; uint32_t val; } timg_int_raw_timers_reg_t; @@ -524,13 +519,13 @@ typedef union { /** t0_int_st : RO; bitpos: [0]; default: 0; * The masked interrupt status bit of the TIMG_T0_INT interrupt. */ - uint32_t t0_int_st: 1; - uint32_t reserved_1: 1; + uint32_t t0_int_st:1; + uint32_t reserved_1:1; /** wdt_int_st : RO; bitpos: [2]; default: 0; * The masked interrupt status bit of the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_st: 1; - uint32_t reserved_3: 29; + uint32_t wdt_int_st:1; + uint32_t reserved_3:29; }; uint32_t val; } timg_int_st_timers_reg_t; @@ -543,13 +538,13 @@ typedef union { /** t0_int_clr : WT; bitpos: [0]; default: 0; * Write 1 to clear the TIMG_T0_INT interrupt. */ - uint32_t t0_int_clr: 1; - uint32_t reserved_1: 1; + uint32_t t0_int_clr:1; + uint32_t reserved_1:1; /** wdt_int_clr : WT; bitpos: [2]; default: 0; * Write 1 to clear the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_clr: 1; - uint32_t reserved_3: 29; + uint32_t wdt_int_clr:1; + uint32_t reserved_3:29; }; uint32_t val; } timg_int_clr_timers_reg_t; @@ -564,8 +559,8 @@ typedef union { /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; * Version control register */ - uint32_t ntimgs_date: 28; - uint32_t reserved_28: 4; + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; }; uint32_t val; } timg_ntimers_date_reg_t; @@ -577,20 +572,20 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0: 28; + uint32_t reserved_0:28; /** etm_en : R/W; bitpos: [28]; default: 1; - * Configures whether to enable timer's ETM task and event. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether to enable timer's ETM task and event. + * 0: Disable + * 1: Enable */ - uint32_t etm_en: 1; - uint32_t reserved_29: 2; + uint32_t etm_en:1; + uint32_t reserved_29:2; /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether to enable gate clock signal for registers. \\ - * 0: Force clock on for registers \\ - * 1: Support clock only when registers are read or written to by software. \\ + * Configures whether to enable gate clock signal for registers. + * 0: Force clock on for registers + * 1: Support clock only when registers are read or written to by software. */ - uint32_t clk_en: 1; + uint32_t clk_en:1; }; uint32_t val; } timg_regclk_reg_t; diff --git a/components/soc/esp32c5/register/soc/trace_reg.h b/components/soc/esp32c5/register/soc/trace_reg.h index 785965af2c..49b798a7be 100644 --- a/components/soc/esp32c5/register/soc/trace_reg.h +++ b/components/soc/esp32c5/register/soc/trace_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,9 +54,9 @@ extern "C" { /** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; * Configures whether to update the value of * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to - * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\ - * 0: Not update\\ - * 1: Update\\ + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + * 0: Not update + * 1: Update */ #define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) #define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) @@ -68,15 +68,20 @@ extern "C" { */ #define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) /** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; - * Represent whether the FIFO is empty. \\1: Empty \\0: Not empty + * Represent whether the FIFO is empty. + * 1: Empty + * 0: Not empty */ #define TRACE_FIFO_EMPTY (BIT(0)) #define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) #define TRACE_FIFO_EMPTY_V 0x00000001U #define TRACE_FIFO_EMPTY_S 0 /** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; - * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait - * state because hart is halted or in reset \\3: Lost state\\ + * Represent the state of the encoder: + * 0: Idle state + * 1: Working state + * 2: Wait state because hart is halted or in reset + * 3: Lost state */ #define TRACE_WORK_STATUS 0x00000003U #define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) @@ -145,29 +150,36 @@ extern "C" { */ #define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) /** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; - * Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\ + * Configure whether to enable the encoder. + * 0: Invalid + * 1: Enable */ #define TRACE_TRIGGER_ON (BIT(0)) #define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) #define TRACE_TRIGGER_ON_V 0x00000001U #define TRACE_TRIGGER_ON_S 0 /** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; - * Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\ + * Configure whether to disable the encoder. + * 0: Invalid + * 1: Disable */ #define TRACE_TRIGGER_OFF (BIT(1)) #define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) #define TRACE_TRIGGER_OFF_V 0x00000001U #define TRACE_TRIGGER_OFF_S 1 /** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; - * Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\ + * Configure the memory writing mode. + * 0: Non-loop mode. + * 1: Loop mode */ #define TRACE_MEM_LOOP (BIT(2)) #define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) #define TRACE_MEM_LOOP_V 0x00000001U #define TRACE_MEM_LOOP_S 2 /** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; - * Configure whether or not enable automatic restart function for the encoder.\\0: - * Disable\\1: Enable\\ + * Configure whether or not enable automatic restart function for the encoder. + * 0: Disable + * 1: Enable */ #define TRACE_RESTART_ENA (BIT(3)) #define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) @@ -179,7 +191,9 @@ extern "C" { */ #define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) /** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; - * Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\ + * Configure whether to enable the trigger signal. + * 0: Disable + * 1:enable */ #define TRACE_DM_TRIGGER_ENA (BIT(0)) #define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) @@ -188,28 +202,36 @@ extern "C" { /** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; * Configure whether to reset, when enabled, if cpu have reset, the encoder will * output a packet to report the address of the last instruction, and upon reset - * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ + * deassertion, the encoder start again. + * 0: Disable + * 0: Enable */ #define TRACE_RESET_ENA (BIT(1)) #define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) #define TRACE_RESET_ENA_V 0x00000001U #define TRACE_RESET_ENA_S 1 /** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; - * Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\ + * Configure whether to enable the halt signal. + * 1: Disable + * 1: Enable */ #define TRACE_HALT_ENA (BIT(2)) #define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) #define TRACE_HALT_ENA_V 0x00000001U #define TRACE_HALT_ENA_S 2 /** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; - * Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\ + * Configure whether to enable the stall signal. + * 0: Disable. + * 1: Enable */ #define TRACE_STALL_ENA (BIT(3)) #define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) #define TRACE_STALL_ENA_V 0x00000001U #define TRACE_STALL_ENA_S 3 /** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; - * Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\ + * Configure the address mode. + * 0: Delta address mode. + * 1: Full address mode. */ #define TRACE_FULL_ADDRESS (BIT(4)) #define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) @@ -217,8 +239,9 @@ extern "C" { #define TRACE_FULL_ADDRESS_S 4 /** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; * Configure whether or not enable implicit exception mode. When enabled,, do not sent - * exception address, only exception cause in exception packets.\\1: enabled\\0: - * disabled\\ + * exception address, only exception cause in exception packets. + * 1: enabled + * 0: disabled */ #define TRACE_IMPLICIT_EXCEPT (BIT(5)) #define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) @@ -230,23 +253,27 @@ extern "C" { */ #define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) /** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; - * Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable + * Configure whether to enable filtering. + * 0: Disable, always match. + * 1: Enable */ #define TRACE_FILTER_EN (BIT(0)) #define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) #define TRACE_FILTER_EN_V 0x00000001U #define TRACE_FILTER_EN_S 0 /** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; - * Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable, - * the comparator must be high in order for the filter to match + * Configure whether to enable the comparator match mode. + * 0: Disable + * 1: Enable, the comparator must be high in order for the filter to match */ #define TRACE_MATCH_COMP (BIT(1)) #define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) #define TRACE_MATCH_COMP_V 0x00000001U #define TRACE_MATCH_COMP_S 1 /** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; - * Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable, - * match privilege levels specified by + * Configure whether to enable the privilege match mode. + * 0: Disable + * 1: Enable, match privilege levels specified by * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. */ #define TRACE_MATCH_PRIVILEGE (BIT(2)) @@ -254,8 +281,9 @@ extern "C" { #define TRACE_MATCH_PRIVILEGE_V 0x00000001U #define TRACE_MATCH_PRIVILEGE_S 2 /** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; - * Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start - * matching from exception cause codes specified by + * Configure whether to enable ecause match mode. + * 0: Disable + * 1: Enable, start matching from exception cause codes specified by * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop * matching upon return from the 1st matching exception. */ @@ -264,8 +292,9 @@ extern "C" { #define TRACE_MATCH_ECAUSE_V 0x00000001U #define TRACE_MATCH_ECAUSE_S 3 /** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; - * Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable, - * start matching from a trap with the interrupt level codes specified by + * Configure whether to enable the interrupt match mode. + * 0: Disable + * 1: Enable, start matching from a trap with the interrupt level codes specified by * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and * stop matching upon return from the 1st matching trap. */ @@ -280,8 +309,9 @@ extern "C" { #define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) /** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; * Configures the privilege level for matching. Valid only when - * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User - * mode. \\1: Machine mode + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. + * 0: User mode. + * 1: Machine mode */ #define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) #define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) @@ -289,8 +319,9 @@ extern "C" { #define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 /** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; * Configures the interrupt level for match. Valid only when when - * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0: - * itype=2. \\0: itype=2. + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. + * 0: itype=2. + * 0: itype=2. */ #define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) #define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) @@ -309,16 +340,23 @@ extern "C" { */ #define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) /** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; - * Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\ + * Configures the input of the primary comparator for matching: + * 0: iaddr + * 1: tval */ #define TRACE_P_INPUT (BIT(0)) #define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) #define TRACE_P_INPUT_V 0x00000001U #define TRACE_P_INPUT_S 0 /** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; - * Configures the function for the primary comparator. \\0: Equal, \\1: Not equal, - * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or - * equal, \\Other: Always match + * Configures the function for the primary comparator. + * 0: Equal, + * 1: Not equal, + * 2: Less than, + * 3: Less than or equal, + * 4: Greater than, + * 5: Greater than or equal, + * Other: Always match */ #define TRACE_P_FUNCTION 0x00000007U #define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) @@ -326,24 +364,32 @@ extern "C" { #define TRACE_P_FUNCTION_S 2 /** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; * Configure whether to explicitly report an instruction address matched against the - * primary comparator. \\0:Not report \\1:Report + * primary comparator. + * 0:Not report + * 1:Report */ #define TRACE_P_NOTIFY (BIT(5)) #define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) #define TRACE_P_NOTIFY_V 0x00000001U #define TRACE_P_NOTIFY_S 5 /** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; - * Configures the input of the secondary comparator for matching: \\0: iaddr \\1: - * tval\\ + * Configures the input of the secondary comparator for matching: + * 0: iaddr + * 1: tval */ #define TRACE_S_INPUT (BIT(8)) #define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) #define TRACE_S_INPUT_V 0x00000001U #define TRACE_S_INPUT_S 8 /** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; - * Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal, - * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or - * equal, \\Other: Always match + * Configures the function for the secondary comparator. + * 0: Equal, + * 1: Not equal, + * 2: Less than, + * 3: Less than or equal, + * 4: Greater than, + * 5: Greater than or equal, + * Other: Always match */ #define TRACE_S_FUNCTION 0x00000007U #define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) @@ -358,10 +404,12 @@ extern "C" { #define TRACE_S_NOTIFY_V 0x00000001U #define TRACE_S_NOTIFY_S 13 /** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; - * Configures the comparator match mode: \\0: Only the primary comparator matches \\1: - * Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or - * secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary - * comparator matches and stop filtering when the secondary comparator matches\\ + * Configures the comparator match mode: + * 0: Only the primary comparator matches + * 1: Both primary and secondary comparator matches(P\&\&S) + * 2:Neither primary or secondary comparator matches !(P\&\&S) + * 3: Start filtering when the primary comparator matches and stop filtering when the + * secondary comparator matches */ #define TRACE_MATCH_MODE 0x00000003U #define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) @@ -404,9 +452,11 @@ extern "C" { #define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU #define TRACE_RESYNC_PROLONGED_S 0 /** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; - * Configures the synchronization mode: \\0: Disable the synchronization counter \\1: - * Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter - * counts by cycle\\ + * Configures the synchronization mode: + * 0: Disable the synchronization counter + * 1: Invalid + * 2: Synchronization counter counts by packet + * 3: Synchronization counter counts by cycle */ #define TRACE_RESYNC_MODE 0x00000003U #define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) @@ -418,8 +468,12 @@ extern "C" { */ #define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; - * Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4 - * \\4:INCR8 \\Others:Invalid + * Configures the AHB burst mode. + * 0: SINGLE + * 1: INCR(length not defined) + * 2:INCR4 + * 4:INCR8 + * Others:Invalid */ #define TRACE_HBURST 0x00000007U #define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) @@ -438,9 +492,10 @@ extern "C" { */ #define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures register clock gating. \\0: Support clock only when the application - * writes registers to save power. \\1:Always force the clock on for registers \\ This - * bit doesn't affect register access. + * Configures register clock gating. + * 0: Support clock only when the application writes registers to save power. + * 1:Always force the clock on for registers + * This bit doesn't affect register access. */ #define TRACE_CLK_EN (BIT(0)) #define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/trace_struct.h b/components/soc/esp32c5/register/soc/trace_struct.h index e3de8f54ab..49ebdb799b 100644 --- a/components/soc/esp32c5/register/soc/trace_struct.h +++ b/components/soc/esp32c5/register/soc/trace_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -58,9 +58,9 @@ typedef union { /** mem_current_addr_update : WT; bitpos: [0]; default: 0; * Configures whether to update the value of * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to - * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\ - * 0: Not update\\ - * 1: Update\\ + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + * 0: Not update + * 1: Update */ uint32_t mem_current_addr_update:1; uint32_t reserved_1:31; @@ -76,12 +76,17 @@ typedef union { typedef union { struct { /** fifo_empty : RO; bitpos: [0]; default: 1; - * Represent whether the FIFO is empty. \\1: Empty \\0: Not empty + * Represent whether the FIFO is empty. + * 1: Empty + * 0: Not empty */ uint32_t fifo_empty:1; /** work_status : RO; bitpos: [2:1]; default: 0; - * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait - * state because hart is halted or in reset \\3: Lost state\\ + * Represent the state of the encoder: + * 0: Idle state + * 1: Working state + * 2: Wait state because hart is halted or in reset + * 3: Lost state */ uint32_t work_status:2; uint32_t reserved_3:29; @@ -153,20 +158,27 @@ typedef union { typedef union { struct { /** trigger_on : WT; bitpos: [0]; default: 0; - * Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\ + * Configure whether to enable the encoder. + * 0: Invalid + * 1: Enable */ uint32_t trigger_on:1; /** trigger_off : WT; bitpos: [1]; default: 0; - * Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\ + * Configure whether to disable the encoder. + * 0: Invalid + * 1: Disable */ uint32_t trigger_off:1; /** mem_loop : R/W; bitpos: [2]; default: 1; - * Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\ + * Configure the memory writing mode. + * 0: Non-loop mode. + * 1: Loop mode */ uint32_t mem_loop:1; /** restart_ena : R/W; bitpos: [3]; default: 1; - * Configure whether or not enable automatic restart function for the encoder.\\0: - * Disable\\1: Enable\\ + * Configure whether or not enable automatic restart function for the encoder. + * 0: Disable + * 1: Enable */ uint32_t restart_ena:1; uint32_t reserved_4:28; @@ -180,31 +192,42 @@ typedef union { typedef union { struct { /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; - * Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\ + * Configure whether to enable the trigger signal. + * 0: Disable + * 1:enable */ uint32_t dm_trigger_ena:1; /** reset_ena : R/W; bitpos: [1]; default: 0; * Configure whether to reset, when enabled, if cpu have reset, the encoder will * output a packet to report the address of the last instruction, and upon reset - * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ + * deassertion, the encoder start again. + * 0: Disable + * 0: Enable */ uint32_t reset_ena:1; /** halt_ena : R/W; bitpos: [2]; default: 0; - * Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\ + * Configure whether to enable the halt signal. + * 1: Disable + * 1: Enable */ uint32_t halt_ena:1; /** stall_ena : R/W; bitpos: [3]; default: 0; - * Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\ + * Configure whether to enable the stall signal. + * 0: Disable. + * 1: Enable */ uint32_t stall_ena:1; /** full_address : R/W; bitpos: [4]; default: 0; - * Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\ + * Configure the address mode. + * 0: Delta address mode. + * 1: Full address mode. */ uint32_t full_address:1; /** implicit_except : R/W; bitpos: [5]; default: 0; * Configure whether or not enable implicit exception mode. When enabled,, do not sent - * exception address, only exception cause in exception packets.\\1: enabled\\0: - * disabled\\ + * exception address, only exception cause in exception packets. + * 1: enabled + * 0: disabled */ uint32_t implicit_except:1; uint32_t reserved_6:26; @@ -218,30 +241,36 @@ typedef union { typedef union { struct { /** filter_en : R/W; bitpos: [0]; default: 0; - * Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable + * Configure whether to enable filtering. + * 0: Disable, always match. + * 1: Enable */ uint32_t filter_en:1; /** match_comp : R/W; bitpos: [1]; default: 0; - * Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable, - * the comparator must be high in order for the filter to match + * Configure whether to enable the comparator match mode. + * 0: Disable + * 1: Enable, the comparator must be high in order for the filter to match */ uint32_t match_comp:1; /** match_privilege : R/W; bitpos: [2]; default: 0; - * Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable, - * match privilege levels specified by + * Configure whether to enable the privilege match mode. + * 0: Disable + * 1: Enable, match privilege levels specified by * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. */ uint32_t match_privilege:1; /** match_ecause : R/W; bitpos: [3]; default: 0; - * Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start - * matching from exception cause codes specified by + * Configure whether to enable ecause match mode. + * 0: Disable + * 1: Enable, start matching from exception cause codes specified by * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop * matching upon return from the 1st matching exception. */ uint32_t match_ecause:1; /** match_interrupt : R/W; bitpos: [4]; default: 0; - * Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable, - * start matching from a trap with the interrupt level codes specified by + * Configure whether to enable the interrupt match mode. + * 0: Disable + * 1: Enable, start matching from a trap with the interrupt level codes specified by * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and * stop matching upon return from the 1st matching trap. */ @@ -258,14 +287,16 @@ typedef union { struct { /** match_choice_privilege : R/W; bitpos: [0]; default: 0; * Configures the privilege level for matching. Valid only when - * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User - * mode. \\1: Machine mode + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. + * 0: User mode. + * 1: Machine mode */ uint32_t match_choice_privilege:1; /** match_value_interrupt : R/W; bitpos: [1]; default: 0; * Configures the interrupt level for match. Valid only when when - * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0: - * itype=2. \\0: itype=2. + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. + * 0: itype=2. + * 0: itype=2. */ uint32_t match_value_interrupt:1; /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; @@ -283,32 +314,47 @@ typedef union { typedef union { struct { /** p_input : R/W; bitpos: [0]; default: 0; - * Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\ + * Configures the input of the primary comparator for matching: + * 0: iaddr + * 1: tval */ uint32_t p_input:1; uint32_t reserved_1:1; /** p_function : R/W; bitpos: [4:2]; default: 0; - * Configures the function for the primary comparator. \\0: Equal, \\1: Not equal, - * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or - * equal, \\Other: Always match + * Configures the function for the primary comparator. + * 0: Equal, + * 1: Not equal, + * 2: Less than, + * 3: Less than or equal, + * 4: Greater than, + * 5: Greater than or equal, + * Other: Always match */ uint32_t p_function:3; /** p_notify : R/W; bitpos: [5]; default: 0; * Configure whether to explicitly report an instruction address matched against the - * primary comparator. \\0:Not report \\1:Report + * primary comparator. + * 0:Not report + * 1:Report */ uint32_t p_notify:1; uint32_t reserved_6:2; /** s_input : R/W; bitpos: [8]; default: 0; - * Configures the input of the secondary comparator for matching: \\0: iaddr \\1: - * tval\\ + * Configures the input of the secondary comparator for matching: + * 0: iaddr + * 1: tval */ uint32_t s_input:1; uint32_t reserved_9:1; /** s_function : R/W; bitpos: [12:10]; default: 0; - * Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal, - * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or - * equal, \\Other: Always match + * Configures the function for the secondary comparator. + * 0: Equal, + * 1: Not equal, + * 2: Less than, + * 3: Less than or equal, + * 4: Greater than, + * 5: Greater than or equal, + * Other: Always match */ uint32_t s_function:3; /** s_notify : R/W; bitpos: [13]; default: 0; @@ -318,10 +364,12 @@ typedef union { uint32_t s_notify:1; uint32_t reserved_14:2; /** match_mode : R/W; bitpos: [17:16]; default: 0; - * Configures the comparator match mode: \\0: Only the primary comparator matches \\1: - * Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or - * secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary - * comparator matches and stop filtering when the secondary comparator matches\\ + * Configures the comparator match mode: + * 0: Only the primary comparator matches + * 1: Both primary and secondary comparator matches(P\&\&S) + * 2:Neither primary or secondary comparator matches !(P\&\&S) + * 3: Start filtering when the primary comparator matches and stop filtering when the + * secondary comparator matches */ uint32_t match_mode:2; uint32_t reserved_18:14; @@ -365,9 +413,11 @@ typedef union { */ uint32_t resync_prolonged:24; /** resync_mode : R/W; bitpos: [25:24]; default: 0; - * Configures the synchronization mode: \\0: Disable the synchronization counter \\1: - * Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter - * counts by cycle\\ + * Configures the synchronization mode: + * 0: Disable the synchronization counter + * 1: Invalid + * 2: Synchronization counter counts by packet + * 3: Synchronization counter counts by cycle */ uint32_t resync_mode:2; uint32_t reserved_26:6; @@ -381,8 +431,12 @@ typedef union { typedef union { struct { /** hburst : R/W; bitpos: [2:0]; default: 0; - * Configures the AHB burst mode. \\0: SIGNAL \\1: INCR(length not defined) \\2:INCR4 - * \\4:INCR8 \\Others:Invalid + * Configures the AHB burst mode. + * 0: SINGLE + * 1: INCR(length not defined) + * 2:INCR4 + * 4:INCR8 + * Others:Invalid */ uint32_t hburst:3; /** max_incr : R/W; bitpos: [5:3]; default: 0; @@ -402,9 +456,10 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures register clock gating. \\0: Support clock only when the application - * writes registers to save power. \\1:Always force the clock on for registers \\ This - * bit doesn't affect register access. + * Configures register clock gating. + * 0: Support clock only when the application writes registers to save power. + * 1:Always force the clock on for registers + * This bit doesn't affect register access. */ uint32_t clk_en:1; uint32_t reserved_1:31; diff --git a/components/soc/esp32c5/register/soc/uart_reg.h b/components/soc/esp32c5/register/soc/uart_reg.h index 1560610f0b..52dcbaf53c 100644 --- a/components/soc/esp32c5/register/soc/uart_reg.h +++ b/components/soc/esp32c5/register/soc/uart_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,7 @@ extern "C" { */ #define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; - * Represents the data UART $n read from FIFO.\\ + * Represents the data UART $n read from FIFO. * Measurement unit: byte. */ #define UART_RXFIFO_RD_BYTE 0x000000FFU @@ -628,16 +628,17 @@ extern "C" { */ #define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; - * Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's - * clock cycle.\\Pulses whose width is lower than this value will be ignored. + * Configures the width of a pulse to be filtered. + * Measurement unit: UART Core's clock cycle. + * Pulses whose width is lower than this value will be ignored. */ #define UART_GLITCH_FILT 0x000000FFU #define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) #define UART_GLITCH_FILT_V 0x000000FFU #define UART_GLITCH_FILT_S 0 /** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable RX signal filter.\\ - * 0: Disable\\ + * Configures whether or not to enable RX signal filter. + * 0: Disable * 1: Enable */ #define UART_GLITCH_FILT_EN (BIT(8)) @@ -711,204 +712,202 @@ extern "C" { */ #define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) /** UART_PARITY : R/W; bitpos: [0]; default: 0; - * Configures the parity check mode.\\ - * 0: Even parity\\ - * 1: Odd parity\\ + * Configures the parity check mode. + * 0: Even parity + * 1: Odd parity */ #define UART_PARITY (BIT(0)) #define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) #define UART_PARITY_V 0x00000001U #define UART_PARITY_S 0 /** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable UART parity check.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART parity check. + * 0: Disable + * 1: Enable */ #define UART_PARITY_EN (BIT(1)) #define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) #define UART_PARITY_EN_V 0x00000001U #define UART_PARITY_EN_S 1 /** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; - * Configures the number of data bits.\\ - * 0: 5 bits\\ - * 1: 6 bits\\ - * 2: 7 bits\\ - * 3: 8 bits\\ + * Configures the number of data bits. + * 0: 5 bits + * 1: 6 bits + * 2: 7 bits + * 3: 8 bits */ #define UART_BIT_NUM 0x00000003U #define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) #define UART_BIT_NUM_V 0x00000003U #define UART_BIT_NUM_S 2 /** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; - * Configures the number of stop bits.\\ - * 0: Invalid. No effect\\ - * 1: 1 bits\\ - * 2: 1.5 bits\\ - * 3: 2 bits\\ + * Configures the number of stop bits. + * 0: Invalid. No effect + * 1: 1 bits + * 2: 1.5 bits + * 3: 2 bits */ #define UART_STOP_BIT_NUM 0x00000003U #define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) #define UART_STOP_BIT_NUM_V 0x00000003U #define UART_STOP_BIT_NUM_S 4 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Configures whether or not to send NULL characters when finishing data - * transmission.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send NULL characters when finishing data transmission. + * 0: Not send + * 1: Send */ #define UART_TXD_BRK (BIT(6)) #define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) #define UART_TXD_BRK_V 0x00000001U #define UART_TXD_BRK_S 6 /** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable IrDA loopback test.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable IrDA loopback test. + * 0: Disable + * 1: Enable */ #define UART_IRDA_DPLX (BIT(7)) #define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) #define UART_IRDA_DPLX_V 0x00000001U #define UART_IRDA_DPLX_S 7 /** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the IrDA transmitter.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the IrDA transmitter. + * 0: Disable + * 1: Enable */ #define UART_IRDA_TX_EN (BIT(8)) #define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) #define UART_IRDA_TX_EN_V 0x00000001U #define UART_IRDA_TX_EN_S 8 /** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; - * Configures the 11th bit of the IrDA transmitter.\\ - * 0: This bit is 0.\\ - * 1: This bit is the same as the 10th bit.\\ + * Configures the 11th bit of the IrDA transmitter. + * 0: This bit is 0. + * 1: This bit is the same as the 10th bit. */ #define UART_IRDA_WCTL (BIT(9)) #define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) #define UART_IRDA_WCTL_V 0x00000001U #define UART_IRDA_WCTL_S 9 /** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; - * Configures whether or not to invert the level of the IrDA transmitter.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of the IrDA transmitter. + * 0: Not invert + * 1: Invert */ #define UART_IRDA_TX_INV (BIT(10)) #define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) #define UART_IRDA_TX_INV_V 0x00000001U #define UART_IRDA_TX_INV_S 10 /** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the level of the IrDA receiver.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of the IrDA receiver. + * 0: Not invert + * 1: Invert */ #define UART_IRDA_RX_INV (BIT(11)) #define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) #define UART_IRDA_RX_INV_V 0x00000001U #define UART_IRDA_RX_INV_S 11 /** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable UART loopback test.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART loopback test. + * 0: Disable + * 1: Enable */ #define UART_LOOPBACK (BIT(12)) #define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) #define UART_LOOPBACK_V 0x00000001U #define UART_LOOPBACK_S 12 /** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable flow control for the transmitter.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable flow control for the transmitter. + * 0: Disable + * 1: Enable */ #define UART_TX_FLOW_EN (BIT(13)) #define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) #define UART_TX_FLOW_EN_V 0x00000001U #define UART_TX_FLOW_EN_S 13 /** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable IrDA protocol.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable IrDA protocol. + * 0: Disable + * 1: Enable */ #define UART_IRDA_EN (BIT(14)) #define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) #define UART_IRDA_EN_V 0x00000001U #define UART_IRDA_EN_S 14 /** UART_RXD_INV : R/W; bitpos: [15]; default: 0; - * Configures whether or not to invert the level of UART RXD signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART RXD signal. + * 0: Not invert + * 1: Invert */ #define UART_RXD_INV (BIT(15)) #define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) #define UART_RXD_INV_V 0x00000001U #define UART_RXD_INV_S 15 /** UART_TXD_INV : R/W; bitpos: [16]; default: 0; - * Configures whether or not to invert the level of UART TXD signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART TXD signal. + * 0: Not invert + * 1: Invert */ #define UART_TXD_INV (BIT(16)) #define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) #define UART_TXD_INV_V 0x00000001U #define UART_TXD_INV_S 16 /** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; - * Configures whether or not to disable data overflow detection for the UART - * receiver.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable data overflow detection for the UART receiver. + * 0: Enable + * 1: Disable */ #define UART_DIS_RX_DAT_OVF (BIT(17)) #define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) #define UART_DIS_RX_DAT_OVF_V 0x00000001U #define UART_DIS_RX_DAT_OVF_S 17 /** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; - * Configures whether or not to store the received data with errors into FIFO.\\ - * 0: Store\\ - * 1: Not store\\ + * Configures whether or not to store the received data with errors into FIFO. + * 0: Store + * 1: Not store */ #define UART_ERR_WR_MASK (BIT(18)) #define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) #define UART_ERR_WR_MASK_V 0x00000001U #define UART_ERR_WR_MASK_S 18 /** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable baud rate detection.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable baud rate detection. + * 0: Disable + * 1: Enable */ #define UART_AUTOBAUD_EN (BIT(19)) #define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) #define UART_AUTOBAUD_EN_V 0x00000001U #define UART_AUTOBAUD_EN_S 19 /** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable clock gating for UART memory.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gating for UART memory. + * 0: Disable + * 1: Enable */ #define UART_MEM_CLK_EN (BIT(20)) #define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) #define UART_MEM_CLK_EN_V 0x00000001U #define UART_MEM_CLK_EN_S 20 /** UART_SW_RTS : R/W; bitpos: [21]; default: 0; - * Configures the RTS signal used in software flow control.\\ - * 0: The UART transmitter is allowed to send data.\\ - * 1: The UART transmitted is not allowed to send data.\\ + * Configures the RTS signal used in software flow control. + * 0: The UART transmitter is allowed to send data. + * 1: The UART transmitted is not allowed to send data. */ #define UART_SW_RTS (BIT(21)) #define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) #define UART_SW_RTS_V 0x00000001U #define UART_SW_RTS_S 21 /** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; - * Configures whether or not to reset the UART RX FIFO.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset the UART RX FIFO. + * 0: Not reset + * 1: Reset */ #define UART_RXFIFO_RST (BIT(22)) #define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) #define UART_RXFIFO_RST_V 0x00000001U #define UART_RXFIFO_RST_S 22 /** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; - * Configures whether or not to reset the UART TX FIFO.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset the UART TX FIFO. + * 0: Not reset + * 1: Reset */ #define UART_TXFIFO_RST (BIT(23)) #define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) @@ -920,68 +919,70 @@ extern "C" { */ #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; - * Configures the threshold for RX FIFO being full.\\Measurement unit: byte. + * Configures the threshold for RX FIFO being full. + * Measurement unit: byte. */ #define UART_RXFIFO_FULL_THRHD 0x000000FFU #define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) #define UART_RXFIFO_FULL_THRHD_V 0x000000FFU #define UART_RXFIFO_FULL_THRHD_S 0 /** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; - * Configures the threshold for TX FIFO being empty.\\Measurement unit: byte. + * Configures the threshold for TX FIFO being empty. + * Measurement unit: byte. */ #define UART_TXFIFO_EMPTY_THRHD 0x000000FFU #define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) #define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU #define UART_TXFIFO_EMPTY_THRHD_S 8 /** UART_CTS_INV : R/W; bitpos: [16]; default: 0; - * Configures whether or not to invert the level of UART CTS signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART CTS signal. + * 0: Not invert + * 1: Invert */ #define UART_CTS_INV (BIT(16)) #define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) #define UART_CTS_INV_V 0x00000001U #define UART_CTS_INV_S 16 /** UART_DSR_INV : R/W; bitpos: [17]; default: 0; - * Configures whether or not to invert the level of UART DSR signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART DSR signal. + * 0: Not invert + * 1: Invert */ #define UART_DSR_INV (BIT(17)) #define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) #define UART_DSR_INV_V 0x00000001U #define UART_DSR_INV_S 17 /** UART_RTS_INV : R/W; bitpos: [18]; default: 0; - * Configures whether or not to invert the level of UART RTS signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART RTS signal. + * 0: Not invert + * 1: Invert */ #define UART_RTS_INV (BIT(18)) #define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) #define UART_RTS_INV_V 0x00000001U #define UART_RTS_INV_S 18 /** UART_DTR_INV : R/W; bitpos: [19]; default: 0; - * Configures whether or not to invert the level of UART DTR signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART DTR signal. + * 0: Not invert + * 1: Invert */ #define UART_DTR_INV (BIT(19)) #define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) #define UART_DTR_INV_V 0x00000001U #define UART_DTR_INV_S 19 /** UART_SW_DTR : R/W; bitpos: [20]; default: 0; - * Configures the DTR signal used in software flow control.\\ - * 0: Data to be transmitted is not ready.\\ - * 1: Data to be transmitted is ready.\\ + * Configures the DTR signal used in software flow control. + * 0: Data to be transmitted is not ready. + * 1: Data to be transmitted is ready. */ #define UART_SW_DTR (BIT(20)) #define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) #define UART_SW_DTR_V 0x00000001U #define UART_SW_DTR_S 20 /** UART_CLK_EN : R/W; bitpos: [21]; default: 0; - * Configures clock gating.\\ - * 0: Support clock only when the application writes registers.\\ - * 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ #define UART_CLK_EN (BIT(21)) #define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) @@ -994,16 +995,17 @@ extern "C" { #define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; * Configures the maximum number of data bytes that can be received during hardware - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ #define UART_RX_FLOW_THRHD 0x000000FFU #define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) #define UART_RX_FLOW_THRHD_V 0x000000FFU #define UART_RX_FLOW_THRHD_S 0 /** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the UART receiver.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the UART receiver. + * 0: Disable + * 1: Enable */ #define UART_RX_FLOW_EN (BIT(8)) #define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) @@ -1081,20 +1083,20 @@ extern "C" { #define UART_WK_CHAR_NUM_V 0x00000007U #define UART_WK_CHAR_NUM_S 18 /** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; - * Configures whether or not to mask wakeup characters.\\ - * 0: Not mask\\ - * 1: Mask\\ + * Configures whether or not to mask wakeup characters. + * 0: Not mask + * 1: Mask */ #define UART_WK_CHAR_MASK 0x0000001FU #define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) #define UART_WK_CHAR_MASK_V 0x0000001FU #define UART_WK_CHAR_MASK_S 21 /** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; - * Configures which wakeup mode to select.\\ - * 0: Mode 0\\ - * 1: Mode 1\\ - * 2: Mode 2\\ - * 3: Mode 3\\ + * Configures which wakeup mode to select. + * 0: Mode 0 + * 1: Mode 1 + * 2: Mode 2 + * 3: Mode 3 */ #define UART_WK_MODE_SEL 0x00000003U #define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) @@ -1121,64 +1123,63 @@ extern "C" { #define UART_XOFF_CHAR_S 8 /** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; * Configures whether the UART transmitter can send XON or XOFF characters when it is - * disabled.\\ - * 0: Cannot send\\ - * 1: Can send\\ + * disabled. + * 0: Cannot send + * 1: Can send */ #define UART_XON_XOFF_STILL_SEND (BIT(16)) #define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) #define UART_XON_XOFF_STILL_SEND_V 0x00000001U #define UART_XON_XOFF_STILL_SEND_S 16 /** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable software flow control.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable software flow control. + * 0: Disable + * 1: Enable */ #define UART_SW_FLOW_CON_EN (BIT(17)) #define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) #define UART_SW_FLOW_CON_EN_V 0x00000001U #define UART_SW_FLOW_CON_EN_S 17 /** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; - * Configures whether or not to remove flow control characters from the received - * data.\\ - * 0: Not move\\ - * 1: Move\\ + * Configures whether or not to remove flow control characters from the received data. + * 0: Not move + * 1: Move */ #define UART_XONOFF_DEL (BIT(18)) #define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) #define UART_XONOFF_DEL_V 0x00000001U #define UART_XONOFF_DEL_S 18 /** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; - * Configures whether the transmitter continues to sending data.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether the transmitter continues to sending data. + * 0: Not send + * 1: Send */ #define UART_FORCE_XON (BIT(19)) #define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) #define UART_FORCE_XON_V 0x00000001U #define UART_FORCE_XON_S 19 /** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; - * Configures whether or not to stop the transmitter from sending data.\\ - * 0: Not stop\\ - * 1: Stop\\ + * Configures whether or not to stop the transmitter from sending data. + * 0: Not stop + * 1: Stop */ #define UART_FORCE_XOFF (BIT(20)) #define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) #define UART_FORCE_XOFF_V 0x00000001U #define UART_FORCE_XOFF_S 20 /** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; - * Configures whether or not to send XON characters.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send XON characters. + * 0: Not send + * 1: Send */ #define UART_SEND_XON (BIT(21)) #define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) #define UART_SEND_XON_V 0x00000001U #define UART_SEND_XON_S 21 /** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; - * Configures whether or not to send XOFF characters.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send XOFF characters. + * 0: Not send + * 1: Send */ #define UART_SEND_XOFF (BIT(22)) #define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) @@ -1191,7 +1192,8 @@ extern "C" { #define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; * Configures the threshold for data in RX FIFO to send XON characters in software - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ #define UART_XON_THRESHOLD 0x000000FFU #define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) @@ -1199,7 +1201,8 @@ extern "C" { #define UART_XON_THRESHOLD_S 0 /** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; * Configures the threshold for data in RX FIFO to send XOFF characters in software - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ #define UART_XOFF_THRESHOLD 0x000000FFU #define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) @@ -1212,7 +1215,8 @@ extern "C" { #define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * Configures the number of NULL characters to be sent after finishing data - * transmission.\\Valid only when UART_TXD_BRK is 1. + * transmission. + * Valid only when UART_TXD_BRK is 1. */ #define UART_TX_BRK_NUM 0x000000FFU #define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) @@ -1225,16 +1229,16 @@ extern "C" { #define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; * Configures the threshold to generate a frame end signal when the receiver takes - * more time to receive one data byte data.\\Measurement unit: bit time (the time to - * transmit 1 bit). + * more time to receive one data byte data. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_RX_IDLE_THRHD 0x000003FFU #define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) #define UART_RX_IDLE_THRHD_V 0x000003FFU #define UART_RX_IDLE_THRHD_S 0 /** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; - * Configures the interval between two data transfers.\\Measurement unit: bit time - * (the time to transmit 1 bit). + * Configures the interval between two data transfers. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_TX_IDLE_NUM 0x000003FFU #define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) @@ -1246,27 +1250,27 @@ extern "C" { */ #define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) /** UART_RS485_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable RS485 mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable RS485 mode. + * 0: Disable + * 1: Enable */ #define UART_RS485_EN (BIT(0)) #define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) #define UART_RS485_EN_V 0x00000001U #define UART_RS485_EN_S 0 /** UART_DL0_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\ - * 0: Not add\\ - * 1: Add\\ + * Configures whether or not to add a turnaround delay of 1 bit before the start bit. + * 0: Not add + * 1: Add */ #define UART_DL0_EN (BIT(1)) #define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) #define UART_DL0_EN_V 0x00000001U #define UART_DL0_EN_S 1 /** UART_DL1_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\ - * 0: Not add\\ - * 1: Add\\ + * Configures whether or not to add a turnaround delay of 1 bit after the stop bit. + * 0: Not add + * 1: Add */ #define UART_DL1_EN (BIT(2)) #define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) @@ -1274,9 +1278,9 @@ extern "C" { #define UART_DL1_EN_S 2 /** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable the receiver for data reception when the - * transmitter is transmitting data in RS485 mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * transmitter is transmitting data in RS485 mode. + * 0: Disable + * 1: Enable */ #define UART_RS485TX_RX_EN (BIT(3)) #define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) @@ -1284,25 +1288,25 @@ extern "C" { #define UART_RS485TX_RX_EN_S 3 /** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; * Configures whether to enable the RS485 transmitter for data transmission when the - * RS485 receiver is busy.\\ - * 0: Disable\\ - * 1: Enable\\ + * RS485 receiver is busy. + * 0: Disable + * 1: Enable */ #define UART_RS485RXBY_TX_EN (BIT(4)) #define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) #define UART_RS485RXBY_TX_EN_V 0x00000001U #define UART_RS485RXBY_TX_EN_S 4 /** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; - * Configures the delay of internal data signals in the receiver.\\Measurement unit: - * bit time (the time to transmit 1 bit).. + * Configures the delay of internal data signals in the receiver. + * Measurement unit: bit time (the time to transmit 1 bit).. */ #define UART_RS485_RX_DLY_NUM (BIT(5)) #define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) #define UART_RS485_RX_DLY_NUM_V 0x00000001U #define UART_RS485_RX_DLY_NUM_S 5 /** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; - * Configures the delay of internal data signals in the transmitter.\\Measurement - * unit: bit time (the time to transmit 1 bit). + * Configures the delay of internal data signals in the transmitter. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_RS485_TX_DLY_NUM 0x0000000FU #define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) @@ -1314,8 +1318,8 @@ extern "C" { */ #define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * Configures the idle time before the receiver receives the first - * AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit). + * Configures the idle time before the receiver receives the first AT_CMD. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_PRE_IDLE_NUM 0x0000FFFFU #define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) @@ -1327,8 +1331,8 @@ extern "C" { */ #define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * Configures the interval between the last AT_CMD and subsequent data.\\Measurement - * unit: bit time (the time to transmit 1 bit). + * Configures the interval between the last AT_CMD and subsequent data. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_POST_IDLE_NUM 0x0000FFFFU #define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) @@ -1340,8 +1344,8 @@ extern "C" { */ #define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; - * Configures the interval between two AT_CMD characters.\\Measurement unit: bit time - * (the time to transmit 1 bit). + * Configures the interval between two AT_CMD characters. + * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_RX_GAP_TOUT 0x0000FFFFU #define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) @@ -1391,9 +1395,9 @@ extern "C" { */ #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable UART receiver's timeout function.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART receiver's timeout function. + * 0: Disable + * 1: Enable */ #define UART_RX_TOUT_EN (BIT(0)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1407,7 +1411,7 @@ extern "C" { #define UART_RX_TOUT_FLOW_DIS_V 0x00000001U #define UART_RX_TOUT_FLOW_DIS_S 1 /** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; - * Configures the amount of time that the bus can remain idle before timeout.\\ + * Configures the amount of time that the bus can remain idle before timeout. * Measurement unit: bit time (the time to transmit 1 bit). */ #define UART_RX_TOUT_THRHD 0x000003FFU @@ -1504,7 +1508,8 @@ extern "C" { #define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the minimum duration time of a low-level pulse. It is used for baud rate - * detection.\\Measurement unit: APB_CLK clock cycle. + * detection. + * Measurement unit: APB_CLK clock cycle. */ #define UART_LOWPULSE_MIN_CNT 0x00000FFFU #define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) @@ -1517,7 +1522,8 @@ extern "C" { #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the maximum duration time for a high-level pulse. It is used for baud - * rate detection.\\Measurement unit: APB_CLK clock cycle. + * rate detection. + * Measurement unit: APB_CLK clock cycle. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU #define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) @@ -1541,18 +1547,18 @@ extern "C" { */ #define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Configures whether or not to enable UART TX clock.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART TX clock. + * 0: Disable + * 1: Enable */ #define UART_TX_SCLK_EN (BIT(24)) #define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) #define UART_TX_SCLK_EN_V 0x00000001U #define UART_TX_SCLK_EN_S 24 /** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Configures whether or not to enable UART RX clock.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART RX clock. + * 0: Disable + * 1: Enable */ #define UART_RX_SCLK_EN (BIT(25)) #define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) @@ -1590,36 +1596,36 @@ extern "C" { */ #define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; - * Represents whether or not the APB TX asynchronous FIFO is full.\\ - * 0: Not full\\ - * 1: Full\\ + * Represents whether or not the APB TX asynchronous FIFO is full. + * 0: Not full + * 1: Full */ #define UART_TX_AFIFO_FULL (BIT(0)) #define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) #define UART_TX_AFIFO_FULL_V 0x00000001U #define UART_TX_AFIFO_FULL_S 0 /** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; - * Represents whether or not the APB TX asynchronous FIFO is empty.\\ - * 0: Not empty\\ - * 1: Empty\\ + * Represents whether or not the APB TX asynchronous FIFO is empty. + * 0: Not empty + * 1: Empty */ #define UART_TX_AFIFO_EMPTY (BIT(1)) #define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) #define UART_TX_AFIFO_EMPTY_V 0x00000001U #define UART_TX_AFIFO_EMPTY_S 1 /** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; - * Represents whether or not the APB RX asynchronous FIFO is full.\\ - * 0: Not full\\ - * 1: Full\\ + * Represents whether or not the APB RX asynchronous FIFO is full. + * 0: Not full + * 1: Full */ #define UART_RX_AFIFO_FULL (BIT(2)) #define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) #define UART_RX_AFIFO_FULL_V 0x00000001U #define UART_RX_AFIFO_FULL_S 2 /** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; - * Represents whether or not the APB RX asynchronous FIFO is empty.\\ - * 0: Not empty\\ - * 1: Empty\\ + * Represents whether or not the APB RX asynchronous FIFO is empty. + * 0: Not empty + * 1: Empty */ #define UART_RX_AFIFO_EMPTY (BIT(3)) #define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) @@ -1631,9 +1637,9 @@ extern "C" { */ #define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; - * Configures whether or not to synchronize registers.\\ - * 0: Not synchronize\\ - * 1: Synchronize\\ + * Configures whether or not to synchronize registers. + * 0: Not synchronize + * 1: Synchronize */ #define UART_REG_UPDATE (BIT(0)) #define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) diff --git a/components/soc/esp32c5/register/soc/uart_struct.h b/components/soc/esp32c5/register/soc/uart_struct.h index d7be70696b..bfc8fffd2a 100644 --- a/components/soc/esp32c5/register/soc/uart_struct.h +++ b/components/soc/esp32c5/register/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,12 @@ extern "C" { */ typedef union { struct { - /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0; - * Represents the data UART $n read from FIFO.\\ + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * Represents the data UART $n read from FIFO. * Measurement unit: byte. */ - uint32_t rxfifo_rd_byte:32; + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } uart_fifo_reg_t; @@ -50,9 +51,9 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable UART receiver's timeout function.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART receiver's timeout function. + * 0: Disable + * 1: Enable */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -60,7 +61,7 @@ typedef union { */ uint32_t rx_tout_flow_dis:1; /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; - * Configures the amount of time that the bus can remain idle before timeout.\\ + * Configures the amount of time that the bus can remain idle before timeout. * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t rx_tout_thrhd:10; @@ -458,13 +459,14 @@ typedef union { typedef union { struct { /** glitch_filt : R/W; bitpos: [7:0]; default: 8; - * Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's - * clock cycle.\\Pulses whose width is lower than this value will be ignored. + * Configures the width of a pulse to be filtered. + * Measurement unit: UART Core's clock cycle. + * Pulses whose width is lower than this value will be ignored. */ uint32_t glitch_filt:8; /** glitch_filt_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable RX signal filter.\\ - * 0: Disable\\ + * Configures whether or not to enable RX signal filter. + * 0: Disable * 1: Enable */ uint32_t glitch_filt_en:1; @@ -479,141 +481,139 @@ typedef union { typedef union { struct { /** parity : R/W; bitpos: [0]; default: 0; - * Configures the parity check mode.\\ - * 0: Even parity\\ - * 1: Odd parity\\ + * Configures the parity check mode. + * 0: Even parity + * 1: Odd parity */ uint32_t parity:1; /** parity_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable UART parity check.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART parity check. + * 0: Disable + * 1: Enable */ uint32_t parity_en:1; /** bit_num : R/W; bitpos: [3:2]; default: 3; - * Configures the number of data bits.\\ - * 0: 5 bits\\ - * 1: 6 bits\\ - * 2: 7 bits\\ - * 3: 8 bits\\ + * Configures the number of data bits. + * 0: 5 bits + * 1: 6 bits + * 2: 7 bits + * 3: 8 bits */ uint32_t bit_num:2; /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; - * Configures the number of stop bits.\\ - * 0: Invalid. No effect\\ - * 1: 1 bits\\ - * 2: 1.5 bits\\ - * 3: 2 bits\\ + * Configures the number of stop bits. + * 0: Invalid. No effect + * 1: 1 bits + * 2: 1.5 bits + * 3: 2 bits */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Configures whether or not to send NULL characters when finishing data - * transmission.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send NULL characters when finishing data transmission. + * 0: Not send + * 1: Send */ uint32_t txd_brk:1; /** irda_dplx : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable IrDA loopback test.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable IrDA loopback test. + * 0: Disable + * 1: Enable */ uint32_t irda_dplx:1; /** irda_tx_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the IrDA transmitter.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the IrDA transmitter. + * 0: Disable + * 1: Enable */ uint32_t irda_tx_en:1; /** irda_wctl : R/W; bitpos: [9]; default: 0; - * Configures the 11th bit of the IrDA transmitter.\\ - * 0: This bit is 0.\\ - * 1: This bit is the same as the 10th bit.\\ + * Configures the 11th bit of the IrDA transmitter. + * 0: This bit is 0. + * 1: This bit is the same as the 10th bit. */ uint32_t irda_wctl:1; /** irda_tx_inv : R/W; bitpos: [10]; default: 0; - * Configures whether or not to invert the level of the IrDA transmitter.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of the IrDA transmitter. + * 0: Not invert + * 1: Invert */ uint32_t irda_tx_inv:1; /** irda_rx_inv : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the level of the IrDA receiver.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of the IrDA receiver. + * 0: Not invert + * 1: Invert */ uint32_t irda_rx_inv:1; /** loopback : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable UART loopback test.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART loopback test. + * 0: Disable + * 1: Enable */ uint32_t loopback:1; /** tx_flow_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable flow control for the transmitter.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable flow control for the transmitter. + * 0: Disable + * 1: Enable */ uint32_t tx_flow_en:1; /** irda_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable IrDA protocol.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable IrDA protocol. + * 0: Disable + * 1: Enable */ uint32_t irda_en:1; /** rxd_inv : R/W; bitpos: [15]; default: 0; - * Configures whether or not to invert the level of UART RXD signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART RXD signal. + * 0: Not invert + * 1: Invert */ uint32_t rxd_inv:1; /** txd_inv : R/W; bitpos: [16]; default: 0; - * Configures whether or not to invert the level of UART TXD signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART TXD signal. + * 0: Not invert + * 1: Invert */ uint32_t txd_inv:1; /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; - * Configures whether or not to disable data overflow detection for the UART - * receiver.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable data overflow detection for the UART receiver. + * 0: Enable + * 1: Disable */ uint32_t dis_rx_dat_ovf:1; /** err_wr_mask : R/W; bitpos: [18]; default: 0; - * Configures whether or not to store the received data with errors into FIFO.\\ - * 0: Store\\ - * 1: Not store\\ + * Configures whether or not to store the received data with errors into FIFO. + * 0: Store + * 1: Not store */ uint32_t err_wr_mask:1; /** autobaud_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable baud rate detection.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable baud rate detection. + * 0: Disable + * 1: Enable */ uint32_t autobaud_en:1; /** mem_clk_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable clock gating for UART memory.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gating for UART memory. + * 0: Disable + * 1: Enable */ uint32_t mem_clk_en:1; /** sw_rts : R/W; bitpos: [21]; default: 0; - * Configures the RTS signal used in software flow control.\\ - * 0: The UART transmitter is allowed to send data.\\ - * 1: The UART transmitted is not allowed to send data.\\ + * Configures the RTS signal used in software flow control. + * 0: The UART transmitter is allowed to send data. + * 1: The UART transmitted is not allowed to send data. */ uint32_t sw_rts:1; /** rxfifo_rst : R/W; bitpos: [22]; default: 0; - * Configures whether or not to reset the UART RX FIFO.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset the UART RX FIFO. + * 0: Not reset + * 1: Reset */ uint32_t rxfifo_rst:1; /** txfifo_rst : R/W; bitpos: [23]; default: 0; - * Configures whether or not to reset the UART TX FIFO.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset the UART TX FIFO. + * 0: Not reset + * 1: Reset */ uint32_t txfifo_rst:1; uint32_t reserved_24:8; @@ -627,47 +627,49 @@ typedef union { typedef union { struct { /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; - * Configures the threshold for RX FIFO being full.\\Measurement unit: byte. + * Configures the threshold for RX FIFO being full. + * Measurement unit: byte. */ uint32_t rxfifo_full_thrhd:8; /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; - * Configures the threshold for TX FIFO being empty.\\Measurement unit: byte. + * Configures the threshold for TX FIFO being empty. + * Measurement unit: byte. */ uint32_t txfifo_empty_thrhd:8; /** cts_inv : R/W; bitpos: [16]; default: 0; - * Configures whether or not to invert the level of UART CTS signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART CTS signal. + * 0: Not invert + * 1: Invert */ uint32_t cts_inv:1; /** dsr_inv : R/W; bitpos: [17]; default: 0; - * Configures whether or not to invert the level of UART DSR signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART DSR signal. + * 0: Not invert + * 1: Invert */ uint32_t dsr_inv:1; /** rts_inv : R/W; bitpos: [18]; default: 0; - * Configures whether or not to invert the level of UART RTS signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART RTS signal. + * 0: Not invert + * 1: Invert */ uint32_t rts_inv:1; /** dtr_inv : R/W; bitpos: [19]; default: 0; - * Configures whether or not to invert the level of UART DTR signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the level of UART DTR signal. + * 0: Not invert + * 1: Invert */ uint32_t dtr_inv:1; /** sw_dtr : R/W; bitpos: [20]; default: 0; - * Configures the DTR signal used in software flow control.\\ - * 0: Data to be transmitted is not ready.\\ - * 1: Data to be transmitted is ready.\\ + * Configures the DTR signal used in software flow control. + * 0: Data to be transmitted is not ready. + * 1: Data to be transmitted is ready. */ uint32_t sw_dtr:1; /** clk_en : R/W; bitpos: [21]; default: 0; - * Configures clock gating.\\ - * 0: Support clock only when the application writes registers.\\ - * 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ uint32_t clk_en:1; uint32_t reserved_22:10; @@ -682,13 +684,14 @@ typedef union { struct { /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; * Configures the maximum number of data bytes that can be received during hardware - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ uint32_t rx_flow_thrhd:8; /** rx_flow_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the UART receiver.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the UART receiver. + * 0: Disable + * 1: Enable */ uint32_t rx_flow_en:1; uint32_t reserved_9:23; @@ -753,17 +756,17 @@ typedef union { */ uint32_t wk_char_num:3; /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; - * Configures whether or not to mask wakeup characters.\\ - * 0: Not mask\\ - * 1: Mask\\ + * Configures whether or not to mask wakeup characters. + * 0: Not mask + * 1: Mask */ uint32_t wk_char_mask:5; /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; - * Configures which wakeup mode to select.\\ - * 0: Mode 0\\ - * 1: Mode 1\\ - * 2: Mode 2\\ - * 3: Mode 3\\ + * Configures which wakeup mode to select. + * 0: Mode 0 + * 1: Mode 1 + * 2: Mode 2 + * 3: Mode 3 */ uint32_t wk_mode_sel:2; uint32_t reserved_28:4; @@ -786,46 +789,45 @@ typedef union { uint32_t xoff_character:8; /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; * Configures whether the UART transmitter can send XON or XOFF characters when it is - * disabled.\\ - * 0: Cannot send\\ - * 1: Can send\\ + * disabled. + * 0: Cannot send + * 1: Can send */ uint32_t xon_xoff_still_send:1; /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable software flow control.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable software flow control. + * 0: Disable + * 1: Enable */ uint32_t sw_flow_con_en:1; /** xonoff_del : R/W; bitpos: [18]; default: 0; - * Configures whether or not to remove flow control characters from the received - * data.\\ - * 0: Not move\\ - * 1: Move\\ + * Configures whether or not to remove flow control characters from the received data. + * 0: Not move + * 1: Move */ uint32_t xonoff_del:1; /** force_xon : R/W; bitpos: [19]; default: 0; - * Configures whether the transmitter continues to sending data.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether the transmitter continues to sending data. + * 0: Not send + * 1: Send */ uint32_t force_xon:1; /** force_xoff : R/W; bitpos: [20]; default: 0; - * Configures whether or not to stop the transmitter from sending data.\\ - * 0: Not stop\\ - * 1: Stop\\ + * Configures whether or not to stop the transmitter from sending data. + * 0: Not stop + * 1: Stop */ uint32_t force_xoff:1; /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; - * Configures whether or not to send XON characters.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send XON characters. + * 0: Not send + * 1: Send */ uint32_t send_xon:1; /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; - * Configures whether or not to send XOFF characters.\\ - * 0: Not send\\ - * 1: Send\\ + * Configures whether or not to send XOFF characters. + * 0: Not send + * 1: Send */ uint32_t send_xoff:1; uint32_t reserved_23:9; @@ -840,12 +842,14 @@ typedef union { struct { /** xon_threshold : R/W; bitpos: [7:0]; default: 0; * Configures the threshold for data in RX FIFO to send XON characters in software - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ uint32_t xon_threshold:8; /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; * Configures the threshold for data in RX FIFO to send XOFF characters in software - * flow control.\\Measurement unit: byte. + * flow control. + * Measurement unit: byte. */ uint32_t xoff_threshold:8; uint32_t reserved_16:16; @@ -860,7 +864,8 @@ typedef union { struct { /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; * Configures the number of NULL characters to be sent after finishing data - * transmission.\\Valid only when UART_TXD_BRK is 1. + * transmission. + * Valid only when UART_TXD_BRK is 1. */ uint32_t tx_brk_num:8; uint32_t reserved_8:24; @@ -875,13 +880,13 @@ typedef union { struct { /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; * Configures the threshold to generate a frame end signal when the receiver takes - * more time to receive one data byte data.\\Measurement unit: bit time (the time to - * transmit 1 bit). + * more time to receive one data byte data. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t rx_idle_thrhd:10; /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; - * Configures the interval between two data transfers.\\Measurement unit: bit time - * (the time to transmit 1 bit). + * Configures the interval between two data transfers. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t tx_idle_num:10; uint32_t reserved_20:12; @@ -895,45 +900,45 @@ typedef union { typedef union { struct { /** rs485_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable RS485 mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable RS485 mode. + * 0: Disable + * 1: Enable */ uint32_t rs485_en:1; /** dl0_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\ - * 0: Not add\\ - * 1: Add\\ + * Configures whether or not to add a turnaround delay of 1 bit before the start bit. + * 0: Not add + * 1: Add */ uint32_t dl0_en:1; /** dl1_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\ - * 0: Not add\\ - * 1: Add\\ + * Configures whether or not to add a turnaround delay of 1 bit after the stop bit. + * 0: Not add + * 1: Add */ uint32_t dl1_en:1; /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable the receiver for data reception when the - * transmitter is transmitting data in RS485 mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * transmitter is transmitting data in RS485 mode. + * 0: Disable + * 1: Enable */ uint32_t rs485tx_rx_en:1; /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; * Configures whether to enable the RS485 transmitter for data transmission when the - * RS485 receiver is busy.\\ - * 0: Disable\\ - * 1: Enable\\ + * RS485 receiver is busy. + * 0: Disable + * 1: Enable */ uint32_t rs485rxby_tx_en:1; /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; - * Configures the delay of internal data signals in the receiver.\\Measurement unit: - * bit time (the time to transmit 1 bit).. + * Configures the delay of internal data signals in the receiver. + * Measurement unit: bit time (the time to transmit 1 bit).. */ uint32_t rs485_rx_dly_num:1; /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; - * Configures the delay of internal data signals in the transmitter.\\Measurement - * unit: bit time (the time to transmit 1 bit). + * Configures the delay of internal data signals in the transmitter. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t rs485_tx_dly_num:4; uint32_t reserved_10:22; @@ -948,15 +953,15 @@ typedef union { struct { uint32_t reserved_0:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; - * Configures whether or not to enable UART TX clock.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART TX clock. + * 0: Disable + * 1: Enable */ uint32_t tx_sclk_en:1; /** rx_sclk_en : R/W; bitpos: [25]; default: 1; - * Configures whether or not to enable UART RX clock.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable UART RX clock. + * 0: Disable + * 1: Enable */ uint32_t rx_sclk_en:1; /** tx_rst_core : R/W; bitpos: [26]; default: 0; @@ -1079,27 +1084,27 @@ typedef union { typedef union { struct { /** tx_afifo_full : RO; bitpos: [0]; default: 0; - * Represents whether or not the APB TX asynchronous FIFO is full.\\ - * 0: Not full\\ - * 1: Full\\ + * Represents whether or not the APB TX asynchronous FIFO is full. + * 0: Not full + * 1: Full */ uint32_t tx_afifo_full:1; /** tx_afifo_empty : RO; bitpos: [1]; default: 1; - * Represents whether or not the APB TX asynchronous FIFO is empty.\\ - * 0: Not empty\\ - * 1: Empty\\ + * Represents whether or not the APB TX asynchronous FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t tx_afifo_empty:1; /** rx_afifo_full : RO; bitpos: [2]; default: 0; - * Represents whether or not the APB RX asynchronous FIFO is full.\\ - * 0: Not full\\ - * 1: Full\\ + * Represents whether or not the APB RX asynchronous FIFO is full. + * 0: Not full + * 1: Full */ uint32_t rx_afifo_full:1; /** rx_afifo_empty : RO; bitpos: [3]; default: 1; - * Represents whether or not the APB RX asynchronous FIFO is empty.\\ - * 0: Not empty\\ - * 1: Empty\\ + * Represents whether or not the APB RX asynchronous FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t rx_afifo_empty:1; uint32_t reserved_4:28; @@ -1115,8 +1120,8 @@ typedef union { typedef union { struct { /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; - * Configures the idle time before the receiver receives the first - * AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit). + * Configures the idle time before the receiver receives the first AT_CMD. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t pre_idle_num:16; uint32_t reserved_16:16; @@ -1130,8 +1135,8 @@ typedef union { typedef union { struct { /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; - * Configures the interval between the last AT_CMD and subsequent data.\\Measurement - * unit: bit time (the time to transmit 1 bit). + * Configures the interval between the last AT_CMD and subsequent data. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t post_idle_num:16; uint32_t reserved_16:16; @@ -1145,8 +1150,8 @@ typedef union { typedef union { struct { /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; - * Configures the interval between two AT_CMD characters.\\Measurement unit: bit time - * (the time to transmit 1 bit). + * Configures the interval between two AT_CMD characters. + * Measurement unit: bit time (the time to transmit 1 bit). */ uint32_t rx_gap_tout:16; uint32_t reserved_16:16; @@ -1211,7 +1216,8 @@ typedef union { struct { /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; * Represents the minimum duration time of a low-level pulse. It is used for baud rate - * detection.\\Measurement unit: APB_CLK clock cycle. + * detection. + * Measurement unit: APB_CLK clock cycle. */ uint32_t lowpulse_min_cnt:12; uint32_t reserved_12:20; @@ -1226,7 +1232,8 @@ typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; * Represents the maximum duration time for a high-level pulse. It is used for baud - * rate detection.\\Measurement unit: APB_CLK clock cycle. + * rate detection. + * Measurement unit: APB_CLK clock cycle. */ uint32_t highpulse_min_cnt:12; uint32_t reserved_12:20; @@ -1269,9 +1276,9 @@ typedef union { typedef union { struct { /** reg_update : R/W/SC; bitpos: [0]; default: 0; - * Configures whether or not to synchronize registers.\\ - * 0: Not synchronize\\ - * 1: Synchronize\\ + * Configures whether or not to synchronize registers. + * 0: Not synchronize + * 1: Synchronize */ uint32_t reg_update:1; uint32_t reserved_1:31; diff --git a/components/soc/esp32c5/register/soc/uhci_reg.h b/components/soc/esp32c5/register/soc/uhci_reg.h index 15b6e1bb5d..b7cee20910 100644 --- a/components/soc/esp32c5/register/soc/uhci_reg.h +++ b/components/soc/esp32c5/register/soc/uhci_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** UHCI_CONF0_REG register * UHCI configuration register */ -#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) /** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; * Write 1 and then write 0 to reset the decoder state machine. */ @@ -30,57 +30,56 @@ extern "C" { #define UHCI_RX_RST_V 0x00000001U #define UHCI_RX_RST_S 1 /** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7; - * Configures to select which uart to connect with UHCI.\\ - * 0: UART0\\ - * 1: UART1\\ + * Configures to select which uart to connect with UHCI. + * 0: UART0 + * 1: UART1 */ #define UHCI_UART_SEL 0x00000007U #define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S) #define UHCI_UART_SEL_V 0x00000007U #define UHCI_UART_SEL_S 2 /** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; - * Configures whether or not to separate the data frame with a special character.\\ - * 0: Not separate\\ - * 1: Separate\\ + * Configures whether or not to separate the data frame with a special character. + * 0: Not separate + * 1: Separate */ #define UHCI_SEPER_EN (BIT(5)) #define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) #define UHCI_SEPER_EN_V 0x00000001U #define UHCI_SEPER_EN_S 5 /** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; - * Configures whether or not to encode the data packet with a formatting header.\\ - * 0: Not use formatting header\\ - * 1: Use formatting header\\ + * Configures whether or not to encode the data packet with a formatting header. + * 0: Not use formatting header + * 1: Use formatting header */ #define UHCI_HEAD_EN (BIT(6)) #define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) #define UHCI_HEAD_EN_V 0x00000001U #define UHCI_HEAD_EN_S 6 /** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable the reception of the 16-bit CRC.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the reception of the 16-bit CRC. + * 0: Disable + * 1: Enable */ #define UHCI_CRC_REC_EN (BIT(7)) #define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) #define UHCI_CRC_REC_EN_V 0x00000001U #define UHCI_CRC_REC_EN_S 7 /** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to stop receiving data when UART is idle.\\ - * 0: Not stop\\ - * 1: Stop\\ + * Configures whether or not to stop receiving data when UART is idle. + * 0: Not stop + * 1: Stop */ #define UHCI_UART_IDLE_EOF_EN (BIT(8)) #define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) #define UHCI_UART_IDLE_EOF_EN_V 0x00000001U #define UHCI_UART_IDLE_EOF_EN_S 8 /** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; - * Configures when the UHCI decoder stops receiving data.\\ - * 0: Stops after receiving 0xC0\\ + * Configures when the UHCI decoder stops receiving data. + * 0: Stops after receiving 0xC0 * 1: Stops when the number of received data bytes reach the specified value. When * UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI - * packet header. when UHCI_HEAD_EN is 0, the specified value is the configured - * value.\\ + * packet header. when UHCI_HEAD_EN is 0, the specified value is the configured value. */ #define UHCI_LEN_EOF_EN (BIT(9)) #define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) @@ -88,18 +87,18 @@ extern "C" { #define UHCI_LEN_EOF_EN_S 9 /** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; * Configures whether or not to enable data integrity check by appending a 16 bit - * CCITT-CRC to the end of the data.\\ - * 0: Disable\\ - * 1: Enable\\ + * CCITT-CRC to the end of the data. + * 0: Disable + * 1: Enable */ #define UHCI_ENCODE_CRC_EN (BIT(10)) #define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) #define UHCI_ENCODE_CRC_EN_V 0x00000001U #define UHCI_ENCODE_CRC_EN_S 10 /** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; - * Configures clock gating.\\ - * 0: Support clock only when the application writes registers.\\ - * 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ #define UHCI_CLK_EN (BIT(11)) #define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) @@ -107,9 +106,9 @@ extern "C" { #define UHCI_CLK_EN_S 11 /** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; * Configures whether or not to stop UHCI from receiving data after UART has received - * a NULL frame.\\ - * 0: Not stop\\ - * 1: Stop\\ + * a NULL frame. + * 0: Not stop + * 1: Stop */ #define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) #define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) @@ -119,7 +118,7 @@ extern "C" { /** UHCI_INT_RAW_REG register * Raw interrupt status */ -#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) /** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt status of UHCI_RX_START_INT. */ @@ -187,7 +186,7 @@ extern "C" { /** UHCI_INT_ST_REG register * Masked interrupt status */ -#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) /** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status of UHCI_RX_START_INT. */ @@ -255,7 +254,7 @@ extern "C" { /** UHCI_INT_ENA_REG register * Interrupt enable bits */ -#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xc) +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) /** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; * Write 1 to enable UHCI_RX_START_INT. */ @@ -323,7 +322,7 @@ extern "C" { /** UHCI_INT_CLR_REG register * Interrupt clear bits */ -#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) /** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear UHCI_RX_START_INT. */ @@ -391,12 +390,12 @@ extern "C" { /** UHCI_CONF1_REG register * UHCI configuration register */ -#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) /** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; * Configures whether or not to enable header checksum validation when UHCI receives a - * data packet.\\ - * 0: Disable\\ - * 1: Enable\\ + * data packet. + * 0: Disable + * 1: Enable */ #define UHCI_CHECK_SUM_EN (BIT(0)) #define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) @@ -404,19 +403,19 @@ extern "C" { #define UHCI_CHECK_SUM_EN_S 0 /** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; * Configures whether or not to enable the sequence number check when UHCI receives a - * data packet.\\ - * 0: Disable\\ - * 1: Enable\\ + * data packet. + * 0: Disable + * 1: Enable */ #define UHCI_CHECK_SEQ_EN (BIT(1)) #define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) #define UHCI_CHECK_SEQ_EN_V 0x00000001U #define UHCI_CHECK_SEQ_EN_S 1 /** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable CRC calculation.\\ - * 0: Disable\\ - * 1: Enable\\ - * Valid only when the Data Integrity Check Present bit in UHCI packet is 1.\\ + * Configures whether or not to enable CRC calculation. + * 0: Disable + * 1: Enable + * Valid only when the Data Integrity Check Present bit in UHCI packet is 1. */ #define UHCI_CRC_DISABLE (BIT(2)) #define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) @@ -424,18 +423,18 @@ extern "C" { #define UHCI_CRC_DISABLE_S 2 /** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; * Configures whether or not to save the packet header when UHCI receives a data - * packet.\\ - * 0: Not save\\ - * 1: Save\\ + * packet. + * 0: Not save + * 1: Save */ #define UHCI_SAVE_HEAD (BIT(3)) #define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) #define UHCI_SAVE_HEAD_V 0x00000001U #define UHCI_SAVE_HEAD_S 3 /** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; - * Configures whether or not to encode the data packet with a checksum.\\ - * 0: Not use checksum\\ - * 1: Use checksum\\ + * Configures whether or not to encode the data packet with a checksum. + * 0: Not use checksum + * 1: Use checksum */ #define UHCI_TX_CHECK_SUM_RE (BIT(4)) #define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) @@ -443,19 +442,18 @@ extern "C" { #define UHCI_TX_CHECK_SUM_RE_S 4 /** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; * Configures whether or not to encode the data packet with an acknowledgment when a - * reliable packet is to be transmitted.\\ - * 0: Not use acknowledgement\\ - * 1: Use acknowledgement\\ + * reliable packet is to be transmitted. + * 0: Not use acknowledgement + * 1: Use acknowledgement */ #define UHCI_TX_ACK_NUM_RE (BIT(5)) #define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) #define UHCI_TX_ACK_NUM_RE_V 0x00000001U #define UHCI_TX_ACK_NUM_RE_S 5 /** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; - * Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT - * state.\\ - * 0: No\\ - * 1: Yes\\ + * Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state. + * 0: No + * 1: Yes */ #define UHCI_WAIT_SW_START (BIT(7)) #define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) @@ -472,17 +470,17 @@ extern "C" { /** UHCI_STATE0_REG register * UHCI receive status */ -#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) /** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; - * Represents the error type when DMA has received a packet with error.\\ - * 0: Invalid. No effect\\ - * 1: Checksum error in the HCI packet\\ - * 2: Sequence number error in the HCI packet\\ - * 3: CRC bit error in the HCI packet\\ + * Represents the error type when DMA has received a packet with error. + * 0: Invalid. No effect + * 1: Checksum error in the HCI packet + * 2: Sequence number error in the HCI packet + * 3: CRC bit error in the HCI packet * 4: 0xC0 is found but the received HCI packet is not complete\ - * 5: 0xC0 is not found when the HCI packet has been received\\ - * 6: CRC check error\\ - * 7: Invalid. No effect\\ + * 5: 0xC0 is not found when the HCI packet has been received + * 6: CRC check error + * 7: Invalid. No effect */ #define UHCI_RX_ERR_CAUSE 0x00000007U #define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) @@ -499,7 +497,7 @@ extern "C" { /** UHCI_STATE1_REG register * UHCI transmit status */ -#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1c) +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) /** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; * Represents the UHCI encoder status. */ @@ -511,20 +509,20 @@ extern "C" { /** UHCI_ESCAPE_CONF_REG register * Escape character configuration */ -#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) /** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; - * Configures whether or not to decode character 0xC0 when DMA receives data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * Configures whether or not to decode character 0xC0 when DMA receives data. + * 0: Not decode + * 1: Decode */ #define UHCI_TX_C0_ESC_EN (BIT(0)) #define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) #define UHCI_TX_C0_ESC_EN_V 0x00000001U #define UHCI_TX_C0_ESC_EN_S 0 /** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; - * Configures whether or not to decode character 0xDB when DMA receives data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * Configures whether or not to decode character 0xDB when DMA receives data. + * 0: Not decode + * 1: Decode */ #define UHCI_TX_DB_ESC_EN (BIT(1)) #define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) @@ -532,9 +530,9 @@ extern "C" { #define UHCI_TX_DB_ESC_EN_S 1 /** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; * Configures whether or not to decode flow control character 0x11 when DMA receives - * data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * data. + * 0: Not decode + * 1: Decode */ #define UHCI_TX_11_ESC_EN (BIT(2)) #define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) @@ -542,29 +540,27 @@ extern "C" { #define UHCI_TX_11_ESC_EN_S 2 /** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; * Configures whether or not to decode flow control character 0x13 when DMA receives - * data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * data. + * 0: Not decode + * 1: Decode */ #define UHCI_TX_13_ESC_EN (BIT(3)) #define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) #define UHCI_TX_13_ESC_EN_V 0x00000001U #define UHCI_TX_13_ESC_EN_S 3 /** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; - * Configures whether or not to replace 0xC0 by special characters when DMA sends - * data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * Configures whether or not to replace 0xC0 by special characters when DMA sends data. + * 0: Not replace + * 1: Replace */ #define UHCI_RX_C0_ESC_EN (BIT(4)) #define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) #define UHCI_RX_C0_ESC_EN_V 0x00000001U #define UHCI_RX_C0_ESC_EN_S 4 /** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; - * Configures whether or not to replace 0xDB by special characters when DMA sends - * data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * Configures whether or not to replace 0xDB by special characters when DMA sends data. + * 0: Not replace + * 1: Replace */ #define UHCI_RX_DB_ESC_EN (BIT(5)) #define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) @@ -572,9 +568,9 @@ extern "C" { #define UHCI_RX_DB_ESC_EN_S 5 /** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; * Configures whether or not to replace flow control character 0x11 by special - * characters when DMA sends data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * characters when DMA sends data. + * 0: Not replace + * 1: Replace */ #define UHCI_RX_11_ESC_EN (BIT(6)) #define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) @@ -582,9 +578,9 @@ extern "C" { #define UHCI_RX_11_ESC_EN_S 6 /** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; * Configures whether or not to replace flow control character 0x13 by special - * characters when DMA sends data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * characters when DMA sends data. + * 0: Not replace + * 1: Replace */ #define UHCI_RX_13_ESC_EN (BIT(7)) #define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) @@ -594,9 +590,10 @@ extern "C" { /** UHCI_HUNG_CONF_REG register * Timeout configuration */ -#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) /** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; - * Configures the timeout value for DMA data reception.\\Measurement unit: ms. + * Configures the timeout value for DMA data reception. + * Measurement unit: ms. */ #define UHCI_TXFIFO_TIMEOUT 0x000000FFU #define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) @@ -610,16 +607,17 @@ extern "C" { #define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U #define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 /** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; - * Configures whether or not to enable the data reception timeout for TX FIFO.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the data reception timeout for TX FIFO. + * 0: Disable + * 1: Enable */ #define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) #define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) #define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U #define UHCI_TXFIFO_TIMEOUT_ENA_S 11 /** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; - * Configures the timeout value for DMA to read data from RAM.\\Measurement unit: ms. + * Configures the timeout value for DMA to read data from RAM. + * Measurement unit: ms. */ #define UHCI_RXFIFO_TIMEOUT 0x000000FFU #define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) @@ -633,9 +631,9 @@ extern "C" { #define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U #define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 /** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; - * Configures whether or not to enable the DMA data transmission timeout.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the DMA data transmission timeout. + * 0: Disable + * 1: Enable */ #define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) #define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) @@ -645,7 +643,7 @@ extern "C" { /** UHCI_ACK_NUM_REG register * UHCI ACK number configuration */ -#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) /** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; * Configures the number of acknowledgements used in software flow control. */ @@ -654,9 +652,9 @@ extern "C" { #define UHCI_ACK_NUM_V 0x00000007U #define UHCI_ACK_NUM_S 0 /** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; - * Configures whether or not load acknowledgements.\\ - * 0: Not load\\ - * 1: Load\\ + * Configures whether or not load acknowledgements. + * 0: Not load + * 1: Load */ #define UHCI_ACK_NUM_LOAD (BIT(3)) #define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) @@ -666,7 +664,7 @@ extern "C" { /** UHCI_RX_HEAD_REG register * UHCI packet header register */ -#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2c) +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) /** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; * Represents the header of the current received packet. */ @@ -678,17 +676,17 @@ extern "C" { /** UHCI_QUICK_SENT_REG register * UHCI quick send configuration register */ -#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) /** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; - * Configures the source of data to be transmitted in single_send mode.\\ - * 0: Q0 register\\ - * 1: Q1 register\\ - * 2: Q2 register\\ - * 3: Q3 register\\ - * 4: Q4 register\\ - * 5: Q5 register\\ - * 6: Q6 register\\ - * 7: Invalid. No effect\\ + * Configures the source of data to be transmitted in single_send mode. + * 0: Q0 register + * 1: Q1 register + * 2: Q2 register + * 3: Q3 register + * 4: Q4 register + * 5: Q5 register + * 6: Q6 register + * 7: Invalid. No effect */ #define UHCI_SINGLE_SEND_NUM 0x00000007U #define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) @@ -702,24 +700,24 @@ extern "C" { #define UHCI_SINGLE_SEND_EN_V 0x00000001U #define UHCI_SINGLE_SEND_EN_S 3 /** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; - * Configures the source of data to be transmitted in always_send mode.\\ - * 0: Q0 register\\ - * 1: Q1 register\\ - * 2: Q2 register\\ - * 3: Q3 register\\ - * 4: Q4 register\\ - * 5: Q5 register\\ - * 6: Q6 register\\ - * 7: Invalid. No effect\\ + * Configures the source of data to be transmitted in always_send mode. + * 0: Q0 register + * 1: Q1 register + * 2: Q2 register + * 3: Q3 register + * 4: Q4 register + * 5: Q5 register + * 6: Q6 register + * 7: Invalid. No effect */ #define UHCI_ALWAYS_SEND_NUM 0x00000007U #define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) #define UHCI_ALWAYS_SEND_NUM_V 0x00000007U #define UHCI_ALWAYS_SEND_NUM_S 4 /** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable always_send mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable always_send mode. + * 0: Disable + * 1: Enable */ #define UHCI_ALWAYS_SEND_EN (BIT(7)) #define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) @@ -729,7 +727,7 @@ extern "C" { /** UHCI_REG_Q0_WORD0_REG register * Q0 WORD0 quick send register */ -#define UHCI_REG_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) /** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q0 register. */ @@ -741,7 +739,7 @@ extern "C" { /** UHCI_REG_Q0_WORD1_REG register * Q0 WORD1 quick send register */ -#define UHCI_REG_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) /** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q0 register. */ @@ -753,7 +751,7 @@ extern "C" { /** UHCI_REG_Q1_WORD0_REG register * Q1 WORD0 quick send register */ -#define UHCI_REG_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3c) +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) /** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q1 register. */ @@ -765,7 +763,7 @@ extern "C" { /** UHCI_REG_Q1_WORD1_REG register * Q1 WORD1 quick send register */ -#define UHCI_REG_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) /** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q1 register. */ @@ -777,7 +775,7 @@ extern "C" { /** UHCI_REG_Q2_WORD0_REG register * Q2 WORD0 quick send register */ -#define UHCI_REG_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) /** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q2 register. */ @@ -789,7 +787,7 @@ extern "C" { /** UHCI_REG_Q2_WORD1_REG register * Q2 WORD1 quick send register */ -#define UHCI_REG_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) /** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q2 register. */ @@ -801,7 +799,7 @@ extern "C" { /** UHCI_REG_Q3_WORD0_REG register * Q3 WORD0 quick send register */ -#define UHCI_REG_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4c) +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) /** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q3 register. */ @@ -813,7 +811,7 @@ extern "C" { /** UHCI_REG_Q3_WORD1_REG register * Q3 WORD1 quick send register */ -#define UHCI_REG_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) /** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q3 register. */ @@ -825,7 +823,7 @@ extern "C" { /** UHCI_REG_Q4_WORD0_REG register * Q4 WORD0 quick send register */ -#define UHCI_REG_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) /** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q4 register. */ @@ -837,7 +835,7 @@ extern "C" { /** UHCI_REG_Q4_WORD1_REG register * Q4 WORD1 quick send register */ -#define UHCI_REG_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) /** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q4 register. */ @@ -849,7 +847,7 @@ extern "C" { /** UHCI_REG_Q5_WORD0_REG register * Q5 WORD0 quick send register */ -#define UHCI_REG_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5c) +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) /** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q5 register. */ @@ -861,7 +859,7 @@ extern "C" { /** UHCI_REG_Q5_WORD1_REG register * Q5 WORD1 quick send register */ -#define UHCI_REG_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) /** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q5 register. */ @@ -873,7 +871,7 @@ extern "C" { /** UHCI_REG_Q6_WORD0_REG register * Q6 WORD0 quick send register */ -#define UHCI_REG_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) /** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q6 register. */ @@ -885,7 +883,7 @@ extern "C" { /** UHCI_REG_Q6_WORD1_REG register * Q6 WORD1 quick register */ -#define UHCI_REG_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) /** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; * Data to be transmitted in Q6 register. */ @@ -897,7 +895,7 @@ extern "C" { /** UHCI_ESC_CONF0_REG register * Escape sequence configuration register 0 */ -#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6c) +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) /** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; * Configures separators to encode data packets. The default value is 0xC0. */ @@ -923,7 +921,7 @@ extern "C" { /** UHCI_ESC_CONF1_REG register * Escape sequence configuration register 1 */ -#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) /** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; * Configures the character that needs to be encoded. The default value is 0xDB used * as the first character of SLIP escape sequence. @@ -950,7 +948,7 @@ extern "C" { /** UHCI_ESC_CONF2_REG register * Escape sequence configuration register 2 */ -#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) /** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; * Configures a character that need to be encoded. The default value is 0x11 used as a * flow control character. @@ -977,7 +975,7 @@ extern "C" { /** UHCI_ESC_CONF3_REG register * Escape sequence configuration register 3 */ -#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) /** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; * Configures the character that needs to be decoded. The default value is 0x13 used * as a flow control character. @@ -1004,10 +1002,11 @@ extern "C" { /** UHCI_PKT_THRES_REG register * Configuration register for packet length */ -#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7c) +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) /** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; - * Configures the maximum value of the packet length.\\Measurement unit: byte.\\Valid - * only when UHCI_HEAD_EN is 0. + * Configures the maximum value of the packet length. + * Measurement unit: byte. + * Valid only when UHCI_HEAD_EN is 0. */ #define UHCI_PKT_THRS 0x00001FFFU #define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) @@ -1017,7 +1016,7 @@ extern "C" { /** UHCI_DATE_REG register * UHCI version control register */ -#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) /** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; * Version control register. */ diff --git a/components/soc/esp32c5/register/soc/uhci_struct.h b/components/soc/esp32c5/register/soc/uhci_struct.h index 3cd1699930..9737beddff 100644 --- a/components/soc/esp32c5/register/soc/uhci_struct.h +++ b/components/soc/esp32c5/register/soc/uhci_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,62 +25,61 @@ typedef union { */ uint32_t rx_rst:1; /** uart_sel : R/W; bitpos: [4:2]; default: 7; - * Configures to select which uart to connect with UHCI.\\ - * 0: UART0\\ - * 1: UART1\\ + * Configures to select which uart to connect with UHCI. + * 0: UART0 + * 1: UART1 */ uint32_t uart_sel:3; /** seper_en : R/W; bitpos: [5]; default: 1; - * Configures whether or not to separate the data frame with a special character.\\ - * 0: Not separate\\ - * 1: Separate\\ + * Configures whether or not to separate the data frame with a special character. + * 0: Not separate + * 1: Separate */ uint32_t seper_en:1; /** head_en : R/W; bitpos: [6]; default: 1; - * Configures whether or not to encode the data packet with a formatting header.\\ - * 0: Not use formatting header\\ - * 1: Use formatting header\\ + * Configures whether or not to encode the data packet with a formatting header. + * 0: Not use formatting header + * 1: Use formatting header */ uint32_t head_en:1; /** crc_rec_en : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable the reception of the 16-bit CRC.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the reception of the 16-bit CRC. + * 0: Disable + * 1: Enable */ uint32_t crc_rec_en:1; /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to stop receiving data when UART is idle.\\ - * 0: Not stop\\ - * 1: Stop\\ + * Configures whether or not to stop receiving data when UART is idle. + * 0: Not stop + * 1: Stop */ uint32_t uart_idle_eof_en:1; /** len_eof_en : R/W; bitpos: [9]; default: 1; - * Configures when the UHCI decoder stops receiving data.\\ - * 0: Stops after receiving 0xC0\\ + * Configures when the UHCI decoder stops receiving data. + * 0: Stops after receiving 0xC0 * 1: Stops when the number of received data bytes reach the specified value. When * UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI - * packet header. when UHCI_HEAD_EN is 0, the specified value is the configured - * value.\\ + * packet header. when UHCI_HEAD_EN is 0, the specified value is the configured value. */ uint32_t len_eof_en:1; /** encode_crc_en : R/W; bitpos: [10]; default: 1; * Configures whether or not to enable data integrity check by appending a 16 bit - * CCITT-CRC to the end of the data.\\ - * 0: Disable\\ - * 1: Enable\\ + * CCITT-CRC to the end of the data. + * 0: Disable + * 1: Enable */ uint32_t encode_crc_en:1; /** clk_en : R/W; bitpos: [11]; default: 0; - * Configures clock gating.\\ - * 0: Support clock only when the application writes registers.\\ - * 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ uint32_t clk_en:1; /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; * Configures whether or not to stop UHCI from receiving data after UART has received - * a NULL frame.\\ - * 0: Not stop\\ - * 1: Stop\\ + * a NULL frame. + * 0: Not stop + * 1: Stop */ uint32_t uart_rx_brk_eof_en:1; uint32_t reserved_13:19; @@ -95,51 +94,50 @@ typedef union { struct { /** check_sum_en : R/W; bitpos: [0]; default: 1; * Configures whether or not to enable header checksum validation when UHCI receives a - * data packet.\\ - * 0: Disable\\ - * 1: Enable\\ + * data packet. + * 0: Disable + * 1: Enable */ uint32_t check_sum_en:1; /** check_seq_en : R/W; bitpos: [1]; default: 1; * Configures whether or not to enable the sequence number check when UHCI receives a - * data packet.\\ - * 0: Disable\\ - * 1: Enable\\ + * data packet. + * 0: Disable + * 1: Enable */ uint32_t check_seq_en:1; /** crc_disable : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable CRC calculation.\\ - * 0: Disable\\ - * 1: Enable\\ - * Valid only when the Data Integrity Check Present bit in UHCI packet is 1.\\ + * Configures whether or not to enable CRC calculation. + * 0: Disable + * 1: Enable + * Valid only when the Data Integrity Check Present bit in UHCI packet is 1. */ uint32_t crc_disable:1; /** save_head : R/W; bitpos: [3]; default: 0; * Configures whether or not to save the packet header when UHCI receives a data - * packet.\\ - * 0: Not save\\ - * 1: Save\\ + * packet. + * 0: Not save + * 1: Save */ uint32_t save_head:1; /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; - * Configures whether or not to encode the data packet with a checksum.\\ - * 0: Not use checksum\\ - * 1: Use checksum\\ + * Configures whether or not to encode the data packet with a checksum. + * 0: Not use checksum + * 1: Use checksum */ uint32_t tx_check_sum_re:1; /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; * Configures whether or not to encode the data packet with an acknowledgment when a - * reliable packet is to be transmitted.\\ - * 0: Not use acknowledgement\\ - * 1: Use acknowledgement\\ + * reliable packet is to be transmitted. + * 0: Not use acknowledgement + * 1: Use acknowledgement */ uint32_t tx_ack_num_re:1; uint32_t reserved_6:1; /** wait_sw_start : R/W; bitpos: [7]; default: 0; - * Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT - * state.\\ - * 0: No\\ - * 1: Yes\\ + * Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state. + * 0: No + * 1: Yes */ uint32_t wait_sw_start:1; /** sw_start : WT; bitpos: [8]; default: 0; @@ -157,57 +155,55 @@ typedef union { typedef union { struct { /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to decode character 0xC0 when DMA receives data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * Configures whether or not to decode character 0xC0 when DMA receives data. + * 0: Not decode + * 1: Decode */ uint32_t tx_c0_esc_en:1; /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; - * Configures whether or not to decode character 0xDB when DMA receives data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * Configures whether or not to decode character 0xDB when DMA receives data. + * 0: Not decode + * 1: Decode */ uint32_t tx_db_esc_en:1; /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; * Configures whether or not to decode flow control character 0x11 when DMA receives - * data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * data. + * 0: Not decode + * 1: Decode */ uint32_t tx_11_esc_en:1; /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; * Configures whether or not to decode flow control character 0x13 when DMA receives - * data.\\ - * 0: Not decode\\ - * 1: Decode\\ + * data. + * 0: Not decode + * 1: Decode */ uint32_t tx_13_esc_en:1; /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; - * Configures whether or not to replace 0xC0 by special characters when DMA sends - * data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * Configures whether or not to replace 0xC0 by special characters when DMA sends data. + * 0: Not replace + * 1: Replace */ uint32_t rx_c0_esc_en:1; /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; - * Configures whether or not to replace 0xDB by special characters when DMA sends - * data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * Configures whether or not to replace 0xDB by special characters when DMA sends data. + * 0: Not replace + * 1: Replace */ uint32_t rx_db_esc_en:1; /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; * Configures whether or not to replace flow control character 0x11 by special - * characters when DMA sends data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * characters when DMA sends data. + * 0: Not replace + * 1: Replace */ uint32_t rx_11_esc_en:1; /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; * Configures whether or not to replace flow control character 0x13 by special - * characters when DMA sends data.\\ - * 0: Not replace\\ - * 1: Replace\\ + * characters when DMA sends data. + * 0: Not replace + * 1: Replace */ uint32_t rx_13_esc_en:1; uint32_t reserved_8:24; @@ -221,7 +217,8 @@ typedef union { typedef union { struct { /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; - * Configures the timeout value for DMA data reception.\\Measurement unit: ms. + * Configures the timeout value for DMA data reception. + * Measurement unit: ms. */ uint32_t txfifo_timeout:8; /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; @@ -229,13 +226,14 @@ typedef union { */ uint32_t txfifo_timeout_shift:3; /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; - * Configures whether or not to enable the data reception timeout for TX FIFO.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the data reception timeout for TX FIFO. + * 0: Disable + * 1: Enable */ uint32_t txfifo_timeout_ena:1; /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; - * Configures the timeout value for DMA to read data from RAM.\\Measurement unit: ms. + * Configures the timeout value for DMA to read data from RAM. + * Measurement unit: ms. */ uint32_t rxfifo_timeout:8; /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; @@ -243,9 +241,9 @@ typedef union { */ uint32_t rxfifo_timeout_shift:3; /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; - * Configures whether or not to enable the DMA data transmission timeout.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable the DMA data transmission timeout. + * 0: Disable + * 1: Enable */ uint32_t rxfifo_timeout_ena:1; uint32_t reserved_24:8; @@ -263,9 +261,9 @@ typedef union { */ uint32_t ack_num:3; /** ack_num_load : WT; bitpos: [3]; default: 0; - * Configures whether or not load acknowledgements.\\ - * 0: Not load\\ - * 1: Load\\ + * Configures whether or not load acknowledgements. + * 0: Not load + * 1: Load */ uint32_t ack_num_load:1; uint32_t reserved_4:28; @@ -279,15 +277,15 @@ typedef union { typedef union { struct { /** single_send_num : R/W; bitpos: [2:0]; default: 0; - * Configures the source of data to be transmitted in single_send mode.\\ - * 0: Q0 register\\ - * 1: Q1 register\\ - * 2: Q2 register\\ - * 3: Q3 register\\ - * 4: Q4 register\\ - * 5: Q5 register\\ - * 6: Q6 register\\ - * 7: Invalid. No effect\\ + * Configures the source of data to be transmitted in single_send mode. + * 0: Q0 register + * 1: Q1 register + * 2: Q2 register + * 3: Q3 register + * 4: Q4 register + * 5: Q5 register + * 6: Q6 register + * 7: Invalid. No effect */ uint32_t single_send_num:3; /** single_send_en : WT; bitpos: [3]; default: 0; @@ -295,21 +293,21 @@ typedef union { */ uint32_t single_send_en:1; /** always_send_num : R/W; bitpos: [6:4]; default: 0; - * Configures the source of data to be transmitted in always_send mode.\\ - * 0: Q0 register\\ - * 1: Q1 register\\ - * 2: Q2 register\\ - * 3: Q3 register\\ - * 4: Q4 register\\ - * 5: Q5 register\\ - * 6: Q6 register\\ - * 7: Invalid. No effect\\ + * Configures the source of data to be transmitted in always_send mode. + * 0: Q0 register + * 1: Q1 register + * 2: Q2 register + * 3: Q3 register + * 4: Q4 register + * 5: Q5 register + * 6: Q6 register + * 7: Invalid. No effect */ uint32_t always_send_num:3; /** always_send_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable always_send mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable always_send mode. + * 0: Disable + * 1: Enable */ uint32_t always_send_en:1; uint32_t reserved_8:24; @@ -596,8 +594,9 @@ typedef union { typedef union { struct { /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; - * Configures the maximum value of the packet length.\\Measurement unit: byte.\\Valid - * only when UHCI_HEAD_EN is 0. + * Configures the maximum value of the packet length. + * Measurement unit: byte. + * Valid only when UHCI_HEAD_EN is 0. */ uint32_t pkt_thrs:13; uint32_t reserved_13:19; @@ -799,15 +798,15 @@ typedef union { typedef union { struct { /** rx_err_cause : RO; bitpos: [2:0]; default: 0; - * Represents the error type when DMA has received a packet with error.\\ - * 0: Invalid. No effect\\ - * 1: Checksum error in the HCI packet\\ - * 2: Sequence number error in the HCI packet\\ - * 3: CRC bit error in the HCI packet\\ + * Represents the error type when DMA has received a packet with error. + * 0: Invalid. No effect + * 1: Checksum error in the HCI packet + * 2: Sequence number error in the HCI packet + * 3: CRC bit error in the HCI packet * 4: 0xC0 is found but the received HCI packet is not complete\ - * 5: 0xC0 is not found when the HCI packet has been received\\ - * 6: CRC check error\\ - * 7: Invalid. No effect\\ + * 5: 0xC0 is not found when the HCI packet has been received + * 6: CRC check error + * 7: Invalid. No effect */ uint32_t rx_err_cause:3; /** decode_state : RO; bitpos: [5:3]; default: 0; diff --git a/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h index 255d08ed4b..38026437b9 100644 --- a/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -640,6 +640,14 @@ extern "C" { #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16)) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16 /** USB_SERIAL_JTAG_TEST_REG register * Registers used for debugging the PHY. @@ -1215,7 +1223,7 @@ extern "C" { * Date register */ #define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368; +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37777456; * register version. */ #define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h index 603db37ff6..f88fa50ca7 100644 --- a/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,8 @@ typedef union { * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * how many data is received, then read data from UART Rx FIFO. */ - uint32_t rdwr_byte:32; + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } usb_serial_jtag_ep1_reg_t; @@ -115,7 +116,12 @@ typedef union { * through GPIO Matrix. */ uint32_t usb_jtag_bridge_en:1; - uint32_t reserved_16:16; + /** usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ + uint32_t usb_phy_tx_edge_sel:1; + uint32_t reserved_17:15; }; uint32_t val; } usb_serial_jtag_conf0_reg_t; @@ -925,7 +931,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36770368; + /** date : R/W; bitpos: [31:0]; default: 37777456; * register version. */ uint32_t date:32; diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h index 1898e1a90e..d5ca03b414 100644 --- a/components/soc/esp32h4/include/soc/reg_base.h +++ b/components/soc/esp32h4/include/soc/reg_base.h @@ -51,7 +51,7 @@ #define DR_REG_INTMTX1_BASE 0x6009B000 #define DR_REG_HP_SYSTEM_BASE 0x6009C000 #define DR_REG_HP_APM_BASE 0x6009D000 -#define DR_REG_CPU_APM_REG_BASE 0x6009E000 +#define DR_REG_CPU_APM_BASE 0x6009E000 #define DR_REG_TEE_BASE 0x6009F000 #define DR_REG_KEYMNG_BASE 0x600A5000 #define DR_REG_AES_BASE 0x600A6000 diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld index 30eb4fa702..68d51cbf84 100644 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -50,7 +50,7 @@ PROVIDE ( INTMTX0 = 0x6009A000 ); PROVIDE ( INTMTX1 = 0x6009B000 ); PROVIDE ( HP_SYSTEM = 0x6009C000 ); PROVIDE ( HP_APM = 0x6009D000 ); -PROVIDE ( CPU_APM_REG = 0x6009E000 ); +PROVIDE ( CPU_APM = 0x6009E000 ); PROVIDE ( TEE = 0x6009F000 ); PROVIDE ( KEYMNG = 0x600A5000 ); PROVIDE ( AES = 0x600A6000 ); diff --git a/components/soc/esp32h4/register/soc/cpu_apm_reg.h b/components/soc/esp32h4/register/soc/cpu_apm_reg.h index 715a98171e..a670134ce6 100644 --- a/components/soc/esp32h4/register/soc/cpu_apm_reg.h +++ b/components/soc/esp32h4/register/soc/cpu_apm_reg.h @@ -14,7 +14,7 @@ extern "C" { /** CPU_APM_REGION_FILTER_EN_REG register * Region filter enable register */ -#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_BASE + 0x0) +#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) /** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; * Configure bit $n (0-7) to enable region $n. * 0: disable @@ -28,7 +28,7 @@ extern "C" { /** CPU_APM_REGION0_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_BASE + 0x4) +#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4) /** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 0. */ @@ -54,7 +54,7 @@ extern "C" { /** CPU_APM_REGION0_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_BASE + 0x8) +#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8) /** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 0. */ @@ -80,7 +80,7 @@ extern "C" { /** CPU_APM_REGION0_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_BASE + 0xc) +#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) /** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 0. */ @@ -155,7 +155,7 @@ extern "C" { /** CPU_APM_REGION1_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_BASE + 0x10) +#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10) /** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 1. */ @@ -181,7 +181,7 @@ extern "C" { /** CPU_APM_REGION1_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_BASE + 0x14) +#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14) /** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 1. */ @@ -207,7 +207,7 @@ extern "C" { /** CPU_APM_REGION1_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_BASE + 0x18) +#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) /** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 1. */ @@ -282,7 +282,7 @@ extern "C" { /** CPU_APM_REGION2_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_BASE + 0x1c) +#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c) /** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 2. */ @@ -308,7 +308,7 @@ extern "C" { /** CPU_APM_REGION2_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_BASE + 0x20) +#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20) /** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 2. */ @@ -334,7 +334,7 @@ extern "C" { /** CPU_APM_REGION2_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_BASE + 0x24) +#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) /** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 2. */ @@ -409,7 +409,7 @@ extern "C" { /** CPU_APM_REGION3_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_BASE + 0x28) +#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28) /** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 3. */ @@ -435,7 +435,7 @@ extern "C" { /** CPU_APM_REGION3_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_BASE + 0x2c) +#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c) /** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 3. */ @@ -461,7 +461,7 @@ extern "C" { /** CPU_APM_REGION3_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_BASE + 0x30) +#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) /** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 3. */ @@ -536,7 +536,7 @@ extern "C" { /** CPU_APM_REGION4_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_BASE + 0x34) +#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34) /** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 4. */ @@ -562,7 +562,7 @@ extern "C" { /** CPU_APM_REGION4_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_BASE + 0x38) +#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38) /** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 4. */ @@ -588,7 +588,7 @@ extern "C" { /** CPU_APM_REGION4_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_BASE + 0x3c) +#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) /** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 4. */ @@ -663,7 +663,7 @@ extern "C" { /** CPU_APM_REGION5_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_BASE + 0x40) +#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40) /** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 5. */ @@ -689,7 +689,7 @@ extern "C" { /** CPU_APM_REGION5_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_BASE + 0x44) +#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44) /** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 5. */ @@ -715,7 +715,7 @@ extern "C" { /** CPU_APM_REGION5_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_BASE + 0x48) +#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) /** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 5. */ @@ -790,7 +790,7 @@ extern "C" { /** CPU_APM_REGION6_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_BASE + 0x4c) +#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c) /** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 6. */ @@ -816,7 +816,7 @@ extern "C" { /** CPU_APM_REGION6_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_BASE + 0x50) +#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50) /** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 6. */ @@ -842,7 +842,7 @@ extern "C" { /** CPU_APM_REGION6_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_BASE + 0x54) +#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) /** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 6. */ @@ -917,7 +917,7 @@ extern "C" { /** CPU_APM_REGION7_ADDR_START_REG register * Region address register */ -#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_BASE + 0x58) +#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58) /** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; * Low 12 bit, start address of region 7. */ @@ -943,7 +943,7 @@ extern "C" { /** CPU_APM_REGION7_ADDR_END_REG register * Region address register */ -#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_BASE + 0x5c) +#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c) /** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; * Low 12 bit, end address of region 7. */ @@ -969,7 +969,7 @@ extern "C" { /** CPU_APM_REGION7_ATTR_REG register * Region access authority attribute register */ -#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_BASE + 0x60) +#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) /** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 7. */ @@ -1044,7 +1044,7 @@ extern "C" { /** CPU_APM_FUNC_CTRL_REG register * APM function control register */ -#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_BASE + 0xc4) +#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) /** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; * PMS M0 function enable */ @@ -1077,7 +1077,7 @@ extern "C" { /** CPU_APM_M0_STATUS_REG register * M0 status register */ -#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_BASE + 0xc8) +#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) /** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1091,7 +1091,7 @@ extern "C" { /** CPU_APM_M0_STATUS_CLR_REG register * M0 status clear register */ -#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xcc) +#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) /** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1103,7 +1103,7 @@ extern "C" { /** CPU_APM_M0_EXCEPTION_INFO0_REG register * M0 exception_info0 register */ -#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xd0) +#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) /** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1129,7 +1129,7 @@ extern "C" { /** CPU_APM_M0_EXCEPTION_INFO1_REG register * M0 exception_info1 register */ -#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xd4) +#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) /** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1141,7 +1141,7 @@ extern "C" { /** CPU_APM_M1_STATUS_REG register * M1 status register */ -#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_BASE + 0xd8) +#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) /** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1155,7 +1155,7 @@ extern "C" { /** CPU_APM_M1_STATUS_CLR_REG register * M1 status clear register */ -#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xdc) +#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) /** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1167,7 +1167,7 @@ extern "C" { /** CPU_APM_M1_EXCEPTION_INFO0_REG register * M1 exception_info0 register */ -#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xe0) +#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) /** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1193,7 +1193,7 @@ extern "C" { /** CPU_APM_M1_EXCEPTION_INFO1_REG register * M1 exception_info1 register */ -#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xe4) +#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) /** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1205,7 +1205,7 @@ extern "C" { /** CPU_APM_M2_STATUS_REG register * M2 status register */ -#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_BASE + 0xe8) +#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_APM_BASE + 0xe8) /** CPU_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1219,7 +1219,7 @@ extern "C" { /** CPU_APM_M2_STATUS_CLR_REG register * M2 status clear register */ -#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xec) +#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xec) /** CPU_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1231,7 +1231,7 @@ extern "C" { /** CPU_APM_M2_EXCEPTION_INFO0_REG register * M2 exception_info0 register */ -#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xf0) +#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xf0) /** CPU_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1257,7 +1257,7 @@ extern "C" { /** CPU_APM_M2_EXCEPTION_INFO1_REG register * M2 exception_info1 register */ -#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xf4) +#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xf4) /** CPU_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1269,7 +1269,7 @@ extern "C" { /** CPU_APM_M3_STATUS_REG register * M3 status register */ -#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_BASE + 0xf8) +#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_APM_BASE + 0xf8) /** CPU_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1283,7 +1283,7 @@ extern "C" { /** CPU_APM_M3_STATUS_CLR_REG register * M3 status clear register */ -#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xfc) +#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xfc) /** CPU_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1295,7 +1295,7 @@ extern "C" { /** CPU_APM_M3_EXCEPTION_INFO0_REG register * M3 exception_info0 register */ -#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0x100) +#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0x100) /** CPU_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1321,7 +1321,7 @@ extern "C" { /** CPU_APM_M3_EXCEPTION_INFO1_REG register * M3 exception_info1 register */ -#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0x104) +#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0x104) /** CPU_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1333,7 +1333,7 @@ extern "C" { /** CPU_APM_INT_EN_REG register * APM interrupt enable register */ -#define CPU_APM_INT_EN_REG (DR_REG_CPU_BASE + 0x118) +#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) /** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; * Configures to enable APM M0 interrupt. * 0: disable @@ -1374,7 +1374,7 @@ extern "C" { /** CPU_APM_CLOCK_GATE_REG register * Clock gating register */ -#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_BASE + 0x7f8) +#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) /** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: enable automatic clock gating @@ -1388,7 +1388,7 @@ extern "C" { /** CPU_APM_DATE_REG register * Version control register */ -#define CPU_APM_DATE_REG (DR_REG_CPU_BASE + 0x7fc) +#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x7fc) /** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37769360; * Version control register. */ diff --git a/components/soc/esp32h4/register/soc/cpu_apm_struct.h b/components/soc/esp32h4/register/soc/cpu_apm_struct.h index 0ddf09dabc..3b2e323616 100644 --- a/components/soc/esp32h4/register/soc/cpu_apm_struct.h +++ b/components/soc/esp32h4/register/soc/cpu_apm_struct.h @@ -567,7 +567,7 @@ typedef struct { volatile cpu_apm_date_reg_t apm_date; } cpu_dev_t; -extern cpu_dev_t CPU_APM_REG; +extern cpu_dev_t CPU_APM; #ifndef __cplusplus _Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");