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bugfix: esprv_intc_int_set_type should not use bitmap parameter

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This commit is contained in:
wuzhenghui
2022-10-14 15:33:53 +08:00
parent 488c79a003
commit 0fd3824f91
5 changed files with 5 additions and 5 deletions
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2
components/esp_hw_support/port/esp32c3/esp_memprot.c
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@ -629,7 +629,7 @@ static esp_err_t esp_mprot_set_intr_matrix(const esp_mprot_mem_t mem_type)
} }
/* Set the type and priority to cache error interrupts. */ /* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_MEMPROT_ERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_type(ETS_MEMPROT_ERR_INUM, INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM); ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM);

2
components/esp_system/port/soc/esp32c3/cache_err_int.c
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@ -58,7 +58,7 @@ void esp_cache_err_int_init(void)
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */ /* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
/* On the hardware side, stat by clearing all the bits reponsible for /* On the hardware side, stat by clearing all the bits reponsible for

2
components/esp_system/port/soc/esp32h2/cache_err_int.c
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@ -58,7 +58,7 @@ void esp_cache_err_int_init(void)
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */ /* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
/* On the hardware side, stat by clearing all the bits reponsible for /* On the hardware side, stat by clearing all the bits reponsible for

2
components/hal/esp32c3/include/hal/interrupt_controller_ll.h
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@ -124,7 +124,7 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level)
*/ */
static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
{ {
esprv_intc_int_set_type(BIT(intr), type); esprv_intc_int_set_type(intr, type);
} }
#ifdef __cplusplus #ifdef __cplusplus

2
components/hal/esp32h2/include/hal/interrupt_controller_ll.h
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@ -124,7 +124,7 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level)
*/ */
static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
{ {
esprv_intc_int_set_type(BIT(intr), type); esprv_intc_int_set_type(intr, type);
} }
#ifdef __cplusplus #ifdef __cplusplus