diff --git a/components/hal/esp8684/include/hal/adc_ll.h b/components/hal/esp8684/include/hal/adc_ll.h index 87c5f56098..7421ec7a7b 100644 --- a/components/hal/esp8684/include/hal/adc_ll.h +++ b/components/hal/esp8684/include/hal/adc_ll.h @@ -98,12 +98,13 @@ typedef struct { */ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) { - // Internal FSM reset wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); - // Internal FSM start wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); - // Internal FSM standby wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); + abort(); //TODO IDF-3908 + // // Internal FSM reset wait time + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); + // // Internal FSM start wait time + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); + // // Internal FSM standby wait time + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); } /** @@ -115,9 +116,10 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa */ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) { - /* Should be called before writing I2C registers. */ - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); + abort(); //TODO IDF-3908 + // /* Should be called before writing I2C registers. */ + // SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); } /** @@ -128,8 +130,9 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) */ static inline void adc_ll_digi_set_clk_div(uint32_t div) { - /* ADC clock devided from digital controller clock clk */ - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); + abort(); //TODO IDF-3908 + // /* ADC clock devided from digital controller clock clk */ + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); } /** @@ -140,7 +143,8 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div) */ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); + abort(); //TODO IDF-3908 + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); } /** @@ -149,7 +153,8 @@ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) */ static inline void adc_ll_digi_convert_limit_enable(void) { - APB_SARADC.ctrl2.meas_num_limit = 1; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl2.meas_num_limit = 1; } /** @@ -158,7 +163,8 @@ static inline void adc_ll_digi_convert_limit_enable(void) */ static inline void adc_ll_digi_convert_limit_disable(void) { - APB_SARADC.ctrl2.meas_num_limit = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl2.meas_num_limit = 0; } /** @@ -184,7 +190,8 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) */ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) { - APB_SARADC.ctrl.sar_patt_len = patt_len - 1; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl.sar_patt_len = patt_len - 1; } /** @@ -199,16 +206,17 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_ */ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) { - uint32_t tab; - uint8_t index = pattern_index / 4; - uint8_t offset = (pattern_index % 4) * 6; - adc_ll_digi_pattern_table_t pattern = {0}; + abort(); //TODO IDF-3908 + // uint32_t tab; + // uint8_t index = pattern_index / 4; + // uint8_t offset = (pattern_index % 4) * 6; + // adc_ll_digi_pattern_table_t pattern = {0}; - pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); - tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value - tab &= (~(0xFC0000 >> offset)); // Clear old data - tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data - APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back + // pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); + // tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value + // tab &= (~(0xFC0000 >> offset)); // Clear old data + // tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + // APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back } /** @@ -218,8 +226,9 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa */ static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) { - APB_SARADC.ctrl.sar_patt_p_clear = 1; - APB_SARADC.ctrl.sar_patt_p_clear = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl.sar_patt_p_clear = 1; + // APB_SARADC.ctrl.sar_patt_p_clear = 0; } /** @@ -230,7 +239,8 @@ static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) */ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) { - APB_SARADC.ctrl.wait_arb_cycle = cycle; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl.wait_arb_cycle = cycle; } /** @@ -241,11 +251,12 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) */ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) { - if (adc_n == ADC_NUM_1) { - APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert - } else { // adc_n == ADC_NUM_2 - APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert - } + abort(); //TODO IDF-3908 + // if (adc_n == ADC_NUM_1) { + // APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert + // } else { // adc_n == ADC_NUM_2 + // APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert + // } } /** @@ -257,7 +268,8 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) */ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) { - APB_SARADC.ctrl2.timer_target = cycle; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl2.timer_target = cycle; } /** @@ -265,7 +277,8 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) */ static inline void adc_ll_digi_trigger_enable(void) { - APB_SARADC.ctrl2.timer_en = 1; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl2.timer_en = 1; } /** @@ -273,7 +286,8 @@ static inline void adc_ll_digi_trigger_enable(void) */ static inline void adc_ll_digi_trigger_disable(void) { - APB_SARADC.ctrl2.timer_en = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl2.timer_en = 0; } /** @@ -286,9 +300,10 @@ static inline void adc_ll_digi_trigger_disable(void) */ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) { - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); - APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; - APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; + abort(); //TODO IDF-3908 + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); + // APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; + // APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; } /** @@ -298,12 +313,13 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div */ static inline void adc_ll_digi_clk_sel(bool use_apll) { - if (use_apll) { - APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock - } else { - APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; // APB clock - } - APB_SARADC.ctrl.sar_clk_gated = 1; + abort(); //TODO IDF-3908 + // if (use_apll) { + // APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock + // } else { + // APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; // APB clock + // } + // APB_SARADC.ctrl.sar_clk_gated = 1; } /** @@ -311,7 +327,8 @@ static inline void adc_ll_digi_clk_sel(bool use_apll) */ static inline void adc_ll_digi_controller_clk_disable(void) { - APB_SARADC.ctrl.sar_clk_gated = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.ctrl.sar_clk_gated = 0; } /** @@ -321,7 +338,8 @@ static inline void adc_ll_digi_controller_clk_disable(void) */ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) { - APB_SARADC.filter_ctrl0.filter_reset = 1; + abort(); //TODO IDF-3908 + // APB_SARADC.filter_ctrl0.filter_reset = 1; } /** @@ -333,13 +351,14 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) */ static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) { - if (idx == ADC_DIGI_FILTER_IDX0) { - APB_SARADC.filter_ctrl0.filter_channel0 = (filter->adc_unit << 3) | (filter->channel & 0x7); - APB_SARADC.filter_ctrl1.filter_factor0 = filter->mode; - } else if (idx == ADC_DIGI_FILTER_IDX1) { - APB_SARADC.filter_ctrl0.filter_channel1 = (filter->adc_unit << 3) | (filter->channel & 0x7); - APB_SARADC.filter_ctrl1.filter_factor1 = filter->mode; - } + abort(); //TODO IDF-3908 + // if (idx == ADC_DIGI_FILTER_IDX0) { + // APB_SARADC.filter_ctrl0.filter_channel0 = (filter->adc_unit << 3) | (filter->channel & 0x7); + // APB_SARADC.filter_ctrl1.filter_factor0 = filter->mode; + // } else if (idx == ADC_DIGI_FILTER_IDX1) { + // APB_SARADC.filter_ctrl0.filter_channel1 = (filter->adc_unit << 3) | (filter->channel & 0x7); + // APB_SARADC.filter_ctrl1.filter_factor1 = filter->mode; + // } } /** @@ -350,15 +369,16 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_ */ static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) { - if (idx == ADC_DIGI_FILTER_IDX0) { - filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel0 >> 3) & 0x1; - filter->channel = APB_SARADC.filter_ctrl0.filter_channel0 & 0x7; - filter->mode = APB_SARADC.filter_ctrl1.filter_factor0; - } else if (idx == ADC_DIGI_FILTER_IDX1) { - filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel1 >> 3) & 0x1; - filter->channel = APB_SARADC.filter_ctrl0.filter_channel1 & 0x7; - filter->mode = APB_SARADC.filter_ctrl1.filter_factor1; - } + abort(); //TODO IDF-3908 + // if (idx == ADC_DIGI_FILTER_IDX0) { + // filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel0 >> 3) & 0x1; + // filter->channel = APB_SARADC.filter_ctrl0.filter_channel0 & 0x7; + // filter->mode = APB_SARADC.filter_ctrl1.filter_factor0; + // } else if (idx == ADC_DIGI_FILTER_IDX1) { + // filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel1 >> 3) & 0x1; + // filter->channel = APB_SARADC.filter_ctrl0.filter_channel1 & 0x7; + // filter->mode = APB_SARADC.filter_ctrl1.filter_factor1; + // } } /** @@ -370,13 +390,14 @@ static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_ */ static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx) { - if (idx == ADC_DIGI_FILTER_IDX0) { - APB_SARADC.filter_ctrl0.filter_channel0 = 0xF; - APB_SARADC.filter_ctrl1.filter_factor0 = 0; - } else if (idx == ADC_DIGI_FILTER_IDX1) { - APB_SARADC.filter_ctrl0.filter_channel1 = 0xF; - APB_SARADC.filter_ctrl1.filter_factor1 = 0; - } + abort(); //TODO IDF-3908 + // if (idx == ADC_DIGI_FILTER_IDX0) { + // APB_SARADC.filter_ctrl0.filter_channel0 = 0xF; + // APB_SARADC.filter_ctrl1.filter_factor0 = 0; + // } else if (idx == ADC_DIGI_FILTER_IDX1) { + // APB_SARADC.filter_ctrl0.filter_channel1 = 0xF; + // APB_SARADC.filter_ctrl1.filter_factor1 = 0; + // } } /** @@ -389,15 +410,16 @@ static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx) */ static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg) { - if (idx == ADC_DIGI_MONITOR_IDX0) { - APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); - APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold; - APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold; - } else { // ADC_DIGI_MONITOR_IDX1 - APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); - APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold; - APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold; - } + abort(); //TODO IDF-3908 + // if (idx == ADC_DIGI_MONITOR_IDX0) { + // APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + // APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold; + // APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold; + // } else { // ADC_DIGI_MONITOR_IDX1 + // APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + // APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold; + // APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold; + // } } /** @@ -408,11 +430,12 @@ static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_ */ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) { - if (idx == ADC_DIGI_MONITOR_IDX0) { - APB_SARADC.thres0_ctrl.thres0_channel = 0xF; - } else { // ADC_DIGI_MONITOR_IDX1 - APB_SARADC.thres1_ctrl.thres1_channel = 0xF; - } + abort(); //TODO IDF-3908 + // if (idx == ADC_DIGI_MONITOR_IDX0) { + // APB_SARADC.thres0_ctrl.thres0_channel = 0xF; + // } else { // ADC_DIGI_MONITOR_IDX1 + // APB_SARADC.thres1_ctrl.thres1_channel = 0xF; + // } } /** @@ -423,7 +446,8 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) */ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); + abort(); //TODO IDF-3908 + // HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); } /** @@ -431,7 +455,8 @@ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) */ static inline void adc_ll_digi_dma_enable(void) { - APB_SARADC.dma_conf.apb_adc_trans = 1; + abort(); //TODO IDF-3908 + // APB_SARADC.dma_conf.apb_adc_trans = 1; } /** @@ -439,7 +464,8 @@ static inline void adc_ll_digi_dma_enable(void) */ static inline void adc_ll_digi_dma_disable(void) { - APB_SARADC.dma_conf.apb_adc_trans = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.dma_conf.apb_adc_trans = 0; } /** @@ -447,8 +473,9 @@ static inline void adc_ll_digi_dma_disable(void) */ static inline void adc_ll_digi_reset(void) { - APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; - APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; + abort(); //TODO IDF-3908 + // APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; + // APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; } /*--------------------------------------------------------------- @@ -462,8 +489,9 @@ static inline void adc_ll_digi_reset(void) */ static inline void adc_ll_pwdet_set_cct(uint32_t cct) { - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; + abort(); //TODO IDF-3908 + // /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + // RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; } /** @@ -474,8 +502,9 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct) */ static inline uint32_t adc_ll_pwdet_get_cct(void) { - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; + abort(); //TODO IDF-3908 + // /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + // return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; } /** @@ -490,16 +519,17 @@ static inline uint32_t adc_ll_pwdet_get_cct(void) */ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) { - if (adc_n == ADC_NUM_1) { - return ADC_RTC_DATA_OK; - } + abort(); //TODO IDF-3908 + // if (adc_n == ADC_NUM_1) { + // return ADC_RTC_DATA_OK; + // } - //The raw data API returns value without channel information. Read value directly from the register - if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { - return ADC_RTC_DATA_FAIL; - } + // //The raw data API returns value without channel information. Read value directly from the register + // if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { + // return ADC_RTC_DATA_FAIL; + // } - return ADC_RTC_DATA_OK; + // return ADC_RTC_DATA_OK; } /*--------------------------------------------------------------- @@ -512,18 +542,19 @@ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, */ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) { - /* Bit1 0:Fsm 1: SW mode - Bit0 0:SW mode power down 1: SW mode power on */ - if (manage == ADC_POWER_SW_ON) { - APB_SARADC.ctrl.sar_clk_gated = 1; - APB_SARADC.ctrl.xpd_sar_force = 3; - } else if (manage == ADC_POWER_BY_FSM) { - APB_SARADC.ctrl.sar_clk_gated = 1; - APB_SARADC.ctrl.xpd_sar_force = 0; - } else if (manage == ADC_POWER_SW_OFF) { - APB_SARADC.ctrl.sar_clk_gated = 0; - APB_SARADC.ctrl.xpd_sar_force = 2; - } + abort(); //TODO IDF-3908 + // /* Bit1 0:Fsm 1: SW mode + // Bit0 0:SW mode power down 1: SW mode power on */ + // if (manage == ADC_POWER_SW_ON) { + // APB_SARADC.ctrl.sar_clk_gated = 1; + // APB_SARADC.ctrl.xpd_sar_force = 3; + // } else if (manage == ADC_POWER_BY_FSM) { + // APB_SARADC.ctrl.sar_clk_gated = 1; + // APB_SARADC.ctrl.xpd_sar_force = 0; + // } else if (manage == ADC_POWER_SW_OFF) { + // APB_SARADC.ctrl.sar_clk_gated = 0; + // APB_SARADC.ctrl.xpd_sar_force = 2; + // } } static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) @@ -543,15 +574,16 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t */ static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) { - if (mode == ADC_ARB_MODE_FIX) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; - } else if (mode == ADC_ARB_MODE_LOOP) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter. - } + abort(); //TODO IDF-3908 + // if (mode == ADC_ARB_MODE_FIX) { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; + // } else if (mode == ADC_ARB_MODE_LOOP) { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0; + // } else { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter. + // } } /** @@ -569,33 +601,34 @@ static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) */ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet) { - if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet; - } - /* Should select highest priority controller. */ - if (pri_rtc > pri_dig) { - if (pri_rtc > pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; - } - } else { - if (pri_dig > pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; - } - } + abort(); //TODO IDF-3908 + // if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet; + // } + // /* Should select highest priority controller. */ + // if (pri_rtc > pri_dig) { + // if (pri_rtc > pri_pwdet) { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; + // } else { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; + // } + // } else { + // if (pri_dig > pri_pwdet) { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; + // } else { + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + // APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; + // } + // } } /* ADC calibration code. */ @@ -604,11 +637,12 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, */ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) { - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); - } + abort(); //TODO IDF-3908 + // if (adc_n == ADC_NUM_1) { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); + // } } /** @@ -623,20 +657,21 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) */ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) { - /* Enable/disable internal connect GND (for calibration). */ - if (adc_n == ADC_NUM_1) { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } - } else { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } - } + abort(); //TODO IDF-3908 + // /* Enable/disable internal connect GND (for calibration). */ + // if (adc_n == ADC_NUM_1) { + // if (internal_gnd) { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + // } + // } else { + // if (internal_gnd) { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + // } + // } } /** @@ -646,11 +681,12 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t */ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) { - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } + abort(); //TODO IDF-3908 + // if (adc_n == ADC_NUM_1) { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + // } } /** @@ -662,15 +698,16 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) */ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) { - uint8_t msb = param >> 8; - uint8_t lsb = param & 0xFF; - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); - } + abort(); //TODO IDF-3908 + // uint8_t msb = param >> 8; + // uint8_t lsb = param & 0xFF; + // if (adc_n == ADC_NUM_1) { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); + // } } /* Temp code end. */ @@ -687,45 +724,46 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par */ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) { - if (en) { - REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); + abort(); //TODO IDF-3908 + // if (en) { + // REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); + // SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); - APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; - APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; - APB_SARADC.onetime_sample.adc1_onetime_sample = 1; - APB_SARADC.onetime_sample.onetime_channel = channel; - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); - if (adc == ADC_NUM_1) { - /* Config test mux to route v_ref to ADC1 Channels */ - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); - } else { - /* Config test mux to route v_ref to ADC2 Channels */ - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); - } - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); - APB_SARADC.onetime_sample.adc1_onetime_sample = 0; - APB_SARADC.onetime_sample.onetime_channel = 0xf; - REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); - REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); - } + // REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); + // SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + // SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + // SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + // APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; + // APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; + // APB_SARADC.onetime_sample.adc1_onetime_sample = 1; + // APB_SARADC.onetime_sample.onetime_channel = channel; + // SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + // if (adc == ADC_NUM_1) { + // /* Config test mux to route v_ref to ADC1 Channels */ + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); + // } else { + // /* Config test mux to route v_ref to ADC2 Channels */ + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + // } + // } else { + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + // APB_SARADC.onetime_sample.adc1_onetime_sample = 0; + // APB_SARADC.onetime_sample.onetime_channel = 0xf; + // REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); + // REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); + // CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + // CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + // CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + // } } /*--------------------------------------------------------------- @@ -740,63 +778,74 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b */ static inline void adc_ll_onetime_start(bool val) { - APB_SARADC.onetime_sample.onetime_start = val; + abort(); //TODO IDF-3908 + // APB_SARADC.onetime_sample.onetime_start = val; } static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel) { - APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); + abort(); //TODO IDF-3908 + // APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); } static inline void adc_ll_onetime_set_atten(adc_atten_t atten) { - APB_SARADC.onetime_sample.onetime_atten = atten; + abort(); //TODO IDF-3908 + // APB_SARADC.onetime_sample.onetime_atten = atten; } static inline void adc_ll_intr_enable(adc_ll_intr_t mask) { - APB_SARADC.int_ena.val |= mask; + abort(); //TODO IDF-3908 + // APB_SARADC.int_ena.val |= mask; } static inline void adc_ll_intr_disable(adc_ll_intr_t mask) { - APB_SARADC.int_ena.val &= ~mask; + abort(); //TODO IDF-3908 + // APB_SARADC.int_ena.val &= ~mask; } static inline void adc_ll_intr_clear(adc_ll_intr_t mask) { - APB_SARADC.int_clr.val |= mask; + abort(); //TODO IDF-3908 + // APB_SARADC.int_clr.val |= mask; } static inline bool adc_ll_intr_get_raw(adc_ll_intr_t mask) { - return (APB_SARADC.int_raw.val & mask); + abort(); //TODO IDF-3908 + // return (APB_SARADC.int_raw.val & mask); } static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask) { - return (APB_SARADC.int_st.val & mask); + abort(); //TODO IDF-3908 + // return (APB_SARADC.int_st.val & mask); } static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) { - if (adc_n == ADC_NUM_1) { - APB_SARADC.onetime_sample.adc1_onetime_sample = enable; - } else { - APB_SARADC.onetime_sample.adc2_onetime_sample = enable; - } + abort(); //TODO IDF-3908 + // if (adc_n == ADC_NUM_1) { + // APB_SARADC.onetime_sample.adc1_onetime_sample = enable; + // } else { + // APB_SARADC.onetime_sample.adc2_onetime_sample = enable; + // } } static inline uint32_t adc_ll_adc1_read(void) { - //On ESP8684, valid data width is 12-bit - return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff); + abort(); //TODO IDF-3908 + // //On ESP8684, valid data width is 12-bit + // return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff); } static inline uint32_t adc_ll_adc2_read(void) { - //On ESP8684, valid data width is 12-bit - return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff); + abort(); //TODO IDF-3908 + // //On ESP8684, valid data width is 12-bit + // return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff); } #ifdef __cplusplus