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feat(gpio): update c5 mp gpio docs

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gaoxu
2024-05-13 14:15:20 +08:00
parent 6def5faab5
commit 1138d7d56a
5 changed files with 8 additions and 4 deletions
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2
components/espcoredump/src/core_dump_uart.c
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@@ -154,7 +154,7 @@ static esp_err_t esp_core_dump_uart_hw_init(void)
//Make sure txd/rxd are enabled //Make sure txd/rxd are enabled
// use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled // use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled
REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU); REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU); //TODO: IDF-9948
gpio_hal_func_sel(&gpio_hal, U0RXD_GPIO_NUM, U0RXD_MUX_FUNC); gpio_hal_func_sel(&gpio_hal, U0RXD_GPIO_NUM, U0RXD_MUX_FUNC);
gpio_hal_func_sel(&gpio_hal, U0TXD_GPIO_NUM, U0TXD_MUX_FUNC); gpio_hal_func_sel(&gpio_hal, U0TXD_GPIO_NUM, U0TXD_MUX_FUNC);
ESP_COREDUMP_LOGI("Press Enter to print core dump to UART..."); ESP_COREDUMP_LOGI("Press Enter to print core dump to UART...");

4
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
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@@ -143,6 +143,10 @@ config SOC_BT_SUPPORTED
bool bool
default y default y
config SOC_PM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M config SOC_XTAL_SUPPORT_40M
bool bool
default y default y

2
components/soc/esp32c5/beta3/include/soc/soc_caps.h
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@@ -81,7 +81,7 @@
#define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3 #define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
#define SOC_BT_SUPPORTED 1 #define SOC_BT_SUPPORTED 1
#define SOC_PHY_SUPPORTED 1 #define SOC_PHY_SUPPORTED 1
// #define SOC_PM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8643 #define SOC_PM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/ /*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1 #define SOC_XTAL_SUPPORT_40M 1

2
docs/en/api-reference/peripherals/gpio/esp32c5.inc
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@@ -9,7 +9,7 @@
.. gpio-summary .. gpio-summary
The {IDF_TARGET_NAME} chip features 27 physical GPIO pins (GPIO0 ~ GPIO26). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. The {IDF_TARGET_NAME} chip features 29 physical GPIO pins (GPIO0 ~ GPIO28). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.