From 11760387761c5b54900c2e3544e852ffb1f7e647 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 17 Dec 2024 17:10:02 +0800 Subject: [PATCH] feat(esp32h21): add H21 esp_rom files (stage3) --- .../esp32h2/include/esp32h2/rom/gpio.h | 2 +- .../esp_rom/esp32h21/Kconfig.soc_caps.in | 88 +++ components/esp_rom/esp32h21/esp_rom_caps.h | 29 + .../esp32h21/include/esp32h21/rom/.gitkeep | 0 .../esp32h21/include/esp32h21/rom/cache.h | 610 ++++++++++++++++++ .../esp32h21/include/esp32h21/rom/ecdsa.h | 28 + .../esp32h21/include/esp32h21/rom/efuse.h | 283 ++++++++ .../esp32h21/include/esp32h21/rom/esp_flash.h | 46 ++ .../esp32h21/include/esp32h21/rom/ets_sys.h | 428 ++++++++++++ .../esp32h21/include/esp32h21/rom/gpio.h | 212 ++++++ .../esp32h21/include/esp32h21/rom/hmac.h | 54 ++ .../include/esp32h21/rom/libc_stubs.h | 94 +++ .../include/esp32h21/rom/rom_layout.h | 97 +++ .../esp32h21/include/esp32h21/rom/rsa_pss.h | 37 ++ .../esp32h21/include/esp32h21/rom/rtc.h | 249 +++++++ .../include/esp32h21/rom/secure_boot.h | 135 ++++ .../esp32h21/include/esp32h21/rom/sha.h | 52 ++ .../esp32h21/include/esp32h21/rom/spi_flash.h | 460 +++++++++++++ .../esp32h21/include/esp32h21/rom/uart.h | 349 ++++++++++ .../esp_rom/esp32h21/ld/esp32h21.rom.api.ld | 63 ++ .../esp_rom/esp32h21/ld/esp32h21.rom.heap.ld | 79 +++ .../esp_rom/esp32h21/ld/esp32h21.rom.ld | 381 +++++++++++ .../esp32h21/ld/esp32h21.rom.libgcc.ld | 112 ++++ .../esp32h21/ld/esp32h21.rom.newlib-nano.ld | 32 + .../esp32h21/ld/esp32h21.rom.newlib.ld | 99 +++ .../esp32h21/ld/esp32h21.rom.spiflash.ld | 166 +++++ .../esp32h21/ld/esp32h21.rom.systimer.ld | 27 + .../esp32h21/ld/esp32h21.rom.version.ld | 15 + .../esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld | 27 + .../esp_rom/include/esp_rom_libc_stubs.h | 2 + components/esp_rom/patches/esp_rom_systimer.c | 2 +- 31 files changed, 4256 insertions(+), 2 deletions(-) create mode 100644 components/esp_rom/esp32h21/Kconfig.soc_caps.in create mode 100644 components/esp_rom/esp32h21/esp_rom_caps.h delete mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/cache.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/secure_boot.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/sha.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/uart.h create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld diff --git a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h index 5829765c60..acd5bac6ca 100644 --- a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h +++ b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h @@ -84,7 +84,7 @@ uint32_t gpio_input_get(void); */ void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); -/** +/**c * @brief disable GPIOs to wakeup the ESP32. * Please do not call this function in SDK. * diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in new file mode 100644 index 0000000000..bd28ce6cab --- /dev/null +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -0,0 +1,88 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_HAL_WDT + bool + default y + +config ESP_ROM_HAS_HAL_SYSTIMER + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y + +config ESP_ROM_HAS_NEWLIB + bool + default y + +config ESP_ROM_HAS_NEWLIB_NANO_FORMAT + bool + default y + +config ESP_ROM_WDT_INIT_PATCH + bool + default y + +config ESP_ROM_RAM_APP_NEEDS_MMU_INIT + bool + default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y + +config ESP_ROM_USB_OTG_NUM + int + default -1 + +config ESP_ROM_HAS_VERSION + bool + default y + +config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB + bool + default y + +config ESP_ROM_HAS_OUTPUT_PUTC_FUNC + bool + default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h new file mode 100644 index 0000000000..936d777b1f --- /dev/null +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs +#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included +#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions +#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions +#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. +#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information +#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. +#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep b/components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h new file mode 100644 index 0000000000..eafc044bc4 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h @@ -0,0 +1,610 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11525 + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 16384 +#define MIN_ICACHE_WAYS 2 +#define MAX_ICACHE_WAYS 2 +#define MAX_CACHE_WAYS 2 +#define MIN_CACHE_LINE_SIZE 32 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 1 +#define CACHE_MEMORY_BANK_NUM 1 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +typedef enum { + MMU_PAGE_MODE_64KB = 0, + MMU_PAGE_MODE_32KB = 1, + MMU_PAGE_MODE_16KB = 2, + MMU_PAGE_MODE_8KB = 3, + MMU_PAGE_MODE_INVALID, +} mmu_page_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid:1; /*!< the tag item is valid or not */ + uint32_t lock:1; /*!< the cache line is locked or not */ + uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ + uint32_t reserved:14; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +struct cache_internal_stub_table { + uint32_t (* icache_line_size)(void); + uint32_t (* icache_addr)(uint32_t addr); + uint32_t (* dcache_addr)(uint32_t addr); + void (* invalidate_icache_items)(uint32_t addr, uint32_t items); + void (* lock_icache_items)(uint32_t addr, uint32_t items); + void (* unlock_icache_items)(uint32_t addr, uint32_t items); + uint32_t (* suspend_icache_autoload)(void); + void (* resume_icache_autoload)(uint32_t autoload); + void (* freeze_icache_enable)(cache_freeze_mode_t mode); + void (* freeze_icache_disable)(void); + int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); +}; + +/* Defined in the interface file, default value is rom_default_cache_internal_table */ +extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + +/* Defined in the interface file, default value is NULL */ +extern const cache_op_cb_t* rom_cache_op_cb; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus. + * + * @param None + * + * @return None + */ +void ROM_Boot_Cache_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t senitive : Config this page should apply flash encryption or not + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32h21, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c3, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode * mode); + +/** + * @brief Set cache page mode. + * + * @param mmu_page_mode_t + * + * @return None + */ +void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode); + +/** + * @brief Get cache page mode. + * + * @param None + * + * @return page mode + */ +mmu_page_mode_t MMU_Get_Page_Mode(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config * config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part of a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + +#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ + Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h b/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h new file mode 100644 index 0000000000..f1c785d6f1 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11496 + +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef enum { + ECDSA_CURVE_P192 = 1, + ECDSA_CURVE_P256 = 2 +} ECDSA_CURVE; + +int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h new file mode 100644 index 0000000000..b33df42b71 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +//TODO: [ESP32H21] IDF-11556 + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32H21 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO8 is low when digital reset. + * 2 for uart print when GPIO8 is high when digital reset. + * 3 for uart force silent + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h b/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h new file mode 100644 index 0000000000..6d48e4be2c --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function + just adds ROM-specific parts +*/ + +struct spi_flash_chip_t; +typedef struct esp_flash_t esp_flash_t; + +/* Structure to wrap "global" data used by esp_flash in ROM */ +typedef struct { + /* Default SPI flash chip, ie main chip attached to the MCU + This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL + */ + esp_flash_t *default_chip; + + /* Global API OS notification start/end/chip_check functions + + These are used by ROM if no other host functions are configured. + */ + struct { + esp_err_t (*start)(esp_flash_t *chip); + esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); + esp_err_t (*chip_check)(esp_flash_t **inout_chip); + } api_funcs; +} esp_flash_rom_global_data_t; + +/** Access a pointer to the global data used by the ROM spi_flash driver + */ +esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h b/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h new file mode 100644 index 0000000000..4bb3a16fcf --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h @@ -0,0 +1,428 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include + +//TODO: [ESP32H21] IDF-11555 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + + + + + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< exception cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstract time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + + + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +/** + * @} + */ + +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) + +//TODO: [ESP32H21] IDF-11555, need to check +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h b/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h new file mode 100644 index 0000000000..4fb5a20173 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h @@ -0,0 +1,212 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/gpio_reg.h" + +//TODO: [ESP32H21] IDF-11611 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +//TODO: [ESP32H21] IDF-11611, need check +#define GPIO_FUNC_IN_HIGH 0x20 +#define GPIO_FUNC_IN_LOW 0x30 + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + + +/** + * @brief Change GPIO(0-27) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need disable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-27) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~27 + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~27 + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x80, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @brief disable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_input_disable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h b/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h new file mode 100644 index 0000000000..a98c0119ca --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "efuse.h" + +//TODO: [ESP32H21] IDF-11495 + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h b/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h new file mode 100644 index 0000000000..8b2b9ebd63 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32-H21 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to +set the address + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table +{ + struct _reent* (*__getreent)(void); + void* (*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void*); + void* (*_realloc_r)(struct _reent *r, void*, size_t); + void* (*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char*); + int (*_rename_r)(struct _reent *r, const char*, const char*); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char*); + int (*_link_r)(struct _reent *r, const char*, const char*); + int (*_stat_r)(struct _reent *r, const char*, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void* (*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); +#ifdef _RETARGETABLE_LOCKING + void (*_retarget_lock_init)(_LOCK_T *lock); + void (*_retarget_lock_init_recursive)(_LOCK_T *lock); + void (*_retarget_lock_close)(_LOCK_T lock); + void (*_retarget_lock_close_recursive)(_LOCK_T lock); + void (*_retarget_lock_acquire)(_LOCK_T lock); + void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); + int (*_retarget_lock_try_acquire)(_LOCK_T lock); + int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); + void (*_retarget_lock_release)(_LOCK_T lock); + void (*_retarget_lock_release_recursive)(_LOCK_T lock); +#else + void (*_lock_init)(_lock_t *lock); + void (*_lock_init_recursive)(_lock_t *lock); + void (*_lock_close)(_lock_t *lock); + void (*_lock_close_recursive)(_lock_t *lock); + void (*_lock_acquire)(_lock_t *lock); + void (*_lock_acquire_recursive)(_lock_t *lock); + int (*_lock_try_acquire)(_lock_t *lock); + int (*_lock_try_acquire_recursive)(_lock_t *lock); + void (*_lock_release)(_lock_t *lock); + void (*_lock_release_recursive)(_lock_t *lock); +#endif + int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); + void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn)); + void (*__sinit) (struct _reent *r); + void (*_cleanup_r) (struct _reent* r); +}; + +extern struct syscall_stub_table *syscall_table_ptr; + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h new file mode 100644 index 0000000000..33355b8db8 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +//TODO: [ESP32H21] IDF-11555 + +#ifdef __cplusplus +extern "C" { +#endif + +#define SUPPORT_BTDM 0 +#define SUPPORT_BTBB 0 +#define SUPPORT_WIFI 0 +#define SUPPORT_USB_DWCOTG 0 +#define SUPPORT_COEXIST 0 +#define SUPPORT_MBEDTLS 0 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ +typedef struct { + void *dram0_stack_shared_mem_start; + void *dram0_rtos_reserved_start; + void *stack_sentry; + void *stack; + +#if SUPPORT_BTDM + void *data_start_btdm; + void *data_end_btdm; + void *bss_start_btdm; + void *bss_end_btdm; + void *data_start_btdm_rom; + void *data_end_btdm_rom; + void *data_start_interface_btdm; + void *data_end_interface_btdm; + void *bss_start_interface_btdm; + void *bss_end_interface_btdm; +#endif + +#if SUPPORT_BTBB + void *dram_start_btbbrom; + void *dram_end_btbbrom; +#endif + + /* Other DRAM ranges */ +#if SUPPORT_BTDM || SUPPORT_WIFI + void *dram_start_phyrom; + void *dram_end_phyrom; +#endif +#if SUPPORT_WIFI + void *dram_start_coexist; + void *dram_end_coexist; + void *dram_start_net80211; + void *dram_end_net80211; + void *dram_start_pp; + void *dram_end_pp; + void *data_start_interface_coexist; + void *data_end_interface_coexist; + void *bss_start_interface_coexist; + void *bss_end_interface_coexist; + void *data_start_interface_net80211; + void *data_end_interface_net80211; + void *bss_start_interface_net80211; + void *bss_end_interface_net80211; + void *data_start_interface_pp; + void *data_end_interface_pp; + void *bss_start_interface_pp; + void *bss_end_interface_pp; +#endif + +#if SUPPORT_USB_DWCOTG + void *dram_start_usb_dwcotg_rom; + void *dram_end_usb_dwcotg_rom; +#else + //Two reserved members are defined here, so the structure will not be broken, + //please keep in mind that there is no memory can be released between + //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom. + void *dram_start_usb_reserved_rom; + void *dram_end_usb_reserved_rom; +#endif + + void *dram_start_uart_rom; + void *dram_end_uart_rom; +} ets_rom_layout_t; + +extern const ets_rom_layout_t * const ets_rom_layout_p; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h new file mode 100644 index 0000000000..c8fb830361 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include + +//TODO: [ESP32H21] IDF-11498 + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h new file mode 100644 index 0000000000..4f72fa87e5 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/lp_aon_reg.h" +#include "soc/reset_reasons.h" +#include "esp_assert.h" + +//TODO: [ESP32H21] IDF-11548 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x50000000 Fast 0x4000 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * RTC_CNTL_STORE0_REG Reserved + * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value + * RTC_CNTL_STORE2_REG Boot time, low word + * RTC_CNTL_STORE3_REG Boot time, high word + * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ + +//TODO: [ESP32H21] IDF-1154, need to check from esp_rom +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define ROM_LOG_CTRL_REG LP_AON_STORE4_REG + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. + +typedef enum { + AWAKE = 0, // +#include +#include "ets_sys.h" +#include "ecdsa.h" +#include "rsa_pss.h" +#include "esp_assert.h" + +//TODO: [ESP32H21] IDF-11500 + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Anti-FI measure: use full words for success/fail, instead of + 0/non-zero +*/ +typedef enum { + SB_SUCCESS = 0x3A5A5AA5, + SB_FAILED = 0x7533885E, +} ets_secure_boot_status_t; + +/* Verify bootloader image (reconfigures cache to map), + with key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If stage_load parameter is true, bootloader is copied into staging + buffer in RAM at the same time. + + If result is SB_SUCCESS, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL +*/ +ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access except for RSA peripheral. + + If result is SB_SUCCESS, the image_digest value is copied into verified_digest. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); + +/* Revoke a public key digest in efuse. + @param index Digest to revoke. Must be 0, 1 or 2. + */ +void ets_secure_boot_revoke_public_key_digest(int index); + +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block + + (Up to 3 in a signature sector are appended to the image) + */ +#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME + +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME + +struct __attribute((packed)) ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + struct { + struct { + uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */ + uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */ + } key; + uint8_t signature[64]; /* r followed by s (both little-endian) */ + uint8_t padding[1031]; + } ecdsa; + uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ + uint8_t _padding[16]; +}; +#endif + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); + +#define MAX_KEY_DIGESTS 3 + +struct ets_secure_boot_key_digests { + const void *key_digests[MAX_KEY_DIGESTS]; + bool allow_key_revoke; +}; + +#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h b/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h new file mode 100644 index 0000000000..3f074aeb76 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "ets_sys.h" + +//TODO: [ESP32H21] IDF-11501 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h b/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h new file mode 100644 index 0000000000..6710d80a7a --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h @@ -0,0 +1,460 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "esp_rom_spiflash.h" + +//TODO: [ESP32H21] IDF-11609 + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +typedef void (* spi_flash_func_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); + +typedef struct { + uint8_t pp_addr_bit_len; + uint8_t se_addr_bit_len; + uint8_t be_addr_bit_len; + uint8_t rd_addr_bit_len; + uint32_t read_sub_len; + uint32_t write_sub_len; + spi_flash_op_t unlock; + spi_flash_erase_t erase_sector; + spi_flash_erase_t erase_block; + spi_flash_rd_t read; + spi_flash_wr_t write; + spi_flash_ewr_t encrypt_write; + spi_flash_func_t check_sus; + spi_flash_wren_t wren; + spi_flash_op_t wait_idle; + spi_flash_erase_area_t erase_area; +} spiflash_legacy_funcs_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from flash by rom code, function usually called by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h b/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h new file mode 100644 index 0000000000..0d166cf872 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_types.h" +#include "esp_attr.h" +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11618 + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +//uart int enable register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, include '\0'. + * + * @return OK. + */ +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart received information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld new file mode 100644 index 0000000000..31fced02bc --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char2 ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_output_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_output_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_output_rx_string = UartRxString ); +PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_output_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); + +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); +PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); +PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); + +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); +PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); +PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); +PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); + +PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); +PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); +PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); +PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld new file mode 100644 index 0000000000..57205290d9 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.heap.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +tlsf_create = 0x400003f4; +tlsf_create_with_pool = 0x400003f8; +tlsf_get_pool = 0x400003fc; +tlsf_add_pool = 0x40000400; +tlsf_remove_pool = 0x40000404; +tlsf_malloc = 0x40000408; +tlsf_memalign = 0x4000040c; +tlsf_memalign_offs = 0x40000410; +tlsf_malloc_addr = 0x40000414; +tlsf_realloc = 0x40000418; +tlsf_free = 0x4000041c; +tlsf_block_size = 0x40000420; +tlsf_size = 0x40000424; +tlsf_pool_overhead = 0x40000428; +tlsf_alloc_overhead = 0x4000042c; +tlsf_walk_pool = 0x40000430; +tlsf_check = 0x40000434; +tlsf_check_pool = 0x40000438; +tlsf_poison_fill_pfunc_set = 0x4000043c; +tlsf_poison_check_pfunc_set = 0x40000440; +multi_heap_get_block_address_impl = 0x40000444; +multi_heap_get_allocated_size_impl = 0x40000448; +multi_heap_register_impl = 0x4000044c; +multi_heap_set_lock = 0x40000450; +multi_heap_os_funcs_init = 0x40000454; +multi_heap_internal_lock = 0x40000458; +multi_heap_internal_unlock = 0x4000045c; +multi_heap_get_first_block = 0x40000460; +multi_heap_get_next_block = 0x40000464; +multi_heap_is_free = 0x40000468; +multi_heap_malloc_impl = 0x4000046c; +multi_heap_free_impl = 0x40000470; +multi_heap_realloc_impl = 0x40000474; +multi_heap_aligned_alloc_impl_offs = 0x40000478; +multi_heap_aligned_alloc_impl = 0x4000047c; +multi_heap_check = 0x40000480; +multi_heap_dump = 0x40000484; +multi_heap_free_size_impl = 0x40000488; +multi_heap_minimum_free_size_impl = 0x4000048c; +multi_heap_get_info_impl = 0x40000490; +/* Data (.data, .bss, .rodata) */ +heap_tlsf_table_ptr = 0x4084ffd8; + +PROVIDE (multi_heap_malloc = multi_heap_malloc_impl); +PROVIDE (multi_heap_free = multi_heap_free_impl); +PROVIDE (multi_heap_realloc = multi_heap_realloc_impl); +PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl); +PROVIDE (multi_heap_register = multi_heap_register_impl); +PROVIDE (multi_heap_get_info = multi_heap_get_info_impl); +PROVIDE (multi_heap_free_size = multi_heap_free_size_impl); +PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl); +PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl); +PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl); +PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl); +PROVIDE (multi_heap_check = multi_heap_check); +PROVIDE (multi_heap_set_lock = multi_heap_set_lock); +PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init); +PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock); +PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock); diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld new file mode 100644 index 0000000000..78ef116c3d --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld @@ -0,0 +1,381 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +analog_super_wdt_reset_happened = 0x4000001c; +rtc_get_wakeup_cause = 0x40000020; +rtc_unhold_all_pads = 0x40000024; +ets_printf = 0x40000028; +ets_install_putc1 = 0x4000002c; +ets_install_putc2 = 0x40000030; +ets_install_uart_printf = 0x40000034; +ets_install_usb_printf = 0x40000038; +ets_get_printf_channel = 0x4000003c; +ets_delay_us = 0x40000040; +ets_get_cpu_frequency = 0x40000044; +ets_update_cpu_frequency = 0x40000048; +ets_install_lock = 0x4000004c; +UartRxString = 0x40000050; +UartGetCmdLn = 0x40000054; +uart_tx_one_char = 0x40000058; +uart_tx_one_char2 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +roundup2 = 0x40000088; +multofup = 0x4000008c; +software_reset = 0x40000090; +software_reset_cpu = 0x40000094; +ets_clk_assist_debug_clock_enable = 0x40000098; +clear_super_wdt_reset_flag = 0x4000009c; +disable_default_watchdog = 0x400000a0; +esp_rom_set_rtc_wake_addr = 0x400000a4; +esp_rom_get_rtc_wake_addr = 0x400000a8; +send_packet = 0x400000ac; +recv_packet = 0x400000b0; +GetUartDevice = 0x400000b4; +UartDwnLdProc = 0x400000b8; +GetSecurityInfoProc = 0x400000bc; +Uart_Init = 0x400000c0; +ets_set_user_start = 0x400000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4001fffc; +ets_ops_table_ptr = 0x4084fff8; +g_saved_pc = 0x4084fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000c8; +mz_free = 0x400000cc; +tdefl_compress = 0x400000d0; +tdefl_compress_buffer = 0x400000d4; +tdefl_compress_mem_to_heap = 0x400000d8; +tdefl_compress_mem_to_mem = 0x400000dc; +tdefl_compress_mem_to_output = 0x400000e0; +tdefl_get_adler32 = 0x400000e4; +tdefl_get_prev_return_status = 0x400000e8; +tdefl_init = 0x400000ec; +tdefl_write_image_to_png_file_in_memory = 0x400000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; +tinfl_decompress = 0x400000f8; +tinfl_decompress_mem_to_callback = 0x400000fc; +tinfl_decompress_mem_to_heap = 0x40000100; +tinfl_decompress_mem_to_mem = 0x40000104; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000108; +esp_rom_spiflash_write_encrypted = 0x4000010c; +esp_rom_spiflash_write_encrypted_dest = 0x40000110; +esp_rom_spiflash_write_encrypted_enable = 0x40000114; +esp_rom_spiflash_write_encrypted_disable = 0x40000118; +esp_rom_spiflash_erase_chip = 0x4000011c; +_esp_rom_spiflash_erase_sector = 0x40000120; +_esp_rom_spiflash_erase_block = 0x40000124; +_esp_rom_spiflash_write = 0x40000128; +_esp_rom_spiflash_read = 0x4000012c; +_esp_rom_spiflash_unlock = 0x40000130; +_SPIEraseArea = 0x40000134; +_SPI_write_enable = 0x40000138; +esp_rom_spiflash_erase_sector = 0x4000013c; +esp_rom_spiflash_erase_block = 0x40000140; +esp_rom_spiflash_write = 0x40000144; +esp_rom_spiflash_read = 0x40000148; +esp_rom_spiflash_unlock = 0x4000014c; +SPIEraseArea = 0x40000150; +SPI_write_enable = 0x40000154; +esp_rom_spiflash_config_param = 0x40000158; +esp_rom_spiflash_read_user_cmd = 0x4000015c; +esp_rom_spiflash_select_qio_pins = 0x40000160; +esp_rom_spi_flash_auto_sus_res = 0x40000164; +esp_rom_spi_flash_send_resume = 0x40000168; +esp_rom_spi_flash_update_id = 0x4000016c; +esp_rom_spiflash_config_clk = 0x40000170; +esp_rom_spiflash_config_readmode = 0x40000174; +esp_rom_spiflash_read_status = 0x40000178; +esp_rom_spiflash_read_statushigh = 0x4000017c; +esp_rom_spiflash_write_status = 0x40000180; +spi_cache_mode_switch = 0x40000184; +spi_common_set_dummy_output = 0x40000188; +spi_common_set_flash_cs_timing = 0x4000018c; +esp_rom_spi_set_address_bit_len = 0x40000190; +SPILock = 0x40000194; +SPIMasterReadModeCnfig = 0x40000198; +SPI_Common_Command = 0x4000019c; +SPI_WakeUp = 0x400001a0; +SPI_block_erase = 0x400001a4; +SPI_chip_erase = 0x400001a8; +SPI_init = 0x400001ac; +SPI_page_program = 0x400001b0; +SPI_read_data = 0x400001b4; +SPI_sector_erase = 0x400001b8; +SelectSpiFunction = 0x400001bc; +SetSpiDrvs = 0x400001c0; +Wait_SPI_Idle = 0x400001c4; +spi_dummy_len_fix = 0x400001c8; +Disable_QMode = 0x400001cc; +Enable_QMode = 0x400001d0; +spi_flash_attach = 0x400001d4; +spi_flash_get_chip_size = 0x400001d8; +spi_flash_guard_set = 0x400001dc; +spi_flash_guard_get = 0x400001e0; +spi_flash_read_encrypted = 0x400001e4; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4084fff0; +rom_spiflash_legacy_data = 0x4084ffec; +g_flash_guard_ops = 0x4084fff4; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_ICache_Line_Size = 0x400005f4; +Cache_Get_Mode = 0x400005f8; +Cache_Address_Through_Cache = 0x400005fc; +ROM_Boot_Cache_Init = 0x40000600; +MMU_Set_Page_Mode = 0x40000604; +MMU_Get_Page_Mode = 0x40000608; +Cache_Invalidate_ICache_Items = 0x4000060c; +Cache_Op_Addr = 0x40000610; +Cache_Invalidate_Addr = 0x40000614; +Cache_Invalidate_ICache_All = 0x40000618; +Cache_Mask_All = 0x4000061c; +Cache_UnMask_Dram0 = 0x40000620; +Cache_Suspend_ICache_Autoload = 0x40000624; +Cache_Resume_ICache_Autoload = 0x40000628; +Cache_Start_ICache_Preload = 0x4000062c; +Cache_ICache_Preload_Done = 0x40000630; +Cache_End_ICache_Preload = 0x40000634; +Cache_Config_ICache_Autoload = 0x40000638; +Cache_Enable_ICache_Autoload = 0x4000063c; +Cache_Disable_ICache_Autoload = 0x40000640; +Cache_Enable_ICache_PreLock = 0x40000644; +Cache_Disable_ICache_PreLock = 0x40000648; +Cache_Lock_ICache_Items = 0x4000064c; +Cache_Unlock_ICache_Items = 0x40000650; +Cache_Lock_Addr = 0x40000654; +Cache_Unlock_Addr = 0x40000658; +Cache_Disable_ICache = 0x4000065c; +Cache_Enable_ICache = 0x40000660; +Cache_Suspend_ICache = 0x40000664; +Cache_Resume_ICache = 0x40000668; +Cache_Freeze_ICache_Enable = 0x4000066c; +Cache_Freeze_ICache_Disable = 0x40000670; +Cache_Set_IDROM_MMU_Size = 0x40000674; +Cache_Get_IROM_MMU_End = 0x40000678; +Cache_Get_DROM_MMU_End = 0x4000067c; +Cache_MMU_Init = 0x40000680; +Cache_MSPI_MMU_Set = 0x40000684; +Cache_Travel_Tag_Memory = 0x40000688; +Cache_Get_Virtual_Addr = 0x4000068c; +Cache_MSPI_MMU_Set_Secure = 0x40000690; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4084ffcc; +rom_cache_internal_table_ptr = 0x4084ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x40000694; +ets_clk_get_cpu_freq = 0x40000698; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_input_get = 0x4000069c; +gpio_matrix_in = 0x400006a0; +gpio_matrix_out = 0x400006a4; + +//TODO: [ESP32H21] IDF-11621 +gpio_output_disable = 0x400006a8; +gpio_output_enable = 0x400006ac; + +gpio_output_set = 0x400006b0; +gpio_pad_hold = 0x400006b4; +gpio_pad_input_disable = 0x400006b8; +gpio_pad_input_enable = 0x400006bc; +gpio_pad_pulldown = 0x400006c0; +gpio_pad_pullup = 0x400006c4; +gpio_pad_select_gpio = 0x400006c8; +gpio_pad_set_drv = 0x400006cc; +gpio_pad_unhold = 0x400006d0; +gpio_pin_wakeup_disable = 0x400006d4; +gpio_pin_wakeup_enable = 0x400006d8; +gpio_bypass_matrix_in = 0x400006dc; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x400006e0; +esprv_intc_int_set_threshold = 0x400006e4; +esprv_intc_int_enable = 0x400006e8; +esprv_intc_int_disable = 0x400006ec; +esprv_intc_int_set_type = 0x400006f0; +PROVIDE( intr_handler_set = 0x400006f4 ); +intr_matrix_set = 0x400006f8; +ets_intr_lock = 0x400006fc; +ets_intr_unlock = 0x40000700; +ets_isr_attach = 0x40000704; +ets_isr_mask = 0x40000708; +ets_isr_unmask = 0x4000070c; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000710; +MD5Init = 0x40000714; +MD5Update = 0x40000718; +MD5Final = 0x4000071c; +crc32_le = 0x40000720; +crc16_le = 0x40000724; +crc8_le = 0x40000728; +crc32_be = 0x4000072c; +crc16_be = 0x40000730; +crc8_be = 0x40000734; +esp_crc8 = 0x40000738; +ets_sha_enable = 0x4000073c; +ets_sha_disable = 0x40000740; +ets_sha_get_state = 0x40000744; +ets_sha_init = 0x40000748; +ets_sha_process = 0x4000074c; +ets_sha_starts = 0x40000750; +ets_sha_update = 0x40000754; +ets_sha_finish = 0x40000758; +ets_sha_clone = 0x4000075c; +ets_hmac_enable = 0x40000760; +ets_hmac_disable = 0x40000764; +ets_hmac_calculate_message = 0x40000768; +ets_hmac_calculate_downstream = 0x4000076c; +ets_hmac_invalidate_downstream = 0x40000770; +ets_jtag_enable_temporarily = 0x40000774; +ets_aes_enable = 0x40000778; +ets_aes_disable = 0x4000077c; +ets_aes_setkey = 0x40000780; +ets_aes_block = 0x40000784; +ets_aes_setkey_dec = 0x40000788; +ets_aes_setkey_enc = 0x4000078c; +ets_bigint_enable = 0x40000790; +ets_bigint_disable = 0x40000794; +ets_bigint_multiply = 0x40000798; +ets_bigint_modmult = 0x4000079c; +ets_bigint_modexp = 0x400007a0; +ets_bigint_wait_finish = 0x400007a4; +ets_bigint_getz = 0x400007a8; +ets_ds_enable = 0x400007ac; +ets_ds_disable = 0x400007b0; +ets_ds_start_sign = 0x400007b4; +ets_ds_is_busy = 0x400007b8; +ets_ds_finish_sign = 0x400007bc; +ets_ds_encrypt_params = 0x400007c0; +ets_mgf1_sha256 = 0x400007c4; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4001fff8; +crc16_le_table_ptr = 0x4001fff4; +crc8_le_table_ptr = 0x4001fff0; +crc32_be_table_ptr = 0x4001ffec; +crc16_be_table_ptr = 0x4001ffe8; +crc8_be_table_ptr = 0x4001ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x400007c8; +ets_efuse_program = 0x400007cc; +ets_efuse_clear_program_registers = 0x400007d0; +ets_efuse_write_key = 0x400007d4; +ets_efuse_get_read_register_address = 0x400007d8; +ets_efuse_get_key_purpose = 0x400007dc; +ets_efuse_key_block_unused = 0x400007e0; +ets_efuse_find_unused_key_block = 0x400007e4; +ets_efuse_rs_calculate = 0x400007e8; +ets_efuse_count_unused_key_blocks = 0x400007ec; +ets_efuse_secure_boot_enabled = 0x400007f0; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007f4; +ets_efuse_cache_encryption_enabled = 0x400007f8; +ets_efuse_download_modes_disabled = 0x400007fc; +ets_efuse_find_purpose = 0x40000800; +ets_efuse_force_send_resume = 0x40000804; +ets_efuse_get_flash_delay_us = 0x40000808; +ets_efuse_get_mac = 0x4000080c; +ets_efuse_get_uart_print_control = 0x40000810; +ets_efuse_direct_boot_mode_disabled = 0x40000814; +ets_efuse_security_download_modes_enabled = 0x40000818; +ets_efuse_jtag_disabled = 0x4000081c; +ets_efuse_usb_print_is_disabled = 0x40000820; +ets_efuse_usb_download_mode_disabled = 0x40000824; +ets_efuse_usb_device_disabled = 0x40000828; +ets_efuse_secure_boot_fast_wake_enabled = 0x4000082c; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x40000830; +ets_rsa_pss_verify = 0x40000834; +ets_ecdsa_verify = 0x40000838; +ets_secure_boot_verify_bootloader_with_keys = 0x4000083c; +ets_secure_boot_verify_signature = 0x40000840; +ets_secure_boot_read_key_digests = 0x40000844; +ets_secure_boot_revoke_public_key_digest = 0x40000848; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x400009bc; +usb_serial_device_rx_one_char_block = 0x400009c0; +usb_serial_device_tx_flush = 0x400009c4; +usb_serial_device_tx_one_char = 0x400009c8; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld new file mode 100644 index 0000000000..af79c5322c --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.libgcc.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgcc + ***************************************/ + +/* Functions */ +__absvdi2 = 0x4000084c; +__absvsi2 = 0x40000850; +__adddf3 = 0x40000854; +__addsf3 = 0x40000858; +__addvdi3 = 0x4000085c; +__addvsi3 = 0x40000860; +__ashldi3 = 0x40000864; +__ashrdi3 = 0x40000868; +__bswapdi2 = 0x4000086c; +__bswapsi2 = 0x40000870; +__clear_cache = 0x40000874; +__clrsbdi2 = 0x40000878; +__clrsbsi2 = 0x4000087c; +__clzdi2 = 0x40000880; +__clzsi2 = 0x40000884; +__cmpdi2 = 0x40000888; +__ctzdi2 = 0x4000088c; +__ctzsi2 = 0x40000890; +__divdc3 = 0x40000894; +__divdf3 = 0x40000898; +__divdi3 = 0x4000089c; +__divsc3 = 0x400008a0; +__divsf3 = 0x400008a4; +__divsi3 = 0x400008a8; +__eqdf2 = 0x400008ac; +__eqsf2 = 0x400008b0; +__extendsfdf2 = 0x400008b4; +__ffsdi2 = 0x400008b8; +__ffssi2 = 0x400008bc; +__fixdfdi = 0x400008c0; +__fixdfsi = 0x400008c4; +__fixsfdi = 0x400008c8; +__fixsfsi = 0x400008cc; +__fixunsdfsi = 0x400008d0; +__fixunssfdi = 0x400008d4; +__fixunssfsi = 0x400008d8; +__floatdidf = 0x400008dc; +__floatdisf = 0x400008e0; +__floatsidf = 0x400008e4; +__floatsisf = 0x400008e8; +__floatundidf = 0x400008ec; +__floatundisf = 0x400008f0; +__floatunsidf = 0x400008f4; +__floatunsisf = 0x400008f8; +__gcc_bcmp = 0x400008fc; +__gedf2 = 0x40000900; +__gesf2 = 0x40000904; +__gtdf2 = 0x40000908; +__gtsf2 = 0x4000090c; +__ledf2 = 0x40000910; +__lesf2 = 0x40000914; +__lshrdi3 = 0x40000918; +__ltdf2 = 0x4000091c; +__ltsf2 = 0x40000920; +__moddi3 = 0x40000924; +__modsi3 = 0x40000928; +__muldc3 = 0x4000092c; +__muldf3 = 0x40000930; +__muldi3 = 0x40000934; +__mulsc3 = 0x40000938; +__mulsf3 = 0x4000093c; +__mulsi3 = 0x40000940; +__mulvdi3 = 0x40000944; +__mulvsi3 = 0x40000948; +__nedf2 = 0x4000094c; +__negdf2 = 0x40000950; +__negdi2 = 0x40000954; +__negsf2 = 0x40000958; +__negvdi2 = 0x4000095c; +__negvsi2 = 0x40000960; +__nesf2 = 0x40000964; +__paritysi2 = 0x40000968; +__popcountdi2 = 0x4000096c; +__popcountsi2 = 0x40000970; +__powidf2 = 0x40000974; +__powisf2 = 0x40000978; +__subdf3 = 0x4000097c; +__subsf3 = 0x40000980; +__subvdi3 = 0x40000984; +__subvsi3 = 0x40000988; +__truncdfsf2 = 0x4000098c; +__ucmpdi2 = 0x40000990; +__udivdi3 = 0x40000994; +__udivmoddi4 = 0x40000998; +__udivsi3 = 0x4000099c; +__udiv_w_sdiv = 0x400009a0; +__umoddi3 = 0x400009a4; +__umodsi3 = 0x400009a8; +__unorddf2 = 0x400009ac; +__unordsf2 = 0x400009b0; +__extenddftf2 = 0x400009b4; +__trunctfdf2 = 0x400009b8; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld new file mode 100644 index 0000000000..166c1ce2d7 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.newlib-nano.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_nano_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005c4; +_fiprintf_r = 0x400005c8; +_fprintf_r = 0x400005cc; +_printf_common = 0x400005d0; +_printf_i = 0x400005d4; +_vfiprintf_r = 0x400005d8; +_vfprintf_r = 0x400005dc; +fiprintf = 0x400005e0; +fprintf = 0x400005e4; +printf = 0x400005e8; +vfiprintf = 0x400005ec; +vfprintf = 0x400005f0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld new file mode 100644 index 0000000000..a596f1709c --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.newlib.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x40000494; +memset = 0x40000498; +memcpy = 0x4000049c; +memmove = 0x400004a0; +memcmp = 0x400004a4; +strcpy = 0x400004a8; +strncpy = 0x400004ac; +strcmp = 0x400004b0; +strncmp = 0x400004b4; +strlen = 0x400004b8; +strstr = 0x400004bc; +bzero = 0x400004c0; +_isatty_r = 0x400004c4; +sbrk = 0x400004c8; +isalnum = 0x400004cc; +isalpha = 0x400004d0; +isascii = 0x400004d4; +isblank = 0x400004d8; +iscntrl = 0x400004dc; +isdigit = 0x400004e0; +islower = 0x400004e4; +isgraph = 0x400004e8; +isprint = 0x400004ec; +ispunct = 0x400004f0; +isspace = 0x400004f4; +isupper = 0x400004f8; +toupper = 0x400004fc; +tolower = 0x40000500; +toascii = 0x40000504; +memccpy = 0x40000508; +memchr = 0x4000050c; +memrchr = 0x40000510; +strcasecmp = 0x40000514; +strcasestr = 0x40000518; +strcat = 0x4000051c; +strdup = 0x40000520; +strchr = 0x40000524; +strcspn = 0x40000528; +strcoll = 0x4000052c; +strlcat = 0x40000530; +strlcpy = 0x40000534; +strlwr = 0x40000538; +strncasecmp = 0x4000053c; +strncat = 0x40000540; +strndup = 0x40000544; +strnlen = 0x40000548; +strrchr = 0x4000054c; +strsep = 0x40000550; +strspn = 0x40000554; +strtok_r = 0x40000558; +strupr = 0x4000055c; +longjmp = 0x40000560; +setjmp = 0x40000564; +abs = 0x40000568; +div = 0x4000056c; +labs = 0x40000570; +ldiv = 0x40000574; +qsort = 0x40000578; +rand_r = 0x4000057c; +rand = 0x40000580; +srand = 0x40000584; +utoa = 0x40000588; +itoa = 0x4000058c; +atoi = 0x40000590; +atol = 0x40000594; +strtol = 0x40000598; +strtoul = 0x4000059c; +fflush = 0x400005a0; +_fflush_r = 0x400005a4; +_fwalk = 0x400005a8; +_fwalk_reent = 0x400005ac; +__smakebuf_r = 0x400005b0; +__swhatbuf_r = 0x400005b4; +__swbuf_r = 0x400005b8; +__swbuf = 0x400005bc; +__swsetup_r = 0x400005c0; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4084ffd4; +_global_impure_ptr = 0x4084ffd0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld new file mode 100644 index 0000000000..98106e0405 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.spiflash.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group spi_flash_cache + ***************************************/ + +/* Functions */ +spi_flash_disable_cache = 0x400001e8; +spi_flash_restore_cache = 0x400001ec; +spi_flash_cache_enabled = 0x400001f0; +spi_flash_enable_cache = 0x400001f4; +esp_enable_cache_flash_wrap = 0x400001f8; + + +/*************************************** + Group spi_flash_mmap + ***************************************/ + +/* Functions */ +spi_flash_mmap_os_func_set = 0x400001fc; +spi_flash_mmap_page_num_init = 0x40000200; +spi_flash_mmap = 0x40000204; +spi_flash_mmap_pages = 0x40000208; +spi_flash_munmap = 0x4000020c; +spi_flash_mmap_dump = 0x40000210; +spi_flash_check_and_flush_cache = 0x40000214; +spi_flash_mmap_get_free_pages = 0x40000218; +spi_flash_cache2phys = 0x4000021c; +spi_flash_phys2cache = 0x40000220; + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +esp_flash_chip_driver_initialized = 0x40000224; +esp_flash_read_id = 0x40000228; +esp_flash_get_size = 0x4000022c; +esp_flash_erase_chip = 0x40000230; +esp_flash_erase_region = 0x40000234; +esp_flash_get_chip_write_protect = 0x40000238; +esp_flash_set_chip_write_protect = 0x4000023c; +esp_flash_get_protectable_regions = 0x40000240; +esp_flash_get_protected_region = 0x40000244; +esp_flash_set_protected_region = 0x40000248; +esp_flash_read = 0x4000024c; +esp_flash_write = 0x40000250; +esp_flash_write_encrypted = 0x40000254; +esp_flash_read_encrypted = 0x40000258; +esp_flash_get_io_mode = 0x4000025c; +esp_flash_set_io_mode = 0x40000260; +spi_flash_boot_attach = 0x40000264; +esp_flash_read_chip_id = 0x40000268; +detect_spi_flash_chip = 0x4000026c; +esp_rom_spiflash_write_disable = 0x40000270; +esp_flash_suspend_cmd_init = 0x40000274; +/* Data (.data, .bss, .rodata) */ +esp_flash_default_chip = 0x4084ffe8; +esp_flash_api_funcs = 0x4084ffe4; + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +spi_flash_chip_generic_probe = 0x40000278; +spi_flash_chip_generic_detect_size = 0x4000027c; +spi_flash_chip_generic_write = 0x40000280; +spi_flash_chip_generic_write_encrypted = 0x40000284; +spi_flash_chip_generic_set_write_protect = 0x40000288; +spi_flash_common_write_status_16b_wrsr = 0x4000028c; +spi_flash_chip_generic_reset = 0x40000290; +spi_flash_chip_generic_erase_chip = 0x40000294; +spi_flash_chip_generic_erase_sector = 0x40000298; +spi_flash_chip_generic_erase_block = 0x4000029c; +spi_flash_chip_generic_page_program = 0x400002a0; +spi_flash_chip_generic_get_write_protect = 0x400002a4; +spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002a8; +spi_flash_chip_generic_read_reg = 0x400002ac; +spi_flash_chip_generic_yield = 0x400002b0; +spi_flash_generic_wait_host_idle = 0x400002b4; +spi_flash_chip_generic_wait_idle = 0x400002b8; +spi_flash_chip_generic_config_host_io_mode = 0x400002bc; +spi_flash_chip_generic_read = 0x400002c0; +spi_flash_common_read_status_8b_rdsr2 = 0x400002c4; +spi_flash_chip_generic_get_io_mode = 0x400002c8; +spi_flash_common_read_status_8b_rdsr = 0x400002cc; +spi_flash_common_write_status_8b_wrsr = 0x400002d0; +spi_flash_common_write_status_8b_wrsr2 = 0x400002d4; +spi_flash_common_set_io_mode = 0x400002d8; +spi_flash_chip_generic_set_io_mode = 0x400002dc; +spi_flash_chip_generic_read_unique_id = 0x400002e0; +spi_flash_chip_generic_get_caps = 0x400002e4; +spi_flash_chip_generic_suspend_cmd_conf = 0x400002e8; +spi_flash_chip_gd_get_io_mode = 0x400002ec; +spi_flash_chip_gd_probe = 0x400002f0; +spi_flash_chip_gd_set_io_mode = 0x400002f4; +/* Data (.data, .bss, .rodata) */ +spi_flash_chip_generic_config_data = 0x4084ffe0; +spi_flash_encryption = 0x4084ffdc; + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +memspi_host_read_id_hs = 0x400002f8; +memspi_host_read_status_hs = 0x400002fc; +memspi_host_flush_cache = 0x40000300; +memspi_host_erase_chip = 0x40000304; +memspi_host_erase_sector = 0x40000308; +memspi_host_erase_block = 0x4000030c; +memspi_host_program_page = 0x40000310; +memspi_host_read = 0x40000314; +memspi_host_set_write_protect = 0x40000318; +memspi_host_set_max_read_len = 0x4000031c; +memspi_host_read_data_slicer = 0x40000320; +memspi_host_write_data_slicer = 0x40000324; + + +/*************************************** + Group hal_spiflash + ***************************************/ + +/* Functions */ +spi_flash_hal_poll_cmd_done = 0x40000328; +spi_flash_hal_device_config = 0x4000032c; +spi_flash_hal_configure_host_io_mode = 0x40000330; +spi_flash_hal_common_command = 0x40000334; +spi_flash_hal_read = 0x40000338; +spi_flash_hal_erase_chip = 0x4000033c; +spi_flash_hal_erase_sector = 0x40000340; +spi_flash_hal_erase_block = 0x40000344; +spi_flash_hal_program_page = 0x40000348; +spi_flash_hal_set_write_protect = 0x4000034c; +spi_flash_hal_host_idle = 0x40000350; +spi_flash_hal_check_status = 0x40000354; +spi_flash_hal_setup_read_suspend = 0x40000358; +spi_flash_hal_setup_auto_suspend_mode = 0x4000035c; +spi_flash_hal_setup_auto_resume_mode = 0x40000360; +spi_flash_hal_disable_auto_suspend_mode = 0x40000364; +spi_flash_hal_disable_auto_resume_mode = 0x40000368; +spi_flash_hal_resume = 0x4000036c; +spi_flash_hal_suspend = 0x40000370; +spi_flash_encryption_hal_enable = 0x40000374; +spi_flash_encryption_hal_disable = 0x40000378; +spi_flash_encryption_hal_prepare = 0x4000037c; +spi_flash_encryption_hal_done = 0x40000380; +spi_flash_encryption_hal_destroy = 0x40000384; +spi_flash_encryption_hal_check = 0x40000388; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld new file mode 100644 index 0000000000..f2e82d522b --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ +/* systimer_hal_init = 0x400003b8; */ +/* systimer_hal_deinit = 0x400003bc; */ +systimer_hal_set_tick_rate_ops = 0x400003c0; +systimer_hal_get_counter_value = 0x400003c4; +systimer_hal_get_time = 0x400003c8; +systimer_hal_set_alarm_target = 0x400003cc; +systimer_hal_set_alarm_period = 0x400003d0; +systimer_hal_get_alarm_value = 0x400003d4; +systimer_hal_enable_alarm_int = 0x400003d8; +systimer_hal_on_apb_freq_update = 0x400003dc; +systimer_hal_counter_value_advance = 0x400003e0; +systimer_hal_enable_counter = 0x400003e4; +systimer_hal_select_alarm_mode = 0x400003e8; +systimer_hal_connect_alarm_counter = 0x400003ec; +systimer_hal_counter_can_stall_by_cpu = 0x400003f0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld new file mode 100644 index 0000000000..c91bb8f06c --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/* ROM version variables for esp32h21 + * + * These addresses should be compatible with any ROM version for this chip. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ +_rom_chip_id = 0x40000010; +_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld new file mode 100644 index 0000000000..6d139bdd04 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ + +/* Patch init function to set clock source +wdt_hal_init = 0x4000038c; +wdt_hal_deinit = 0x40000390; +*/ + +/* Functions */ +wdt_hal_config_stage = 0x40000394; +wdt_hal_write_protect_disable = 0x40000398; +wdt_hal_write_protect_enable = 0x4000039c; +wdt_hal_enable = 0x400003a0; +wdt_hal_disable = 0x400003a4; +wdt_hal_handle_intr = 0x400003a8; +wdt_hal_feed = 0x400003ac; +wdt_hal_set_flashboot_en = 0x400003b0; +wdt_hal_is_enabled = 0x400003b4; diff --git a/components/esp_rom/include/esp_rom_libc_stubs.h b/components/esp_rom/include/esp_rom_libc_stubs.h index 7db1a26281..734860864a 100644 --- a/components/esp_rom/include/esp_rom_libc_stubs.h +++ b/components/esp_rom/include/esp_rom_libc_stubs.h @@ -25,6 +25,8 @@ #include "esp32c5/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/libc_stubs.h" +#elif CONFIG_IDF_TARGET_ESP32H21 +#include "esp32h21/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32P4 #include "esp32p4/rom/libc_stubs.h" #endif diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index 7de32f09e6..944d9f879e 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200) -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER;