From 4e411d9e3b8c3ca2c69d204806d8dabd87e1c6fa Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Thu, 19 Jan 2023 20:30:17 +0700 Subject: [PATCH 01/25] tools: add triplet i686-linux-gnu for distributions --- tools/idf_tools.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/idf_tools.py b/tools/idf_tools.py index f98e38215a..8a17ed224d 100755 --- a/tools/idf_tools.py +++ b/tools/idf_tools.py @@ -146,6 +146,7 @@ class Platforms: 'Linux-i686': PLATFORM_LINUX32, 'FreeBSD-i386': PLATFORM_LINUX32, 'i586-linux-gnu': PLATFORM_LINUX32, + 'i686-linux-gnu': PLATFORM_LINUX32, PLATFORM_LINUX_ARM64: PLATFORM_LINUX_ARM64, 'Linux-arm64': PLATFORM_LINUX_ARM64, 'Linux-aarch64': PLATFORM_LINUX_ARM64, From d867b110226b5ad50e7ff82b69b5638ad3c1e3e8 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 3 Feb 2023 09:12:37 +0700 Subject: [PATCH 02/25] tools: update toolchain version to 'esp-12.2.0_20230208' Closes https://github.com/espressif/esp-idf/issues/5308 --- tools/tools.json | 236 +++++++++++++++++++++++------------------------ 1 file changed, 116 insertions(+), 120 deletions(-) diff --git a/tools/tools.json b/tools/tools.json index 350402a2e3..d1e6c0e1b5 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -172,56 +172,55 @@ "xtensa-esp32-elf-gcc", "--version" ], - "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)\\s*([0-9\\.]+)", - "version_regex_replace": "\\1-\\2", + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "698d8407e18275d18feb7d1afdb68800b97904fbe39080422fb8609afa49df30", - "size": 64781328, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-linux-amd64.tar.xz" + "sha256": "4d2e02ef47f1a93a4dcfdbaecd486adfaab4c0e26deea2c18d6385527f39f864", + "size": 67006496, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" }, "linux-arm64": { - "sha256": "48ed01abff1e89e6fe1c3ebe4e00df6a0a67e53ae24979970464a4a3b64aa622", - "size": 60675980, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-linux-arm64.tar.xz" + "sha256": "9e211a182b6ea0396a41c78f52f51d964e7875fe274ea9c81111bf0dbc90c516", + "size": 60751692, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-aarch64-linux-gnu.tar.xz" }, "linux-armel": { - "sha256": "0e6131a9ab4e3da0a153ee75097012823ccf21f90c69368c3bf53c8a086736f8", - "size": 59117264, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-linux-armel.tar.xz" + "sha256": "2ddd91fb98b79b30042b7918eef60cf10c7bd5b1da853e83b65f293b96dec800", + "size": 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"292b19ea6186508a923fb6fd0103977e001d4eb8e77836c7e3d6ce6e5fa7d305", + "size": 69446616, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-i686-linux-gnu.tar.xz" }, "macos": { - "sha256": "1c9d873c56469e3abec1e4214b7200d36804a605d4f0991e539b1577415409bf", - "size": 68189688, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-macos.tar.xz" + "sha256": "b09d87fdb1dc32cd1d718935065ef931b101a14df6b17be56748e52640955bff", + "size": 65895468, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz" }, "macos-arm64": { - "sha256": "297249b0dc5307fd496c4d85d960b69824996c0c450a8c92f8414a5fd32a7c3b", - "size": 58460768, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-macos-arm64.tar.xz" + "sha256": "f50acab2b216e9475dc5313b3e4b424cbc70d0abd23ba1818aff4a019165da8e", + "size": 57168044, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-aarch64-apple-darwin.tar.xz" }, - "name": "esp-2022r1-11.2.0", + "name": "esp-12.2.0_20230208", "status": "recommended", "win32": { - "sha256": "858ee049d6d8de730ed3e30285c4adc1a9cdfe077b591ed0b6f2bfa5e3564f53", - "size": 129786756, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-win32.zip" + "sha256": "62bb6428d107ed3f44c212c77ecf24804b74c97327b0f0ad2029c656c6dbd6ee", + "size": 130847086, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-i686-w64-mingw32.zip" }, "win64": { - "sha256": "f469aff6a71113e3a145466d814184339e02248b158357766970646f5d2a3da7", - "size": 133936844, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32-elf-gcc11_2_0-esp-2022r1-win64.zip" + "sha256": "8febfe4a6476efc69012390106c8c660a14418f025137b0513670c72124339cf", + "size": 134985117, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-w64-mingw32.zip" } } ] @@ -246,56 +245,55 @@ "xtensa-esp32s2-elf-gcc", "--version" ], - "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)\\s*([0-9\\.]+)", - "version_regex_replace": "\\1-\\2", + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "56e5913b6662b8eec7d6b46780e668bc7e7cebef239e326a74f764c92a3cc841", - "size": 51546516, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-linux-amd64.tar.xz" + "sha256": "a1bd8f0252aae02cff2c289f742fbdbaa2c24644cc30e883d118253ea4df1799", + "size": 64374532, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" }, "linux-arm64": { - "sha256": "2f0ccc9d40279d6407ed9547250fb0434f16060faa94460c52b74614a38a1e21", - "size": 46338036, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-linux-arm64.tar.xz" + "sha256": "48e88053e92bab1bf8d6dbad7ddb4d140c537159d607a36e73e74e1f5f23c892", + "size": 58021880, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-aarch64-linux-gnu.tar.xz" }, "linux-armel": { - "sha256": "f71974c4aaf3f637f6adaa28bbbdf3a911db3385e0ab1544844513ec65185cc5", - "size": 43326084, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-linux-armel.tar.xz" + "sha256": "37cdd619fa56ce884570cedd00dd2f4a5eb9a1fce3755a2f4b9279d1136e47c1", + "size": 59627080, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-arm-linux-gnueabi.tar.xz" }, "linux-armhf": { - "sha256": "73e3be22c993f1112fcb1f7631d82552a6b759f82f12cfb78e669c7303d92b25", - "size": 44856580, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-linux-armhf.tar.xz" + "sha256": "99a7b34e8826d0c0b5703e5a4e7db8716b9738fa4f03eed759f383a10617e788", + "size": 59762112, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-arm-linux-gnueabihf.tar.xz" }, "linux-i686": { - "sha256": "504efe97ce24561537bd442494b1046fc8fb9cc43a1c06ef1afa4652b7517201", - "size": 53807024, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-linux-i686.tar.xz" + "sha256": "d9b79e9e3204fa8e40f9942ea1197a83ae1527e3711a45bc17171ff5fec43e54", + "size": 69013172, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-i686-linux-gnu.tar.xz" }, "macos": { - "sha256": "f53da9423490001727c5b6c3b8e1602b887783f0ed68e5defbb3c7712ada9631", - "size": 53568496, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-macos.tar.xz" + "sha256": "e7b2fbacd8186b24d1b1264ad6cf639f476d51f5d908fb79504abfe6281d3c8c", + "size": 65634524, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz" }, "macos-arm64": { - "sha256": "3592e0fbdb2ca438c7360d93fd62ef0e05ead2fc8144eff344bbe1971d333287", - "size": 44218948, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-macos-arm64.tar.xz" + "sha256": "d2c997ce5f43a93c3787c224aa8742b0cd87443794514ab2153cd629665506f0", + "size": 57290936, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-aarch64-apple-darwin.tar.xz" }, - "name": "esp-2022r1-11.2.0", + "name": "esp-12.2.0_20230208", "status": "recommended", "win32": { - "sha256": "96b873210438713a84ea6e39e591cdbbeef453cb431d8392ac3fa2e68a48bc97", - "size": 94981372, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-win32.zip" + "sha256": "1e6dac5162ab75f94b88c47ebeabb6600c652fb4f615ed07c1724d037c02fd19", + "size": 131273859, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-i686-w64-mingw32.zip" }, "win64": { - "sha256": "9ab0387e08047916bbf7ff0d2eb974c710bcf2e042cb04037b4dd93c9186f676", - "size": 99074758, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s2-elf-gcc11_2_0-esp-2022r1-win64.zip" + "sha256": "8a785cc4e0838cebe404f82c0ead7a0f9ac5fabc660a742e33a41ddac6326cc1", + "size": 135373049, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-w64-mingw32.zip" } } ] @@ -320,56 +318,55 @@ "xtensa-esp32s3-elf-gcc", "--version" ], - "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)\\s*([0-9\\.]+)", - "version_regex_replace": "\\1-\\2", + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "5058b2e724166c34ca09ec2d5377350252de8bce5039b06c00352f9a8151f76e", - "size": 51899328, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-linux-amd64.tar.xz" + "sha256": "29b5ea6b30d98231f0c17f2327404109e0abf59b48d0f2890d9d9899678a89a3", + "size": 67512340, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" }, "linux-arm64": { - "sha256": "d2c6fb98a5018139a9f5af6eb808e968f1381a5b34547a185f4dec142b0fa44e", - "size": 45458872, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-linux-arm64.tar.xz" + "sha256": "30a1fed3ab6341feb1ae986ee55f227df6a594293ced13c65a0136eb4681087d", + "size": 60207516, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-aarch64-linux-gnu.tar.xz" }, "linux-armel": { - "sha256": "9944e67d95a5de9875670c5cd5cb0bb282ebac235a38b5fd6d53069813fead9e", - "size": 44532116, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-linux-armel.tar.xz" + "sha256": "c180836bf43b90b4b7c24166a3bd4156c74c8e58bb85761aa58da98d076e6f48", + "size": 57151040, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-arm-linux-gnueabi.tar.xz" }, "linux-armhf": { - "sha256": "c0a8836dd709605f8d68ea1fd6e8ae79b3fa76274bfffdd8e79eeadc8f1f3ce1", - "size": 44840304, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-linux-armhf.tar.xz" + "sha256": "4cc1adee141de67ffb7e94e53d30bf4e120ef07d4063fecc2153c69ad4b54f7f", + "size": 60955732, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-arm-linux-gnueabihf.tar.xz" }, "linux-i686": { - "sha256": "0feccf884e36b6e93c27c793729199b18df22a409557b16c90b2883a6748e041", - "size": 53956012, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-linux-i686.tar.xz" + "sha256": "9a968f58085c66b41ca13af8d652e5250df0f8d8e17988e34846be9c76672cab", + "size": 68403124, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-i686-linux-gnu.tar.xz" }, "macos": { - "sha256": "2b46730adc6afd8115e0be9365050a87f9523617e5e58ee35cb85ff1ddf2756c", - "size": 54256036, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-macos.tar.xz" + "sha256": "30375231847a9070e4e0acb3102b7d35a60448a55536bfa113c677c449da3eef", + "size": 68227240, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz" }, "macos-arm64": { - "sha256": "bb449ac62b9917638b35234c98ce03ddf1cac75c2d80fbd67c46ecec08369838", - "size": 44835256, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-macos-arm64.tar.xz" + "sha256": "ae9a1a3e12c0b6f6f28a3878f5964e91a410350248586c90db94f8bdaeef7695", + "size": 57080804, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-aarch64-apple-darwin.tar.xz" }, - "name": "esp-2022r1-11.2.0", + "name": "esp-12.2.0_20230208", "status": "recommended", "win32": { - "sha256": "0c9ec6d296b66523e3990b195b6597dfc4030f2335bf904b614f990ad6dabbde", - "size": 95241895, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-win32.zip" + "sha256": "3ddf51774817e815e5d41c312a90c1159226978fb45fd0d4f7085c567f8b73ab", + "size": 131134034, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-i686-w64-mingw32.zip" }, "win64": { - "sha256": "7213a0bf22607e9c70febaabef37822c2ae5e071ac53d6467e6031b02bb0b2bf", - "size": 99495535, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/xtensa-esp32s3-elf-gcc11_2_0-esp-2022r1-win64.zip" + "sha256": "1d15ca65e3508388a86d8bed3048c46d07538f5bc88d3e4296f9c03152087cd1", + "size": 135381926, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-w64-mingw32.zip" } } ] @@ -466,56 +463,55 @@ "riscv32-esp-elf-gcc", "--version" ], - "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)\\s*([0-9\\.]+)", - "version_regex_replace": "\\1-\\2", + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "52710f804df4a033a2b621cc16cfa21023b42052819a51e35a2a164140bbf665", - "size": 110107900, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64.tar.xz" + "sha256": "21694e5ee506f5e52908b12c6b5be7044d87cf34bb4dfcd151d0a10ea09dedc1", + "size": 131410024, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" }, "linux-arm64": { - "sha256": "812a18f2ecdc3f72c1d098c4e8baa968841099ce9d9ecf95baea85ff71e11013", - "size": 104279292, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-arm64.tar.xz" + "sha256": "aefbf1e6f2c91a10e8995399d2003502e167e8c95e77f40957309e843700906a", + "size": 125863404, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-aarch64-linux-gnu.tar.xz" }, "linux-armel": { - "sha256": "bc6e3ff8323d1f8b137374788b5615152281aab9e7561c55ab1504145677b6c7", - "size": 102802824, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-armel.tar.xz" + "sha256": "9740cbddb4cb5e05382991c83d8c96a5fb7d87046449e77791b3b0de29a3ddd8", + "size": 121040676, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-arm-linux-gnueabi.tar.xz" }, "linux-armhf": { - "sha256": "63f85a089fcd06939ed5e7e72ee5cdca590aa470075e409c0a4c59ef1cab3a7b", - "size": 102657540, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-armhf.tar.xz" + "sha256": "ee6210b1068802ed8486543c1f313cb8ac64571c20d51bf50fdb34ad4c457018", + "size": 123564880, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-arm-linux-gnueabihf.tar.xz" }, "linux-i686": { - "sha256": "39d7295c30a23b5ea91baf61c207718ce86d4b1589014b030e121300370f696d", - "size": 111505972, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-i686.tar.xz" + "sha256": "9207fe3d1413cf29fad6dc4bdc9a35f538b0b2c48a70e9a89d2f0e930c346aed", + "size": 133871120, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-i686-linux-gnu.tar.xz" }, "macos": { - "sha256": "d3a6f42b02a5f1485ba3fa92b8a9d9f307f643420e22b3765e88bbe4570aee01", - "size": 112060920, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-macos.tar.xz" + "sha256": "78cd1afe458fceb7c2657fe346edb0ecfde3b8743ccf7a7a7509c456cad9de9a", + "size": 135635672, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz" }, "macos-arm64": { - "sha256": "23d9a715d932a3af57fd7393b0789f88d0f70fedaf5b803deb9ab81dee271bd6", - "size": 101254152, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-macos-arm64.tar.xz" + "sha256": "6c0a4151afb258766911fc7bcfe5f4fee6ee2cd9a5ff25542bc1228c1203a3f9", + "size": 119346172, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-aarch64-apple-darwin.tar.xz" }, - "name": "esp-2022r1-11.2.0", + "name": "esp-12.2.0_20230208", "status": "recommended", "win32": { - "sha256": "3e677ef068d7f154d33b0d3788b5f985c5066d110028eac44e0f76b3bda4429b", - "size": 268053767, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-win32.zip" + "sha256": "a5dfbb6dbf6fc6c6ea9beb2723af059ba3c5b2c86c2f0dc3b21afdc7bb229bf5", + "size": 324863847, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-i686-w64-mingw32.zip" }, "win64": { - "sha256": "324a5c679fef75313766cc48d3433c48bf23985a11b5070c5d19144538c6357b", - "size": 271158759, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-win64.zip" + "sha256": "9deae9e0013b2f7bbf017f9c8135755bfa89522f337c7dca35872bf12ec08176", + "size": 328092732, + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/riscv32-esp-elf-12.2.0_20230208-x86_64-w64-mingw32.zip" } } ] From 5389ac4e0424372cd9fd3acafdf8d40f660cdfdf Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 10 Oct 2022 18:16:45 +0400 Subject: [PATCH 03/25] tools: cmake: ignore linker RWX segment warnings --- components/ulp/cmake/CMakeLists.txt | 1 + tools/cmake/project.cmake | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt index 9adaa36c40..545b863d1a 100644 --- a/components/ulp/cmake/CMakeLists.txt +++ b/components/ulp/cmake/CMakeLists.txt @@ -69,6 +69,7 @@ if(ULP_COCPU_IS_RISCV) target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/include" "${IDF_PATH}/components/ulp/ulp_riscv/shared/include") target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.peripherals.ld) + target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments") target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU) else() diff --git a/tools/cmake/project.cmake b/tools/cmake/project.cmake index a6d8273f11..00d94c8a6a 100644 --- a/tools/cmake/project.cmake +++ b/tools/cmake/project.cmake @@ -559,6 +559,15 @@ macro(project project_name) target_link_options(${project_elf} PRIVATE "-Wl,--defsym=IDF_TARGET_${idf_target}=0") # Enable map file output target_link_options(${project_elf} PRIVATE "-Wl,--Map=${mapfile}") + # Check if linker supports --no-warn-rwx-segments + execute_process(COMMAND ${CMAKE_LINKER} "--no-warn-rwx-segments" "--version" + RESULT_VARIABLE result + OUTPUT_QUIET + ERROR_QUIET) + if(${result} EQUAL 0) + # Do not print RWX segment warnings + target_link_options(${project_elf} PRIVATE "-Wl,--no-warn-rwx-segments") + endif() unset(idf_target) endif() From c5ae3c67f1ea5b235a1bec0776e530dae2750d9f Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 20 Jan 2023 12:55:59 +0700 Subject: [PATCH 04/25] Revert "tools: bypass atomic instruction variant for esp32c6 temporarily" This reverts commit 08f05420c0cb405bf67f2d524cfc1be25ed65a7a. --- tools/cmake/toolchain-esp32c6.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/cmake/toolchain-esp32c6.cmake b/tools/cmake/toolchain-esp32c6.cmake index 7242a1ac42..ff3ba0b65f 100644 --- a/tools/cmake/toolchain-esp32c6.cmake +++ b/tools/cmake/toolchain-esp32c6.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imac ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imac ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imac --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) From 61a7342acd74db7d3f258a2378175d7d03e8c478 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:59:02 +0700 Subject: [PATCH 05/25] tools: add riscv zicsr/zifencei because they were separated from i https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4 --- components/ulp/cmake/toolchain-ulp-riscv.cmake | 6 +++--- tools/cmake/toolchain-esp32c2.cmake | 6 +++--- tools/cmake/toolchain-esp32c3.cmake | 6 +++--- tools/cmake/toolchain-esp32c6.cmake | 6 +++--- tools/cmake/toolchain-esp32h2.cmake | 6 +++--- tools/cmake/toolchain-esp32h4.cmake | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/components/ulp/cmake/toolchain-ulp-riscv.cmake b/components/ulp/cmake/toolchain-ulp-riscv.cmake index 5e1b497b6a..be94b1f329 100644 --- a/components/ulp/cmake/toolchain-ulp-riscv.cmake +++ b/components/ulp/cmake/toolchain-ulp-riscv.cmake @@ -5,11 +5,11 @@ set(CMAKE_C_COMPILER "riscv32-esp-elf-gcc") set(CMAKE_CXX_COMPILER "riscv32-esp-elf-g++") set(CMAKE_ASM_COMPILER "riscv32-esp-elf-gcc") -set(CMAKE_C_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections" +set(CMAKE_C_FLAGS "-Os -march=rv32imc_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections" CACHE STRING "C Compiler Base Flags") -set(CMAKE_CXX_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections" +set(CMAKE_CXX_FLAGS "-Os -march=rv32imc_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections" CACHE STRING "C++ Compiler Base Flags") set(CMAKE_ASM_FLAGS "-march=rv32imc -x assembler-with-cpp" CACHE STRING "Assembler Base Flags") -set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc --specs=nano.specs --specs=nosys.specs" +set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc_zicsr_zifencei --specs=nano.specs --specs=nosys.specs" CACHE STRING "Linker Base Flags") diff --git a/tools/cmake/toolchain-esp32c2.cmake b/tools/cmake/toolchain-esp32c2.cmake index 7242a1ac42..2eb3a62d64 100644 --- a/tools/cmake/toolchain-esp32c2.cmake +++ b/tools/cmake/toolchain-esp32c2.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/toolchain-esp32c3.cmake b/tools/cmake/toolchain-esp32c3.cmake index 8fc3a19c49..d6c5745e92 100644 --- a/tools/cmake/toolchain-esp32c3.cmake +++ b/tools/cmake/toolchain-esp32c3.cmake @@ -7,14 +7,14 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc ${CMAKE_C_FLAGS}" +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc ${CMAKE_CXX_FLAGS}" +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/toolchain-esp32c6.cmake b/tools/cmake/toolchain-esp32c6.cmake index ff3ba0b65f..6415daa59b 100644 --- a/tools/cmake/toolchain-esp32c6.cmake +++ b/tools/cmake/toolchain-esp32c6.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imac ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imac ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imac --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imac_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/toolchain-esp32h2.cmake b/tools/cmake/toolchain-esp32h2.cmake index 7242a1ac42..2eb3a62d64 100644 --- a/tools/cmake/toolchain-esp32h2.cmake +++ b/tools/cmake/toolchain-esp32h2.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/toolchain-esp32h4.cmake b/tools/cmake/toolchain-esp32h4.cmake index 7242a1ac42..2eb3a62d64 100644 --- a/tools/cmake/toolchain-esp32h4.cmake +++ b/tools/cmake/toolchain-esp32h4.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) From 2ef621562193d396184490c5aa2232b5781aa344 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 17 Feb 2023 18:01:50 +0800 Subject: [PATCH 06/25] tools: change esp32h2 march to rv32imac_zicsr_zifencei --- tools/cmake/toolchain-esp32h2.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/cmake/toolchain-esp32h2.cmake b/tools/cmake/toolchain-esp32h2.cmake index 2eb3a62d64..6415daa59b 100644 --- a/tools/cmake/toolchain-esp32h2.cmake +++ b/tools/cmake/toolchain-esp32h2.cmake @@ -7,12 +7,12 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) -remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ +remove_duplicated_flags("-nostartfiles -march=rv32imac_zicsr_zifencei --specs=nosys.specs \ ${CMAKE_EXE_LINKER_FLAGS}" UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) From 0da15a7a19c97d38569ddbe3b919045834408c25 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Wed, 15 Feb 2023 15:01:52 +0700 Subject: [PATCH 07/25] build: add option COMPILER_DISABLE_GCC12_WARNINGS --- CMakeLists.txt | 5 +++++ Kconfig | 7 +++++++ tools/idf_py_actions/hints.yml | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 111891ebce..5869c4c1e4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -179,6 +179,11 @@ if(NOT ${CMAKE_C_COMPILER_VERSION} VERSION_LESS 8.0.0) endif() endif() +if(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS) + list(APPEND compile_options "-Wno-address" + "-Wno-use-after-free") +endif() + # GCC-specific options if(CMAKE_C_COMPILER_ID STREQUAL "GNU") list(APPEND compile_options "-fstrict-volatile-bitfields" diff --git a/Kconfig b/Kconfig index 0265e12a11..4f56b70c34 100644 --- a/Kconfig +++ b/Kconfig @@ -505,6 +505,13 @@ mainmenu "Espressif IoT Development Framework Configuration" This option can be enabled for RISC-V targets only. + config COMPILER_DISABLE_GCC12_WARNINGS + bool "Disable new warnings introduced in GCC 12" + default "n" + help + Enable this option if use GCC 12 or newer, and want to disable warnings which don't appear with + GCC 11. + config COMPILER_DUMP_RTL_FILES bool "Dump RTL files during compilation" help diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index 564553c57e..3a076619fb 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -294,3 +294,8 @@ - re: "Error: libusb_open\\(\\) failed with LIBUSB_ERROR_ACCESS" hint: "OpenOCD process does not have permissions to access the USB JTAG/serial device. Please use 'LIBUSB_DEBUG=1 idf.py openocd' to find out the device name and check its access rights." + +- + re: "(-Werror=address|-Werror=use-after-free)" + hint: "The warning(s) '{}' may appear after compiler update above GCC-12\nTo suppress these warnings use 'idf.py menuconfig' to enable configure option 'Compiler options' -> 'Disable new warnings introduced in GCC 12'\nPlease note that this is not a permanent solution, and this option will be removed in a future update of the ESP-IDF.\nIt is strongly recommended to fix all warnings, as they may indicate potential issues!" + match_to_output: True From 21d7fd9b03cf24a11e33e9e4e1e07e00e257f262 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 12 Dec 2022 16:00:24 +0700 Subject: [PATCH 08/25] gcov: use original libgcov.a with redefined symbols --- components/app_trace/CMakeLists.txt | 58 +++++++++++++++++++++++---- components/app_trace/gcov/gcov_rtio.c | 18 ++++++++- components/app_trace/gcov/io_sym.map | 7 ++++ 3 files changed, 74 insertions(+), 9 deletions(-) create mode 100644 components/app_trace/gcov/io_sym.map diff --git a/components/app_trace/CMakeLists.txt b/components/app_trace/CMakeLists.txt index bc5e42547b..0968a31a82 100644 --- a/components/app_trace/CMakeLists.txt +++ b/components/app_trace/CMakeLists.txt @@ -1,8 +1,16 @@ set(srcs "app_trace.c" "app_trace_util.c" - "host_file_io.c" - "gcov/gcov_rtio.c") + "host_file_io.c") + +if(CONFIG_APPTRACE_GCOV_ENABLE) + if("${CMAKE_C_COMPILER_ID}" STREQUAL "GNU") + list(APPEND srcs + "gcov/gcov_rtio.c") + else() + fail_at_build_time(app_trace "Only GNU compiler can link with Gcov library") + endif() +endif() set(include_dirs "include") @@ -54,13 +62,49 @@ idf_component_register(SRCS "${srcs}" REQUIRES esp_timer LDFRAGMENTS linker.lf) -# disable --coverage for this component, as it is used as transport -# for gcov -target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-profile-arcs" "-fno-test-coverage") - # Force app_trace to also appear later than gcov in link line idf_component_get_property(app_trace app_trace COMPONENT_LIB) -target_link_libraries(${COMPONENT_LIB} INTERFACE $ gcov $ c) + +if(CONFIG_APPTRACE_GCOV_ENABLE) + # The original Gcov library from toolchain will be objcopy with symbols redefinitions (see file gcov/io_sym.map). + # This needs because ESP has no file-system onboard, and redefined functions solves this problem and transmits + # output file to host PC. + + # Set a name for Gcov library + set(GCOV_LIB libgcov_rtio) + + # Set include direcrory of Gcov internal headers + execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=plugin + OUTPUT_VARIABLE gcc_plugin_dir + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_QUIET) + set_source_files_properties(gcov/gcov_rtio.c + PROPERTIES COMPILE_FLAGS "-I${gcc_plugin_dir}/include") + + # Copy libgcov.a with symbols redefinition + find_library(GCOV_LIBRARY_PATH gcov ${CMAKE_C_IMPLICIT_LINK_DIRECTORIES}) + add_custom_command(OUTPUT ${GCOV_LIB}.a + COMMAND ${_CMAKE_TOOLCHAIN_PREFIX}objcopy + --redefine-syms ${CMAKE_CURRENT_LIST_DIR}/gcov/io_sym.map + ${GCOV_LIBRARY_PATH} ${GCOV_LIB}.a + MAIN_DEPENDENCY ${GCOV_LIBRARY_PATH} + VERBATIM) + add_custom_target(${GCOV_LIB}_target DEPENDS ${GCOV_LIB}.a) + add_library(${GCOV_LIB} STATIC IMPORTED) + set_target_properties(${GCOV_LIB} + PROPERTIES + IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/${GCOV_LIB}.a) + add_dependencies(${GCOV_LIB} ${GCOV_LIB}_target) + add_dependencies(${COMPONENT_LIB} ${GCOV_LIB}) + + # disable --coverage for this component, as it is used as transport for gcov + target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-profile-arcs" "-fno-test-coverage") + target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=__gcov_init") + + target_link_libraries(${COMPONENT_LIB} INTERFACE ${GCOV_LIB} $ c) +else() + target_link_libraries(${COMPONENT_LIB} INTERFACE $ c) +endif() # This function adds a dependency on the given component if the component is included into the build. function(maybe_add_component component_name) diff --git a/components/app_trace/gcov/gcov_rtio.c b/components/app_trace/gcov/gcov_rtio.c index 614c3c8ebc..80b67563fc 100644 --- a/components/app_trace/gcov/gcov_rtio.c +++ b/components/app_trace/gcov/gcov_rtio.c @@ -103,7 +103,7 @@ static int esp_dbg_stub_gcov_entry(void) return ESP_OK; } -int gcov_rtio_atexit(void (*function)(void) __attribute__ ((unused))) +void gcov_rtio_init(void) { uint32_t capabilities = 0; ESP_EARLY_LOGV(TAG, "%s", __FUNCTION__); @@ -112,7 +112,6 @@ int gcov_rtio_atexit(void (*function)(void) __attribute__ ((unused))) esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_CAPABILITIES, capabilities | ESP_DBG_STUB_CAP_GCOV_TASK); } esp_register_freertos_tick_hook(gcov_create_task_tick_hook); - return ESP_OK; } void esp_gcov_dump(void) @@ -172,4 +171,19 @@ long gcov_rtio_ftell(void *stream) ESP_EARLY_LOGV(TAG, "%s(%p) = %ld", __FUNCTION__, stream, ret); return ret; } + +void gcov_rtio_setbuf(void *arg1 __attribute__ ((unused)), void *arg2 __attribute__ ((unused))) +{ + return; +} + +/* Wrappers for Gcov functions */ + +extern void __real___gcov_init(void *info); +void __wrap___gcov_init(void *info) +{ + __real___gcov_init(info); + gcov_rtio_init(); +} + #endif diff --git a/components/app_trace/gcov/io_sym.map b/components/app_trace/gcov/io_sym.map new file mode 100644 index 0000000000..727766648b --- /dev/null +++ b/components/app_trace/gcov/io_sym.map @@ -0,0 +1,7 @@ +fopen gcov_rtio_fopen +fclose gcov_rtio_fclose +fwrite gcov_rtio_fwrite +fread gcov_rtio_fread +fseek gcov_rtio_fseek +ftell gcov_rtio_ftell +setbuf gcov_rtio_setbuf From 8849b1b5aaf6bc3596faa2a3d4dc3729d02aaa78 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Tue, 31 Jan 2023 19:35:10 +0700 Subject: [PATCH 09/25] newlib: fix and add new atomic tests for multicore chips --- components/newlib/stdatomic.c | 14 + .../newlib/test_apps/main/CMakeLists.txt | 2 +- .../newlib/test_apps/main/test_stdatomic.c | 376 ++++++++++++++++-- .../newlib/test_apps/sdkconfig.defaults | 2 + 4 files changed, 350 insertions(+), 44 deletions(-) diff --git a/components/newlib/stdatomic.c b/components/newlib/stdatomic.c index 1904e533af..54de84e6d2 100644 --- a/components/newlib/stdatomic.c +++ b/components/newlib/stdatomic.c @@ -520,3 +520,17 @@ void CLANG_ATOMIC_SUFFIX( __atomic_store ) (size_t size, volatile void *dest, vo _ATOMIC_EXIT_CRITICAL(state); } CLANG_DECLARE_ALIAS( __atomic_store) + +bool CLANG_ATOMIC_SUFFIX(__atomic_compare_exchange) (size_t size, volatile void *ptr, void *expected, void *desired, int success_memorder, int failure_memorder) { + bool ret = false; + unsigned state = _ATOMIC_ENTER_CRITICAL(); + if (!memcmp((void *)ptr, expected, size)) { + memcpy((void *)ptr, (const void *)desired, size); + ret = true; + } else { + memcpy((void *)expected, (const void *)ptr, size); + } + _ATOMIC_EXIT_CRITICAL(state); + return ret; +} +CLANG_DECLARE_ALIAS( __atomic_compare_exchange) diff --git a/components/newlib/test_apps/main/CMakeLists.txt b/components/newlib/test_apps/main/CMakeLists.txt index b54d173420..f59015d02c 100644 --- a/components/newlib/test_apps/main/CMakeLists.txt +++ b/components/newlib/test_apps/main/CMakeLists.txt @@ -3,5 +3,5 @@ idf_component_register(SRCS "test_stdatomic.c" "test_misc.c" "test_file.c" - REQUIRES test_utils + REQUIRES pthread test_utils PRIV_REQUIRES unity vfs) diff --git a/components/newlib/test_apps/main/test_stdatomic.c b/components/newlib/test_apps/main/test_stdatomic.c index 2485598c2f..aa4c2a8361 100644 --- a/components/newlib/test_apps/main/test_stdatomic.c +++ b/components/newlib/test_apps/main/test_stdatomic.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -10,6 +10,8 @@ #include #include #include +#include "esp_pthread.h" +#include "freertos/portmacro.h" #include "unity.h" #include "unity_fixture.h" @@ -30,7 +32,7 @@ TEST_TEAR_DOWN(stdatomic) { } -TEST(stdatomic, test_64bit_atomics) +TEST(stdatomic, test_64bit_atomics_fetch_op) { unsigned long long x64 = 0; g_atomic64 = 0; // calls atomic_store @@ -40,12 +42,18 @@ TEST(stdatomic, test_64bit_atomics) x64 += atomic_fetch_and(&g_atomic64, 0xf0f0f0f0f0f0f0f0ULL); x64 += atomic_fetch_sub(&g_atomic64, 0x0f0f0f0f0f0f0f0fULL); x64 += atomic_fetch_add(&g_atomic64, 0x2222222222222222ULL); +#ifndef __clang__ + x64 += __atomic_fetch_nand_8 (&g_atomic64, 0xAAAAAAAAAAAAAAAAULL, 0); + TEST_ASSERT_EQUAL_HEX64(0x9797979797979797ULL, x64); + TEST_ASSERT_EQUAL_HEX64(0xDDDDDDDDDDDDDDDDULL, g_atomic64); // calls atomic_load +#else TEST_ASSERT_EQUAL_HEX64(0x6464646464646464ULL, x64); TEST_ASSERT_EQUAL_HEX64(0x3333333333333333ULL, g_atomic64); // calls atomic_load +#endif } -TEST(stdatomic, test_32bit_atomics) +TEST(stdatomic, test_32bit_atomics_fetch_op) { unsigned int x32 = 0; g_atomic32 = 0; @@ -55,12 +63,18 @@ TEST(stdatomic, test_32bit_atomics) x32 += atomic_fetch_and(&g_atomic32, 0xf0f0f0f0U); x32 += atomic_fetch_sub(&g_atomic32, 0x0f0f0f0fU); x32 += atomic_fetch_add(&g_atomic32, 0x22222222U); +#ifndef __clang__ + x32 += __atomic_fetch_nand_4 (&g_atomic32, 0xAAAAAAAAU, 0); - TEST_ASSERT_EQUAL_HEX32(0x64646464, x32); - TEST_ASSERT_EQUAL_HEX32(0x33333333, g_atomic32); + TEST_ASSERT_EQUAL_HEX32(0x97979797U, x32); + TEST_ASSERT_EQUAL_HEX32(0xDDDDDDDDU, g_atomic32); +#else + TEST_ASSERT_EQUAL_HEX32(0x64646464U, x32); + TEST_ASSERT_EQUAL_HEX32(0x33333333U, g_atomic32); // calls atomic_load +#endif } -TEST(stdatomic, test_16bit_atomics) +TEST(stdatomic, test_16bit_atomics_fetch_op) { unsigned int x16 = 0; g_atomic16 = 0; @@ -70,12 +84,18 @@ TEST(stdatomic, test_16bit_atomics) x16 += atomic_fetch_and(&g_atomic16, 0xf0f0); x16 += atomic_fetch_sub(&g_atomic16, 0x0f0f); x16 += atomic_fetch_add(&g_atomic16, 0x2222); +#ifndef __clang__ + x16 += __atomic_fetch_nand_2 (&g_atomic16, 0xAAAA, 0); + TEST_ASSERT_EQUAL_HEX16(0x9797, x16); + TEST_ASSERT_EQUAL_HEX16(0xDDDD, g_atomic16); +#else TEST_ASSERT_EQUAL_HEX16(0x6464, x16); - TEST_ASSERT_EQUAL_HEX16(0x3333, g_atomic16); + TEST_ASSERT_EQUAL_HEX16(0x3333, g_atomic16); // calls atomic_load +#endif } -TEST(stdatomic, test_8bit_atomics) +TEST(stdatomic, test_8bit_atomics_fetch_op) { unsigned int x8 = 0; g_atomic8 = 0; @@ -85,52 +105,322 @@ TEST(stdatomic, test_8bit_atomics) x8 += atomic_fetch_and(&g_atomic8, 0xf0); x8 += atomic_fetch_sub(&g_atomic8, 0x0f); x8 += atomic_fetch_add(&g_atomic8, 0x22); +#ifndef __clang__ + x8 += __atomic_fetch_nand_1 (&g_atomic8, 0xAA, 0); + TEST_ASSERT_EQUAL_HEX8(0x97, x8); + TEST_ASSERT_EQUAL_HEX8(0xDD, g_atomic8); +#else TEST_ASSERT_EQUAL_HEX8(0x64, x8); - TEST_ASSERT_EQUAL_HEX16(0x33, g_atomic8); + TEST_ASSERT_EQUAL_HEX8(0x33, g_atomic8); // calls atomic_load +#endif } -static void *exclusion_test_task(void *arg); - -TEST(stdatomic, test_exclusion) +#ifndef __clang__ +TEST(stdatomic, test_64bit_atomics_op_fetch) { - /* Check 64-bit atomics for exclusion. - * Only atomic_fetch_add/sub are checked, since all 64-bit atomics use the - * same locking implementation. - */ - g_atomic64 = 0; - pthread_t thread1; - pthread_t thread2; - pthread_create(&thread1, NULL, exclusion_test_task, (void*) 1); - pthread_create(&thread2, NULL, exclusion_test_task, (void*) 0); - pthread_join(thread1, NULL); - pthread_join(thread2, NULL); + unsigned long long x64 = 0; + g_atomic64 = 0; // calls atomic_store - TEST_ASSERT_EQUAL(0, g_atomic64); + x64 += __atomic_or_fetch_8 (&g_atomic64, 0x1111111111111111ULL, 0); + x64 += __atomic_xor_fetch_8(&g_atomic64, 0x3333333333333333ULL, 0); + x64 += __atomic_and_fetch_8(&g_atomic64, 0xf0f0f0f0f0f0f0f0ULL, 0); + x64 += __atomic_sub_fetch_8(&g_atomic64, 0x0f0f0f0f0f0f0f0fULL, 0); + x64 += __atomic_add_fetch_8(&g_atomic64, 0x2222222222222222ULL, 0); + x64 += __atomic_nand_fetch_8(&g_atomic64, 0xAAAAAAAAAAAAAAAAULL, 0); + + TEST_ASSERT_EQUAL_HEX64(0x7575757575757574ULL, x64); + TEST_ASSERT_EQUAL_HEX64(0xDDDDDDDDDDDDDDDDULL, g_atomic64); // calls atomic_load } -/* Two threads run in parallel, incrementing and decrementing - * a single 64-bit variable. In the end the variable should - * have the same value as at the start. - */ -static void* exclusion_test_task(void *varg) +TEST(stdatomic, test_32bit_atomics_op_fetch) { - int arg = (int) varg; - for (int i = 0; i < 1000000; ++i) { - if (arg == 0) { - atomic_fetch_add(&g_atomic64, 1ULL); - } else { - atomic_fetch_sub(&g_atomic64, 1ULL); - } - } - return NULL; + unsigned int x32 = 0; + g_atomic32 = 0; + + x32 += __atomic_or_fetch_4 (&g_atomic32, 0x11111111U, 0); + x32 += __atomic_xor_fetch_4(&g_atomic32, 0x33333333U, 0); + x32 += __atomic_and_fetch_4(&g_atomic32, 0xf0f0f0f0U, 0); + x32 += __atomic_sub_fetch_4(&g_atomic32, 0x0f0f0f0fU, 0); + x32 += __atomic_add_fetch_4(&g_atomic32, 0x22222222U, 0); + x32 += __atomic_nand_fetch_4 (&g_atomic32, 0xAAAAAAAAU, 0); + + TEST_ASSERT_EQUAL_HEX32(0x75757574U, x32); + TEST_ASSERT_EQUAL_HEX32(0xDDDDDDDDU, g_atomic32); } +TEST(stdatomic, test_16bit_atomics_op_fetch) +{ + unsigned int x16 = 0; + g_atomic16 = 0; + + x16 += __atomic_or_fetch_2 (&g_atomic16, 0x1111, 0); + x16 += __atomic_xor_fetch_2(&g_atomic16, 0x3333, 0); + x16 += __atomic_and_fetch_2(&g_atomic16, 0xf0f0, 0); + x16 += __atomic_sub_fetch_2(&g_atomic16, 0x0f0f, 0); + x16 += __atomic_add_fetch_2(&g_atomic16, 0x2222, 0); + x16 += __atomic_nand_fetch_2 (&g_atomic16, 0xAAAA, 0); + + TEST_ASSERT_EQUAL_HEX16(0x7574, x16); + TEST_ASSERT_EQUAL_HEX16(0xDDDD, g_atomic16); +} + +TEST(stdatomic, test_8bit_atomics_op_fetch) +{ + unsigned int x8 = 0; + g_atomic8 = 0; + + x8 += __atomic_or_fetch_1 (&g_atomic8, 0x11, 0); + x8 += __atomic_xor_fetch_1(&g_atomic8, 0x33, 0); + x8 += __atomic_and_fetch_1(&g_atomic8, 0xf0, 0); + x8 += __atomic_sub_fetch_1(&g_atomic8, 0x0f, 0); + x8 += __atomic_add_fetch_1(&g_atomic8, 0x22, 0); + x8 += __atomic_nand_fetch_1 (&g_atomic8, 0xAA, 0); + + TEST_ASSERT_EQUAL_HEX8(0x74, x8); + TEST_ASSERT_EQUAL_HEX8(0xDD, g_atomic8); +} + +#endif // #ifndef __clang__ + + +#define TEST_EXCLUSION(n) TEST(stdatomic, test_ ## n ## bit_exclusion) \ +{ \ + g_atomic ## n = 0; \ + pthread_t thread1; \ + pthread_t thread2; \ + esp_pthread_cfg_t cfg = esp_pthread_get_default_config(); \ + cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS; \ + esp_pthread_set_cfg(&cfg); \ + pthread_create(&thread1, NULL, exclusion_task_ ## n, (void*) 1); \ + cfg.pin_to_core = xPortGetCoreID(); \ + esp_pthread_set_cfg(&cfg); \ + pthread_create(&thread2, NULL, exclusion_task_ ## n, (void*) 0); \ + pthread_join(thread1, NULL); \ + pthread_join(thread2, NULL); \ + TEST_ASSERT_EQUAL(0, g_atomic ## n); \ +} + +#define TEST_EXCLUSION_TASK(n) static void* exclusion_task_ ## n(void *varg) \ +{ \ + int arg = (int) varg; \ + for (int i = 0; i < 1000000; ++i) { \ + if (arg == 0) { \ + atomic_fetch_add(&g_atomic ## n, 1ULL); \ + } else { \ + atomic_fetch_sub(&g_atomic ## n, 1ULL); \ + } \ + } \ + return NULL; \ +} + +TEST_EXCLUSION_TASK(64) +TEST_EXCLUSION(64) + +TEST_EXCLUSION_TASK(32) +TEST_EXCLUSION(32) + +TEST_EXCLUSION_TASK(16) +TEST_EXCLUSION(16) + +TEST_EXCLUSION_TASK(8) +TEST_EXCLUSION(8) + + +#define ITER_COUNT 20000 + +#define TEST_RACE_OPERATION(NAME, LHSTYPE, PRE, POST, INIT, FINAL) \ + \ +static _Atomic LHSTYPE var_##NAME = (INIT); \ + \ +static void *test_thread_##NAME (void *arg) \ +{ \ + for (int i = 0; i < ITER_COUNT; i++) \ + { \ + PRE var_##NAME POST; \ + } \ + return NULL; \ +} \ + \ +TEST(stdatomic, test_ ##NAME) \ +{ \ + pthread_t thread_id1; \ + pthread_t thread_id2; \ + esp_pthread_cfg_t cfg = esp_pthread_get_default_config(); \ + cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS; \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id1, NULL, test_thread_##NAME, NULL); \ + cfg.pin_to_core = xPortGetCoreID(); \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id2, NULL, test_thread_##NAME, NULL); \ + pthread_join (thread_id1, NULL); \ + pthread_join (thread_id2, NULL); \ + TEST_ASSERT_EQUAL((FINAL), var_##NAME); \ +} + +TEST_RACE_OPERATION (uint8_add, uint8_t, , += 1, 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_add_3, uint8_t, , += 3, 0, (uint8_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_postinc, uint8_t, , ++, 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_preinc, uint8_t, ++, , 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_sub, uint8_t, , -= 1, 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_sub_3, uint8_t, , -= 3, 0, (uint8_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_postdec, uint8_t, , --, 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_predec, uint8_t, --, , 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint8_mul, uint8_t, , *= 3, 1, (uint8_t) 0x1) + +TEST_RACE_OPERATION (uint16_add, uint16_t, , += 1, 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_add_3, uint16_t, , += 3, 0, (uint16_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_postinc, uint16_t, , ++, 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_preinc, uint16_t, ++, , 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_sub, uint16_t, , -= 1, 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_sub_3, uint16_t, , -= 3, 0, (uint16_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_postdec, uint16_t, , --, 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_predec, uint16_t, --, , 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint16_mul, uint16_t, , *= 3, 1, (uint16_t) 0x6D01) + +TEST_RACE_OPERATION (uint32_add, uint32_t, , += 1, 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_add_3, uint32_t, , += 3, 0, (uint32_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_postinc, uint32_t, , ++, 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_preinc, uint32_t, ++, , 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_sub, uint32_t, , -= 1, 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_sub_3, uint32_t, , -= 3, 0, (uint32_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_postdec, uint32_t, , --, 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_predec, uint32_t, --, , 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint32_mul, uint32_t, , *= 3, 1, (uint32_t) 0xC1E36D01U) + +TEST_RACE_OPERATION (uint64_add, uint64_t, , += 1, 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_add_3, uint64_t, , += 3, 0, (uint64_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_add_neg, uint64_t, , += 1, -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION (uint64_postinc, uint64_t, , ++, 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_postinc_neg, uint64_t, , ++, -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION (uint64_preinc, uint64_t, ++, , 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_preinc_neg, uint64_t, ++, , -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION (uint64_sub, uint64_t, , -= 1, 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_sub_3, uint64_t, , -= 3, 0, (uint64_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_sub_neg, uint64_t, , -= 1, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION (uint64_postdec, uint64_t, , --, 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_postdec_neg, uint64_t, , --, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION (uint64_predec, uint64_t, --, , 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION (uint64_predec_neg, uint64_t, --, , 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION (uint64_mul, uint64_t, , *= 3, 1, (uint64_t) 0x988EE974C1E36D01ULL) + +TEST_RACE_OPERATION (float_add, float, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_float_add, _Complex float, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (float_postinc, float, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (float_preinc, float, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (float_sub, float, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_float_sub, _Complex float, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (float_postdec, float, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (float_predec, float, --, , 0, -(2*ITER_COUNT)) + +TEST_RACE_OPERATION (double_add, double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_double_add, _Complex double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (double_postinc, double, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (double_preinc, double, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (double_sub, double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_double_sub, _Complex double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (double_postdec, double, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (double_predec, double, --, , 0, -(2*ITER_COUNT)) + +TEST_RACE_OPERATION (long_double_add, long double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_long_double_add, _Complex long double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (long_double_postinc, long double, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (long_double_sub, long double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (long_double_preinc, long double, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (complex_long_double_sub, _Complex long double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (long_double_postdec, long double, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (long_double_predec, long double, --, , 0, -(2*ITER_COUNT)) + + TEST_GROUP_RUNNER(stdatomic) { - RUN_TEST_CASE(stdatomic, test_64bit_atomics) - RUN_TEST_CASE(stdatomic, test_32bit_atomics) - RUN_TEST_CASE(stdatomic, test_16bit_atomics) - RUN_TEST_CASE(stdatomic, test_8bit_atomics) - RUN_TEST_CASE(stdatomic, test_exclusion) + RUN_TEST_CASE(stdatomic, test_64bit_atomics_fetch_op) + RUN_TEST_CASE(stdatomic, test_32bit_atomics_fetch_op) + RUN_TEST_CASE(stdatomic, test_16bit_atomics_fetch_op) + RUN_TEST_CASE(stdatomic, test_8bit_atomics_fetch_op) + +#ifndef __clang__ + RUN_TEST_CASE(stdatomic, test_64bit_atomics_op_fetch) + RUN_TEST_CASE(stdatomic, test_32bit_atomics_op_fetch) + RUN_TEST_CASE(stdatomic, test_16bit_atomics_op_fetch) + RUN_TEST_CASE(stdatomic, test_8bit_atomics_op_fetch) +#endif + + RUN_TEST_CASE(stdatomic, test_64bit_exclusion) + RUN_TEST_CASE(stdatomic, test_32bit_exclusion) + RUN_TEST_CASE(stdatomic, test_16bit_exclusion) + RUN_TEST_CASE(stdatomic, test_8bit_exclusion) + + RUN_TEST_CASE(stdatomic, test_uint8_add) + RUN_TEST_CASE(stdatomic, test_uint8_add_3); + RUN_TEST_CASE(stdatomic, test_uint8_postinc); + RUN_TEST_CASE(stdatomic, test_uint8_preinc); + RUN_TEST_CASE(stdatomic, test_uint8_sub); + RUN_TEST_CASE(stdatomic, test_uint8_sub_3); + RUN_TEST_CASE(stdatomic, test_uint8_postdec); + RUN_TEST_CASE(stdatomic, test_uint8_predec); + RUN_TEST_CASE(stdatomic, test_uint8_mul); + + RUN_TEST_CASE(stdatomic, test_uint16_add); + RUN_TEST_CASE(stdatomic, test_uint16_add_3); + RUN_TEST_CASE(stdatomic, test_uint16_postinc); + RUN_TEST_CASE(stdatomic, test_uint16_preinc); + RUN_TEST_CASE(stdatomic, test_uint16_sub); + RUN_TEST_CASE(stdatomic, test_uint16_sub_3); + RUN_TEST_CASE(stdatomic, test_uint16_postdec); + RUN_TEST_CASE(stdatomic, test_uint16_predec); + RUN_TEST_CASE(stdatomic, test_uint16_mul); + + RUN_TEST_CASE(stdatomic, test_uint32_add); + RUN_TEST_CASE(stdatomic, test_uint32_add_3); + RUN_TEST_CASE(stdatomic, test_uint32_postinc); + RUN_TEST_CASE(stdatomic, test_uint32_preinc); + RUN_TEST_CASE(stdatomic, test_uint32_sub); + RUN_TEST_CASE(stdatomic, test_uint32_sub_3); + RUN_TEST_CASE(stdatomic, test_uint32_postdec); + RUN_TEST_CASE(stdatomic, test_uint32_predec); + RUN_TEST_CASE(stdatomic, test_uint32_mul); + + RUN_TEST_CASE(stdatomic, test_uint64_add); + RUN_TEST_CASE(stdatomic, test_uint64_add_3); + RUN_TEST_CASE(stdatomic, test_uint64_add_neg); + RUN_TEST_CASE(stdatomic, test_uint64_sub); + RUN_TEST_CASE(stdatomic, test_uint64_sub_3); + RUN_TEST_CASE(stdatomic, test_uint64_sub_neg); + RUN_TEST_CASE(stdatomic, test_uint64_postinc); + RUN_TEST_CASE(stdatomic, test_uint64_postinc_neg); + RUN_TEST_CASE(stdatomic, test_uint64_preinc); + RUN_TEST_CASE(stdatomic, test_uint64_preinc_neg); + RUN_TEST_CASE(stdatomic, test_uint64_postdec); + RUN_TEST_CASE(stdatomic, test_uint64_postdec_neg); + RUN_TEST_CASE(stdatomic, test_uint64_predec); + RUN_TEST_CASE(stdatomic, test_uint64_predec_neg); + RUN_TEST_CASE(stdatomic, test_uint64_mul); + + RUN_TEST_CASE(stdatomic, test_float_add); + RUN_TEST_CASE(stdatomic, test_complex_float_add); + RUN_TEST_CASE(stdatomic, test_float_postinc); + RUN_TEST_CASE(stdatomic, test_float_preinc); + RUN_TEST_CASE(stdatomic, test_float_sub); + RUN_TEST_CASE(stdatomic, test_complex_float_sub); + RUN_TEST_CASE(stdatomic, test_float_postdec); + RUN_TEST_CASE(stdatomic, test_float_predec); + + RUN_TEST_CASE(stdatomic, test_double_add); + RUN_TEST_CASE(stdatomic, test_complex_double_add); + RUN_TEST_CASE(stdatomic, test_double_postinc); + RUN_TEST_CASE(stdatomic, test_double_preinc); + RUN_TEST_CASE(stdatomic, test_double_sub); + RUN_TEST_CASE(stdatomic, test_complex_double_sub); + RUN_TEST_CASE(stdatomic, test_double_postdec); + RUN_TEST_CASE(stdatomic, test_double_predec); + + RUN_TEST_CASE(stdatomic, test_long_double_add); + RUN_TEST_CASE(stdatomic, test_complex_long_double_add); + RUN_TEST_CASE(stdatomic, test_long_double_postinc); + RUN_TEST_CASE(stdatomic, test_long_double_preinc); + RUN_TEST_CASE(stdatomic, test_long_double_sub); + RUN_TEST_CASE(stdatomic, test_complex_long_double_sub); + RUN_TEST_CASE(stdatomic, test_long_double_postdec); + RUN_TEST_CASE(stdatomic, test_long_double_predec); } diff --git a/components/newlib/test_apps/sdkconfig.defaults b/components/newlib/test_apps/sdkconfig.defaults index 61bf4b9395..6881a9742e 100644 --- a/components/newlib/test_apps/sdkconfig.defaults +++ b/components/newlib/test_apps/sdkconfig.defaults @@ -1,3 +1,5 @@ CONFIG_UNITY_ENABLE_FIXTURE=y CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n CONFIG_UNITY_ENABLE_64BIT=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=n +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=n From a32bbedcd98b7a540b1aa55ef362299cd042a45f Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Tue, 31 Jan 2023 23:19:21 +0700 Subject: [PATCH 10/25] newlib: implement 8/16-bit atomic operations for riscv --- components/newlib/port/CMakeLists.txt | 4 + components/newlib/port/riscv/port_stdatomic.S | 659 ++++++++++++++++++ components/newlib/stdatomic.c | 12 + 3 files changed, 675 insertions(+) create mode 100644 components/newlib/port/riscv/port_stdatomic.S diff --git a/components/newlib/port/CMakeLists.txt b/components/newlib/port/CMakeLists.txt index a9187d56a4..c4c37abfd0 100644 --- a/components/newlib/port/CMakeLists.txt +++ b/components/newlib/port/CMakeLists.txt @@ -1 +1,5 @@ target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/esp_time_impl.c") + +if(CONFIG_IDF_TARGET_ARCH_RISCV) + target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/riscv/port_stdatomic.S") +endif() diff --git a/components/newlib/port/riscv/port_stdatomic.S b/components/newlib/port/riscv/port_stdatomic.S new file mode 100644 index 0000000000..b43fb03db9 --- /dev/null +++ b/components/newlib/port/riscv/port_stdatomic.S @@ -0,0 +1,659 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#if __riscv_atomic == 1 + +.macro ALIGNED_PTR_2 ptr, offset + andi \ptr, a0, -4 // aligned ptr + sub \offset, a0, \ptr + slli \offset, \offset, 3 // offset (in bits) between ptr and aligned ptr + li t6, 24 + bne \offset, t6, 1f // do atomic operation in case var is not splited between 2 words + lr.w t2, (a0) // invokes 'Load access fault!' +1: +.endm + + .global __atomic_load_2 + .type __atomic_load_2, @function +__atomic_load_2: + ALIGNED_PTR_2 t0, t1 + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_load_2, . - __atomic_load_2 + + + .global __atomic_store_2 + .type __atomic_store_2, @function +__atomic_store_2: + ALIGNED_PTR_2 t0, t1 + li t6, 0xffff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + sll t5, a1, t1 // t5 - shifted new value to easy place into aligned memory +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - masked aliged memory. Atomic variable part is zeroed here + or t4, t5, t3 // t4 - combine desire half-word with half-word from origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + ret + .size __atomic_store_2, . - __atomic_store_2 + + + .global __atomic_exchange_2 + .type __atomic_exchange_2, @function +__atomic_exchange_2: + ALIGNED_PTR_2 t0, t1 + li t6, 0xffff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + sll t5, a1, t1 // t5 - shifted new value to easy place into aligned memory +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - masked aliged memory. Atomic variable part is zeroed here + or t4, t5, t3 // t4 - combine desire half-word with half-word from origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + srl t4, t2, t1 + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_exchange_2, . - __atomic_exchange_2 + + + .global __atomic_compare_exchange_2 + .type __atomic_compare_exchange_2, @function +__atomic_compare_exchange_2: + ALIGNED_PTR_2 t0, t1 + li t6, 0xffff0000 + srl t6, t6, t1 // t6 - bitwise mask (0xffff0000/0x0000ffff) + lhu t5, (a1) + sll t5, t5, t1 // t5 - shifted expect value to easy compare with aligned memory + sll t4, a2, t1 // t4 - shifted desired value to easy place into aligned memory +1: // do not change registers (t0, t1, t4, t5) after this label + not t6, t6 + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - prepare half-word from aligned memory to compare with expected (t5) + bne t3, t5, 2f + not t6, t6 + and t2, t2, t6 + or t3, t4, t2 // t3 - combine desire half-word with half-word from origin aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + li a0, 1 + ret +2: + srl t3, t3, t1 + sh t3, (a1) // store atomic value into expect variable + li a0, 0 + ret + .size __atomic_compare_exchange_2, . - __atomic_compare_exchange_2 + + + .global __atomic_fetch_or_2 + .type __atomic_fetch_or_2, @function +__atomic_fetch_or_2: + ALIGNED_PTR_2 t0, t1 + sll t2, a1, t1 // t2 - shifted value half-word. + amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + slli a0, t0, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_fetch_or_2, . - __atomic_fetch_or_2 + + + .global __atomic_or_fetch_2 + .type __atomic_or_fetch_2, @function +__atomic_or_fetch_2: + ALIGNED_PTR_2 t0, t1 + sll t2, a1, t1 // t2 - shifted value half-word. + amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + slli a0, t2, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_or_fetch_2, . - __atomic_or_fetch_2 + + + .global __atomic_fetch_xor_2 + .type __atomic_fetch_xor_2, @function +__atomic_fetch_xor_2: + ALIGNED_PTR_2 t0, t1 + sll t2, a1, t1 // t2 - shifted value half-word. + amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + slli a0, t0, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_fetch_xor_2, . - __atomic_fetch_xor_2 + + + .global __atomic_xor_fetch_2 + .type __atomic_xor_fetch_2, @function +__atomic_xor_fetch_2: + ALIGNED_PTR_2 t0, t1 + sll t2, a1, t1 // t2 - shifted value half-word. + amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + slli a0, t2, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_xor_fetch_2, . - __atomic_xor_fetch_2 + + + .global __atomic_fetch_and_2 + .type __atomic_fetch_and_2, @function +__atomic_fetch_and_2: + ALIGNED_PTR_2 t0, t1 + li t6, 0xffff0000 // t6 - bitwise mask + srl t6, t6, t1 // t6 - using to fill non-atomic bytes with 0xff in aligned memory + sll t2, a1, t1 // t2 - shifted value half-word. + or t2, t2, t6 // t2 - 0xXXXXffff or 0xffffXXXX where is value halfword + amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + slli a0, t0, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_fetch_and_2, . - __atomic_fetch_and_2 + + + .global __atomic_and_fetch_2 + .type __atomic_and_fetch_2, @function +__atomic_and_fetch_2: + ALIGNED_PTR_2 t0, t1 + li t6, 0xffff0000 // t6 - bitwise mask + srl t6, t6, t1 // t6 - using to fill non-atomic bytes with 0xff in aligned memory + sll t2, a1, t1 // t2 - shifted value half-word. + or t2, t2, t6 // t2 - 0xXXXXffff or 0xffffXXXX where XXXX is value halfword + amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + slli a0, t2, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_and_fetch_2, . - __atomic_and_fetch_2 + + + .global __atomic_fetch_nand_2 + .type __atomic_fetch_nand_2, @function +__atomic_fetch_nand_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff + sll t5, t5, t1 // t5 - bitwise mask + not t6, t5 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + and t3, t3, a1 + not t3, t3 // t3 - atomic value to write + sll t3, t3, t1 + and t4, t2, t6 // t4 - masked aliged memory. Atomic variable part is zeroed here + or t4, t4, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t4, t4, (t0) // t3 - atomic write result (0 - success) + bnez t4, 1b + srl t4, t2, t1 + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_fetch_nand_2, . - __atomic_fetch_nand_2 + + + .global __atomic_nand_fetch_2 + .type __atomic_nand_fetch_2, @function +__atomic_nand_fetch_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff + sll t5, t5, t1 // t5 - bitwise mask + not t6, t5 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + and t3, t3, a1 + not t3, t3 // t3 - atomic value to write + sll t3, t3, t1 + and t4, t2, t6 // t4 - masked aliged memory. Atomic variable part is zeroed here + or t4, t4, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t4, t4, (t0) // t3 - atomic write result (0 - success) + bnez t4, 1b + srl t4, t2, t1 + slli a0, t3, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_nand_fetch_2, . - __atomic_nand_fetch_2 + + + .global __atomic_fetch_sub_2 + .type __atomic_fetch_sub_2, @function +__atomic_fetch_sub_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff // t5 - bitwise mask + not t6, t5 + srl t6, t6, t1 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl a0, t2, t1 + and a0, a0, t5 // a0 - value in atomic before performing operation + sub t3, a0, a1 + and t3, t3, t5 // t3 - value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + ret + .size __atomic_fetch_sub_2, . - __atomic_fetch_sub_2 + + + .global __atomic_sub_fetch_2 + .type __atomic_sub_fetch_2, @function +__atomic_sub_fetch_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff // t5 - bitwise mask + not t6, t5 + srl t6, t6, t1 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + and t4, t4, t5 + sub t4, t4, a1 + and t4, t4, t5 // t4 - value to be written to atomic + sll t4, t4, t1 + and t2, t2, t6 + or t4, t4, t2 // t4 - value to be written into aligned memory + sc.w t2, t4, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + srl t4, t4, t1 + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_sub_fetch_2, . - __atomic_sub_fetch_2 + + + .global __atomic_fetch_add_2 + .type __atomic_fetch_add_2, @function +__atomic_fetch_add_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff // t5 - bitwise mask + not t6, t5 + srl t6, t6, t1 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + and t4, t4, t5 // t4 - half-word value in atomic before performing operation + add t3, t4, a1 + and t4, t4, t5 // t3 - half-word value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_fetch_add_2, . - __atomic_fetch_add_2 + + + .global __atomic_add_fetch_2 + .type __atomic_add_fetch_2, @function +__atomic_add_fetch_2: + ALIGNED_PTR_2 t0, t1 + li t5, 0xffff // t5 - bitwise mask + not t6, t5 + srl t6, t6, t1 // t6 - bitwise mask +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + and t4, t4, t5 + add t4, t4, a1 + and t4, t4, t5 // t4 - value to be written to atomic + sll t4, t4, t1 + and t2, t2, t6 + or t4, t4, t2 // t4 - value to be written into aligned memory + sc.w t2, t4, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + srl t4, t4, t1 + slli a0, t4, 0x10 + srli a0, a0, 0x10 + ret + .size __atomic_add_fetch_2, . - __atomic_add_fetch_2 + + + .global __atomic_load_1 + .type __atomic_load_1, @function +__atomic_load_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + andi a0, t4, 0xff + ret + .size __atomic_load_1, . - __atomic_load_1 + + + .global __atomic_store_1 + .type __atomic_store_1, @function +__atomic_store_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + sll t5, a1, t1 // t5 - shifted new value to easy place into aligned memory +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - masked aliged memory. Atomic variable part is zeroed here + or t4, t5, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + ret + .size __atomic_store_1, . - __atomic_store_1 + + + .global __atomic_exchange_1 + .type __atomic_exchange_1, @function +__atomic_exchange_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + sll t5, a1, t1 // t5 - shifted new value to easy place into aligned memory +1: // do not change registers (t0, t1, t5, t6) after this label + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - masked aliged memory. Atomic variable part is zeroed here + or t4, t5, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + srl t4, t2, t1 + andi a0, t4, 0xff + ret + .size __atomic_exchange_1, . - __atomic_exchange_1 + + + .global __atomic_compare_exchange_1 + .type __atomic_compare_exchange_1, @function +__atomic_compare_exchange_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask + lbu t5, (a1) + sll t5, t5, t1 // t5 - shifted expect value to easy compare with aligned memory + sll t4, a2, t1 // t4 - shifted desired value to easy place into aligned memory +1: // do not change registers (t0, t1, t4, t5) after this label + not t6, t6 + lr.w t2, (t0) // t2 - load atomic + and t3, t2, t6 // t3 - prepare half-word from aligned memory to compare with expected (t5) + bne t3, t5, 2f // goto fail + not t6, t6 + and t2, t2, t6 + or t3, t4, t2 // t3 - combine desire half-word with half-word from origin aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b // retry + li a0, 1 + ret +2: + srl t3, t3, t1 + sb t3, (a1) // store atomic value into expect variable + li a0, 0 + ret + .size __atomic_compare_exchange_1, . - __atomic_compare_exchange_1 + + + .global __atomic_fetch_or_1 + .type __atomic_fetch_or_1, @function +__atomic_fetch_or_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + sll t2, a1, t1 // t2 - shifted value half-word. + amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + andi a0, t0, 0xff + ret + .size __atomic_fetch_or_1, . - __atomic_fetch_or_1 + + + .global __atomic_or_fetch_1 + .type __atomic_or_fetch_1, @function +__atomic_or_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + sll t2, a1, t1 // t2 - shifted byte-word value. + amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + andi a0, t2, 0xff + ret + .size __atomic_or_fetch_1, . - __atomic_or_fetch_1 + + + .global __atomic_fetch_xor_1 + .type __atomic_fetch_xor_1, @function +__atomic_fetch_xor_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + sll t2, a1, t1 // t2 - shifted value byte-word. + amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + andi a0, t0, 0xff + ret + .size __atomic_fetch_xor_1, . - __atomic_fetch_xor_1 + + + .global __atomic_xor_fetch_1 + .type __atomic_xor_fetch_1, @function +__atomic_xor_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + sll t2, a1, t1 // t2 - shifted value byte-word. + amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + andi a0, t2, 0xff + ret + .size __atomic_xor_fetch_1, . - __atomic_xor_fetch_1 + + + .global __atomic_fetch_and_1 + .type __atomic_fetch_and_1, @function +__atomic_fetch_and_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 + li t6, 0xff // t6 - bitwise mask + sll t6, t6, t1 // t6 - using to fill non-atomic bytes with 0xff in aligned memory + not t6, t6 + sll t2, a1, t1 // t2 - shifted value byte-word. + or t2, t2, t6 // t2 - (0xXXffffff or 0xffXXffff ...) where XX - new value to write + amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t0, t0, t1 + andi a0, t0, 0xff + ret + .size __atomic_fetch_and_1, . - __atomic_fetch_and_1 + + + .global __atomic_and_fetch_1 + .type __atomic_and_fetch_1, @function +__atomic_and_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 + li t6, 0xff // t6 - bitwise mask + sll t6, t6, t1 // t6 - using to fill non-atomic bytes with 0xff in aligned memory + not t6, t6 + sll t2, a1, t1 // t2 - shifted value byte-word. + or t2, t2, t6 // t2 - (0xXXffffff or 0xffXXffff ...) where XX - new value to write + amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed + srl t2, t2, t1 + andi a0, t2, 0xff + ret + .size __atomic_and_fetch_1, . - __atomic_and_fetch_1 + + + .global __atomic_nand_fetch_1 + .type __atomic_nand_fetch_1, @function +__atomic_nand_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + and t3, t3, a1 + not t3, t3 // t3 - atomic value to write + sll t3, t3, t1 + and t4, t2, t6 // t4 - masked aliged memory. Atomic variable part is zeroed here + or t4, t4, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + srl t4, t4, t1 + andi a0, t4, 0xff + ret + .size __atomic_nand_fetch_1, . - __atomic_nand_fetch_1 + + + .global __atomic_fetch_nand_1 + .type __atomic_fetch_nand_1, @function +__atomic_fetch_nand_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + and t3, t3, a1 + not t3, t3 // t3 - atomic value to write + sll t3, t3, t1 + and t4, t2, t6 // t4 - masked aliged memory. Atomic variable part is zeroed here + or t4, t4, t3 // t4 - combine desire byte-word with origin aligned memory + sc.w t3, t4, (t0) // t3 - atomic write result (0 - success) + bnez t3, 1b + srl t4, t2, t1 + andi a0, t4, 0xff + ret + .size __atomic_fetch_nand_1, . - __atomic_fetch_nand_1 + + + .global __atomic_fetch_sub_1 + .type __atomic_fetch_sub_1, @function +__atomic_fetch_sub_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + andi t4, t4, 0xff // t4 - value in atomic before performing operation + sub t3, t4, a1 + andi t3, t3, 0xff // t3 - value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + andi a0, t4, 0xff + ret + .size __atomic_fetch_sub_1, . - __atomic_fetch_sub_1 + + + .global __atomic_sub_fetch_1 + .type __atomic_sub_fetch_1, @function +__atomic_sub_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + andi t3, t3, 0xff // t3 - value in atomic before performing operation + sub t3, t3, a1 + andi t3, t3, 0xff // t3 - value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + srl t3, t3, t1 + andi a0, t3, 0xff + ret + .size __atomic_sub_fetch_1, . - __atomic_sub_fetch_1 + + + .global __atomic_fetch_add_1 + .type __atomic_fetch_add_1, @function +__atomic_fetch_add_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t4, t2, t1 + andi t4, t4, 0xff // t4 - value in atomic before performing operation + add t3, t4, a1 + andi t3, t3, 0xff // t3 - value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + andi a0, t4, 0xff + ret + .size __atomic_fetch_add_1, . - __atomic_fetch_add_1 + + + .global __atomic_add_fetch_1 + .type __atomic_add_fetch_1, @function +__atomic_add_fetch_1: + andi t0, a0, -4 // t0 - aligned ptr + sub t1, a0, t0 + slli t1, t1, 3 // t1 - offset (in bits) between ptr and aligned ptr + li t6, 0xff + sll t6, t6, t1 + not t6, t6 // t6 - bitwise mask +1: // do not change registers (t0, t1, t6) after this label + lr.w t2, (t0) // t2 - load atomic + srl t3, t2, t1 + andi t3, t3, 0xff // t3 - value in atomic before performing operation + add t3, t3, a1 + andi t3, t3, 0xff // t3 - value to be written to atomic + sll t3, t3, t1 + and t2, t2, t6 + or t3, t3, t2 // t3 - value to be written into aligned memory + sc.w t2, t3, (t0) // t2 - atomic write result (0 - success) + bnez t2, 1b + srl t3, t3, t1 + andi a0, t3, 0xff + ret + .size __atomic_add_fetch_1, . - __atomic_add_fetch_1 + +#endif // if __riscv_atomic == 1 diff --git a/components/newlib/stdatomic.c b/components/newlib/stdatomic.c index 54de84e6d2..ae52f83ed5 100644 --- a/components/newlib/stdatomic.c +++ b/components/newlib/stdatomic.c @@ -434,6 +434,18 @@ ATOMIC_STORE(1, unsigned char) ATOMIC_STORE(2, short unsigned int) ATOMIC_STORE(4, unsigned int) +#elif __riscv_atomic == 1 + +bool CLANG_ATOMIC_SUFFIX(__atomic_always_lock_free) (unsigned int size, const volatile void *) { + return size <= sizeof(int); +} +CLANG_DECLARE_ALIAS( __atomic_always_lock_free) + +bool CLANG_ATOMIC_SUFFIX(__atomic_is_lock_free) (unsigned int size, const volatile void *) { + return size <= sizeof(int); +} +CLANG_DECLARE_ALIAS( __atomic_is_lock_free) + #endif // !HAS_ATOMICS_32 #if !HAS_ATOMICS_64 From d4b7be4a739cbab070e0c3dd2a195304cdf23cbf Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:34:31 +0700 Subject: [PATCH 11/25] bt: fix gcc-12 compile errors --- .../api/core/esp_ble_mesh_provisioning_api.c | 2 +- components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c | 4 ++-- .../esp_ble_mesh/btc/btc_ble_mesh_config_model.c | 10 +++++----- .../esp_ble_mesh/btc/btc_ble_mesh_generic_model.c | 12 ++++++------ .../esp_ble_mesh/btc/btc_ble_mesh_health_model.c | 4 ++-- .../esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c | 4 ++-- components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c | 14 ++++++-------- .../esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c | 12 ++++++------ .../btc/btc_ble_mesh_time_scene_model.c | 2 +- .../bt/host/bluedroid/bta/gatt/bta_gatts_act.c | 6 ++---- .../bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c | 4 ++-- components/bt/host/bluedroid/stack/smp/smp_l2c.c | 2 +- .../bluedroid/classic_bt/bt_discovery/README.md | 4 ++-- .../bluedroid/classic_bt/bt_discovery/main/main.c | 2 +- .../classic_bt/bt_hid_mouse_device/main/main.c | 2 +- 15 files changed, 40 insertions(+), 44 deletions(-) diff --git a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c index a2fcfd9c72..017164a7c2 100644 --- a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c +++ b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c @@ -494,7 +494,7 @@ esp_err_t esp_ble_mesh_set_fast_prov_info(esp_ble_mesh_fast_prov_info_t *fast_pr arg.set_fast_prov_info.iv_index = fast_prov_info->iv_index; arg.set_fast_prov_info.offset = fast_prov_info->offset; arg.set_fast_prov_info.match_len = fast_prov_info->match_len; - if (fast_prov_info->match_len && fast_prov_info->match_val) { + if (fast_prov_info->match_len) { memcpy(arg.set_fast_prov_info.match_val, fast_prov_info->match_val, fast_prov_info->match_len); } return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_mesh_prov_args_t), NULL, NULL) diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c index 8fba9e9fed..01d0ece010 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c @@ -50,7 +50,7 @@ static void btc_ble_mesh_ble_free_req_data(btc_msg_t *msg) #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN esp_ble_mesh_ble_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -116,7 +116,7 @@ void btc_ble_mesh_ble_call_handler(btc_msg_t *msg) esp_ble_mesh_ble_cb_param_t param = {0}; btc_ble_mesh_ble_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c index 08b2b7a4dd..1057d867fa 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c @@ -87,7 +87,7 @@ void btc_ble_mesh_config_client_arg_deep_free(btc_msg_t *msg) { btc_ble_mesh_config_client_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -232,7 +232,7 @@ static void btc_ble_mesh_config_client_free_req_data(btc_msg_t *msg) { esp_ble_mesh_cfg_client_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -618,7 +618,7 @@ void btc_ble_mesh_config_client_call_handler(btc_msg_t *msg) btc_ble_mesh_config_client_args_t *arg = NULL; esp_ble_mesh_cfg_client_cb_param_t cb = {0}; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -656,7 +656,7 @@ void btc_ble_mesh_config_client_cb_handler(btc_msg_t *msg) { esp_ble_mesh_cfg_client_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -748,7 +748,7 @@ void btc_ble_mesh_config_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_cfg_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c index 760c6e5c64..ea64584b19 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c @@ -111,7 +111,7 @@ void btc_ble_mesh_generic_client_arg_deep_free(btc_msg_t *msg) { btc_ble_mesh_generic_client_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -295,7 +295,7 @@ static void btc_ble_mesh_generic_client_free_req_data(btc_msg_t *msg) { esp_ble_mesh_generic_client_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -447,7 +447,7 @@ void btc_ble_mesh_generic_client_call_handler(btc_msg_t *msg) esp_ble_mesh_generic_client_cb_param_t cb = {0}; bt_mesh_client_common_param_t common = {0}; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -507,7 +507,7 @@ void btc_ble_mesh_generic_client_cb_handler(btc_msg_t *msg) { esp_ble_mesh_generic_client_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -629,7 +629,7 @@ static void btc_ble_mesh_generic_server_free_req_data(btc_msg_t *msg) { esp_ble_mesh_generic_server_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -738,7 +738,7 @@ void btc_ble_mesh_generic_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_generic_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c index 2a84fea629..8be7fdee36 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c @@ -551,7 +551,7 @@ void btc_ble_mesh_health_server_call_handler(btc_msg_t *msg) esp_ble_mesh_health_server_cb_param_t param = {0}; btc_ble_mesh_health_server_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -577,7 +577,7 @@ void btc_ble_mesh_health_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_health_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c index c5412eb802..8c96ef8286 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c @@ -452,7 +452,7 @@ static void btc_ble_mesh_lighting_server_free_req_data(btc_msg_t *msg) { esp_ble_mesh_lighting_server_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -553,7 +553,7 @@ void btc_ble_mesh_lighting_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_lighting_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c index dfeaddb002..59be9f5d87 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c @@ -124,7 +124,7 @@ void btc_ble_mesh_prov_arg_deep_free(btc_msg_t *msg) { btc_ble_mesh_prov_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -200,7 +200,7 @@ void btc_ble_mesh_model_arg_deep_free(btc_msg_t *msg) { btc_ble_mesh_model_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -309,7 +309,7 @@ static void btc_ble_mesh_model_free_req_data(btc_msg_t *msg) { esp_ble_mesh_model_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -2278,9 +2278,7 @@ void btc_ble_mesh_prov_call_handler(btc_msg_t *msg) /* Callback operation completion events */ btc_ble_mesh_prov_set_complete_cb(¶m, act); - if (msg->arg) { - btc_ble_mesh_prov_arg_deep_free(msg); - } + btc_ble_mesh_prov_arg_deep_free(msg); return; } @@ -2307,7 +2305,7 @@ void btc_ble_mesh_model_call_handler(btc_msg_t *msg) btc_ble_mesh_model_args_t *arg = NULL; int err = 0; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -2403,7 +2401,7 @@ void btc_ble_mesh_model_cb_handler(btc_msg_t *msg) { esp_ble_mesh_model_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c index 4c6007fa64..d0df2febda 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c @@ -179,7 +179,7 @@ void btc_ble_mesh_sensor_client_arg_deep_free(btc_msg_t *msg) { btc_ble_mesh_sensor_client_args_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -378,7 +378,7 @@ static void btc_ble_mesh_sensor_client_free_req_data(btc_msg_t *msg) { esp_ble_mesh_sensor_client_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -529,7 +529,7 @@ void btc_ble_mesh_sensor_client_call_handler(btc_msg_t *msg) esp_ble_mesh_sensor_client_cb_param_t cb = {0}; bt_mesh_client_common_param_t common = {0}; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -589,7 +589,7 @@ void btc_ble_mesh_sensor_client_cb_handler(btc_msg_t *msg) { esp_ble_mesh_sensor_client_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -761,7 +761,7 @@ static void btc_ble_mesh_sensor_server_free_req_data(btc_msg_t *msg) { esp_ble_mesh_sensor_server_cb_param_t *arg = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } @@ -870,7 +870,7 @@ void btc_ble_mesh_sensor_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_sensor_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c index 0c5503ab7d..dde61d4138 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c @@ -456,7 +456,7 @@ void btc_ble_mesh_time_scene_server_cb_handler(btc_msg_t *msg) { esp_ble_mesh_time_scene_server_cb_param_t *param = NULL; - if (!msg || !msg->arg) { + if (!msg) { BT_ERR("%s, Invalid parameter", __func__); return; } diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c b/components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c index 5320f66711..ca2538696d 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c @@ -699,7 +699,7 @@ void bta_gatts_indicate_handle (tBTA_GATTS_CB *p_cb, tBTA_GATTS_DATA *p_msg) cb_data.req_data.data_len = 0; cb_data.req_data.handle = p_msg->api_indicate.attr_id; - if (p_msg->api_indicate.value && (p_msg->api_indicate.len > 0)) { + if (p_msg->api_indicate.len > 0) { cb_data.req_data.value = (uint8_t *) osi_malloc(p_msg->api_indicate.len); if (cb_data.req_data.value != NULL) { memset(cb_data.req_data.value, 0, p_msg->api_indicate.len); @@ -709,9 +709,7 @@ void bta_gatts_indicate_handle (tBTA_GATTS_CB *p_cb, tBTA_GATTS_DATA *p_msg) APPL_TRACE_ERROR("%s, malloc failed", __func__); } } else { - if (p_msg->api_indicate.value) { - APPL_TRACE_ERROR("%s, incorrect length", __func__); - } + APPL_TRACE_ERROR("%s, incorrect length", __func__); } (*p_rcb->p_cback)(BTA_GATTS_CONF_EVT, &cb_data); if (cb_data.req_data.value != NULL) { diff --git a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c index 4f254c605f..e42c590cd4 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c +++ b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c @@ -1472,10 +1472,10 @@ void btc_hf_cb_handler(btc_msg_t *msg) case BTA_AG_AT_D_EVT: { do { - if (event == BTA_AG_AT_D_EVT && p_data->val.str) { // dial_number_or_memory + if (event == BTA_AG_AT_D_EVT) { // dial_number_or_memory memset(¶m, 0, sizeof(esp_hf_cb_param_t)); param.out_call.num_or_loc = osi_malloc((strlen(p_data->val.str) + 1) * sizeof(char)); - sprintf(param.out_call.num_or_loc, p_data->val.str); + sprintf(param.out_call.num_or_loc, "%s", p_data->val.str); btc_hf_cb_to_app(ESP_HF_DIAL_EVT, ¶m); send_indicator_update(BTA_AG_IND_CALLSETUP,BTA_AG_CALLSETUP_OUTGOING); osi_free(param.out_call.num_or_loc); diff --git a/components/bt/host/bluedroid/stack/smp/smp_l2c.c b/components/bt/host/bluedroid/stack/smp/smp_l2c.c index 67dd1ac5ae..a6f0670598 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_l2c.c +++ b/components/bt/host/bluedroid/stack/smp/smp_l2c.c @@ -111,7 +111,7 @@ static void smp_connect_callback (UINT16 channel, BD_ADDR bd_addr, BOOLEAN conne if (transport == BT_TRANSPORT_BR_EDR || memcmp(bd_addr, dummy_bda, BD_ADDR_LEN) == 0) { return; } - if(!connected && &p_cb->rsp_timer_ent) { + if(!connected) { //free timer btu_free_timer(&p_cb->rsp_timer_ent); } diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_discovery/README.md b/examples/bluetooth/bluedroid/classic_bt/bt_discovery/README.md index df62b40717..663337986c 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_discovery/README.md +++ b/examples/bluetooth/bluedroid/classic_bt/bt_discovery/README.md @@ -219,7 +219,7 @@ for (int i = 0; i < param->disc_res.num_prop; i++) { Pay attention that some Bluetooth devices may put their name in EIR data. We can get the device name from EIR data. ```c -if (p_dev->eir && p_dev->bdname_len == 0) { +if (p_dev->bdname_len == 0) { get_name_from_eir(p_dev->eir, p_dev->bdname, &p_dev->bdname_len); } ``` @@ -266,4 +266,4 @@ for (int i = 0; i < param->rmt_srvcs.num_uuids; i++) { ## Conclusion -We have reviewed the Bluetooth discovery example code. This example searches for nearby devices. When the device of interest is found, the example searches for the services of this device. We can get the device discovery result and service discovery result from the GAP callback, which is registered in advance. \ No newline at end of file +We have reviewed the Bluetooth discovery example code. This example searches for nearby devices. When the device of interest is found, the example searches for the services of this device. We can get the device discovery result and service discovery result from the GAP callback, which is registered in advance. diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_discovery/main/main.c b/examples/bluetooth/bluedroid/classic_bt/bt_discovery/main/main.c index df854cd22c..b73c055edd 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_discovery/main/main.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_discovery/main/main.c @@ -181,7 +181,7 @@ static void update_device_info(esp_bt_gap_cb_param_t *param) p_dev->eir_len = eir_len; } - if (p_dev->eir && p_dev->bdname_len == 0) { + if (p_dev->bdname_len == 0) { get_name_from_eir(p_dev->eir, p_dev->bdname, &p_dev->bdname_len); } diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_hid_mouse_device/main/main.c b/examples/bluetooth/bluedroid/classic_bt/bt_hid_mouse_device/main/main.c index faf28f61b7..372f1e80a7 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_hid_mouse_device/main/main.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_hid_mouse_device/main/main.c @@ -262,7 +262,7 @@ void esp_bt_hidd_cb(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param) ESP_LOGI(TAG, "setting hid parameters success!"); ESP_LOGI(TAG, "setting to connectable, discoverable"); esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); - if (param->register_app.in_use && param->register_app.bd_addr != NULL) { + if (param->register_app.in_use) { ESP_LOGI(TAG, "start virtual cable plug!"); esp_bt_hid_device_connect(param->register_app.bd_addr); } From 49af663dfb00addd3a863725f00d20e14fada692 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:35:34 +0700 Subject: [PATCH 12/25] esp_system: fix gcc-12 compile errors --- components/esp_system/debug_stubs.c | 1 - components/esp_system/port/arch/riscv/panic_arch.c | 1 - components/esp_system/test/test_backtrace.c | 3 ++- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/components/esp_system/debug_stubs.c b/components/esp_system/debug_stubs.c index 7d1a255278..7de24bf1dd 100644 --- a/components/esp_system/debug_stubs.c +++ b/components/esp_system/debug_stubs.c @@ -55,7 +55,6 @@ static void esp_dbg_stubs_data_free(void *addr) { ESP_LOGV(TAG, "%s %p", __func__, addr); free(addr); - ESP_LOGV(TAG, "%s EXIT %p", __func__, addr); } void esp_dbg_stubs_init(void) diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c index 8ad790160c..2010d004f1 100644 --- a/components/esp_system/port/arch/riscv/panic_arch.c +++ b/components/esp_system/port/arch/riscv/panic_arch.c @@ -348,7 +348,6 @@ void panic_arch_fill_info(void *frame, panic_info_t *info) info->description = "Exception was unhandled."; info->addr = (void *) regs->mepc; - info->frame = ®s; } static void panic_print_basic_backtrace(const void *frame, int core) diff --git a/components/esp_system/test/test_backtrace.c b/components/esp_system/test/test_backtrace.c index 11a82b83f0..034c5201ae 100644 --- a/components/esp_system/test/test_backtrace.c +++ b/components/esp_system/test/test_backtrace.c @@ -19,6 +19,7 @@ #include "esp_intr_alloc.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" +#include "hal/misc.h" #define SW_ISR_LEVEL_1 7 #define SW_ISR_LEVEL_3 29 @@ -83,7 +84,7 @@ TEST_CASE("Test backtrace from interrupt watchdog timeout", "[reset_reason][rese static void write_char_crash(char c) { esp_rom_uart_putc(c); - *(char*) 0x00000001 = 0; + hal_memset((void *)0x00000001, 0, 1); } TEST_CASE("Test backtrace with a ROM function", "[reset_reason][reset=StoreProhibited,SW_CPU_RESET]") From 75642ca07a69acfe73fca081c5330b6924b80fdf Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:36:43 +0700 Subject: [PATCH 13/25] vfs: fix gcc-12 compile errors --- components/vfs/vfs_semihost.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/vfs/vfs_semihost.c b/components/vfs/vfs_semihost.c index 267f85cafc..f1af8fb992 100644 --- a/components/vfs/vfs_semihost.c +++ b/components/vfs/vfs_semihost.c @@ -326,7 +326,7 @@ static DIR* vfs_semihost_opendir(void* ctx, const char *restrict path) return NULL; } - strncpy(semihost_dirp->path, path, MIN(strlen(path), sizeof(semihost_dirp->path) - 1)); + strncpy(semihost_dirp->path, path, sizeof(semihost_dirp->path) - 1); ESP_LOGV(TAG, "%s: '%s'", __func__, path); int ret_fd = semihosting_opendir(path, (int)&semihost_dirp->id); if (ret_fd < 0) { From a7e51b2509a7338a4375cac52be284813de543a5 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:37:27 +0700 Subject: [PATCH 14/25] protocomm: fix gcc-12 compile errors --- components/protocomm/src/transports/protocomm_ble.c | 2 +- components/protocomm/src/transports/protocomm_nimble.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/protocomm/src/transports/protocomm_ble.c b/components/protocomm/src/transports/protocomm_ble.c index 90f18cc7c0..5af270353c 100644 --- a/components/protocomm/src/transports/protocomm_ble.c +++ b/components/protocomm/src/transports/protocomm_ble.c @@ -484,7 +484,7 @@ static void protocomm_ble_cleanup(void) esp_err_t protocomm_ble_start(protocomm_t *pc, const protocomm_ble_config_t *config) { - if (!pc || !config || !config->device_name || !config->nu_lookup) { + if (!pc || !config || !config->nu_lookup) { return ESP_ERR_INVALID_ARG; } diff --git a/components/protocomm/src/transports/protocomm_nimble.c b/components/protocomm/src/transports/protocomm_nimble.c index 806b8775ad..ab2b80f35d 100644 --- a/components/protocomm/src/transports/protocomm_nimble.c +++ b/components/protocomm/src/transports/protocomm_nimble.c @@ -844,7 +844,7 @@ static void free_gatt_ble_misc_memory(simple_ble_cfg_t *ble_config) esp_err_t protocomm_ble_start(protocomm_t *pc, const protocomm_ble_config_t *config) { - if (!pc || !config || !config->device_name || !config->nu_lookup) { + if (!pc || !config || !config->nu_lookup) { return ESP_ERR_INVALID_ARG; } From adcdfa641cc6587eed06bf1d982b606324c93412 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 11:37:59 +0700 Subject: [PATCH 15/25] wpa_supplicant: fix gcc-12 compile errors --- components/wpa_supplicant/src/common/bss.c | 2 +- components/wpa_supplicant/src/tls/pkcs1.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/wpa_supplicant/src/common/bss.c b/components/wpa_supplicant/src/common/bss.c index 3e200d5b26..5868328c54 100644 --- a/components/wpa_supplicant/src/common/bss.c +++ b/components/wpa_supplicant/src/common/bss.c @@ -109,7 +109,7 @@ static int wpa_bss_known(struct wpa_supplicant *wpa_s, struct wpa_bss *bss) { struct wifi_ssid *ssid = esp_wifi_sta_get_prof_ssid_internal(); - if (ssid->ssid == NULL || ssid->len == 0) + if (ssid->len == 0) return 0; if (ssid->len == bss->ssid_len && os_memcmp(ssid->ssid, bss->ssid, ssid->len) == 0) diff --git a/components/wpa_supplicant/src/tls/pkcs1.c b/components/wpa_supplicant/src/tls/pkcs1.c index 49e439d027..f4c84f6207 100644 --- a/components/wpa_supplicant/src/tls/pkcs1.c +++ b/components/wpa_supplicant/src/tls/pkcs1.c @@ -322,8 +322,6 @@ int pkcs1_v15_sig_ver(struct crypto_public_key *pk, return -1; } - os_free(decrypted); - if (hdr.payload + hdr.length != decrypted + decrypted_len) { wpa_printf(MSG_INFO, "PKCS #1: Extra data after signature - reject"); @@ -332,8 +330,10 @@ int pkcs1_v15_sig_ver(struct crypto_public_key *pk, hdr.payload + hdr.length, decrypted + decrypted_len - hdr.payload - hdr.length); + os_free(decrypted); return -1; } + os_free(decrypted); return 0; } From bda5befdf5770e8516e1d3fb0221a4633629e4e5 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 15:07:00 +0700 Subject: [PATCH 16/25] esp_hid: fix gcc-12 compile errors --- components/esp_hid/src/bt_hidd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_hid/src/bt_hidd.c b/components/esp_hid/src/bt_hidd.c index 3b388f805e..ab3d346053 100644 --- a/components/esp_hid/src/bt_hidd.c +++ b/components/esp_hid/src/bt_hidd.c @@ -569,7 +569,7 @@ void bt_hidd_cb(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param) case ESP_HIDD_REGISTER_APP_EVT: { if (param->register_app.status == ESP_HIDD_SUCCESS) { ESP_LOGD(TAG, "Setting hid parameters success!"); - if (param->register_app.in_use && param->register_app.bd_addr != NULL) { + if (param->register_app.in_use) { ESP_LOGI(TAG, "Start virtual cable plug!"); esp_bt_hid_device_connect(param->register_app.bd_addr); } From 4b54c4920327f08d5faae4d55a5dec6c963dfd09 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 22:46:38 +0700 Subject: [PATCH 17/25] heap: fix gcc-12 compile errors --- components/heap/test_apps/main/test_realloc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/components/heap/test_apps/main/test_realloc.c b/components/heap/test_apps/main/test_realloc.c index 9a25d4fbfa..17f293bc6b 100644 --- a/components/heap/test_apps/main/test_realloc.c +++ b/components/heap/test_apps/main/test_realloc.c @@ -20,10 +20,11 @@ TEST_CASE("realloc shrink buffer in place", "[heap]") { - void *x = malloc(64); + // pointers converted to int to avoid warning -Wuse-after-free + int x = (int) malloc(64); TEST_ASSERT(x); - void *y = realloc(x, 48); - TEST_ASSERT_EQUAL_PTR(x, y); + int y = (int) realloc((void *) x, 48); + TEST_ASSERT_EQUAL_UINT32((uint32_t) x, (uint32_t) y); } #endif From ddd645e2c0e63c6686a4dbcee8fa5a33122fda5f Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 6 Feb 2023 22:46:58 +0700 Subject: [PATCH 18/25] esp_event: fix gcc-12 compile errors --- components/esp_event/esp_event.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/components/esp_event/esp_event.c b/components/esp_event/esp_event.c index e82cc66d7b..d6c9d8f886 100644 --- a/components/esp_event/esp_event.c +++ b/components/esp_event/esp_event.c @@ -631,6 +631,7 @@ esp_err_t esp_event_loop_run(esp_event_loop_handle_t event_loop, TickType_t tick esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop) { assert(event_loop); + ESP_LOGD(TAG, "deleting loop %p", (void*) event_loop); esp_event_loop_instance_t* loop = (esp_event_loop_instance_t*) event_loop; SemaphoreHandle_t loop_mutex = loop->mutex; @@ -677,8 +678,6 @@ esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop) #endif vSemaphoreDelete(loop_mutex); - ESP_LOGD(TAG, "deleted loop %p", (void*) event_loop); - return ESP_OK; } From 1e3c18a94aa1578a9522db187f0d9999b560baaa Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 17 Feb 2023 16:53:50 +0800 Subject: [PATCH 19/25] esp_hw_support: fix gcc-12 compile errors --- components/esp_hw_support/sleep_retention.c | 56 +++++++++------------ 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c index 7a79204770..ef5bebee6e 100644 --- a/components/esp_hw_support/sleep_retention.c +++ b/components/esp_hw_support/sleep_retention.c @@ -198,16 +198,14 @@ void sleep_retention_entries_show_memories(void) void * sleep_retention_find_link_by_id(int id) { void *link = NULL; - if (&s_retention.lock) { - _lock_acquire_recursive(&s_retention.lock); - if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && - s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { - for (int entry = 0; (link == NULL && entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries)); entry++) { - link = regdma_find_link_by_id(s_retention.lists[s_retention.highpri].entries[entry], entry, id); - } + _lock_acquire_recursive(&s_retention.lock); + if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && + s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { + for (int entry = 0; (link == NULL && entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries)); entry++) { + link = regdma_find_link_by_id(s_retention.lists[s_retention.highpri].entries[entry], entry, id); } - _lock_release_recursive(&s_retention.lock); } + _lock_release_recursive(&s_retention.lock); return link; } @@ -331,23 +329,21 @@ static void sleep_retention_entries_all_destroy_wrapper(uint32_t module) void sleep_retention_entries_destroy(int module) { assert(module != 0); - if (&s_retention.lock) { - _lock_acquire_recursive(&s_retention.lock); - sleep_retention_entries_join(); - sleep_retention_entries_stats(); - sleep_retention_entries_all_destroy_wrapper(module); - if (s_retention.modules == 0) { - sleep_retention_entries_check_and_distroy_final_default(); - pmu_sleep_disable_regdma_backup(); - memset((void *)s_retention.lists, 0, sizeof(s_retention.lists)); - s_retention.highpri = (uint8_t)-1; - _lock_release_recursive(&s_retention.lock); - _lock_close_recursive(&s_retention.lock); - s_retention.lock = NULL; - return; - } - _lock_acquire_recursive(&s_retention.lock); + _lock_acquire_recursive(&s_retention.lock); + sleep_retention_entries_join(); + sleep_retention_entries_stats(); + sleep_retention_entries_all_destroy_wrapper(module); + if (s_retention.modules == 0) { + sleep_retention_entries_check_and_distroy_final_default(); + pmu_sleep_disable_regdma_backup(); + memset((void *)s_retention.lists, 0, sizeof(s_retention.lists)); + s_retention.highpri = (uint8_t)-1; + _lock_release_recursive(&s_retention.lock); + _lock_close_recursive(&s_retention.lock); + s_retention.lock = NULL; + return; } + _lock_acquire_recursive(&s_retention.lock); } static esp_err_t sleep_retention_entries_create_impl(const sleep_retention_entries_config_t retent[], int num, regdma_link_priority_t priority, int module) @@ -447,14 +443,12 @@ error: void sleep_retention_entries_get(sleep_retention_entries_t *entries) { memset(entries, 0, sizeof(sleep_retention_entries_t)); - if (&s_retention.lock) { - _lock_acquire_recursive(&s_retention.lock); - if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && - s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { - memcpy(entries, &s_retention.lists[s_retention.highpri].entries, sizeof(sleep_retention_entries_t)); - } - _lock_release_recursive(&s_retention.lock); + _lock_acquire_recursive(&s_retention.lock); + if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && + s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { + memcpy(entries, &s_retention.lists[s_retention.highpri].entries, sizeof(sleep_retention_entries_t)); } + _lock_release_recursive(&s_retention.lock); } uint32_t IRAM_ATTR sleep_retention_get_modules(void) From 85b48bfcc0a9d9a812d432d652208b3e06e5a69f Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Tue, 7 Feb 2023 22:56:05 +0700 Subject: [PATCH 20/25] esp_netif: fix test_app_vfs_l2tap stack overflow --- .../test_app_vfs_l2tap/main/test_vfs_l2tap.c | 64 +++++++++++-------- 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c b/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c index 0dfcfdbb1c..31386083dd 100644 --- a/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c +++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c @@ -40,8 +40,12 @@ #define DEFAULT_SEND_DELAY_MS 1000 +#define IN_BUFFER_SIZE 1500 + static const char *TAG = "l2tap_test"; +char *in_buffer; + typedef struct { esp_netif_t *eth_netif; esp_eth_mac_t *mac; @@ -67,6 +71,19 @@ typedef struct { /* ============================================================================= * Common Routines * ============================================================================= */ + +void setUp(void) { + in_buffer = calloc(IN_BUFFER_SIZE, sizeof(*in_buffer)); + if (!in_buffer) { + abort(); + } +} + +void tearDown(void) { + free(in_buffer); + in_buffer = NULL; +} + /** * @brief Event handler for Ethernet events * @@ -286,7 +303,7 @@ typedef struct { static void open_read_task(void *task_param) { - char in_buffer[300] = { 0 }; + const size_t in_buf_size = 300; open_close_task_ctrl_t *task_control = (open_close_task_ctrl_t *)task_param; task_control->eth_tap_fd = open("/dev/net/tap", 0); @@ -321,11 +338,11 @@ static void open_read_task(void *task_param) ESP_LOGI(TAG, "task1: select timeout"); // get an error when try to use closed fd - TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, sizeof(in_buffer))); + TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size)); } else { ESP_LOGI(TAG, "task1: going to block on read..."); // it is expected that blocking read is unblocked by close - TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, sizeof(in_buffer))); + TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size)); ESP_LOGI(TAG, "task1: unblocked"); } xSemaphoreGive(task_control->sem); @@ -419,7 +436,6 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") test_vfs_eth_network_t eth_network_hndls; int eth_tap_fd; int n; - char in_buffer[1500] = { 0 }; int loop_cnt = 0; TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL)); @@ -452,7 +468,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") // Verify the read does not block while (loop_cnt < 100) { - if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) { + if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) { ESP_LOG_BUFFER_HEX(TAG, in_buffer, n); ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -473,7 +489,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") // Verify non-blocking successful read operations used along with select // ========================================================== ESP_LOGI(TAG, "Verify non-blocking successful read operations used along with select..."); - memset(in_buffer, 0, sizeof(in_buffer)); + memset(in_buffer, 0, IN_BUFFER_SIZE); // Wait up to x seconds struct timeval tv; tv.tv_sec = 4; @@ -491,7 +507,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") TEST_ASSERT_GREATER_THAN(-1, FD_ISSET(eth_tap_fd, &rfds)); loop_cnt = 0; while (loop_cnt < 100) { - if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) { + if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) { ESP_LOG_BUFFER_HEX(TAG, in_buffer, n); ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -508,7 +524,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") // Verify non-blocking unsuccessful read operations used along with select // ========================================================== ESP_LOGI(TAG, "Verify non-blocking unsuccessful read operations used along with select..."); - memset(in_buffer, 0, sizeof(in_buffer)); + memset(in_buffer, 0, IN_BUFFER_SIZE); // Wait up to x seconds tv.tv_sec = 2; tv.tv_usec = 0; @@ -521,7 +537,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]") TEST_ASSERT_EQUAL(0, select(eth_tap_fd + 1, &rfds, NULL, NULL, &tv)); TEST_ASSERT_EQUAL(EAGAIN, errno); - n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_EQUAL(EAGAIN, errno); TEST_ASSERT_EQUAL(-1, n); @@ -540,7 +556,6 @@ TEST_CASE("esp32 l2tap - blocking read", "[ethernet]") test_vfs_eth_network_t eth_network_hndls; int eth_tap_fd; int n; - char in_buffer[1500] = { 0 }; int loop_cnt = 0; TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL)); @@ -573,7 +588,7 @@ TEST_CASE("esp32 l2tap - blocking read", "[ethernet]") // Verify the read does block while (loop_cnt < 100) { - if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) { + if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) { ESP_LOG_BUFFER_HEX(TAG, in_buffer, n); ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -660,6 +675,7 @@ static void multi_fds_task (void *task_param) uint16_t eth_filter = task_info->eth_filter; int eth_tap_fds[NUM_OF_FDS]; + test_vfs_eth_tap_msg_t recv_msg; test_vfs_eth_tap_msg_t test_msg = { .header = { .src.addr = {0}, @@ -667,7 +683,6 @@ static void multi_fds_task (void *task_param) .type = 0, } }; - char in_buffer[sizeof(test_msg)] = { 0 }; for (int i = 0; i < sizeof(eth_tap_fds) / sizeof(int); i++) { eth_tap_fds[i] = open("/dev/net/tap", O_NONBLOCK); @@ -691,7 +706,7 @@ static void multi_fds_task (void *task_param) test_msg.cnt = msg_cnt; TEST_ASSERT_NOT_EQUAL(-1, write(eth_tap_fds[i], &test_msg, sizeof(test_msg))); - memset(in_buffer, 0, sizeof(in_buffer)); + memset(&recv_msg, 0, sizeof(recv_msg)); struct timeval tv; tv.tv_sec = 0; @@ -702,9 +717,9 @@ static void multi_fds_task (void *task_param) FD_SET(eth_tap_fds[i], &rfds); if (select(eth_tap_fds[i] + 1, &rfds, NULL, NULL, &tv) > -1) { if (FD_ISSET(eth_tap_fds[i], &rfds)) { - int n = read(eth_tap_fds[i], in_buffer, sizeof(in_buffer)); + int n = read(eth_tap_fds[i], &recv_msg, sizeof(recv_msg)); TEST_ASSERT_GREATER_THAN(0, n); - TEST_ASSERT_EQUAL(msg_cnt, ((test_vfs_eth_tap_msg_t *)in_buffer)->cnt); + TEST_ASSERT_EQUAL(msg_cnt, recv_msg.cnt); } else { TEST_FAIL_MESSAGE("time out, frame was not successfully written (due to possible race condition)"); } @@ -755,7 +770,6 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]") { test_vfs_eth_network_t eth_network_hndls; int eth_tap_fd; - char in_buffer[1500] = { 0 }; TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL)); ethernet_init(ð_network_hndls); @@ -791,7 +805,7 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]") .send_delay_ms = DEFAULT_SEND_DELAY_MS, }; xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); - int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -816,7 +830,7 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]") send_task_ctrl.eth_type = eth_type_filter; xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); ESP_LOGI(TAG, "Verify that the message with new Etherbet type is received..."); - n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -852,7 +866,6 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]") { test_vfs_eth_network_t eth_network_hndls; int eth_tap_fd; - char in_buffer[1500] = { 0 }; TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL)); ethernet_init(ð_network_hndls); @@ -886,7 +899,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]") .send_delay_ms = DEFAULT_SEND_DELAY_MS, }; xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); - int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -897,7 +910,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]") TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_G_INTF_DEVICE, &if_key_str)); TEST_ASSERT_EQUAL_STRING("ETH_DEF", if_key_str); xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 10, NULL); // set higher priority, we need to be sure that "send" task closes FD prior main task - n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -922,7 +935,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]") TEST_ASSERT_EQUAL(eth_type_filter, eth_type_filter_get); xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); - n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -967,7 +980,6 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]") { test_vfs_eth_network_t eth_network_hndls; int eth_tap_fd; - char in_buffer[1500] = { 0 }; TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL)); ethernet_init(ð_network_hndls); @@ -996,7 +1008,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]") }; // Confirm the read blocks by default xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); - int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer)); + int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE); TEST_ASSERT_GREATER_THAN(0, n); TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); @@ -1012,7 +1024,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]") int loop_cnt = 0; xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); while (loop_cnt < 100) { - if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) { + if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) { TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); break; } else { @@ -1039,7 +1051,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]") loop_cnt = 0; xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL); while (loop_cnt < 100) { - if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) { + if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) { TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n); break; } else { From 84ff4d6e372fa25a56ac48e20d6b50a05fed67c2 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 13 Feb 2023 22:37:11 +0700 Subject: [PATCH 21/25] esp_rom: always inline cache.h functions for esp32 --- components/esp_rom/include/esp32/rom/cache.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_rom/include/esp32/rom/cache.h b/components/esp_rom/include/esp32/rom/cache.h index fd28e9f1f0..5b56d7e046 100644 --- a/components/esp_rom/include/esp32/rom/cache.h +++ b/components/esp_rom/include/esp32/rom/cache.h @@ -65,7 +65,7 @@ void mmu_init(int cpu_no); * 4 : mmu table to be written is out of range * 5 : vaddr is out of range */ -static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num) +static inline __attribute__((always_inline)) unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num) { extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num); @@ -118,7 +118,7 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vadd * * @return None */ -static inline void IRAM_ATTR Cache_Read_Init(int cpu_no) +static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Init(int cpu_no) { extern void Cache_Read_Init_rom(int cpu_no); DPORT_STALL_OTHER_CPU_START(); @@ -134,7 +134,7 @@ static inline void IRAM_ATTR Cache_Read_Init(int cpu_no) * * @return None */ -static inline void IRAM_ATTR Cache_Flush(int cpu_no) +static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Flush(int cpu_no) { extern void Cache_Flush_rom(int cpu_no); DPORT_STALL_OTHER_CPU_START(); @@ -150,7 +150,7 @@ static inline void IRAM_ATTR Cache_Flush(int cpu_no) * * @return None */ -static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no) +static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Disable(int cpu_no) { extern void Cache_Read_Disable_rom(int cpu_no); DPORT_STALL_OTHER_CPU_START(); @@ -166,7 +166,7 @@ static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no) * * @return None */ -static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no) +static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Enable(int cpu_no) { extern void Cache_Read_Enable_rom(int cpu_no); DPORT_STALL_OTHER_CPU_START(); From 36d0e275a077c4df4337200b96d866af420d214c Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 13 Feb 2023 12:36:51 +0700 Subject: [PATCH 22/25] hal: always inline clk_tree_ll functions --- .../hal/esp32/include/hal/clk_tree_ll.h | 66 +++++++++---------- .../hal/esp32c2/include/hal/clk_tree_ll.h | 50 +++++++------- .../hal/esp32c3/include/hal/clk_tree_ll.h | 52 +++++++-------- .../hal/esp32c6/include/hal/clk_tree_ll.h | 56 ++++++++-------- .../hal/esp32h2/include/hal/clk_tree_ll.h | 66 +++++++++---------- .../hal/esp32h4/include/hal/clk_tree_ll.h | 48 +++++++------- .../hal/esp32s2/include/hal/clk_tree_ll.h | 64 +++++++++--------- .../hal/esp32s3/include/hal/clk_tree_ll.h | 50 +++++++------- 8 files changed, 226 insertions(+), 226 deletions(-) diff --git a/components/hal/esp32/include/hal/clk_tree_ll.h b/components/hal/esp32/include/hal/clk_tree_ll.h index d6a15c2bed..79ea9fc003 100644 --- a/components/hal/esp32/include/hal/clk_tree_ll.h +++ b/components/hal/esp32/include/hal/clk_tree_ll.h @@ -127,7 +127,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Power up APLL circuit */ -static inline void clk_ll_apll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -136,7 +136,7 @@ static inline void clk_ll_apll_enable(void) /** * @brief Power down APLL circuit */ -static inline void clk_ll_apll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -147,7 +147,7 @@ static inline void clk_ll_apll_disable(void) * * @return True if APLL is under force power down; otherwise false */ -static inline bool clk_ll_apll_is_fpd(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_is_fpd(void) { return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); } @@ -160,7 +160,7 @@ static inline bool clk_ll_apll_is_fpd(void) * @param[out] sdm1 Frequency adjustment parameter, 0..255 * @param[out] sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) { *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV); *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0); @@ -177,7 +177,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3 * @param sdm1 Frequency adjustment parameter, 0..255 * @param sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { uint8_t sdm_stop_val_2 = CLK_LL_APLL_SDM_STOP_VAL_2_REV1; if (is_rev0) { @@ -196,7 +196,7 @@ static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t /** * @brief Set APLL calibration parameters */ -static inline void clk_ll_apll_set_calibration(void) +static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void) { REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1); REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2); @@ -208,7 +208,7 @@ static inline void clk_ll_apll_set_calibration(void) * * @return True if calibration is done; otherwise false */ -static inline bool clk_ll_apll_calibration_is_done(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void) { return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END); } @@ -218,7 +218,7 @@ static inline bool clk_ll_apll_calibration_is_done(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k // Default mode as CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL @@ -244,7 +244,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd status CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M); @@ -255,7 +255,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K); } @@ -283,7 +283,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -296,7 +296,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -307,7 +307,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -317,7 +317,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -325,7 +325,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -333,7 +333,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -343,7 +343,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -351,7 +351,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -359,7 +359,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -367,7 +367,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -375,7 +375,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -385,7 +385,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -395,7 +395,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) * * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. */ -static inline uint32_t clk_ll_bbpll_get_freq_mhz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void) { // ESP32 BBPLL frequency is determined by the cpu freq sel uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); @@ -641,7 +641,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @return Divider. Returns 0 means invalid. */ -static inline uint32_t clk_ll_cpu_get_divider_from_apll(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void) { // APLL path divider choice shares the same register with CPUPERIOD_SEL uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); @@ -695,7 +695,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -718,7 +718,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -739,7 +739,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D4: @@ -759,7 +759,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -788,7 +788,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -804,7 +804,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -857,7 +857,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -875,7 +875,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -887,7 +887,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32c2/include/hal/clk_tree_ll.h b/components/hal/esp32c2/include/hal/clk_tree_ll.h index 3329f4dd07..169056a628 100644 --- a/components/hal/esp32c2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c2/include/hal/clk_tree_ll.h @@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -95,7 +95,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -106,7 +106,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -116,7 +116,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -124,7 +124,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -132,7 +132,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -142,7 +142,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -150,7 +150,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -158,7 +158,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -166,7 +166,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -174,7 +174,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -184,7 +184,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -388,7 +388,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -411,7 +411,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -432,7 +432,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -452,7 +452,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -470,7 +470,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -483,7 +483,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -493,7 +493,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -512,7 +512,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -583,7 +583,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -595,7 +595,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } @@ -605,7 +605,7 @@ static inline uint32_t clk_ll_rtc_slow_load_cal(void) * * @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes */ -static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) { REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us); REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32); @@ -616,7 +616,7 @@ static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) * * @return The value used to correct the time obtained from the rtc timer when the calibration value changes */ -static inline uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) +static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) { return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32); } diff --git a/components/hal/esp32c3/include/hal/clk_tree_ll.h b/components/hal/esp32c3/include/hal/clk_tree_ll.h index 1eec6acfd6..57cd49fcdf 100644 --- a/components/hal/esp32c3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c3/include/hal/clk_tree_ll.h @@ -81,7 +81,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -100,7 +100,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -148,7 +148,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -161,7 +161,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -172,7 +172,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -182,7 +182,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -190,7 +190,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -198,7 +198,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -208,7 +208,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -216,7 +216,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -224,7 +224,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -232,7 +232,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -240,7 +240,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -250,7 +250,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -495,7 +495,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -518,7 +518,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -539,7 +539,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -559,7 +559,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -577,7 +577,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -590,7 +590,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -600,7 +600,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -619,7 +619,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -672,7 +672,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -690,7 +690,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -702,7 +702,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h index afa24bea94..8f8cfaa5ae 100644 --- a/components/hal/esp32c6/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c6/include/hal/clk_tree_ll.h @@ -83,7 +83,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { // No need to configure anything for OSC_SLOW_CLK @@ -102,7 +102,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); @@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } @@ -121,7 +121,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Enable rc32k xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -130,7 +130,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Disable rc32k xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -141,7 +141,7 @@ static inline void clk_ll_rc32k_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; } @@ -167,7 +167,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; } @@ -175,7 +175,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 1; } @@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 0; } @@ -193,7 +193,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_fosc; } @@ -201,7 +201,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1; } @@ -209,7 +209,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0; } @@ -219,7 +219,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } @@ -227,7 +227,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; } @@ -235,7 +235,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; } @@ -245,7 +245,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_osc32k; } @@ -566,7 +566,7 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide * * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) */ -static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC32K: @@ -589,7 +589,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s * * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) */ -static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) { uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; switch (clk_sel) { @@ -609,7 +609,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -635,7 +635,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; switch (clk_sel) { @@ -657,7 +657,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_RC_FAST: @@ -677,7 +677,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; switch (clk_sel) { @@ -695,7 +695,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { // No divider on the target, always return divider = 1 return 1; @@ -717,7 +717,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -734,7 +734,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -773,7 +773,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -785,7 +785,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32h2/include/hal/clk_tree_ll.h b/components/hal/esp32h2/include/hal/clk_tree_ll.h index 19d3d1983a..236cc9f6c3 100644 --- a/components/hal/esp32h2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h2/include/hal/clk_tree_ll.h @@ -80,7 +80,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Enable the internal oscillator output for LP_PLL_CLK */ -static inline void clk_ll_lp_pll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_enable(void) { // Enable lp_pll xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL); @@ -89,7 +89,7 @@ static inline void clk_ll_lp_pll_enable(void) /** * @brief Disable the internal oscillator output for LP_PLL_CLK */ -static inline void clk_ll_lp_pll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void) { // Disable lp_pll xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL); @@ -100,7 +100,7 @@ static inline void clk_ll_lp_pll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { // No need to configure anything for OSC_SLOW_CLK @@ -119,7 +119,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); @@ -130,7 +130,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } @@ -138,7 +138,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Enable rc32k xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -147,7 +147,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Disable rc32k xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -158,7 +158,7 @@ static inline void clk_ll_rc32k_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; } @@ -184,7 +184,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; } @@ -192,7 +192,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 1; } @@ -200,7 +200,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 0; } @@ -210,7 +210,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_fosc; } @@ -218,7 +218,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1; } @@ -226,7 +226,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0; } @@ -236,7 +236,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } @@ -244,7 +244,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; } @@ -252,7 +252,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; } @@ -262,7 +262,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_osc32k; } @@ -455,7 +455,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi * * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) */ -static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC32K: @@ -478,7 +478,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s * * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) */ -static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) { uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; switch (clk_sel) { @@ -498,7 +498,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; switch (clk_sel) { @@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_lp_pll_clk_src_t */ -static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) { uint32_t field_value; switch (in_sel) { @@ -568,7 +568,7 @@ static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_lp_pll_clk_src_t values) */ -static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) +static inline __attribute__((always_inline)) soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) { uint32_t clk_sel = REGI2C_READ_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF); switch (clk_sel) { @@ -586,7 +586,7 @@ static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) * * @return LP_PLL clock frequency, in MHz */ -static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz(void) { // The target has a fixed 8MHz LP_PLL return CLK_LL_PLL_8M_FREQ_MHZ; @@ -597,7 +597,7 @@ static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_RC_FAST: @@ -620,7 +620,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; switch (clk_sel) { @@ -640,7 +640,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -651,7 +651,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { // No divider on the target, always return divider = 1 return 1; @@ -662,7 +662,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -679,7 +679,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -718,7 +718,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -730,7 +730,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32h4/include/hal/clk_tree_ll.h b/components/hal/esp32h4/include/hal/clk_tree_ll.h index 24adea1c0a..6afa9205a9 100644 --- a/components/hal/esp32h4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h4/include/hal/clk_tree_ll.h @@ -77,7 +77,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k (or only for mode == CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL?) clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -96,7 +96,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -109,7 +109,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -124,7 +124,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Configure rc32k REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); @@ -135,7 +135,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32k_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Configure rc32k REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); @@ -146,7 +146,7 @@ static inline void clk_ll_rc32k_disable(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -154,7 +154,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -164,7 +164,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -172,7 +172,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); } @@ -180,7 +180,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); } @@ -190,7 +190,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN); } @@ -198,7 +198,7 @@ static inline bool clk_ll_rc32k_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -206,7 +206,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -216,7 +216,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -383,7 +383,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -406,7 +406,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -427,7 +427,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -447,7 +447,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -465,7 +465,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -478,7 +478,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -488,7 +488,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -507,7 +507,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -558,7 +558,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -570,7 +570,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32s2/include/hal/clk_tree_ll.h b/components/hal/esp32s2/include/hal/clk_tree_ll.h index ae4b9f0b96..f7d67937ee 100644 --- a/components/hal/esp32s2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s2/include/hal/clk_tree_ll.h @@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Power up APLL circuit */ -static inline void clk_ll_apll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -103,7 +103,7 @@ static inline void clk_ll_apll_enable(void) /** * @brief Power down APLL circuit */ -static inline void clk_ll_apll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -117,7 +117,7 @@ static inline void clk_ll_apll_disable(void) * @param[out] sdm1 Frequency adjustment parameter, 0..255 * @param[out] sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) { *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV); *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0); @@ -133,7 +133,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3 * @param sdm1 Frequency adjustment parameter, 0..255 * @param sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2); REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0); @@ -146,7 +146,7 @@ static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_ /** * @brief Set APLL calibration parameters */ -static inline void clk_ll_apll_set_calibration(void) +static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void) { REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1); REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2); @@ -158,7 +158,7 @@ static inline void clk_ll_apll_set_calibration(void) * * @return True if calibration is done; otherwise false */ -static inline bool clk_ll_apll_calibration_is_done(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void) { return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END); } @@ -168,7 +168,7 @@ static inline bool clk_ll_apll_calibration_is_done(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -187,7 +187,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -200,7 +200,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -235,7 +235,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -248,7 +248,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -259,7 +259,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -269,7 +269,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -277,7 +277,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -285,7 +285,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -295,7 +295,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -303,7 +303,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -311,7 +311,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -319,7 +319,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -327,7 +327,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -337,7 +337,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @return Divider. Returns 0 means invalid. */ -static inline uint32_t clk_ll_cpu_get_divider_from_apll(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void) { // APLL path divider choice depends on PLL_FREQ_SEL and CPUPERIOD_SEL uint32_t pll_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); @@ -611,7 +611,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -634,7 +634,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -655,7 +655,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D4: @@ -675,7 +675,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -693,7 +693,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -716,7 +716,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -747,7 +747,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -765,7 +765,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -777,7 +777,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h index c247c36b3f..c2534134a7 100644 --- a/components/hal/esp32s3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s3/include/hal/clk_tree_ll.h @@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -101,7 +101,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -114,7 +114,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -149,7 +149,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -162,7 +162,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -173,7 +173,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -191,7 +191,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -199,7 +199,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -209,7 +209,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -217,7 +217,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -225,7 +225,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -233,7 +233,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -241,7 +241,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -251,7 +251,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -501,7 +501,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -566,7 +566,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -584,7 +584,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -597,7 +597,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -607,7 +607,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -626,7 +626,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -665,7 +665,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -677,7 +677,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } From 1e65ea8889604a5f40a46fde5408246fc048ac37 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Sat, 18 Feb 2023 18:49:30 +0800 Subject: [PATCH 23/25] hal: always inline mmu_ll_check_valid_paddr_region for esp32h2 --- components/hal/esp32h2/include/hal/mmu_ll.h | 1 + 1 file changed, 1 insertion(+) diff --git a/components/hal/esp32h2/include/hal/mmu_ll.h b/components/hal/esp32h2/include/hal/mmu_ll.h index 22b97d3db5..c4c17d7bb7 100644 --- a/components/hal/esp32h2/include/hal/mmu_ll.h +++ b/components/hal/esp32h2/include/hal/mmu_ll.h @@ -119,6 +119,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t * @return * True for valid */ +__attribute__((always_inline)) static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len) { (void)mmu_id; From e4eca000f715350c24a2a418ea680f1a25a3cf11 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 10 Feb 2023 00:45:24 +0700 Subject: [PATCH 24/25] docs: add EN GCC-12.2.0 migration guide --- .../migration-guides/release-5.x/5.1/gcc.rst | 79 ++++++++++++++++++ .../release-5.x/5.1/index.rst | 1 + .../migration-guides/release-5.x/5.1/gcc.rst | 81 +++++++++++++++++++ .../release-5.x/5.1/index.rst | 1 + 4 files changed, 162 insertions(+) create mode 100644 docs/en/migration-guides/release-5.x/5.1/gcc.rst create mode 100644 docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst diff --git a/docs/en/migration-guides/release-5.x/5.1/gcc.rst b/docs/en/migration-guides/release-5.x/5.1/gcc.rst new file mode 100644 index 0000000000..fe4bd1d434 --- /dev/null +++ b/docs/en/migration-guides/release-5.x/5.1/gcc.rst @@ -0,0 +1,79 @@ +GCC +*** + +:link_to_translation:`zh_CN:[中文]` + + +GCC Version +=========== + +The previous GCC version was GCC 11.2.0. This has now been upgraded to GCC 12.2.0 on all targets. Users that need to port their code from GCC 11.2.0 to 12.2.0 should refer to the series of official GCC porting guides listed below: + +* `Porting to GCC 12 `_ + + +Warnings +======== + +The upgrade to GCC 12.2.0 has resulted in the addition of new warnings, or enhancements to existing warnings. The full details of all GCC warnings can be found in `GCC Warning Options `_. Users are advised to double-check their code, then fix the warnings if possible. Unfortunately, depending on the warning and the complexity of the user's code, some warnings will be false positives that require non-trivial fixes. In such cases, users can choose to suppress the warning in multiple ways. This section outlines some common warnings that users are likely to encounter and ways to fix them. + + +``-Wuse-after-free`` +-------------------- + +Typically, this warning should not produce false-positives for release-level code. But this may appear in test cases. There is an example of how it was fixed in IDF's test_realloc.c. + +.. code-block:: c + + void *x = malloc(64); + void *y = realloc(x, 48); + TEST_ASSERT_EQUAL_PTR(x, y); + +Pointers may be converted to int to avoid warning ``-Wuse-after-free``. + +.. code-block:: c + + int x = (int) malloc(64); + int y = (int) realloc((void *) x, 48); + TEST_ASSERT_EQUAL_UINT32((uint32_t) x, (uint32_t) y); + +``-Waddress`` +------------- + +GCC 12.2.0 introduces an enhanced version of the ``-Waddress`` warning option, which is now more eager in detecting the checking of pointers to an array in if-statements. + +The following code will trigger the warning: + +.. code-block:: c + + char array[8]; + ... + if (array) + memset(array, 0xff, sizeof(array)); + + +Eliminating unnecessary checks resolves the warning. + +.. code-block:: c + + char array[8]; + ... + memset(array, 0xff, sizeof(array)); + + +RISC-V Builds Outside of IDF +============================ + +The RISC-V extensions ``zicsr`` and ``zifencei`` have been separated from the ``I`` extension. GCC 12 reflects this change, and as a result, when building for RISC-V ESP32 chips outside of the IDF framework, you must include the ``_zicsr_zifencei`` postfix when specifying the -march option in your build system. + +Example: + +.. code-block:: bash + + riscv32-esp-elf-gcc main.c -march=rv32imac + +Now is replaced with: + +.. code-block:: bash + + riscv32-esp-elf-gcc main.c -march=rv32imac_zicsr_zifencei diff --git a/docs/en/migration-guides/release-5.x/5.1/index.rst b/docs/en/migration-guides/release-5.x/5.1/index.rst index 98840beaef..35a89aca69 100644 --- a/docs/en/migration-guides/release-5.x/5.1/index.rst +++ b/docs/en/migration-guides/release-5.x/5.1/index.rst @@ -6,6 +6,7 @@ Migration from 5.0 to 5.1 .. toctree:: :maxdepth: 1 + gcc peripherals storage networking diff --git a/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst b/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst new file mode 100644 index 0000000000..3993566a8d --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst @@ -0,0 +1,81 @@ +GCC +*** + +:link_to_translation:`en:[English]` + + +GCC 版本 +======== + +ESP-IDF 之前使用的 GCC 版本为 11.2.0，现已针对所有芯片目标升级至 GCC 12.2.0。若需要将您的代码从 GCC 11.2.0 迁移到 GCC 12.2.0，请参考以下官方 GCC 迁移指南。 + +* `迁移至 GCC 9 `_ +* `迁移至 GCC 10 `_ +* `迁移至 GCC 11 `_ + + +警告 +==== + +升级至 GCC 12.2.0 后会触发新警告，或是导致原有警告内容发生变化。所有 GCC 警告的详细内容，请参考 `GCC 警告选项 `_。建议用户仔细检查代码，并设法解决这些警告。但由于某些警告的特殊性及用户代码的复杂性，有些警告可能为误报，需要进行关键修复。在这种情况下，用户可以采取多种方式来抑制这些警告。本节介绍了用户可能遇到的常见警告及如何抑制这些警告。 + + +``-Wuse-after-free`` +-------------------- + +Typically, this warning should not produce false-positives for release-level code. But may appear in test cases. There is an example of how it was fixed in IDF's test_realloc.c + +.. code-block:: c + + void *x = malloc(64); + void *y = realloc(x, 48); + TEST_ASSERT_EQUAL_PTR(x, y); + +Pointers may be converted to int to avoid warning ``-Wuse-after-free`` + +.. code-block:: c + + int x = (int) malloc(64); + int y = (int) realloc((void *) x, 48); + TEST_ASSERT_EQUAL_UINT32((uint32_t) x, (uint32_t) y); + +``-Waddress`` +------------- + +GCC 12.2.0 introduces an enhanced version of the ``-Waddress`` warning option, which is now more eager in detecting the checking of pointers to array in if-statements. + +The following code will trigger the warning: + +.. code-block:: c + + char array[8]; + ... + if (array) + memset(array, 0xff, sizeof(array)); + + +Eliminating unnecessary check resolves the warning. + +.. code-block:: c + + char array[8]; + ... + memset(array, 0xff, sizeof(array)); + + +RISCV Builds Outside of IDF +=========================== + +The RISCV extensions ``zicsr`` and ``zifencei`` have been separated from the ``I`` extension. GCC 12 reflects this change, and as a result, when building for RISCV ESP32 chips outside of the IDF framework, you must include the ``_zicsr_zifencei`` postfix when specifying the -march option in your build system. + +Example: + +.. code-block:: bash + + riscv32-esp-elf-gcc main.c -march=rv32imac + +Is now replaced with: + +.. code-block:: bash + + riscv32-esp-elf-gcc main.c -march=rv32imac_zicsr_zifencei diff --git a/docs/zh_CN/migration-guides/release-5.x/5.1/index.rst b/docs/zh_CN/migration-guides/release-5.x/5.1/index.rst index ea870e49a8..03c107bdac 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.1/index.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.1/index.rst @@ -6,6 +6,7 @@ .. toctree:: :maxdepth: 1 + gcc peripherals storage networking From 262699683d2ba9c4c550e6b88ee81cf9da2c80d6 Mon Sep 17 00:00:00 2001 From: Wang Zi Yan Date: Wed, 15 Feb 2023 10:56:52 +0800 Subject: [PATCH 25/25] docs: add CN GCC-12.2.0 migration guide --- .../migration-guides/release-5.x/5.1/gcc.rst | 30 +++++++++---------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst b/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst index 3993566a8d..60a4e7666d 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.1/gcc.rst @@ -1,4 +1,4 @@ -GCC +GCC *** :link_to_translation:`en:[English]` @@ -7,23 +7,21 @@ GCC GCC 版本 ======== -ESP-IDF 之前使用的 GCC 版本为 11.2.0，现已针对所有芯片目标升级至 GCC 12.2.0。若需要将您的代码从 GCC 11.2.0 迁移到 GCC 12.2.0，请参考以下官方 GCC 迁移指南。 +ESP-IDF 之前使用的 GCC 版本为 11.2.0，现已针对所有芯片目标升级至 GCC 12.2.0。若您需要将代码从 GCC 11.2.0 迁移到 GCC 12.2.0，请参考以下 GCC 官方迁移指南。 -* `迁移至 GCC 9 `_ -* `迁移至 GCC 10 `_ -* `迁移至 GCC 11 `_ +* `迁移至 GCC 12 `_ 警告 ==== -升级至 GCC 12.2.0 后会触发新警告，或是导致原有警告内容发生变化。所有 GCC 警告的详细内容，请参考 `GCC 警告选项 `_。建议用户仔细检查代码，并设法解决这些警告。但由于某些警告的特殊性及用户代码的复杂性，有些警告可能为误报，需要进行关键修复。在这种情况下，用户可以采取多种方式来抑制这些警告。本节介绍了用户可能遇到的常见警告及如何抑制这些警告。 +升级至 GCC 12.2.0 后会触发新警告，或是导致原有警告内容发生变化。了解所有 GCC 警告的详细内容，请参考 `GCC 警告选项 `_。建议用户仔细检查代码，并尽量解决这些警告。但由于某些警告的特殊性及用户代码的复杂性，有些警告可能为误报，需要进行关键修复。在这种情况下，用户可以采取多种方式来抑制警告。本节介绍了用户可能遇到的常见警告及如何修复这些警告。 ``-Wuse-after-free`` -------------------- -Typically, this warning should not produce false-positives for release-level code. But may appear in test cases. There is an example of how it was fixed in IDF's test_realloc.c +一般而言，此警告不会针对发布版本的代码产生误报，但是这种情况可能出现在测试用例中。以下示例为如何在 IDF 的 test_realloc.c 中修复该警告。 .. code-block:: c @@ -31,7 +29,7 @@ Typically, this warning should not produce false-positives for release-level cod void *y = realloc(x, 48); TEST_ASSERT_EQUAL_PTR(x, y); -Pointers may be converted to int to avoid warning ``-Wuse-after-free`` +将指针转换为 int 可以避免出现 ``-Wuse-after-free`` 警告。 .. code-block:: c @@ -42,9 +40,9 @@ Pointers may be converted to int to avoid warning ``-Wuse-after-free`` ``-Waddress`` ------------- -GCC 12.2.0 introduces an enhanced version of the ``-Waddress`` warning option, which is now more eager in detecting the checking of pointers to array in if-statements. +GCC 12.2.0 引入了增强版 ``-Waddress`` 警告选项，该选项对 if 语句中的数组指针检查更加敏感。 -The following code will trigger the warning: +以下代码将触发警告： .. code-block:: c @@ -54,7 +52,7 @@ The following code will trigger the warning: memset(array, 0xff, sizeof(array)); -Eliminating unnecessary check resolves the warning. +删去不必要的检查可以消除警告。 .. code-block:: c @@ -63,18 +61,18 @@ Eliminating unnecessary check resolves the warning. memset(array, 0xff, sizeof(array)); -RISCV Builds Outside of IDF -=========================== +在 IDF 框架之外构建 RISC-V +============================ -The RISCV extensions ``zicsr`` and ``zifencei`` have been separated from the ``I`` extension. GCC 12 reflects this change, and as a result, when building for RISCV ESP32 chips outside of the IDF framework, you must include the ``_zicsr_zifencei`` postfix when specifying the -march option in your build system. +RISC-V 的 ``zicsr`` 和 ``zifencei`` 扩展现已独立于 ``I`` 扩展，这一变化在 GCC 12 中也有所体现。因此，在 IDF 框架之外构建 RISC-V ESP32 芯片时，请在构建系统中指定 -march 选项时添加 ``_zicsr_zifencei`` 后缀。示例如下。 -Example: +原为： .. code-block:: bash riscv32-esp-elf-gcc main.c -march=rv32imac -Is now replaced with: +现为： .. code-block:: bash