From 149872131aea205b60c537bfbadc3c22c589c5f4 Mon Sep 17 00:00:00 2001 From: Darian Leung Date: Tue, 7 Jun 2022 14:47:05 +0800 Subject: [PATCH] hal: Move dedicated GPIO LL and HAL This commit moves the dedicated GPIO LL and HAL functions from cpu_ll.h to dedic_gpio_cpu_ll.h. - cpu_ll_enable_cycle_count() has also been removed due to lack of feasible usage scenarios --- components/driver/gpio/dedic_gpio.c | 10 ++-- components/driver/include/driver/dedic_gpio.h | 2 +- .../test_apps/gpio/main/test_dedicated_gpio.c | 18 +++---- components/hal/esp32c2/include/hal/cpu_ll.h | 33 ------------ .../esp32c2/include/hal/dedic_gpio_cpu_ll.h | 51 +++++++++++++++++++ components/hal/esp32c3/include/hal/cpu_ll.h | 33 ------------ .../esp32c3/include/hal/dedic_gpio_cpu_ll.h | 51 +++++++++++++++++++ components/hal/esp32h2/include/hal/cpu_ll.h | 33 ------------ .../esp32h2/include/hal/dedic_gpio_cpu_ll.h | 51 +++++++++++++++++++ components/hal/esp32s2/include/hal/cpu_ll.h | 24 --------- .../esp32s2/include/hal/dedic_gpio_cpu_ll.h | 41 +++++++++++++++ components/hal/esp32s3/include/hal/cpu_ll.h | 24 --------- .../esp32s3/include/hal/dedic_gpio_cpu_ll.h | 50 ++++++++++++++++++ .../api-reference/peripherals/dedic_gpio.rst | 4 +- docs/en/migration-guides/peripherals.rst | 7 +++ .../api-reference/peripherals/dedic_gpio.rst | 2 +- 16 files changed, 269 insertions(+), 165 deletions(-) create mode 100644 components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h diff --git a/components/driver/gpio/dedic_gpio.c b/components/driver/gpio/dedic_gpio.c index 0b6ba6e434..2c2848085f 100644 --- a/components/driver/gpio/dedic_gpio.c +++ b/components/driver/gpio/dedic_gpio.c @@ -19,7 +19,7 @@ #include "soc/gpio_periph.h" #include "soc/io_mux_reg.h" #include "hal/cpu_hal.h" -#include "hal/cpu_ll.h" +#include "hal/dedic_gpio_cpu_ll.h" #include "hal/gpio_hal.h" #include "esp_private/periph_ctrl.h" #include "esp_rom_gpio.h" @@ -271,7 +271,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false); } #if !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE - cpu_ll_enable_dedic_gpio_output(s_platform[core_id]->out_occupied_mask); + dedic_gpio_cpu_ll_enable_output(s_platform[core_id]->out_occupied_mask); #endif // !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE } @@ -353,14 +353,14 @@ void dedic_gpio_bundle_write(dedic_gpio_bundle_handle_t bundle, uint32_t mask, u { // For performance reasons, we don't want to check the validation of parameters here // Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id) - cpu_ll_write_dedic_gpio_mask(bundle->out_mask & (mask << bundle->out_offset), value << bundle->out_offset); + dedic_gpio_cpu_ll_write_mask(bundle->out_mask & (mask << bundle->out_offset), value << bundle->out_offset); } uint32_t dedic_gpio_bundle_read_out(dedic_gpio_bundle_handle_t bundle) { // For performance reasons, we don't want to check the validation of parameters here // Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id) - uint32_t value = cpu_ll_read_dedic_gpio_out(); + uint32_t value = dedic_gpio_cpu_ll_read_out(); return (value & bundle->out_mask) >> (bundle->out_offset); } @@ -368,7 +368,7 @@ uint32_t dedic_gpio_bundle_read_in(dedic_gpio_bundle_handle_t bundle) { // For performance reasons, we don't want to check the validation of parameters here // Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id) - uint32_t value = cpu_ll_read_dedic_gpio_in(); + uint32_t value = dedic_gpio_cpu_ll_read_in(); return (value & bundle->in_mask) >> (bundle->in_offset); } diff --git a/components/driver/include/driver/dedic_gpio.h b/components/driver/include/driver/dedic_gpio.h index 4a54f65191..1d32f19dab 100644 --- a/components/driver/include/driver/dedic_gpio.h +++ b/components/driver/include/driver/dedic_gpio.h @@ -74,7 +74,7 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle); * - ESP_FAIL: Get channel mask failed because of other error * * @note Each bundle should have at least one mask (in or/and out), based on bundle configuration. - * @note With the returned mask, user can directly invoke LL function like "cpu_ll_write_dedic_gpio_mask" + * @note With the returned mask, user can directly invoke LL function like "dedic_gpio_cpu_ll_write_mask" * or write assembly code with dedicated GPIO instructions, to get better performance on GPIO manipulation. */ esp_err_t dedic_gpio_get_out_mask(dedic_gpio_bundle_handle_t bundle, uint32_t *mask); diff --git a/components/driver/test_apps/gpio/main/test_dedicated_gpio.c b/components/driver/test_apps/gpio/main/test_dedicated_gpio.c index 6a81648912..a83ae94f99 100644 --- a/components/driver/test_apps/gpio/main/test_dedicated_gpio.c +++ b/components/driver/test_apps/gpio/main/test_dedicated_gpio.c @@ -11,7 +11,7 @@ #include "unity_test_utils.h" #include "esp_rom_sys.h" #include "soc/soc_caps.h" -#include "hal/cpu_ll.h" +#include "hal/dedic_gpio_cpu_ll.h" #include "driver/gpio.h" #include "driver/dedic_gpio.h" @@ -67,7 +67,7 @@ static void test_dedic_gpio_on_specific_core(void *args) { test_dedic_task_context_t *ctx = (test_dedic_task_context_t *)args; uint32_t value = 0; - cpu_ll_write_dedic_gpio_all(0x0); // clear all out channels + dedic_gpio_cpu_ll_write_all(0x0); // clear all out channels // configure a group of GPIOs, output only const int bundleA_gpios[] = {ctx->gpios[0], ctx->gpios[1]}; @@ -112,21 +112,21 @@ static void test_dedic_gpio_on_specific_core(void *args) dedic_gpio_bundle_write(bundleA, 0x01, 0x01); dedic_gpio_bundle_write(bundleB, 0x03, 0x03); - value = cpu_ll_read_dedic_gpio_out(); + value = dedic_gpio_cpu_ll_read_out(); TEST_ASSERT_EQUAL(0x0D, value); // 1101 - value = cpu_ll_read_dedic_gpio_in(); + value = dedic_gpio_cpu_ll_read_in(); TEST_ASSERT_EQUAL(0x03, value); // 11 dedic_gpio_bundle_write(bundleB, 0x02, 0x0); - value = cpu_ll_read_dedic_gpio_out(); + value = dedic_gpio_cpu_ll_read_out(); TEST_ASSERT_EQUAL(0x05, value); // 0101 - value = cpu_ll_read_dedic_gpio_in(); + value = dedic_gpio_cpu_ll_read_in(); TEST_ASSERT_EQUAL(0x01, value); // 01 - cpu_ll_write_dedic_gpio_all(0x0F); // Set all out channels - value = cpu_ll_read_dedic_gpio_out(); + dedic_gpio_cpu_ll_write_all(0x0F); // Set all out channels + value = dedic_gpio_cpu_ll_read_out(); TEST_ASSERT_EQUAL(0x0F, value); - value = cpu_ll_read_dedic_gpio_in(); + value = dedic_gpio_cpu_ll_read_in(); TEST_ASSERT_EQUAL(0x03, value); // 11 TEST_ASSERT_EQUAL(0x03, dedic_gpio_bundle_read_out(bundleA)); // 11 TEST_ASSERT_EQUAL(0x00, dedic_gpio_bundle_read_in(bundleA)); // input is not enabled for bundleA diff --git a/components/hal/esp32c2/include/hal/cpu_ll.h b/components/hal/esp32c2/include/hal/cpu_ll.h index 7ccffb1550..853a498726 100644 --- a/components/hal/esp32c2/include/hal/cpu_ll.h +++ b/components/hal/esp32c2/include/hal/cpu_ll.h @@ -21,11 +21,6 @@ #define CSR_PCMR_MACHINE 0x7e1 #define CSR_PCCR_MACHINE 0x7e2 -/*fast gpio*/ -#define CSR_GPIO_OEN_USER 0x803 -#define CSR_GPIO_IN_USER 0x804 -#define CSR_GPIO_OUT_USER 0x805 - #ifdef __cplusplus extern "C" { #endif @@ -204,34 +199,6 @@ static inline void cpu_ll_waiti(void) asm volatile ("wfi\n"); } -static inline void cpu_ll_enable_dedic_gpio_output(uint32_t mask) -{ - RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); -} - -static inline void cpu_ll_write_dedic_gpio_all(uint32_t value) -{ - RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); -} - -static inline uint32_t cpu_ll_read_dedic_gpio_in(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); - return value; -} - -static inline uint32_t cpu_ll_read_dedic_gpio_out(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); - return value; -} - -static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) -{ - RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); - RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); -} - static inline void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set) { uint32_t old_value; diff --git a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..6bf8e536e9 --- /dev/null +++ b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c3/include/hal/cpu_ll.h b/components/hal/esp32c3/include/hal/cpu_ll.h index 7ccffb1550..853a498726 100644 --- a/components/hal/esp32c3/include/hal/cpu_ll.h +++ b/components/hal/esp32c3/include/hal/cpu_ll.h @@ -21,11 +21,6 @@ #define CSR_PCMR_MACHINE 0x7e1 #define CSR_PCCR_MACHINE 0x7e2 -/*fast gpio*/ -#define CSR_GPIO_OEN_USER 0x803 -#define CSR_GPIO_IN_USER 0x804 -#define CSR_GPIO_OUT_USER 0x805 - #ifdef __cplusplus extern "C" { #endif @@ -204,34 +199,6 @@ static inline void cpu_ll_waiti(void) asm volatile ("wfi\n"); } -static inline void cpu_ll_enable_dedic_gpio_output(uint32_t mask) -{ - RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); -} - -static inline void cpu_ll_write_dedic_gpio_all(uint32_t value) -{ - RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); -} - -static inline uint32_t cpu_ll_read_dedic_gpio_in(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); - return value; -} - -static inline uint32_t cpu_ll_read_dedic_gpio_out(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); - return value; -} - -static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) -{ - RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); - RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); -} - static inline void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set) { uint32_t old_value; diff --git a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..6bf8e536e9 --- /dev/null +++ b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/cpu_ll.h b/components/hal/esp32h2/include/hal/cpu_ll.h index 023e57185a..c93fbe8ef4 100644 --- a/components/hal/esp32h2/include/hal/cpu_ll.h +++ b/components/hal/esp32h2/include/hal/cpu_ll.h @@ -19,11 +19,6 @@ #define CSR_PCMR_MACHINE 0x7e1 #define CSR_PCCR_MACHINE 0x7e2 -/*fast gpio*/ -#define CSR_GPIO_OEN_USER 0x803 -#define CSR_GPIO_IN_USER 0x804 -#define CSR_GPIO_OUT_USER 0x805 - #ifdef __cplusplus extern "C" { #endif @@ -197,34 +192,6 @@ static inline void cpu_ll_waiti(void) asm volatile ("wfi\n"); } -static inline void cpu_ll_enable_dedic_gpio_output(uint32_t mask) -{ - RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); -} - -static inline void cpu_ll_write_dedic_gpio_all(uint32_t value) -{ - RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); -} - -static inline uint32_t cpu_ll_read_dedic_gpio_in(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); - return value; -} - -static inline uint32_t cpu_ll_read_dedic_gpio_out(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); - return value; -} - -static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) -{ - RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); - RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); -} - static inline void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set) { uint32_t old_value; diff --git a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..6bf8e536e9 --- /dev/null +++ b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/include/hal/cpu_ll.h b/components/hal/esp32s2/include/hal/cpu_ll.h index bfb9ce5e3b..f3b0ea874f 100644 --- a/components/hal/esp32s2/include/hal/cpu_ll.h +++ b/components/hal/esp32s2/include/hal/cpu_ll.h @@ -166,30 +166,6 @@ static inline void cpu_ll_set_vecbase(const void* vecbase) asm volatile ("wsr %0, vecbase" :: "r" (vecbase)); } -static inline uint32_t cpu_ll_read_dedic_gpio_in(void) -{ - uint32_t value = 0; - asm volatile("get_gpio_in %0" : "=r"(value) : :); - return value; -} - -static inline uint32_t cpu_ll_read_dedic_gpio_out(void) -{ - uint32_t value = 0; - asm volatile("rur.gpio_out %0" : "=r"(value) : :); - return value; -} - -static inline void cpu_ll_write_dedic_gpio_all(uint32_t value) -{ - asm volatile("wur.gpio_out %0"::"r"(value):); -} - -static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) -{ - asm volatile("wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):); -} - static inline void cpu_ll_waiti(void) { asm volatile ("waiti 0\n"); diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..eb29b57097 --- /dev/null +++ b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = 0; + asm volatile("get_gpio_in %0" : "=r"(value) : :); + return value; +} + +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = 0; + asm volatile("rur.gpio_out %0" : "=r"(value) : :); + return value; +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + asm volatile("wur.gpio_out %0"::"r"(value):); +} + +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + asm volatile("wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s3/include/hal/cpu_ll.h b/components/hal/esp32s3/include/hal/cpu_ll.h index 92b1daf4b2..c9b9e6c792 100644 --- a/components/hal/esp32s3/include/hal/cpu_ll.h +++ b/components/hal/esp32s3/include/hal/cpu_ll.h @@ -174,30 +174,6 @@ static inline void cpu_ll_waiti(void) asm volatile ("waiti 0\n"); } -static inline uint32_t cpu_ll_read_dedic_gpio_in(void) -{ - uint32_t value = 0; - asm volatile("ee.get_gpio_in %0" : "=r"(value) : :); - return value; -} - -static inline uint32_t cpu_ll_read_dedic_gpio_out(void) -{ - uint32_t value = 0; - asm volatile("rur.gpio_out %0" : "=r"(value) : :); - return value; -} - -static inline void cpu_ll_write_dedic_gpio_all(uint32_t value) -{ - asm volatile("wur.gpio_out %0"::"r"(value):); -} - -static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) -{ - asm volatile("ee.wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):); -} - static inline void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set) { __asm__ __volatile__ ( diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..945d05dc19 --- /dev/null +++ b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#include "soc/soc_caps.h" + +#include "xt_instr_macros.h" +#include "xtensa/config/specreg.h" +#include "xtensa/config/extreg.h" +#include "esp_bit_defs.h" +#include "esp_attr.h" +#include "xtensa/config/core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = 0; + asm volatile("ee.get_gpio_in %0" : "=r"(value) : :); + return value; +} + +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = 0; + asm volatile("rur.gpio_out %0" : "=r"(value) : :); + return value; +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + asm volatile("wur.gpio_out %0"::"r"(value):); +} + +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + asm volatile("ee.wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):); +} + +#ifdef __cplusplus +} +#endif diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst index 121cc30f7b..feeda38b17 100644 --- a/docs/en/api-reference/peripherals/dedic_gpio.rst +++ b/docs/en/api-reference/peripherals/dedic_gpio.rst @@ -86,7 +86,7 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod 1. Allocate a GPIO bundle: :cpp:func:`dedic_gpio_new_bundle` 2. Query the mask occupied by that bundle: :cpp:func:`dedic_gpio_get_out_mask` or/and :cpp:func:`dedic_gpio_get_in_mask` -3. Call CPU LL apis (e.g. `cpu_ll_write_dedic_gpio_mask`) or write assembly code with that mask +3. Call CPU LL apis (e.g. `dedic_gpio_cpu_ll_write_mask`) or write assembly code with that mask 4. The fasted way of toggling IO is to use the dedicated "set/clear" instructions: .. only:: esp32s2 or esp32s3 @@ -113,7 +113,7 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod For details of supported dedicated GPIO instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__]. -Some of the dedicated CPU instructions are also wrapped inside `hal/dedic_gpio_ll.h` as helper inline functions. +Some of the dedicated CPU instructions are also wrapped inside ``hal/dedic_gpio_cpu_ll.h`` as helper inline functions. .. note:: Writing assembly code in application could make your code hard to port between targets, because those customized instructions are not guaranteed to remain the same format on different targets. diff --git a/docs/en/migration-guides/peripherals.rst b/docs/en/migration-guides/peripherals.rst index 4b3c9a88ea..e951ef55cb 100644 --- a/docs/en/migration-guides/peripherals.rst +++ b/docs/en/migration-guides/peripherals.rst @@ -248,3 +248,10 @@ LCD - ``mcpwm_sync_enable`` is removed. To configure synchronization, please use :cpp:func:`mcpwm_sync_configure`. - ``mcpwm_isr_register`` is removed. You can register event callbacks, for capture channels. e.g. :cpp:member:`mcpwm_capture_config_t::capture_cb`. - ``mcpwm_carrier_oneshot_mode_disable`` is removed. Disable the first pulse (a.k.a the one-shot pulse) in the carrier is not supported by hardware. + +.. only:: SOC_DEDICATED_GPIO_SUPPORTED + + Dedicated GPIO Driver + --------------------- + + - All of the dedicated GPIO related LL functionsn in ``cpu_ll.h`` have been moved to ``dedic_gpio_cpu_ll.h`` and renamed. \ No newline at end of file diff --git a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst index 2fe1153931..de9d985674 100644 --- a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst @@ -113,7 +113,7 @@ GPIO 捆绑包操作 有关支持的专用 GPIO 指令的详细信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_CN_URL}#riscvcpu>`__]. -一些专用的 CPU 指令也包含在 `hal/dedic_gpio_ll.h` 中，作为辅助内联函数。 +一些专用的 CPU 指令也包含在 `hal/dedic_gpio_cpu_ll.h` 中，作为辅助内联函数。 .. note:: 由于自定义指令在不同目标上可能会有不同的格式，在应用程序中编写汇编代码可能会让代码难以在不同的芯片架构之间移植。