diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 99a3fb9221..708f4c0404 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -23,7 +23,7 @@ repos: exclude: *whitespace_excludes - id: check-executables-have-shebangs - id: file-contents-sorter - files: 'tools/ci/executable-list.txt' + files: '(tools\/ci\/executable-list\.txt|tools\/ci\/mypy_ignore_list\.txt)' - id: mixed-line-ending args: ['-f=lf'] - id: double-quote-string-fixer diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 5d453aed5b..fdacf11697 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -21,6 +21,7 @@ #include "soc/gpio_sig_map.h" #include "soc/rtc.h" #include "hal/clk_gate_ll.h" +#include "hal/gpio_hal.h" #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/usb/cdc_acm.h" #include "esp32s2/rom/usb/usb_common.h" @@ -69,8 +70,8 @@ void bootloader_console_init(void) uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM || uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) { // Change default UART pins back to GPIOs - PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, PIN_FUNC_GPIO); // Route GPIO signals to/from pins const uint32_t tx_idx = uart_periph_signal[uart_num].tx_sig; const uint32_t rx_idx = uart_periph_signal[uart_num].rx_sig; diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c index 538ed38b63..8bb97957a3 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c @@ -25,6 +25,7 @@ #include "soc/spi_reg.h" #include "soc/soc_caps.h" #include "soc/soc_pins.h" +#include "hal/gpio_hal.h" #include "flash_qio_mode.h" #include "bootloader_common.h" #include "bootloader_flash_config.h" @@ -87,7 +88,7 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); } else { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); @@ -102,14 +103,14 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0); esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0); //select pin function gpio - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); // flash clock signal should come from IO MUX. // set drive ability for clock - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); uint32_t flash_id = g_rom_flashchip.device_id; diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index 4bc9e37bf7..b385b17b5c 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -34,6 +34,7 @@ #include "soc/io_mux_reg.h" #include "soc/rtc.h" #include "soc/spi_periph.h" +#include "hal/gpio_hal.h" #include "esp32/rom/cache.h" #include "esp_rom_gpio.h" @@ -61,7 +62,7 @@ void bootloader_configure_spi_pins(int drv) pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); } else { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); @@ -76,14 +77,14 @@ void bootloader_configure_spi_pins(int drv) esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0); //select pin function gpio - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); // flash clock signal should come from IO MUX. // set drive ability for clock - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); #if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64 diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 70c22b840d..a39965b633 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -55,7 +55,6 @@ endif() if(${target} STREQUAL "esp32s3") list(APPEND srcs "adc_common.c" - "dac_common.c" "dedic_gpio.c" "gdma.c" "spi_slave_hd.c" diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c index c3ca788305..63cecee53e 100644 --- a/components/driver/adc_common.c +++ b/components/driver/adc_common.c @@ -30,7 +30,7 @@ #include "hal/adc_types.h" #include "hal/adc_hal.h" -#if SOC_DAC_PERIPH_NUM > 0 +#if SOC_DAC_SUPPORTED #include "driver/dac.h" #include "hal/dac_hal.h" #endif @@ -248,7 +248,9 @@ static void adc_rtc_chan_init(adc_unit_t adc_unit) if (adc_unit & ADC_UNIT_1) { /* Workaround: Disable the synchronization operation function of ADC1 and DAC. If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */ +#if SOC_DAC_SUPPORTED dac_hal_rtc_sync_by_adc(false); +#endif adc_hal_rtc_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT); adc_hal_set_sar_clk_div(ADC_NUM_1, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_1)); #ifdef CONFIG_IDF_TARGET_ESP32 @@ -532,6 +534,7 @@ static inline void adc2_init(void) static inline void adc2_dac_disable( adc2_channel_t channel) { +#if SOC_DAC_SUPPORTED #ifdef CONFIG_IDF_TARGET_ESP32 if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 1 dac_output_disable(DAC_CHANNEL_1); @@ -545,6 +548,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel) dac_output_disable(DAC_CHANNEL_2); } #endif +#endif // SOC_DAC_SUPPORTED } /** diff --git a/components/driver/dedic_gpio.c b/components/driver/dedic_gpio.c index 118c9aa5d0..c9254f2aa9 100644 --- a/components/driver/dedic_gpio.c +++ b/components/driver/dedic_gpio.c @@ -25,6 +25,7 @@ #include "soc/io_mux_reg.h" #include "hal/cpu_hal.h" #include "hal/cpu_ll.h" +#include "hal/gpio_hal.h" #include "driver/periph_ctrl.h" #include "esp_rom_gpio.h" #include "freertos/FreeRTOS.h" @@ -267,13 +268,13 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // route dedicated GPIO channel signals to GPIO matrix if (config->flags.in_en) { for (size_t i = 0; i < config->array_size; i++) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO); esp_rom_gpio_connect_in_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[in_offset + i], config->flags.in_invert); } } if (config->flags.out_en) { for (size_t i = 0; i < config->array_size; i++) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false); } } diff --git a/components/driver/esp32s3/include/driver/dac.h b/components/driver/esp32s3/include/driver/dac.h deleted file mode 100644 index 6efcc5c2b0..0000000000 --- a/components/driver/esp32s3/include/driver/dac.h +++ /dev/null @@ -1,80 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include "driver/dac_common.h" - -#ifdef __cplusplus -extern "C" { -#endif -/*--------------------------------------------------------------- - Digital controller setting ----------------------------------------------------------------*/ - -/** - * @brief DAC digital controller initialization. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_init(void); - -/** - * @brief DAC digital controller deinitialization. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_deinit(void); - -/** - * @brief Setting the DAC digital controller. - * - * @param cfg Pointer to digital controller paramter. See ``dac_digi_config_t``. - * - * @return - * - ESP_OK success - * - ESP_ERR_INVALID_ARG Parameter error - */ -esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg); - -/** - * @brief DAC digital controller start output voltage. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_start(void); - -/** - * @brief DAC digital controller stop output voltage. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_stop(void); - -/** - * @brief Reset DAC digital controller FIFO. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_fifo_reset(void); - -/** - * @brief Reset DAC digital controller. - * @return - * - ESP_OK success - */ -esp_err_t dac_digi_reset(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/driver/gpio.c b/components/driver/gpio.c index d29803621f..ec9294d6a3 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -392,7 +392,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) } /* By default, all the pins have to be configured as GPIO pins. */ - PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO); } io_num++; diff --git a/components/driver/i2c.c b/components/driver/i2c.c index eb24c0a83f..522555c866 100644 --- a/components/driver/i2c.c +++ b/components/driver/i2c.c @@ -26,6 +26,7 @@ #include "esp_pm.h" #include "soc/soc_memory_layout.h" #include "hal/i2c_hal.h" +#include "hal/gpio_hal.h" #include "soc/i2c_periph.h" #include "driver/i2c.h" #include "driver/periph_ctrl.h" @@ -832,7 +833,7 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s scl_in_sig = i2c_periph_signal[i2c_num].scl_in_sig; if (sda_io_num >= 0) { gpio_set_level(sda_io_num, I2C_IO_INIT_LEVEL); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[sda_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[sda_io_num], PIN_FUNC_GPIO); gpio_set_direction(sda_io_num, GPIO_MODE_INPUT_OUTPUT_OD); if (sda_pullup_en == GPIO_PULLUP_ENABLE) { @@ -845,7 +846,7 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s } if (scl_io_num >= 0) { gpio_set_level(scl_io_num, I2C_IO_INIT_LEVEL); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO); gpio_set_direction(scl_io_num, GPIO_MODE_INPUT_OUTPUT_OD); esp_rom_gpio_connect_out_signal(scl_io_num, scl_out_sig, 0, 0); esp_rom_gpio_connect_in_signal(scl_io_num, scl_in_sig, 0); diff --git a/components/driver/i2s.c b/components/driver/i2s.c index e705467491..9dd867b674 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -24,6 +24,7 @@ #include "soc/lldesc.h" #include "driver/gpio.h" #include "driver/i2s.h" +#include "hal/gpio_hal.h" #if SOC_I2S_SUPPORTS_ADC_DAC #include "driver/dac.h" #include "hal/i2s_hal.h" @@ -118,7 +119,7 @@ static inline void gpio_matrix_out_check(int gpio, uint32_t signal_idx, bool out { //if pin = -1, do not need to configure if (gpio != -1) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO); gpio_set_direction(gpio, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv); } @@ -127,7 +128,7 @@ static inline void gpio_matrix_out_check(int gpio, uint32_t signal_idx, bool out static inline void gpio_matrix_in_check(int gpio, uint32_t signal_idx, bool inv) { if (gpio != -1) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO); //Set direction, for some GPIOs, the input function are not enabled as default. gpio_set_direction(gpio, GPIO_MODE_INPUT); esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv); diff --git a/components/driver/include/driver/dedic_gpio.h b/components/driver/include/driver/dedic_gpio.h index f7d9b4a6cc..f381e2c64b 100644 --- a/components/driver/include/driver/dedic_gpio.h +++ b/components/driver/include/driver/dedic_gpio.h @@ -20,6 +20,8 @@ #include "esp_attr.h" #include "soc/soc_caps.h" +#if SOC_DEDICATED_GPIO_SUPPORTED + #ifdef __cplusplus extern "C" { #endif @@ -171,3 +173,5 @@ esp_err_t dedic_gpio_bundle_set_interrupt_and_callback(dedic_gpio_bundle_handle_ #ifdef __cplusplus } #endif + +#endif //SOC_DEDICATED_GPIO_SUPPORTED diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index c166ffa279..aac81566fc 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -3,7 +3,7 @@ // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -494,28 +494,6 @@ esp_err_t gpio_sleep_set_direction(gpio_num_t gpio_num, gpio_mode_t mode); * - ESP_ERR_INVALID_ARG : Parameter error */ esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull); - -#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL -/** - * @brief Emulate ESP32S2 behaviour to backup FUN_PU, FUN_PD information - * - * @note Need to be called before sleep. - * - * @return - * - ESP_OK Success - */ -esp_err_t gpio_sleep_pupd_config_apply(gpio_num_t gpio_num); - -/** - * @brief Emulate ESP32S2 behaviour to restore FUN_PU, FUN_PD information - * - * @note Need to be called after sleep. - * - * @return - * - ESP_OK Success - */ -esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num); -#endif #endif #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP diff --git a/components/driver/include/driver/i2c.h b/components/driver/include/driver/i2c.h index 30488fc570..a2076cc459 100644 --- a/components/driver/include/driver/i2c.h +++ b/components/driver/include/driver/i2c.h @@ -33,9 +33,39 @@ extern "C" { #define I2C_APB_CLK_FREQ APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */ -#define I2C_NUM_0 (0) /*!< I2C port 0 */ -#define I2C_NUM_1 (1) /*!< I2C port 1 */ #define I2C_NUM_MAX (SOC_I2C_NUM) /*!< I2C port max */ +#define I2C_NUM_0 (0) /*!< I2C port 0 */ +#if SOC_I2C_NUM >= 2 +#define I2C_NUM_1 (1) /*!< I2C port 1 */ +#endif + +// I2C clk flags for users to use, can be expanded in the future. +#define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/ +#define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/ +#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP (1 << 1) /*!< For light sleep mode.*/ + +/** + * @brief I2C initialization parameters + */ +typedef struct{ + i2c_mode_t mode; /*!< I2C mode */ + int sda_io_num; /*!< GPIO number for I2C sda signal */ + int scl_io_num; /*!< GPIO number for I2C scl signal */ + bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/ + bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/ + + union { + struct { + uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */ + } master; /*!< I2C master config */ + struct { + uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */ + uint16_t slave_addr; /*!< I2C address for slave mode */ + } slave; /*!< I2C slave config */ + }; + uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/ +} i2c_config_t; + typedef void *i2c_cmd_handle_t; /*!< I2C command handle */ diff --git a/components/driver/include/driver/i2s.h b/components/driver/include/driver/i2s.h index e5968ad3f7..6b53db68a2 100644 --- a/components/driver/include/driver/i2s.h +++ b/components/driver/include/driver/i2s.h @@ -25,6 +25,7 @@ #include "hal/i2s_types.h" #include "driver/periph_ctrl.h" #include "esp_intr_alloc.h" + #if SOC_I2S_SUPPORTS_ADC_DAC #include "driver/adc.h" #endif @@ -82,21 +83,6 @@ esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin); esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t dsr); #endif -/** - * @brief Set I2S dac mode, I2S built-in DAC is disabled by default - * - * @param dac_mode DAC mode configurations - see i2s_dac_mode_t - * - * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip. - * If either of the built-in DAC channel are enabled, the other one can not - * be used as RTC DAC function at the same time. - * - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG Parameter error - */ -esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode); - /** * @brief Install and start I2S driver. * @@ -331,7 +317,23 @@ esp_err_t i2s_adc_enable(i2s_port_t i2s_num); * - ESP_ERR_INVALID_STATE Driver state error */ esp_err_t i2s_adc_disable(i2s_port_t i2s_num); -#endif + +/** + * @brief Set I2S dac mode, I2S built-in DAC is disabled by default + * + * @param dac_mode DAC mode configurations - see i2s_dac_mode_t + * + * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip. + * If either of the built-in DAC channel are enabled, the other one can not + * be used as RTC DAC function at the same time. + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + */ +esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode); +#endif //SOC_I2S_SUPPORTS_ADC_DAC + #ifdef __cplusplus } diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h index ea8878223c..4cdcf74ba4 100644 --- a/components/driver/include/driver/rtc_io.h +++ b/components/driver/include/driver/rtc_io.h @@ -17,10 +17,12 @@ #include #include "esp_err.h" -#include "driver/gpio.h" #include "soc/soc_caps.h" #include "soc/rtc_io_periph.h" #include "hal/rtc_io_types.h" +#include "driver/gpio.h" + + #ifdef __cplusplus extern "C" { #endif @@ -42,6 +44,7 @@ static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio() +#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED /** * @brief Get RTC IO index number by gpio number. * @@ -52,15 +55,9 @@ static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) */ static inline int rtc_io_number_get(gpio_num_t gpio_num) { -#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED return rtc_io_num_map[gpio_num]; -#else - return gpio_num; -#endif } -#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED - /** * @brief Init a GPIO as RTC GPIO * diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h index 9a7d5d81e6..5fee265c0a 100644 --- a/components/driver/include/driver/spi_common.h +++ b/components/driver/include/driver/spi_common.h @@ -106,7 +106,7 @@ typedef struct { int sclk_io_num; ///< GPIO pin for Spi CLocK signal, or -1 if not used. int quadwp_io_num; ///< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used. int quadhd_io_num; ///< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used. - int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4094 if 0. + int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` if DMA is disabled. uint32_t flags; ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags. int intr_flags; /**< Interrupt flag for the bus to set the priority, and IRAM attribute, see * ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored diff --git a/components/driver/include/esp_private/gpio.h b/components/driver/include/esp_private/gpio.h new file mode 100644 index 0000000000..1c4811393c --- /dev/null +++ b/components/driver/include/esp_private/gpio.h @@ -0,0 +1,45 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "sdkconfig.h" +#include + +#include "soc/soc_caps.h" +#include "driver/gpio.h" + +#if SOC_GPIO_SUPPORT_SLP_SWITCH +#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL +/** + * @brief Emulate ESP32S2 behaviour to backup FUN_PU, FUN_PD information + * + * @note Need to be called before sleep. + * + * @return + * - ESP_OK Success + */ +esp_err_t gpio_sleep_pupd_config_apply(gpio_num_t gpio_num); + +/** + * @brief Emulate ESP32S2 behaviour to restore FUN_PU, FUN_PD information + * + * @note Need to be called after sleep. + * + * @return + * - ESP_OK Success + */ +esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num); +#endif +#endif diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 64f12e8bd9..79e942b6d9 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -21,6 +21,7 @@ #include "soc/rtc.h" #include "soc/soc_caps.h" #include "hal/ledc_hal.h" +#include "hal/gpio_hal.h" #include "driver/ledc.h" #include "esp_rom_gpio.h" #include "esp_rom_sys.h" @@ -355,7 +356,7 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc LEDC_ARG_CHECK(ledc_channel < LEDC_CHANNEL_MAX, "ledc_channel"); LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0); return ESP_OK; @@ -402,7 +403,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf) ledc_channel, gpio_num, duty, timer_select ); /*set LEDC signal in gpio matrix*/ - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0); diff --git a/components/driver/mcpwm.c b/components/driver/mcpwm.c index 6cab15d37e..45ed81c47b 100644 --- a/components/driver/mcpwm.c +++ b/components/driver/mcpwm.c @@ -24,6 +24,7 @@ #include "driver/periph_ctrl.h" #include "sdkconfig.h" #include "hal/mcpwm_hal.h" +#include "hal/gpio_hal.h" #include "esp_rom_gpio.h" typedef struct { @@ -109,7 +110,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); // we enabled both input and output mode for GPIO used here, which can help to simulate trigger source especially in test code - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); if (io_signal <= MCPWM2B) { // Generator output signal MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_INPUT_OUTPUT); diff --git a/components/driver/pcnt.c b/components/driver/pcnt.c index e04e177242..8d02df1ee2 100644 --- a/components/driver/pcnt.c +++ b/components/driver/pcnt.c @@ -19,6 +19,7 @@ #include "driver/periph_ctrl.h" #include "driver/pcnt.h" #include "hal/pcnt_hal.h" +#include "hal/gpio_hal.h" #include "esp_rom_gpio.h" #define PCNT_CHANNEL_ERR_STR "PCNT CHANNEL ERROR" @@ -85,14 +86,14 @@ static inline esp_err_t _pcnt_set_pin(pcnt_port_t pcnt_port, pcnt_unit_t unit, p PCNT_CHECK(GPIO_IS_VALID_GPIO(ctrl_io) || ctrl_io < 0, PCNT_GPIO_ERR_STR, ESP_ERR_INVALID_ARG); if (pulse_io >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[pulse_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[pulse_io], PIN_FUNC_GPIO); gpio_set_direction(pulse_io, GPIO_MODE_INPUT); gpio_set_pull_mode(pulse_io, GPIO_PULLUP_ONLY); esp_rom_gpio_connect_in_signal(pulse_io, pcnt_periph_signals.units[unit].channels[channel].pulse_sig, 0); } if (ctrl_io >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[ctrl_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[ctrl_io], PIN_FUNC_GPIO); gpio_set_direction(ctrl_io, GPIO_MODE_INPUT); gpio_set_pull_mode(ctrl_io, GPIO_PULLUP_ONLY); esp_rom_gpio_connect_in_signal(ctrl_io, pcnt_periph_signals.units[unit].channels[channel].control_sig, 0); diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 12c29dde30..8c75f9ffbf 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -30,6 +30,7 @@ #include "soc/rtc.h" #include "hal/rmt_hal.h" #include "hal/rmt_ll.h" +#include "hal/gpio_hal.h" #include "esp_rom_gpio.h" #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR" @@ -536,7 +537,7 @@ esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_n (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); if (mode == RMT_MODE_TX) { RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); diff --git a/components/driver/sdio_slave.c b/components/driver/sdio_slave.c index 3f9ffd9fa0..5d259be381 100644 --- a/components/driver/sdio_slave.c +++ b/components/driver/sdio_slave.c @@ -98,6 +98,7 @@ The driver of FIFOs works as below: #include "driver/periph_ctrl.h" #include "driver/gpio.h" #include "hal/sdio_slave_hal.h" +#include "hal/gpio_hal.h" #define SDIO_SLAVE_CHECK(res, str, ret_val) do { if(!(res)){\ @@ -280,7 +281,7 @@ static void configure_pin(int pin, uint32_t func, bool pullup) assert(reg != UINT32_MAX); PIN_INPUT_ENABLE(reg); - PIN_FUNC_SELECT(reg, sdmmc_func); + gpio_hal_iomux_func_sel(reg, sdmmc_func); PIN_SET_DRV(reg, drive_strength); gpio_pulldown_dis(pin); if (pullup) { @@ -322,7 +323,7 @@ static void recover_pin(int pin, int sdio_func) int func = REG_GET_FIELD(reg, MCU_SEL); if (func == sdio_func) { gpio_set_direction(pin, GPIO_MODE_INPUT); - PIN_FUNC_SELECT(reg, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(reg, PIN_FUNC_GPIO); } } diff --git a/components/driver/sdmmc_host.c b/components/driver/sdmmc_host.c index f3a740c5fb..30b5bdd22e 100644 --- a/components/driver/sdmmc_host.c +++ b/components/driver/sdmmc_host.c @@ -29,6 +29,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "soc/sdmmc_periph.h" +#include "hal/gpio_hal.h" #define SDMMC_EVENT_QUEUE_LENGTH 32 @@ -303,7 +304,7 @@ static void configure_pin(int pin) uint32_t reg = GPIO_PIN_MUX_REG[pin]; assert(reg != UINT32_MAX); PIN_INPUT_ENABLE(reg); - PIN_FUNC_SELECT(reg, sdmmc_func); + gpio_hal_iomux_func_sel(reg, sdmmc_func); PIN_SET_DRV(reg, drive_strength); } diff --git a/components/driver/sigmadelta.c b/components/driver/sigmadelta.c index 043a996fba..b0e436f320 100644 --- a/components/driver/sigmadelta.c +++ b/components/driver/sigmadelta.c @@ -17,6 +17,7 @@ #include "driver/sigmadelta.h" #include "esp_heap_caps.h" #include "hal/sigmadelta_hal.h" +#include "hal/gpio_hal.h" #include "esp_rom_gpio.h" static const char *TAG = "sigma-delta"; @@ -57,7 +58,7 @@ static inline esp_err_t _sigmadelta_set_pin(sigmadelta_port_t sigmadelta_port, s { SIGMADELTA_OBJ_CHECK(sigmadelta_port); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(gpio_num, sigma_delta_periph_signals.channels[channel].sd_sig, 0, 0); return ESP_OK; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index f0e6cae24b..618b3d1f0e 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -30,6 +30,7 @@ #include "driver/spi_common_internal.h" #include "stdatomic.h" #include "hal/spi_hal.h" +#include "hal/gpio_hal.h" #include "esp_rom_gpio.h" #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" @@ -498,7 +499,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]); #endif - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO); } if (bus_config->miso_io_num >= 0) { if (miso_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) { @@ -511,7 +512,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]); #endif - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO); } if (bus_config->quadwp_io_num >= 0) { gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -520,7 +521,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]); #endif - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO); } if (bus_config->quadhd_io_num >= 0) { gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -529,7 +530,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]); #endif - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO); } if (bus_config->sclk_io_num >= 0) { if (sclk_need_output) { @@ -542,7 +543,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]); #endif - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO); } } @@ -582,7 +583,7 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, } if (cs_num == 0) esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO); } } diff --git a/components/driver/test/test_common_spi.c b/components/driver/test/test_common_spi.c index e302aae771..0081d2446d 100644 --- a/components/driver/test/test_common_spi.c +++ b/components/driver/test/test_common_spi.c @@ -2,6 +2,7 @@ #include "driver/spi_slave.h" #include "esp_log.h" #include "driver/gpio.h" +#include "hal/gpio_hal.h" int test_freq_default[]=TEST_FREQ_DEFAULT(); @@ -202,13 +203,13 @@ void master_free_device_bus(spi_device_handle_t spi) void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); GPIO.func_out_sel_cfg[gpio_num].func_sel = signal_idx; } void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); GPIO.func_in_sel_cfg[signal_idx].func_sel = gpio_num; } diff --git a/components/driver/test/test_dac.c b/components/driver/test/test_dac.c index 31f0e8e142..2708901551 100644 --- a/components/driver/test/test_dac.c +++ b/components/driver/test/test_dac.c @@ -12,8 +12,9 @@ #include "nvs_flash.h" #include "test_utils.h" #include "driver/i2s.h" +#include "soc/soc_caps.h" -#if !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if SOC_DAC_SUPPORTED #include "driver/dac.h" #include "esp_adc_cal.h" @@ -182,4 +183,4 @@ TEST_CASE("esp32s2 adc2-dac with adc2 calibration", "[adc-dac]") } #endif -#endif // !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#endif // SOC_DAC_SUPPORTED diff --git a/components/driver/test/test_i2c.c b/components/driver/test/test_i2c.c index 06965eacd7..3fab130012 100644 --- a/components/driver/test/test_i2c.c +++ b/components/driver/test/test_i2c.c @@ -17,6 +17,7 @@ #include "soc/uart_struct.h" #include "driver/periph_ctrl.h" #include "esp_rom_gpio.h" +#include "hal/gpio_hal.h" #define DATA_LENGTH 512 /*! #include "sdkconfig.h" #include "hal/cpu_hal.h" +#include "hal/gpio_hal.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_log.h" @@ -63,7 +64,7 @@ static void rmt_setup_testbench(int tx_channel, int rx_channel, uint32_t flags) } // Routing internal signals by IO Matrix (bind rmt tx and rx signal on the same GPIO) - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[RMT_DATA_IO], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[RMT_DATA_IO], PIN_FUNC_GPIO); TEST_ESP_OK(gpio_set_direction(RMT_DATA_IO, GPIO_MODE_INPUT_OUTPUT)); esp_rom_gpio_connect_out_signal(RMT_DATA_IO, RMT_SIG_OUT0_IDX + tx_channel, 0, 0); esp_rom_gpio_connect_in_signal(RMT_DATA_IO, RMT_SIG_IN0_IDX + rx_channel, 0); diff --git a/components/driver/uart.c b/components/driver/uart.c index a396f6d604..bf21ac3f80 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -22,6 +22,7 @@ #include "freertos/semphr.h" #include "freertos/ringbuf.h" #include "hal/uart_hal.h" +#include "hal/gpio_hal.h" #include "soc/uart_periph.h" #include "soc/rtc_cntl_reg.h" #include "driver/uart.h" @@ -597,23 +598,23 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r UART_CHECK((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), "cts_io_num error", ESP_FAIL); if(tx_io_num >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO); gpio_set_level(tx_io_num, 1); esp_rom_gpio_connect_out_signal(tx_io_num, uart_periph_signal[uart_num].tx_sig, 0, 0); } if(rx_io_num >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO); gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY); gpio_set_direction(rx_io_num, GPIO_MODE_INPUT); esp_rom_gpio_connect_in_signal(rx_io_num, uart_periph_signal[uart_num].rx_sig, 0); } if(rts_io_num >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO); gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(rts_io_num, uart_periph_signal[uart_num].rts_sig, 0, 0); } if(cts_io_num >= 0) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO); gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY); gpio_set_direction(cts_io_num, GPIO_MODE_INPUT); esp_rom_gpio_connect_in_signal(cts_io_num, uart_periph_signal[uart_num].cts_sig, 0); diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c index a94883d986..0e329fc6d9 100644 --- a/components/esp32/spiram_psram.c +++ b/components/esp32/spiram_psram.c @@ -33,6 +33,7 @@ #include "soc/efuse_periph.h" #include "soc/soc_caps.h" #include "driver/gpio.h" +#include "hal/gpio_hal.h" #include "driver/spi_common_internal.h" #include "driver/periph_ctrl.h" #include "bootloader_common.h" @@ -752,18 +753,18 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t //select pin function gpio if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) { //flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK); } else { //flash clock signal should come from GPIO matrix. - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO); } - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO); uint32_t flash_id = g_rom_flashchip.device_id; if (flash_id == FLASH_ID_GD25LQ32C) { diff --git a/components/esp32/test/test_ahb_arb.c b/components/esp32/test/test_ahb_arb.c index 9fa555b418..1b3c3d5126 100644 --- a/components/esp32/test/test_ahb_arb.c +++ b/components/esp32/test/test_ahb_arb.c @@ -4,6 +4,7 @@ #include #include "esp32/rom/lldesc.h" #include "driver/periph_ctrl.h" +#include "hal/gpio_hal.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" @@ -36,16 +37,16 @@ static void lcdIfaceInit(void) //Init pins to i2s functions SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); diff --git a/components/esp32/test/test_fastbus.c b/components/esp32/test/test_fastbus.c index 39adbe7616..d90f3debf3 100644 --- a/components/esp32/test/test_fastbus.c +++ b/components/esp32/test/test_fastbus.c @@ -10,6 +10,7 @@ #include "unity.h" #include "soc/uart_periph.h" #include "soc/dport_reg.h" +#include "hal/gpio_hal.h" #include "driver/gpio.h" @@ -104,8 +105,8 @@ TEST_CASE("Fast I/O bus test", "[hw][ignore]") } gpio_pullup_dis(10); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD); int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S); WRITE_PERI_REG(UART_CONF1_REG(1), reg_val); diff --git a/components/esp32/test/test_unal_dma.c b/components/esp32/test/test_unal_dma.c index 7984138070..f568e4d3d4 100644 --- a/components/esp32/test/test_unal_dma.c +++ b/components/esp32/test/test_unal_dma.c @@ -5,6 +5,7 @@ #include #include "esp32/rom/lldesc.h" #include "driver/periph_ctrl.h" +#include "hal/gpio_hal.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" @@ -32,16 +33,16 @@ static void dmaMemcpy(void *in, void *out, int len) //Init pins to i2s functions SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); diff --git a/components/esp32s3/spiram_psram.c b/components/esp32s3/spiram_psram.c index c909d8ec1f..a7e295a135 100644 --- a/components/esp32s3/spiram_psram.c +++ b/components/esp32s3/spiram_psram.c @@ -39,6 +39,7 @@ #include "soc/soc.h" #include "soc/io_mux_reg.h" #include "driver/gpio.h" +#include "hal/gpio_hal.h" #include "driver/spi_common_internal.h" #include "driver/spi_common.h" #include "driver/periph_ctrl.h" @@ -379,10 +380,10 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); if (psram_io.psram_cs_io == SPI_CS1_GPIO_NUM) { - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], FUNC_SPICS1_SPICS1); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], FUNC_SPICS1_SPICS1); } else { esp_rom_gpio_connect_out_signal(psram_io.psram_cs_io, SPICS1_OUT_IDX, 0, 0); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], PIN_FUNC_GPIO); } } diff --git a/components/esp_eth/src/esp_eth_mac_esp32.c b/components/esp_eth/src/esp_eth_mac_esp32.c index 45d99788d0..e9c051dd6d 100644 --- a/components/esp_eth/src/esp_eth_mac_esp32.c +++ b/components/esp_eth/src/esp_eth_mac_esp32.c @@ -28,6 +28,7 @@ #include "freertos/semphr.h" #include "hal/cpu_hal.h" #include "hal/emac.h" +#include "hal/gpio_hal.h" #include "soc/soc.h" #include "sdkconfig.h" #include "esp_rom_gpio.h" @@ -318,14 +319,14 @@ static void emac_esp32_init_smi_gpio(emac_esp32_t *emac) /* Setup SMI MDC GPIO */ gpio_set_direction(emac->smi_mdc_gpio_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(emac->smi_mdc_gpio_num, EMAC_MDC_O_IDX, false, false); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[emac->smi_mdc_gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[emac->smi_mdc_gpio_num], PIN_FUNC_GPIO); } if (emac->smi_mdio_gpio_num >= 0) { /* Setup SMI MDIO GPIO */ gpio_set_direction(emac->smi_mdio_gpio_num, GPIO_MODE_INPUT_OUTPUT); esp_rom_gpio_connect_out_signal(emac->smi_mdio_gpio_num, EMAC_MDO_O_IDX, false, false); esp_rom_gpio_connect_in_signal(emac->smi_mdio_gpio_num, EMAC_MDI_I_IDX, false); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[emac->smi_mdio_gpio_num], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[emac->smi_mdio_gpio_num], PIN_FUNC_GPIO); } } diff --git a/components/esp_eth/src/esp_eth_mac_w5500.c b/components/esp_eth/src/esp_eth_mac_w5500.c index ce69385a83..1f97d7fd68 100644 --- a/components/esp_eth/src/esp_eth_mac_w5500.c +++ b/components/esp_eth/src/esp_eth_mac_w5500.c @@ -93,6 +93,7 @@ static esp_err_t w5500_read(emac_w5500_t *emac, uint32_t address, void *value, u esp_err_t ret = ESP_OK; spi_transaction_t trans = { + .flags = len <= 4 ? SPI_TRANS_USE_RXDATA : 0, // use direct reads for registers to prevent overwrites by 4-byte boundary writes .cmd = (address >> W5500_ADDR_OFFSET), .addr = ((address & 0xFFFF) | (W5500_ACCESS_MODE_READ << W5500_RWB_OFFSET) | W5500_SPI_OP_MODE_VDM), .length = 8 * len, @@ -107,6 +108,9 @@ static esp_err_t w5500_read(emac_w5500_t *emac, uint32_t address, void *value, u } else { ret = ESP_ERR_TIMEOUT; } + if ((trans.flags&SPI_TRANS_USE_RXDATA) && len <= 4) { + memcpy(value, trans.rx_data, len); // copy register values to output + } return ret; } @@ -498,6 +502,16 @@ static esp_err_t emac_w5500_set_peer_pause_ability(esp_eth_mac_t *mac, uint32_t return ESP_ERR_NOT_SUPPORTED; } +static inline bool is_w5500_sane_for_rxtx(emac_w5500_t *emac) +{ + uint8_t phycfg; + /* phy is ok for rx and tx operations if bits RST and LNK are set (no link down, no reset) */ + if (w5500_read(emac, W5500_REG_PHYCFGR, &phycfg, 1) == ESP_OK && (phycfg & 0x8001)) { + return true; + } + return false; +} + static esp_err_t emac_w5500_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length) { esp_err_t ret = ESP_OK; @@ -521,10 +535,14 @@ static esp_err_t emac_w5500_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t MAC_CHECK(w5500_send_command(emac, W5500_SCR_SEND, 100) == ESP_OK, "issue SEND command failed", err, ESP_FAIL); // pooling the TX done event + int retry = 0; uint8_t status = 0; - do { + while (!(status & W5500_SIR_SEND)) { MAC_CHECK(w5500_read(emac, W5500_REG_SOCK_IR(0), &status, sizeof(status)) == ESP_OK, "read SOCK0 IR failed", err, ESP_FAIL); - } while (!(status & W5500_SIR_SEND)); + if ((retry++ > 3 && !is_w5500_sane_for_rxtx(emac)) || retry > 10) { + return ESP_FAIL; + } + } // clear the event bit status = W5500_SIR_SEND; MAC_CHECK(w5500_write(emac, W5500_REG_SOCK_IR(0), &status, sizeof(status)) == ESP_OK, "write SOCK0 IR failed", err, ESP_FAIL); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 66cc3ccd71..74cc4b54cf 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -54,13 +54,13 @@ #include "esp32/rom/cache.h" #include "esp32/clk.h" #include "esp32/rom/rtc.h" -#include "driver/gpio.h" +#include "esp_private/gpio.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/rtc.h" #include "soc/extmem_reg.h" -#include "driver/gpio.h" +#include "esp_private/gpio.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/clk.h" #include "esp32s3/rom/cache.h" @@ -702,6 +702,7 @@ esp_err_t esp_light_sleep_start(void) esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); #else s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); #endif /* diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test/test_rtc_clk.c index 1a12903905..8d0496efdb 100644 --- a/components/esp_hw_support/test/test_rtc_clk.c +++ b/components/esp_hw_support/test/test_rtc_clk.c @@ -153,7 +153,7 @@ TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]") uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz); - TEST_ASSERT_INT32_WITHIN(500000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz); + TEST_ASSERT_INT32_WITHIN(650000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz); } TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]") diff --git a/components/esp_pm/include/esp_pm.h b/components/esp_pm/include/esp_pm.h index 4d5146316b..86a404286f 100644 --- a/components/esp_pm/include/esp_pm.h +++ b/components/esp_pm/include/esp_pm.h @@ -63,6 +63,14 @@ typedef enum { */ esp_err_t esp_pm_configure(const void* config); +/** + * @brief Get implementation-specific power management configuration + * @param config pointer to implementation-specific configuration structure (e.g. esp_pm_config_esp32) + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the pointer is null + */ +esp_err_t esp_pm_get_configuration(void* config); /** * @brief Opaque handle to the power management lock diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 599304987e..535de8859d 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -322,6 +322,31 @@ esp_err_t esp_pm_configure(const void* vconfig) return ESP_OK; } +esp_err_t esp_pm_get_configuration(void* vconfig) +{ + if (vconfig == NULL) { + return ESP_ERR_INVALID_ARG; + } + +#if CONFIG_IDF_TARGET_ESP32 + esp_pm_config_esp32_t* config = (esp_pm_config_esp32_t*) vconfig; +#elif CONFIG_IDF_TARGET_ESP32S2 + esp_pm_config_esp32s2_t* config = (esp_pm_config_esp32s2_t*) vconfig; +#elif CONFIG_IDF_TARGET_ESP32S3 + esp_pm_config_esp32s3_t* config = (esp_pm_config_esp32s3_t*) vconfig; +#elif CONFIG_IDF_TARGET_ESP32C3 + esp_pm_config_esp32c3_t* config = (esp_pm_config_esp32c3_t*) vconfig; +#endif + + portENTER_CRITICAL(&s_switch_lock); + config->light_sleep_enable = s_light_sleep_en; + config->max_freq_mhz = s_cpu_freq_by_mode[PM_MODE_CPU_MAX].freq_mhz; + config->min_freq_mhz = s_cpu_freq_by_mode[PM_MODE_APB_MIN].freq_mhz; + portEXIT_CRITICAL(&s_switch_lock); + + return ESP_OK; +} + static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void) { /* TODO: optimize using ffs/clz */ diff --git a/components/espcoredump/src/core_dump_uart.c b/components/espcoredump/src/core_dump_uart.c index a04967d95c..f510afde38 100644 --- a/components/espcoredump/src/core_dump_uart.c +++ b/components/espcoredump/src/core_dump_uart.c @@ -15,6 +15,7 @@ #include "soc/uart_periph.h" #include "soc/gpio_periph.h" #include "driver/gpio.h" +#include "hal/gpio_hal.h" #include "esp_core_dump_types.h" #include "esp_core_dump_port.h" #include "esp_core_dump_common.h" @@ -147,8 +148,8 @@ void esp_core_dump_to_uart(panic_info_t *info) //Make sure txd/rxd are enabled // use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD); ESP_COREDUMP_LOGI("Press Enter to print core dump to UART..."); const int cpu_ticks_per_ms = esp_clk_cpu_freq() / 1000; diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 86dcdd3edc..e709ee1397 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -70,7 +70,6 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32s3") list(APPEND srcs - "dac_hal.c" "gdma_hal.c" "lcd_hal.c" "pcnt_hal.c" diff --git a/components/hal/component.mk b/components/hal/component.mk index 4c9254ba5f..da3d6456b9 100644 --- a/components/hal/component.mk +++ b/components/hal/component.mk @@ -7,3 +7,7 @@ COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave ifndef CONFIG_ETH_USE_ESP32_EMAC COMPONENT_OBJEXCLUDE += esp32/emac_hal.o endif + +ifdef IS_BOOTLOADER_BUILD + COMPONENT_OBJEXCLUDE += esp32/emac_hal.o +endif diff --git a/components/hal/esp32/emac_hal.c b/components/hal/esp32/emac_hal.c index b1ca6ff76f..5ba3c4aec9 100644 --- a/components/hal/esp32/emac_hal.c +++ b/components/hal/esp32/emac_hal.c @@ -17,6 +17,7 @@ #include "soc/gpio_periph.h" #include "soc/rtc.h" #include "hal/emac.h" +#include "hal/gpio_hal.h" #define ETH_CRC_LENGTH (4) @@ -63,27 +64,27 @@ void emac_hal_lowlevel_init(emac_hal_context_t *hal) { /* GPIO configuration */ /* TX_EN to GPIO21 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]); /* TXD0 to GPIO19 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]); /* TXD1 to GPIO22 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]); /* RXD0 to GPIO25 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]); /* RXD1 to GPIO26 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]); /* CRS_DV to GPIO27 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]); #if CONFIG_ETH_RMII_CLK_INPUT #if CONFIG_ETH_RMII_CLK_IN_GPIO == 0 /* RMII clock (50MHz) input to GPIO0 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]); #else #error "ESP32 EMAC only support input RMII clock to GPIO0" @@ -92,15 +93,15 @@ void emac_hal_lowlevel_init(emac_hal_context_t *hal) #if CONFIG_ETH_RMII_CLK_OUTPUT #if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0 /* APLL clock output to GPIO0 (must be configured to 50MHz!) */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]); #elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 16 /* RMII CLK (50MHz) output to GPIO16 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]); #elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 17 /* RMII CLK (50MHz) output to GPIO17 */ - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180); PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]); #endif #endif // CONFIG_ETH_RMII_CLK_OUTPUT diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index a421cab413..8c1acb3a1c 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -567,6 +567,17 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + PIN_FUNC_SELECT(pin_name, func); +} + /** * @brief Set peripheral output to an GPIO pad through the IOMUX. * @@ -580,7 +591,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } #ifdef __cplusplus diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index 5fdd8f38bb..6ba4d601b9 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -32,6 +32,17 @@ extern "C" { #endif +/* + * The following defines are used to disable USB JTAG when pins 18 and pins 19 + * are set to be used as GPIO. + * See gpio_pad_select_gpio() below. + * + * TODO: Delete these definitions once the USB device registers definition is + * merged. + */ +#define USB_DEVICE_CONF0_REG (0x60043018) +#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) + // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -379,6 +390,20 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { + CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(pin_name, func); +} + /** * @brief Set peripheral output to an GPIO pad through the IOMUX. * @@ -392,7 +417,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index aa02c11199..d6330db630 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -391,6 +391,17 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + PIN_FUNC_SELECT(pin_name, func); +} + /** * @brief Set peripheral output to an GPIO pad through the IOMUX. * @@ -404,7 +415,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) diff --git a/components/hal/esp32s3/include/hal/dac_ll.h b/components/hal/esp32s3/include/hal/dac_ll.h deleted file mode 100644 index 7e5f3621b0..0000000000 --- a/components/hal/esp32s3/include/hal/dac_ll.h +++ /dev/null @@ -1,206 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - -#pragma once - -#include -#include "soc/dac_periph.h" -#include "hal/dac_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Power on dac module and start output voltage. - * - * @note Before powering up, make sure the DAC PAD is set to RTC PAD and floating status. - * @param channel DAC channel num. - */ -static inline void dac_ll_power_on(dac_channel_t channel) -{ - RTCIO.pad_dac[channel].dac_xpd_force = 1; - RTCIO.pad_dac[channel].xpd_dac = 1; -} - -/** - * Power done dac module and stop output voltage. - * - * @param channel DAC channel num. - */ -static inline void dac_ll_power_down(dac_channel_t channel) -{ - RTCIO.pad_dac[channel].dac_xpd_force = 0; - RTCIO.pad_dac[channel].xpd_dac = 0; -} - -/** - * Output voltage with value (8 bit). - * - * @param channel DAC channel num. - * @param value Output value. Value range: 0 ~ 255. - * The corresponding range of voltage is 0v ~ VDD3P3_RTC. - */ -static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value) -{ - if (channel == DAC_CHANNEL_1) { - SENS.sar_dac_ctrl2.dac_cw_en1 = 0; - RTCIO.pad_dac[channel].dac = value; - } else if (channel == DAC_CHANNEL_2) { - SENS.sar_dac_ctrl2.dac_cw_en2 = 0; - RTCIO.pad_dac[channel].dac = value; - } -} - -/** - * Enable/disable the synchronization operation function of ADC1 and DAC. - * - * @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. - * - * @param enable Enable or disable adc and dac synchronization function. - */ -static inline void dac_ll_rtc_sync_by_adc(bool enable) -{ - // SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable; -} - -/************************************/ -/* DAC cosine wave generator API's */ -/************************************/ -/** - * Enable cosine wave generator output. - */ -static inline void dac_ll_cw_generator_enable(void) -{ - SENS.sar_dac_ctrl1.sw_tone_en = 1; -} - -/** - * Disable cosine wave generator output. - */ -static inline void dac_ll_cw_generator_disable(void) -{ - SENS.sar_dac_ctrl1.sw_tone_en = 0; -} - -/** - * Enable the cosine wave generator of DAC channel. - * - * @param channel DAC channel num. - * @param enable - */ -static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) -{ - if (channel == DAC_CHANNEL_1) { - SENS.sar_dac_ctrl2.dac_cw_en1 = enable; - } else if (channel == DAC_CHANNEL_2) { - SENS.sar_dac_ctrl2.dac_cw_en2 = enable; - } -} - -/** - * Set frequency of cosine wave generator output. - * - * @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error. - * @param freq_hz CW generator frequency. Range: 130(130Hz) ~ 55000(100KHz). - */ -static inline void dac_ll_cw_set_freq(uint32_t freq) -{ - uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX; - SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq; -} - -/** - * Set the amplitude of the cosine wave generator output. - * - * @param channel DAC channel num. - * @param scale The multiple of the amplitude. The max amplitude is VDD3P3_RTC. - */ -static inline void dac_ll_cw_set_scale(dac_channel_t channel, dac_cw_scale_t scale) -{ - if (channel == DAC_CHANNEL_1) { - SENS.sar_dac_ctrl2.dac_scale1 = scale; - } else if (channel == DAC_CHANNEL_2) { - SENS.sar_dac_ctrl2.dac_scale2 = scale; - } -} - -/** - * Set the phase of the cosine wave generator output. - * - * @param channel DAC channel num. - * @param scale Phase value. - */ -static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cw_phase_t phase) -{ - if (channel == DAC_CHANNEL_1) { - SENS.sar_dac_ctrl2.dac_inv1 = phase; - } else if (channel == DAC_CHANNEL_2) { - SENS.sar_dac_ctrl2.dac_inv2 = phase; - } -} - -/** - * Set the voltage value of the DC component of the cosine wave generator output. - * - * @note The DC offset setting should be after phase setting. - * @note Unreasonable settings can cause the signal to be oversaturated. - * @param channel DAC channel num. - * @param offset DC value. Range: -128 ~ 127. - */ -static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset) -{ - if (channel == DAC_CHANNEL_1) { - if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) { - offset = 0 - offset; - } - SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset); - } else if (channel == DAC_CHANNEL_2) { - if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) { - offset = 0 - offset; - } - SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset); - } -} - -/************************************/ -/* DAC DMA API's */ -/************************************/ -/** - * Enable DAC output data from I2S DMA. - * I2S_CLK connect to DAC_CLK, I2S_DATA_OUT connect to DAC_DATA. - */ -static inline void dac_ll_dma_enable(void) -{ - SENS.sar_dac_ctrl1.dac_dig_force = 1; -} - -/** - * Disable DAC output data from I2S DMA. - */ -static inline void dac_ll_dma_disable(void) -{ - SENS.sar_dac_ctrl1.dac_dig_force = 0; -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index 783def85e6..234b477578 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -391,6 +391,17 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + PIN_FUNC_SELECT(pin_name, func); +} + /** * @brief Set peripheral output to an GPIO pad through the IOMUX. * @@ -404,7 +415,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 5a403f529c..018b4be128 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -466,6 +466,14 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, gpio_num_t gpio #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +#define gpio_hal_iomux_func_sel(pin_name, func) gpio_ll_iomux_func_sel(pin_name, func) + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h index 3d5864dc10..12147c78b7 100644 --- a/components/hal/include/hal/i2c_types.h +++ b/components/hal/include/hal/i2c_types.h @@ -79,36 +79,9 @@ typedef enum { I2C_SCLK_MAX, } i2c_sclk_t; -// I2C clk flags for users to use, can be expanded in the future. -#define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/ -#define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/ -#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP (1 << 1) /*!< For light sleep mode.*/ - /// Use the highest speed that is available for the clock source picked by clk_flags #define I2C_CLK_FREQ_MAX (-1) -/** - * @brief I2C initialization parameters - */ -typedef struct{ - i2c_mode_t mode; /*!< I2C mode */ - int sda_io_num; /*!< GPIO number for I2C sda signal */ - int scl_io_num; /*!< GPIO number for I2C scl signal */ - bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/ - bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/ - - union { - struct { - uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */ - } master; /*!< I2C master config */ - struct { - uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */ - uint16_t slave_addr; /*!< I2C address for slave mode */ - } slave; /*!< I2C slave config */ - }; - uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/ -} i2c_config_t; - #if CONFIG_IDF_TARGET_ESP32 typedef enum{ I2C_CMD_RESTART = 0, /*!hostname)) { + if (header.questions && !header.answers && _str_null_or_empty(_mdns_server->hostname)) { free(parsed_packet); return; } @@ -2815,13 +2815,12 @@ void mdns_parse_packet(mdns_rx_packet_t * packet) if (parsed_packet->discovery && _mdns_name_is_discovery(name, type)) { discovery = true; - } else { - if (!name->sub && _mdns_name_is_ours(name)) { - ours = true; - if (name->service && name->service[0] && name->proto && name->proto[0]) { - service = _mdns_get_service_item(name->service, name->proto); - } + } else if (!name->sub && _mdns_name_is_ours(name)) { + ours = true; + if (name->service && name->service[0] && name->proto && name->proto[0]) { + service = _mdns_get_service_item(name->service, name->proto); } + } else { if (!parsed_packet->authoritative || record_type == MDNS_NS) { //skip this record continue; diff --git a/components/mdns/mdns_networking.c b/components/mdns/mdns_networking.c index 152ab2798e..48d11918ba 100644 --- a/components/mdns/mdns_networking.c +++ b/components/mdns/mdns_networking.c @@ -38,7 +38,7 @@ static esp_err_t _udp_pcb_main_init(void) _pcb_main = NULL; return ESP_ERR_INVALID_STATE; } - _pcb_main->mcast_ttl = 1; + _pcb_main->mcast_ttl = 255; _pcb_main->remote_port = MDNS_SERVICE_PORT; ip_addr_copy(_pcb_main->remote_ip, *(IP_ANY_TYPE)); udp_recv(_pcb_main, &_udp_recv, _mdns_server); diff --git a/components/mdns/private_include/mdns_private.h b/components/mdns/private_include/mdns_private.h index 60dfeb4ee5..9ed0dcfbd1 100644 --- a/components/mdns/private_include/mdns_private.h +++ b/components/mdns/private_include/mdns_private.h @@ -32,7 +32,11 @@ * such as lwIP mdns resolver (used by standard POSIX API like getaddrinfo, gethostbyname) * could not correctly resolve advertised names. */ +#ifndef CONFIG_MDNS_STRICT_MODE #define MDNS_STRICT_MODE 0 +#else +#define MDNS_STRICT_MODE 1 +#endif #if !MDNS_STRICT_MODE /* mDNS responders sometimes repeat queries in responses diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 909659df9d..488acd8382 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -60,6 +60,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CAPS_ECO_VER_MAX 3 +#define SOC_DAC_SUPPORTED 1 #define SOC_MCPWM_SUPPORTED 1 #define SOC_SDMMC_HOST_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 diff --git a/components/soc/esp32c3/include/soc/gpio_caps.h b/components/soc/esp32c3/include/soc/gpio_caps.h index 770b7b2ad1..8da8d2194a 100644 --- a/components/soc/esp32c3/include/soc/gpio_caps.h +++ b/components/soc/esp32c3/include/soc/gpio_caps.h @@ -30,11 +30,6 @@ extern "C" { // GPIO0~5 on ESP32C3 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) -#define GPIO_MODE_DEF_DISABLE (0) -#define GPIO_MODE_DEF_INPUT (BIT0) -#define GPIO_MODE_DEF_OUTPUT (BIT1) -#define GPIO_MODE_DEF_OD (BIT2) - #define SOC_GPIO_VALID_GPIO_MASK ((1U<os_func->start(chip->os_func_data); PIN_INPUT_ENABLE(iomux_reg); if (use_iomux) { - PIN_FUNC_SELECT(iomux_reg, spics_func); + gpio_hal_iomux_func_sel(iomux_reg, spics_func); } else { #if SOC_GPIO_PIN_COUNT <= 32 GPIO.enable_w1ts.val = (0x1 << cs_io_num); @@ -143,7 +144,7 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f if (cs_id == 0) { esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false); } - PIN_FUNC_SELECT(iomux_reg, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(iomux_reg, PIN_FUNC_GPIO); } chip->os_func->end(chip->os_func_data); } diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index e1044db6b1..d61294040a 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -273,44 +273,13 @@ static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int } } +#if CONFIG_IDF_TARGET_ESP32 static void setup_bus(spi_host_device_t host_id) { if (host_id == SPI1_HOST) { ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n"); //no need to initialize the bus, however the CLK may need one more output if it's on the usual place of PSRAM -#ifdef EXTRA_SPI1_CLK_IO esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0); -#endif - -#if !DISABLED_FOR_TARGETS(ESP32) -#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT - //Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2. - int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin; - int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin; - gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in); - gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false); - gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in); - gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false); -#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT -#endif //!DISABLED_FOR_TARGETS(ESP32) - -#if !DISABLED_FOR_TARGETS(ESP32) - } else if (host_id == SPI2_HOST) { - ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1); - spi_bus_config_t fspi_bus_cfg = { - .mosi_io_num = FSPI_PIN_NUM_MOSI, - .miso_io_num = FSPI_PIN_NUM_MISO, - .sclk_io_num = FSPI_PIN_NUM_CLK, - .quadhd_io_num = FSPI_PIN_NUM_HD, - .quadwp_io_num = FSPI_PIN_NUM_WP, - .max_transfer_sz = 64, - }; -#ifdef FORCE_GPIO_MATRIX - fspi_bus_cfg.quadhd_io_num = 5; -#endif - esp_err_t ret = spi_bus_initialize(host_id, &fspi_bus_cfg, 0); - TEST_ESP_OK(ret); -#endif //currently the SPI bus for main flash chip is initialized through GPIO matrix } else if (host_id == SPI2_HOST) { ESP_LOGI(TAG, "setup flash on SPI%d (HSPI) CS0...\n", host_id + 1); @@ -322,25 +291,9 @@ static void setup_bus(spi_host_device_t host_id) .quadwp_io_num = HSPI_PIN_NUM_WP, .max_transfer_sz = 64, }; -#if !DISABLED_FOR_TARGETS(ESP32S2) -#ifdef FORCE_GPIO_MATRIX - hspi_bus_cfg.quadhd_io_num = 23; -#endif -#endif esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0); TEST_ESP_OK(ret); - -#if !DISABLED_FOR_TARGETS(ESP32) - // HSPI have no multiline mode, use GPIO to pull those pins up - gpio_set_direction(HSPI_PIN_NUM_HD, GPIO_MODE_OUTPUT); - gpio_set_level(HSPI_PIN_NUM_HD, 1); - - gpio_set_direction(HSPI_PIN_NUM_WP, GPIO_MODE_OUTPUT); - gpio_set_level(HSPI_PIN_NUM_WP, 1); -#endif - } -#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) - else if (host_id == VSPI_HOST) { + } else if (host_id == SPI3_HOST) { ESP_LOGI(TAG, "setup flash on SPI%d (VSPI) CS0...\n", host_id + 1); spi_bus_config_t vspi_bus_cfg = { .mosi_io_num = VSPI_PIN_NUM_MOSI, @@ -350,17 +303,63 @@ static void setup_bus(spi_host_device_t host_id) .quadwp_io_num = VSPI_PIN_NUM_WP, .max_transfer_sz = 64, }; -#ifdef FORCE_GPIO_MATRIX - vspi_bus_cfg.quadhd_io_num = 23; -#endif esp_err_t ret = spi_bus_initialize(host_id, &vspi_bus_cfg, 0); TEST_ESP_OK(ret); - } -#endif // disabled for esp32s2 - else { + } else { ESP_LOGE(TAG, "invalid bus"); } } +#else // FOR ESP32-S2, ESP32-S3, ESP32-C3 +static void setup_bus(spi_host_device_t host_id) +{ + if (host_id == SPI1_HOST) { + ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n"); +#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT + //Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2. + int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin; + int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin; + gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in); + gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false); + gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in); + gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false); +#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + //currently the SPI bus for main flash chip is initialized through GPIO matrix + } else if (host_id == SPI2_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1); + spi_bus_config_t fspi_bus_cfg = { + .mosi_io_num = FSPI_PIN_NUM_MOSI, + .miso_io_num = FSPI_PIN_NUM_MISO, + .sclk_io_num = FSPI_PIN_NUM_CLK, + .quadhd_io_num = FSPI_PIN_NUM_HD, + .quadwp_io_num = FSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &fspi_bus_cfg, 0); + TEST_ESP_OK(ret); + } else if (host_id == SPI3_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%d (HSPI) CS0...\n", host_id + 1); + spi_bus_config_t hspi_bus_cfg = { + .mosi_io_num = HSPI_PIN_NUM_MOSI, + .miso_io_num = HSPI_PIN_NUM_MISO, + .sclk_io_num = HSPI_PIN_NUM_CLK, + .quadhd_io_num = HSPI_PIN_NUM_HD, + .quadwp_io_num = HSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0); + TEST_ESP_OK(ret); + + // HSPI have no multiline mode, use GPIO to pull those pins up + gpio_set_direction(HSPI_PIN_NUM_HD, GPIO_MODE_OUTPUT); + gpio_set_level(HSPI_PIN_NUM_HD, 1); + + gpio_set_direction(HSPI_PIN_NUM_WP, GPIO_MODE_OUTPUT); + gpio_set_level(HSPI_PIN_NUM_WP, 1); + } else { + ESP_LOGE(TAG, "invalid bus"); + } +} +#endif // CONFIG_IDF_TARGET_ESP32 static void release_bus(int host_id) { diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt index 625ff97154..6eb57e091e 100644 --- a/components/ulp/cmake/CMakeLists.txt +++ b/components/ulp/cmake/CMakeLists.txt @@ -43,7 +43,7 @@ endif() set(ULP_MAP_GEN ${PYTHON} ${IDF_PATH}/components/ulp/esp32ulp_mapgen.py) -get_filename_component(sdkconfig_dir ${SDKCONFIG} DIRECTORY) +get_filename_component(sdkconfig_dir ${SDKCONFIG_HEADER} DIRECTORY) foreach(include ${COMPONENT_INCLUDES}) list(APPEND component_includes -I${include}) @@ -62,7 +62,7 @@ get_filename_component(ULP_LD_SCRIPT ${ULP_LD_TEMPLATE} NAME) add_custom_command(OUTPUT ${ULP_LD_SCRIPT} COMMAND ${CMAKE_C_COMPILER} -E -P -xc -o ${ULP_LD_SCRIPT} ${ULP_PREPROCESSOR_ARGS} ${ULP_LD_TEMPLATE} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS ${ULP_LD_TEMPLATE} + DEPENDS ${ULP_LD_TEMPLATE} ${SDKCONFIG_HEADER} VERBATIM) add_custom_target(${ULP_APP_NAME}_ld_script DEPENDS ${ULP_LD_SCRIPT} diff --git a/components/ulp/project_include.cmake b/components/ulp/project_include.cmake index bb261688ea..27341b93ef 100644 --- a/components/ulp/project_include.cmake +++ b/components/ulp/project_include.cmake @@ -60,7 +60,7 @@ function(ulp_embed_binary app_name s_sources exp_dep_srcs) -DCOMPONENT_DIR=${COMPONENT_DIR} -DCOMPONENT_INCLUDES=$ -DIDF_PATH=${idf_path} - -DSDKCONFIG=${SDKCONFIG_HEADER} + -DSDKCONFIG_HEADER=${SDKCONFIG_HEADER} -DPYTHON=${python} -DULP_COCPU_IS_RISCV=${ULP_IS_RISCV} ${extra_cmake_args} diff --git a/docs/conf_common.py b/docs/conf_common.py index 7358c3bfef..e6b8f18965 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -207,7 +207,7 @@ conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS, 'SOC_DEDICATED_GPIO_SUPPORTED':DEDIC_GPIO_DOCS, 'SOC_SPIRAM_SUPPORTED':SPIRAM_DOCS, 'SOC_PCNT_SUPPORTED':PCNT_DOCS, - 'SOC_DAC_PERIPH_NUM':DAC_DOCS, + 'SOC_DAC_SUPPORTED':DAC_DOCS, 'SOC_TOUCH_SENSOR_NUM':TOUCH_SENSOR_DOCS, 'SOC_ULP_SUPPORTED':ULP_DOCS, 'SOC_RISCV_COPROC_SUPPORTED':RISCV_COPROC_DOCS, diff --git a/docs/en/api-reference/peripherals/index.rst b/docs/en/api-reference/peripherals/index.rst index d218b39636..a10c5763e3 100644 --- a/docs/en/api-reference/peripherals/index.rst +++ b/docs/en/api-reference/peripherals/index.rst @@ -8,7 +8,7 @@ Peripherals API ADC - :SOC_DAC_PERIPH_NUM: DAC + :SOC_DAC_SUPPORTED: DAC General Purpose Timer GPIO (including RTC low power I/O) :SOC_DEDICATED_GPIO_SUPPORTED: Dedicated GPIO diff --git a/docs/idf_extensions/format_idf_target.py b/docs/idf_extensions/format_idf_target.py index 8455cb82ae..6ed598b396 100644 --- a/docs/idf_extensions/format_idf_target.py +++ b/docs/idf_extensions/format_idf_target.py @@ -57,11 +57,11 @@ class StringSubstituter: TRM_EN_URL = {'esp32': 'https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf', 'esp32s2': 'https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf', - 'esp32c3': '#'} + 'esp32c3': 'https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf'} TRM_CN_URL = {'esp32': 'https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_cn.pdf', 'esp32s2': 'https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_cn.pdf', - 'esp32c3': '#'} + 'esp32c3': 'https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_cn.pdf'} RE_PATTERN = re.compile(r'^\s*{IDF_TARGET_(\w+?):(.+?)}', re.MULTILINE) def __init__(self): diff --git a/docs/zh_CN/api-reference/peripherals/index.rst b/docs/zh_CN/api-reference/peripherals/index.rst index c885842ebf..5dd2a718fe 100644 --- a/docs/zh_CN/api-reference/peripherals/index.rst +++ b/docs/zh_CN/api-reference/peripherals/index.rst @@ -7,7 +7,7 @@ :maxdepth: 1 ADC - :SOC_DAC_PERIPH_NUM: DAC + :SOC_DAC_SUPPORTED: DAC 通用定时器 GPIO (包括 RTC 低功耗 I/O) :SOC_DEDICATED_GPIO_SUPPORTED: 专用 GPIO diff --git a/examples/protocols/pppos_client/main/Kconfig.projbuild b/examples/protocols/pppos_client/main/Kconfig.projbuild index f0237c6d98..a7f45c7bd0 100644 --- a/examples/protocols/pppos_client/main/Kconfig.projbuild +++ b/examples/protocols/pppos_client/main/Kconfig.projbuild @@ -54,6 +54,23 @@ menu "Example Configuration" Enter the peer phone number that you want to send message to. endif + config EXAMPLE_UART_ISR_IN_RAM + bool "Use UART ISR in RAM" + default n + select UART_ISR_IN_IRAM + help + Enable placing UART ISR to IRAM. + This options is useful if PPPoS client needs to perform + flash operations (e.g. OTA) while keeping the network operational. + + config EXAMPLE_LCP_ECHO + bool "Enable LCP ECHO" + default n + select LWIP_ENABLE_LCP_ECHO + help + Enable this option to make use of LCP keepalive using + LCP_ECHO_INTERVAL and LCP_MAXECHOFAILS to default values + menu "UART Configuration" config EXAMPLE_MODEM_UART_TX_PIN int "TXD Pin Number" diff --git a/examples/protocols/static_ip/CMakeLists.txt b/examples/protocols/static_ip/CMakeLists.txt new file mode 100644 index 0000000000..a91bebf1fe --- /dev/null +++ b/examples/protocols/static_ip/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(static_ip) diff --git a/examples/protocols/static_ip/Makefile b/examples/protocols/static_ip/Makefile new file mode 100644 index 0000000000..bd2c6fc15a --- /dev/null +++ b/examples/protocols/static_ip/Makefile @@ -0,0 +1,8 @@ +# +# This is a project Makefile. It is assumed the directory this Makefile resides in is a +# project subdirectory. +# + +PROJECT_NAME := static_ip + +include $(IDF_PATH)/make/project.mk diff --git a/examples/protocols/static_ip/README.md b/examples/protocols/static_ip/README.md new file mode 100644 index 0000000000..27abccc27e --- /dev/null +++ b/examples/protocols/static_ip/README.md @@ -0,0 +1,85 @@ +# WiFi station example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + + +## How to use example + +### Configure the project + +``` +idf.py menuconfig +``` + +Set following parameters under Example Configuration Options: + +* Set `WiFi SSID` and `WiFi Password` and `Maximal retry` under Example Configuration Options. + +* Set `Static IP address` of your device static IP. + +* Set `Static netmask address` of your device static netmask address. + +* Set `Static gateway address` of your device static gateway address. + +### Build and Flash + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example Output +Note that the output, in particular the order of the output, may vary depending on the environment. + +Console output if station connects to AP successfully: +``` +I (563) static_ip: ESP_WIFI_MODE_STA +I (573) wifi:wifi driver task: 3ffc1bfc, prio:23, stack:6656, core=0 +I (573) system_api: Base MAC address is not set +I (573) system_api: read default base MAC address from EFUSE +I (603) wifi:wifi firmware version: 6b2834e +I (603) wifi:wifi certification version: v7.0 +I (603) wifi:config NVS flash: enabled +I (603) wifi:config nano formating: disabled +I (613) wifi:Init data frame dynamic rx buffer num: 32 +I (613) wifi:Init management frame dynamic rx buffer num: 32 +I (623) wifi:Init management short buffer num: 32 +I (623) wifi:Init dynamic tx buffer num: 32 +I (633) wifi:Init static rx buffer size: 1600 +I (633) wifi:Init static rx buffer num: 10 +I (643) wifi:Init dynamic rx buffer num: 32 +I (643) wifi_init: rx ba win: 6 +I (643) wifi_init: tcpip mbox: 32 +I (653) wifi_init: udp mbox: 6 +I (653) wifi_init: tcp mbox: 6 +I (653) wifi_init: tcp tx win: 5744 +I (663) wifi_init: tcp rx win: 5744 +I (663) wifi_init: tcp mss: 1440 +I (673) wifi_init: WiFi IRAM OP enabled +I (673) wifi_init: WiFi RX IRAM OP enabled +I (723) phy_init: phy_version 4660,0162888,Dec 23 2020 +W (723) phy_init: failed to load RF calibration data (0xffffffff), falling back to full calibration +I (1093) wifi:mode : sta (4c:11:ae:ea:69:fc) +I (1093) wifi:enable tsf +I (1093) static_ip: wifi_init_sta finished. +I (2313) wifi:new:<11,0>, old:<1,0>, ap:<255,255>, sta:<11,0>, prof:1 +I (3053) wifi:state: init -> auth (b0) +I (3083) wifi:state: auth -> assoc (0) +I (3213) wifi:new:<11,2>, old:<11,0>, ap:<255,255>, sta:<11,2>, prof:1 +I (3213) wifi:state: assoc -> run (10) +I (3233) wifi:connected with myssid, aid = 2, channel 11, 40D, bssid = 34:29:12:43:c5:40 +I (3233) wifi:security: WPA2-PSK, phy: bgn, rssi: -7 +I (3243) wifi:pm start, type: 1 + +I (3253) esp_netif_handlers: sta ip: 192.168.4.2, mask: 255.255.255.0, gw: 192.168.4.1 +I (3253) static_ip: static ip:192.168.4.2 +I (3253) static_ip: connected to ap SSID:myssid password:mypassword +W (3273) wifi:idx:0 (ifx:0, 34:29:12:43:c5:40), tid:5, ssn:2, winSize:64 +I (3303) wifi:AP's beacon interval = 102400 us, DTIM period = 1 +I (3303) wifi:new:<11,0>, old:<11,2>, ap:<255,255>, sta:<11,0>, prof:1 +``` diff --git a/examples/protocols/static_ip/main/CMakeLists.txt b/examples/protocols/static_ip/main/CMakeLists.txt new file mode 100644 index 0000000000..e9d8891a84 --- /dev/null +++ b/examples/protocols/static_ip/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "static_ip_example_main.c" + INCLUDE_DIRS ".") diff --git a/examples/protocols/static_ip/main/Kconfig.projbuild b/examples/protocols/static_ip/main/Kconfig.projbuild new file mode 100644 index 0000000000..7fbda28f6a --- /dev/null +++ b/examples/protocols/static_ip/main/Kconfig.projbuild @@ -0,0 +1,38 @@ +menu "Example Configuration" + + config EXAMPLE_WIFI_SSID + string "WiFi SSID" + default "myssid" + help + SSID (network name) for the example to connect to. + + config EXAMPLE_WIFI_PASSWORD + string "WiFi Password" + default "mypassword" + help + WiFi password (WPA or WPA2) for the example to use. + + config EXAMPLE_MAXIMUM_RETRY + int "Maximum retry" + default 5 + help + Set the Maximum retry to avoid station reconnecting to the AP unlimited when the AP is really inexistent. + + config EXAMPLE_STATIC_IP_ADDR + string "Static IP address" + default "192.168.4.2" + help + Set static IP address. + + config EXAMPLE_STATIC_NETMASK_ADDR + string "Static netmask address" + default "255.255.255.0" + help + Set static netmask address. + + config EXAMPLE_STATIC_GW_ADDR + string "Static gateway address" + default "192.168.4.1" + help + Set static gateway address. +endmenu diff --git a/examples/protocols/static_ip/main/component.mk b/examples/protocols/static_ip/main/component.mk new file mode 100644 index 0000000000..0adf45649a --- /dev/null +++ b/examples/protocols/static_ip/main/component.mk @@ -0,0 +1,8 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# diff --git a/examples/protocols/static_ip/main/static_ip_example_main.c b/examples/protocols/static_ip/main/static_ip_example_main.c new file mode 100644 index 0000000000..2589faa322 --- /dev/null +++ b/examples/protocols/static_ip/main/static_ip_example_main.c @@ -0,0 +1,172 @@ +/* Static IP Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/event_groups.h" +#include "esp_system.h" +#include "esp_wifi.h" +#include "esp_event.h" +#include "esp_log.h" +#include "nvs_flash.h" + +/* The examples use configuration that you can set via project configuration menu + + If you'd rather not, just change the below entries to strings with + the config you want - ie #define EXAMPLE_WIFI_SSID "mywifissid" +*/ +#define EXAMPLE_WIFI_SSID CONFIG_EXAMPLE_WIFI_SSID +#define EXAMPLE_WIFI_PASS CONFIG_EXAMPLE_WIFI_PASSWORD +#define EXAMPLE_MAXIMUM_RETRY CONFIG_EXAMPLE_MAXIMUM_RETRY +#define EXAMPLE_STATIC_IP_ADDR CONFIG_EXAMPLE_STATIC_IP_ADDR +#define EXAMPLE_STATIC_NETMASK_ADDR CONFIG_EXAMPLE_STATIC_NETMASK_ADDR +#define EXAMPLE_STATIC_GW_ADDR CONFIG_EXAMPLE_STATIC_GW_ADDR + +/* FreeRTOS event group to signal when we are connected*/ +static EventGroupHandle_t s_wifi_event_group; + +/* The event group allows multiple bits for each event, but we only care about two events: + * - we are connected to the AP with an IP + * - we failed to connect after the maximum amount of retries */ +#define WIFI_CONNECTED_BIT BIT0 +#define WIFI_FAIL_BIT BIT1 + +static const char *TAG = "static_ip"; + +static int s_retry_num = 0; + +static void example_set_static_ip(esp_netif_t *netif) +{ + if (esp_netif_dhcpc_stop(netif) != ESP_OK) { + ESP_LOGE(TAG, "Failed to stop dhcp client"); + return; + } + esp_netif_ip_info_t ip; + memset(&ip, 0 , sizeof(esp_netif_ip_info_t)); + ip.ip.addr = ipaddr_addr(EXAMPLE_STATIC_IP_ADDR); + ip.netmask.addr = ipaddr_addr(EXAMPLE_STATIC_NETMASK_ADDR); + ip.gw.addr = ipaddr_addr(EXAMPLE_STATIC_GW_ADDR); + if (esp_netif_set_ip_info(netif, &ip) != ESP_OK) { + ESP_LOGE(TAG, "Failed to set ip info"); + return; + } + ESP_LOGD(TAG, "Success to set static ip: %s, netmask: %s, gw: %s", EXAMPLE_STATIC_IP_ADDR, EXAMPLE_STATIC_NETMASK_ADDR, EXAMPLE_STATIC_GW_ADDR); +} + +static void event_handler(void* arg, esp_event_base_t event_base, + int32_t event_id, void* event_data) +{ + if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_START) { + esp_wifi_connect(); + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_CONNECTED) { + example_set_static_ip(arg); + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_DISCONNECTED) { + if (s_retry_num < EXAMPLE_MAXIMUM_RETRY) { + esp_wifi_connect(); + s_retry_num++; + ESP_LOGI(TAG, "retry to connect to the AP"); + } else { + xEventGroupSetBits(s_wifi_event_group, WIFI_FAIL_BIT); + } + ESP_LOGI(TAG,"connect to the AP fail"); + } else if (event_base == IP_EVENT && event_id == IP_EVENT_STA_GOT_IP) { + ip_event_got_ip_t* event = (ip_event_got_ip_t*) event_data; + ESP_LOGI(TAG, "static ip:" IPSTR, IP2STR(&event->ip_info.ip)); + s_retry_num = 0; + xEventGroupSetBits(s_wifi_event_group, WIFI_CONNECTED_BIT); + } +} + +void wifi_init_sta(void) +{ + s_wifi_event_group = xEventGroupCreate(); + + ESP_ERROR_CHECK(esp_netif_init()); + + ESP_ERROR_CHECK(esp_event_loop_create_default()); + + esp_netif_t *sta_netif = esp_netif_create_default_wifi_sta(); + assert(sta_netif); + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_wifi_init(&cfg)); + + esp_event_handler_instance_t instance_any_id; + esp_event_handler_instance_t instance_got_ip; + ESP_ERROR_CHECK(esp_event_handler_instance_register(WIFI_EVENT, + ESP_EVENT_ANY_ID, + &event_handler, + sta_netif, + &instance_any_id)); + ESP_ERROR_CHECK(esp_event_handler_instance_register(IP_EVENT, + IP_EVENT_STA_GOT_IP, + &event_handler, + sta_netif, + &instance_got_ip)); + + wifi_config_t wifi_config = { + .sta = { + .ssid = EXAMPLE_WIFI_SSID, + .password = EXAMPLE_WIFI_PASS, + /* Setting a password implies station will connect to all security modes including WEP/WPA. + * However these modes are deprecated and not advisable to be used. Incase your Access point + * doesn't support WPA2, these mode can be enabled by commenting below line */ + .threshold.authmode = WIFI_AUTH_WPA2_PSK, + + .pmf_cfg = { + .capable = true, + .required = false + }, + }, + }; + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA) ); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config) ); + ESP_ERROR_CHECK(esp_wifi_start() ); + + ESP_LOGI(TAG, "wifi_init_sta finished."); + + /* Waiting until either the connection is established (WIFI_CONNECTED_BIT) or connection failed for the maximum + * number of re-tries (WIFI_FAIL_BIT). The bits are set by event_handler() (see above) */ + EventBits_t bits = xEventGroupWaitBits(s_wifi_event_group, + WIFI_CONNECTED_BIT | WIFI_FAIL_BIT, + pdFALSE, + pdFALSE, + portMAX_DELAY); + + /* xEventGroupWaitBits() returns the bits before the call returned, hence we can test which event actually + * happened. */ + if (bits & WIFI_CONNECTED_BIT) { + ESP_LOGI(TAG, "connected to ap SSID:%s password:%s", + EXAMPLE_WIFI_SSID, EXAMPLE_WIFI_PASS); + } else if (bits & WIFI_FAIL_BIT) { + ESP_LOGI(TAG, "Failed to connect to SSID:%s, password:%s", + EXAMPLE_WIFI_SSID, EXAMPLE_WIFI_PASS); + } else { + ESP_LOGE(TAG, "UNEXPECTED EVENT"); + } + + /* The event will not be processed after unregister */ + ESP_ERROR_CHECK(esp_event_handler_instance_unregister(IP_EVENT, IP_EVENT_STA_GOT_IP, instance_got_ip)); + ESP_ERROR_CHECK(esp_event_handler_instance_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, instance_any_id)); + vEventGroupDelete(s_wifi_event_group); +} + +void app_main(void) +{ + //Initialize NVS + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + ESP_LOGI(TAG, "ESP_WIFI_MODE_STA"); + wifi_init_sta(); +} diff --git a/install.fish b/install.fish index ecbadb046e..6d84017ba6 100755 --- a/install.fish +++ b/install.fish @@ -1,6 +1,6 @@ #!/usr/bin/env fish -set basedir $PWD +set basedir (realpath (dirname (status -f))) set -x IDF_PATH $basedir diff --git a/tools/ci/check_type_comments.py b/tools/ci/check_type_comments.py index 3e415ad95d..4b41405269 100755 --- a/tools/ci/check_type_comments.py +++ b/tools/ci/check_type_comments.py @@ -66,9 +66,6 @@ def check_files(files): # type: (List[str]) -> List[str] if not types_valid(file_name): type_issues.append(file_name) - ignore_list.sort() - updated_list.sort() - if updated_list != ignore_list: with open(IGNORE_LIST_MYPY, 'w') as f: for item in updated_list: diff --git a/tools/ci/mypy_ignore_list.txt b/tools/ci/mypy_ignore_list.txt index 7e21f9292b..ce38e751c5 100644 --- a/tools/ci/mypy_ignore_list.txt +++ b/tools/ci/mypy_ignore_list.txt @@ -240,8 +240,6 @@ tools/idf_py_actions/serial_ext.py tools/idf_py_actions/tools.py tools/idf_py_actions/uf2_ext.py tools/idf_size.py -tools/idf.py -tools/idf_tools.py tools/kconfig_new/confgen.py tools/kconfig_new/confserver.py tools/kconfig_new/esp-windows-curses/setup.py diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index 52631a1005..de7be4d5a7 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -130,9 +130,11 @@ function(__build_init idf_path) # Must be global so as to be accessible from any subdirectory in custom projects. add_library(__idf_build_target STATIC IMPORTED GLOBAL) - set_default(python "python") + # Set the Python path (which may be passed in via -DPYTHON=) and store in a build property + set_default(PYTHON "python") + file(TO_CMAKE_PATH ${PYTHON} PYTHON) + idf_build_set_property(PYTHON ${PYTHON}) - idf_build_set_property(PYTHON ${python}) idf_build_set_property(IDF_PATH ${idf_path}) idf_build_set_property(__PREFIX idf) @@ -273,8 +275,12 @@ function(__build_check_python) message(STATUS "Checking Python dependencies...") execute_process(COMMAND "${python}" "${idf_path}/tools/check_python_dependencies.py" RESULT_VARIABLE result) - if(NOT result EQUAL 0) + if(result EQUAL 1) + # check_python_dependencies returns error code 1 on failure message(FATAL_ERROR "Some Python dependencies must be installed. Check above message for details.") + elseif(NOT result EQUAL 0) + # means check_python_dependencies.py failed to run at all, result should be an error message + message(FATAL_ERROR "Failed to run Python dependency check. Python: ${python}, Error: ${result}") endif() endif() endfunction() diff --git a/tools/cmake/project.cmake b/tools/cmake/project.cmake index 7b993b6801..ee10942650 100644 --- a/tools/cmake/project.cmake +++ b/tools/cmake/project.cmake @@ -6,12 +6,15 @@ cmake_minimum_required(VERSION 3.5) # call. include(${CMAKE_CURRENT_LIST_DIR}/idf.cmake) +# setting PYTHON variable here for compatibility only, new code should use +# idf_build_get_property(variable PYTHON) +idf_build_get_property(PYTHON PYTHON) +if(NOT PYTHON) + message(FATAL_ERROR "Internal error, PYTHON build property not set correctly.") +endif() + +# legacy variable for compatibility set(IDFTOOL ${PYTHON} "${IDF_PATH}/tools/idf.py") -# Internally, the Python interpreter is already set to 'python'. Re-set here -# to be absolutely sure. -set_default(PYTHON "python") -file(TO_CMAKE_PATH ${PYTHON} PYTHON) -idf_build_set_property(PYTHON ${PYTHON}) # On processing, checking Python required modules can be turned off if it was # already checked externally.