feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'feature/esp32_d2wd_support' into 'master'

Browse Source 
ESP32-D2WD support

Support ESP32-D2WD with integrated flash in ESP-IDF.

Includes fix for https://github.com/espressif/esp-idf/issues /521


See merge request !639
This commit is contained in:
Ivan Grokhotkov
2017-04-14 20:57:39 +08:00
parent 4ba62a6b45 b99d5df922
commit 15ec487fde
9 changed files with 90 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
components/esp32/include/rom/efuse.h
View File

@@ -60,15 +60,20 @@ void ets_efuse_program_op(void);
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads.
* @brief Read spi flash pin configuration from Efuse
*
* @param null
*
* @return uint32_t: 0, invalid, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
* @return
* - 0 for default SPI pins.
* - 1 for default HSPI pins.
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
*/
uint32_t ets_efuse_get_spiconfig(void);
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)

34
components/esp32/include/rom/spi_flash.h
View File

@@ -279,25 +279,13 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode, bool legacy);
/**
* @brief Config SPI Flash read mode when Flash is running in some mode.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_master_config_readmode(esp_rom_spiflash_read_mode_t mode);
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
/**
* @brief Config SPI Flash clock divisor.
@@ -524,6 +512,24 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr,
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
/** @brief Enable Quad I/O pin functions
*
* @note Please do not call this function in SDK.
*
* Sets the HD & WP pin functions for Quad I/O modes, based on the
* efuse SPI pin configuration.
*
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
*
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
*
*/

1
components/esp32/ld/esp32.rom.ld
View File

@@ -1537,6 +1537,7 @@ PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );
PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );
PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );
PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );
PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
/*

2
components/esp32/ld/esp32.rom.spiflash.ld
View File

@@ -10,7 +10,7 @@ PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062944 );
PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 ); /* SPIMasterReadModeCnfig */
PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );