feat(cache): supported cache panic on c5

components/esp_system/port/soc/esp32c5/cache_err_int.c

@@ -61,10 +61,12 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
-    /* On the hardware side, start by clearing all the bits reponsible for cache access error */
+    /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
+    /* Enable the fail tracer */
+    cache_ll_l1_enable_fail_tracer(0, true);
 
     /* Enable the interrupts for cache error. */
     ESP_INTR_ENABLE(ETS_CACHEERR_INUM);

components/hal/esp32c5/include/hal/cache_ll.h

@@ -10,6 +10,7 @@
 
 #include <stdbool.h>
 #include "soc/cache_reg.h"
+#include "soc/cache_struct.h"
 #include "soc/ext_mem_defs.h"
 #include "rom/cache.h"
 #include "hal/cache_types.h"
@@ -24,9 +25,6 @@ extern "C" {
 #define CACHE_LL_DEFAULT_IBUS_MASK                  CACHE_BUS_IBUS0
 #define CACHE_LL_DEFAULT_DBUS_MASK                  CACHE_BUS_DBUS0
 
-#define CACHE_LL_L1_ACCESS_EVENT_MASK               (1<<4)
-#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL         (1<<4)
-
 #define CACHE_LL_ID_ALL                             1   //All of the caches in a type and level, make this value greater than any ID
 #define CACHE_LL_LEVEL_INT_MEM                      0   //Cache level for accessing internal mem
 #define CACHE_LL_LEVEL_EXT_MEM                      1   //Cache level for accessing external mem
@@ -34,6 +32,9 @@ extern "C" {
 #define CACHE_LL_LEVEL_NUMS                         1   //Number of cache levels
 #define CACHE_LL_L1_ICACHE_AUTOLOAD                 (1<<0)
 
+#define CACHE_LL_L1_ACCESS_EVENT_MASK               (0x1f)
+
+
 /**
  * @brief Check if Cache auto preload is enabled or not.
  *
@@ -290,45 +291,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
     return valid;
 }
 
+/**
+ * Enable the Cache fail tracer
+ *
+ * @param cache_id    cache ID
+ * @param en          enable / disable
+ */
+static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
+{
+    CACHE.trace_ena.l1_cache_trace_ena = en;
+}
+
 /*------------------------------------------------------------------------------
  * Interrupt
  *----------------------------------------------------------------------------*/
 /**
  * @brief Enable Cache access error interrupt
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  */
 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    // TODO: [ESP32C5] IDF-8646 (inherit from C6)
+    CACHE.l1_cache_acs_fail_int_ena.val |= mask;
-    SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
 }
 
 /**
  * @brief Clear Cache access error interrupt status
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  */
 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    // TODO: [ESP32C5] IDF-8646 (inherit from C6)
+    CACHE.l1_cache_acs_fail_int_clr.val = mask;
-    SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
 }
 
 /**
  * @brief Get Cache access error interrupt status
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  *
  * @return            Status mask
  */
 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
 {
-    // TODO: [ESP32C5] IDF-8646 (inherit from C6)
+    return CACHE.l1_cache_acs_fail_int_st.val & mask;
-    return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
 }
 
 #ifdef __cplusplus

components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c

@@ -96,7 +96,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
 #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST"
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#else
 #define CACHE_ERROR_REASON "Cache error,SW_CPU"
 #endif