diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 4fd7ac1757..674f3cfa1a 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -89,6 +89,10 @@ if(NOT BOOTLOADER_BUILD AND NOT esp_tee_build) list(APPEND srcs "i2c_hal.c" "i2c_hal_iram.c") endif() + if(CONFIG_SOC_I3C_MASTER_SUPPORTED) + list(APPEND srcs "i3c_master_hal.c") + endif() + if(CONFIG_SOC_ISP_SUPPORTED) list(APPEND srcs "isp_hal.c") endif() diff --git a/components/hal/esp32p4/include/hal/i3c_master_ll.h b/components/hal/esp32p4/include/hal/i3c_master_ll.h new file mode 100644 index 0000000000..43bab471ea --- /dev/null +++ b/components/hal/esp32p4/include/hal/i3c_master_ll.h @@ -0,0 +1,447 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for I3C register operations + +#pragma once + +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/soc_caps.h" +#include "soc/clk_tree_defs.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "soc/lpperi_struct.h" +#include "hal/misc.h" +#include "soc/i3c_mst_mem_struct.h" +#include "soc/i3c_mst_struct.h" +#include "soc/i3c_mst_reg.h" +#include "hal/i3c_master_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define I3C_LL_GET_HW(num) (((num) == 0) ? (&I3C_MST) : NULL) +#define I3C_LL_MASTER_EVENT_INTR (I3C_MST_TRANSFER_COMPLETE_INT_ENA_M | I3C_MST_COMMAND_DONE_INT_ENA_M | I3C_MST_TX_DATA_BUF_THLD_INT_ENA_M | I3C_MST_RX_DATA_BUF_THLD_INT_ENA_M) +#define I3C_LL_MASTER_FIFO_LENGTH (128) +#define I3C_LL_MASTER_TRANSMIT_EVENT_INTR (I3C_MST_TX_DATA_BUF_THLD_INT_ENA_M | I3C_MST_TRANSFER_COMPLETE_INT_ENA_M | I3C_MST_COMMAND_DONE_INT_ENA_M) +#define I3C_LL_MASTER_RECEIVE_EVENT_INTR (I3C_MST_RX_DATA_BUF_THLD_INT_ENA_M | I3C_MST_TRANSFER_COMPLETE_INT_ENA_M | I3C_MST_COMMAND_DONE_INT_ENA_M) + +typedef enum { + I3C_MASTER_LL_FIFO_WM_LENGTH_2 = 0x0, + I3C_MASTER_LL_FIFO_WM_LENGTH_4 = 0x1, + I3C_MASTER_LL_FIFO_WM_LENGTH_8 = 0x2, + I3C_MASTER_LL_FIFO_WM_LENGTH_16 = 0x3, + I3C_MASTER_LL_FIFO_WM_LENGTH_31 = 0x4, +} i3c_master_ll_fifo_wm_enum_t; + +/** + * @brief Set the clock source for the I3C master + * + * @param hw I3C master hardware instance + * @param src_clk Clock source, (1) for PLL_F160M, (0) for XTAL + */ +static inline void i3c_master_ll_set_source_clk(i3c_mst_dev_t *hw, i3c_master_clock_source_t src_clk) +{ + // src_clk : (1) for PLL_F160M, (0) for XTAL + if (hw == &I3C_MST) { + HP_SYS_CLKRST.peri_clk_ctrl119.reg_i3c_mst_clk_src_sel = (src_clk == I3C_MASTER_CLK_SRC_PLL_F160M) ? 1 : 0; + } else { + HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define i3c_master_ll_set_source_clk(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i3c_master_ll_set_source_clk(__VA_ARGS__);} while(0) + +/** + * @brief Set the device address table for the I3C master + * + * @param hw I3C master hardware instance + * @param addr_table Device address table + * @param device_number Number of devices + */ +static inline void i3c_master_ll_set_address_device_table(i3c_mst_dev_t *hw, i3c_master_address_table_t *addr_table, size_t device_number) +{ + for (int i = 0; i < device_number; i++) { + I3C_MST_MEM.dev_addr_table[i].val = addr_table[i].dat.val; + } +} + +/** + * @brief Enable or disable the bus clock for the I3C master + * + * @param hw I3C master hardware instance + * @param enable Whether to enable the bus clock + */ +static inline void i3c_master_ll_enable_bus_clock(i3c_mst_dev_t *hw, bool enable) +{ + if (hw == &I3C_MST) { + HP_SYS_CLKRST.soc_clk_ctrl2.reg_i3c_mst_apb_clk_en = enable; + } else { + HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define i3c_master_ll_enable_bus_clock(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i3c_master_ll_enable_bus_clock(__VA_ARGS__);} while(0) + +/** + * @brief Enable or disable the clock for the I3C master + * + * @param hw I3C master hardware instance + * @param enable Whether to enable the clock + */ +static inline void i3c_master_ll_enable_controller_clock(i3c_mst_dev_t *hw, bool enable) +{ + if (hw == &I3C_MST) { + HP_SYS_CLKRST.peri_clk_ctrl119.reg_i3c_mst_clk_en = enable; + } else { + HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define i3c_master_ll_enable_controller_clock(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i3c_master_ll_enable_controller_clock(__VA_ARGS__);} while(0) + +/** + * @brief Reset the I3C master registers + * + * @param hw I3C master hardware instance + */ +static inline void i3c_master_ll_reset_register(i3c_mst_dev_t *hw) +{ + if (hw == &I3C_MST) { + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_i3cmst = 1; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_i3cmst = 0; + } else { + HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define i3c_master_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i3c_master_ll_reset_register(__VA_ARGS__);} while(0) + +/** + * @brief Set the command table for the I3C master + * + * @param hw I3C master hardware instance + * @param command_buf Command buffer + * @param command_num Number of commands + */ +static inline void i3c_master_ll_set_command(i3c_mst_dev_t *hw, i3c_master_command_table_t *command_buf, size_t command_num) +{ + for (int i = 0; i < command_num; i++) { + I3C_MST_MEM.command_buf_port.reg_command = command_buf[i].cmd_l.val; + I3C_MST_MEM.command_buf_port.reg_command = command_buf[i].cmd_h.val; + } +} + +/** + * @brief Start a transaction on the I3C master + * + * @param hw I3C master hardware instance + */ +static inline void i3c_master_ll_start_transaction(i3c_mst_dev_t *hw) +{ + hw->device_ctrl.reg_trans_start = 1; + hw->device_ctrl.reg_trans_start = 0; +} + +/** + * @brief Set the open-drain timing for I3C master + * + * @param hw I3C master hardware instance + * @param clock_source_freq Clock source frequency + * @param scl_freq SCL frequency + */ +static inline void i3c_master_ll_set_i3c_open_drain_timing(i3c_mst_dev_t *hw, uint32_t clock_source_freq, uint32_t scl_freq) +{ + uint32_t period_cnt = clock_source_freq / scl_freq / 2; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i3c_mst_od_time, reg_i3c_mst_od_high_period, (period_cnt - 1)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i3c_mst_od_time, reg_i3c_mst_od_low_period, (period_cnt - 1)); +} + +/** + * @brief Set the fast mode timing for I2C master + * + * @param hw I3C master hardware instance + * @param clock_source_freq Clock source frequency + * @param scl_freq SCL frequency + */ +static inline void i3c_master_ll_set_i2c_fast_mode_timing(i3c_mst_dev_t *hw, uint32_t clock_source_freq, uint32_t scl_freq) +{ + uint32_t period_cnt = clock_source_freq / scl_freq / 2; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i2c_fm_time, reg_i2c_fm_high_period, (period_cnt - 1)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i2c_fm_time, reg_i2c_fm_low_period, (period_cnt - 1)); +} + +/** + * @brief Set the push-pull timing for I3C master + * + * @param hw I3C master hardware instance + * @param clock_source_freq Clock source frequency + * @param scl_freq SCL frequency + */ +static inline void i3c_master_ll_set_i3c_push_pull_timing(i3c_mst_dev_t *hw, uint32_t clock_source_freq, uint32_t scl_freq) +{ + uint32_t period_cnt = clock_source_freq / scl_freq / 2; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i3c_mst_pp_time, reg_i3c_mst_pp_high_period, (period_cnt - 1)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->scl_i3c_mst_pp_time, reg_i3c_mst_pp_low_period, (period_cnt - 1)); +} + +/** + * @brief Set the restart setup time for I3C master + * + * @param hw I3C master hardware instance + * @param time_ns Time in nanoseconds + * @param clock_source_period_ns Clock source period in nanoseconds + */ +static inline void i3c_master_ll_set_restart_setup_time(i3c_mst_dev_t *hw, uint32_t time_ns, uint32_t clock_source_period_ns) +{ + hw->scl_rstart_setup.reg_scl_rstart_setup_time = (time_ns + clock_source_period_ns) / clock_source_period_ns; +} + +/** + * @brief Set the start hold time for I3C master + * + * @param hw I3C master hardware instance + * @param time_ns Time in nanoseconds + * @param clock_source_period_ns Clock source period in nanoseconds + */ +static inline void i3c_master_ll_set_start_hold_time(i3c_mst_dev_t *hw, uint32_t time_ns, uint32_t clock_source_period_ns) +{ + hw->scl_start_hold.reg_scl_start_hold_time = time_ns / clock_source_period_ns + 1; +} + +/** + * @brief Set the stop hold time for I3C master + * + * @param hw I3C master hardware instance + * @param time_ns Time in nanoseconds + * @param clock_source_period_ns Clock source period in nanoseconds + */ +static inline void i3c_master_ll_set_stop_hold_time(i3c_mst_dev_t *hw, uint32_t time_ns, uint32_t clock_source_period_ns) +{ + hw->scl_stop_hold.reg_scl_stop_hold_time = time_ns / clock_source_period_ns + 1; +} + +/** + * @brief Set the stop setup time for I3C master + * + * @param hw I3C master hardware instance + * @param time_ns Time in nanoseconds + * @param clock_source_period_ns Clock source period in nanoseconds + */ +static inline void i3c_master_ll_set_stop_setup_time(i3c_mst_dev_t *hw, uint32_t time_ns, uint32_t clock_source_period_ns) +{ + hw->scl_stop_setup.reg_scl_stop_setup_time = (time_ns + clock_source_period_ns) / clock_source_period_ns; +} + +/** + * @brief Get the data byte count from the I3C master + * + * @param hw I3C master hardware instance + * @param count Pointer to store the data byte count + */ +static inline void i3c_master_ll_get_data_byte_count(i3c_mst_dev_t *hw, uint32_t *count) +{ + *count = I3C_MST.present_state1.data_byte_cnt; +} + +/** + * @brief Read data from the RX port of the I3C master + * + * @param hw I3C master hardware instance + * @param data Pointer to store the read data + * @param length Length of data to read + */ +static inline void i3c_master_ll_read_rx_port(i3c_mst_dev_t *hw, uint8_t *data, size_t length) +{ + uint32_t data_word = 0; + int x = 0; + uint32_t *data_u32 = (uint32_t *)data; + for (x = 0; x < (int)length / 4; x++) { + data_u32[x] = I3C_MST_MEM.rx_data_port.rx_data_port; + } + if (length % 4) { + data_word = I3C_MST_MEM.rx_data_port.rx_data_port; + for (int i = 0; i < length % 4; i++) { + data[x * 4 + i] = (data_word >> 8 * i) & 0xFF; + } + } +} + +/** + * @brief Write data to the TX port of the I3C master + * + * @param hw I3C master hardware instance + * @param data Pointer to the data to write + * @param length Length of data to write + */ +__attribute__((always_inline)) +static inline void i3c_master_ll_write_tx_port(i3c_mst_dev_t *hw, const uint8_t *data, size_t length) +{ + int x = 0; + uint32_t data_word = 0; + const uint32_t *data_u32 = (const uint32_t *)data; + for (x = 0; x < (int)length / 4; x++) { + I3C_MST_MEM.tx_data_port.reg_tx_data_port = data_u32[x]; + } + + if (length % 4) { + data_word = 0; + for (int i = 0; i < length % 4; i++) { + data_word |= (data[x * 4 + i] << 8 * i); + } + I3C_MST_MEM.tx_data_port.reg_tx_data_port = data_word; + } +} + +/** + * @brief Get the interrupt status register of the I3C master + * + * @param dev I3C master hardware instance + * @return Pointer to the interrupt status register + */ +static inline volatile void *i3c_master_ll_get_interrupt_status_reg(i3c_mst_dev_t *dev) +{ + return &dev->int_st; +} + +/** + * @brief Clear the interrupt mask for the I3C master + * + * @param dev I3C master hardware instance + * @param mask Interrupt mask to clear + */ +__attribute__((always_inline)) +static inline void i3c_master_ll_clear_intr_mask(i3c_mst_dev_t *dev, uint32_t mask) +{ + dev->int_clr.val = mask; +} + +/** + * @brief Enable the interrupt mask for the I3C master + * + * @param dev I3C master hardware instance + * @param mask Interrupt mask to enable + */ +__attribute__((always_inline)) +static inline void i3c_master_ll_enable_intr_mask(i3c_mst_dev_t *dev, uint32_t mask) +{ + dev->int_st_ena.val |= mask; +} + +/** + * @brief Disable the interrupt mask for the I3C master + * + * @param dev I3C master hardware instance + * @param mask Interrupt mask to disable + */ +__attribute__((always_inline)) +static inline void i3c_master_ll_disable_intr_mask(i3c_mst_dev_t *dev, uint32_t mask) +{ + dev->int_st_ena.val &= (~mask); +} + +/** + * @brief Get the interrupt mask status for the I3C master + * + * @param dev I3C master hardware instance + * @param intr_status Pointer to store the interrupt status + */ +__attribute__((always_inline)) +static inline void i3c_master_ll_get_intr_mask(i3c_mst_dev_t *dev, uint32_t *intr_status) +{ + *intr_status = dev->int_st.val; +} + +/** + * @brief Get the TX FIFO empty count for the I3C master + * + * @param dev I3C master hardware instance + * @return TX FIFO empty count + */ +static inline uint8_t i3c_master_ll_get_tx_fifo_empty_count(i3c_mst_dev_t *dev) +{ + return dev->data_buffer_status_level.tx_data_buf_empty_cnt; +} + +/** + * @brief Get the RX FIFO full count for the I3C master + * + * @param dev I3C master hardware instance + * @return RX FIFO full count + */ +static inline uint8_t i3c_master_ll_get_rx_fifo_full_count(i3c_mst_dev_t *dev) +{ + return dev->data_buffer_status_level.rx_data_buf_cnt; +} + +/** + * @brief Set the TX data FIFO watermark threshold for the I3C master + * + * @param dev I3C master hardware instance + * @param fifo_wm FIFO watermark threshold + */ +static inline void i3c_master_ll_set_tx_data_fifo_wm_threshold(i3c_mst_dev_t *dev, i3c_master_ll_fifo_wm_enum_t fifo_wm) +{ + dev->data_buffer_thld_ctrl.reg_tx_data_buf_thld = fifo_wm; +} + +/** + * @brief Set the RX data FIFO watermark threshold for the I3C master + * + * @param dev I3C master hardware instance + * @param fifo_wm FIFO watermark threshold + */ +static inline void i3c_master_ll_set_rx_data_fifo_wm_threshold(i3c_mst_dev_t *dev, i3c_master_ll_fifo_wm_enum_t fifo_wm) +{ + dev->data_buffer_thld_ctrl.reg_rx_data_buf_thld = fifo_wm; +} + +/** + * @brief Enable or disable TX by DMA for the I3C master + * + * @param dev I3C master hardware instance + * @param enable Whether to enable TX by DMA + */ +static inline void i3c_master_ll_enable_tx_by_dma(i3c_mst_dev_t *dev, bool enable) +{ + dev->device_ctrl.reg_dma_tx_en = enable; +} + +/** + * @brief Enable or disable RX by DMA for the I3C master + * + * @param dev I3C master hardware instance + * @param enable Whether to enable RX by DMA + */ +static inline void i3c_master_ll_enable_rx_by_dma(i3c_mst_dev_t *dev, bool enable) +{ + dev->device_ctrl.reg_dma_rx_en = enable; +} + +/** + * @brief Get the response buffer value from the I3C master + * + * @param dev I3C master hardware instance + * @return Response buffer value + */ +static inline uint32_t i3c_master_ll_get_response_buffer_value(i3c_mst_dev_t *dev) +{ + return I3C_MST_MEM.response_buf_port.response; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/i3c_master_hal.c b/components/hal/i3c_master_hal.c new file mode 100644 index 0000000000..4f1bebf889 --- /dev/null +++ b/components/hal/i3c_master_hal.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "hal/i3c_master_hal.h" +#include "hal/i3c_master_ll.h" +#include "hal/i3c_master_types.h" + +void i3c_master_hal_init(i3c_master_hal_context_t *hal, int i3c_port) +{ + if (hal->dev == NULL) { + hal->dev = I3C_LL_GET_HW(i3c_port); + } +} + +void i3c_master_hal_deinit(i3c_master_hal_context_t *hal) +{ + hal->dev = NULL; +} diff --git a/components/hal/include/hal/i3c_master_hal.h b/components/hal/include/hal/i3c_master_hal.h new file mode 100644 index 0000000000..cfdf1fae09 --- /dev/null +++ b/components/hal/include/hal/i3c_master_hal.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/readme.md + ******************************************************************************/ + +// The HAL layer for I3C master + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_I3C_MASTER_SUPPORTED +#include "hal/i3c_master_types.h" +#include "hal/i3c_master_ll.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_I3C_MASTER_SUPPORTED + +typedef struct i3c_mst_dev_t *i3c_master_soc_handle_t; // I3C master SOC layer handle + +/** + * @brief I3C master hal Context definition + */ +typedef struct { + i3c_master_soc_handle_t dev; +} i3c_master_hal_context_t; + +/** + * @brief Initialize the I3C master HAL context + * + * @param hal HAL context + * @param i3c_port I3C port number + */ +void i3c_master_hal_init(i3c_master_hal_context_t *hal, int i3c_port); + +/** + * @brief Deinitialize the I3C master HAL context + * + * @param hal HAL context + */ +void i3c_master_hal_deinit(i3c_master_hal_context_t *hal); + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/i3c_master_types.h b/components/hal/include/hal/i3c_master_types.h new file mode 100644 index 0000000000..a6a208e400 --- /dev/null +++ b/components/hal/include/hal/i3c_master_types.h @@ -0,0 +1,257 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/soc_caps.h" +#include "soc/clk_tree_defs.h" +#include "hal/hal_utils.h" + +/** + * @brief I3C Master Command Table Entry + * + * This structure represents a command entry for the I3C master. It is used + * to define and execute different types of I3C commands, including address + * assignment, immediate commands, and regular transfers. Each entry consists + * of two parts: the low part (`cmd_l`) and the high part (`cmd_h`). + */ +typedef struct { + /** + * @brief Command Low Part (cmd_l) + * + * This union defines the command attributes for different types of I3C commands. + */ + union { + /** + * @brief Address Assignment Command + * + * Used for dynamically assigning addresses to devices on the I3C bus. + */ + struct { + uint32_t cmd_attr : 3; ///< Command type (0: regular, 1: immediate, 2: address assignment). + uint32_t tid : 4; ///< Transaction ID, used as an identification tag for this command. The same value shall be reflected in the Response Descriptor + uint32_t cmd : 8; ///< Transfer Command CCC value, specifies CCC code. + uint32_t reserved15 : 1; ///< Reserved bit. + uint32_t dev_indx : 5; ///< Indicates the DAT table index for the slave device being addressed with the transfer. Static and Device addressing related information will be stored to this index in the DAT. This field is reserved in Broadcast CCC transfer. + uint32_t reserved21 : 5; ///< Reserved bits. + uint32_t dev_cnt : 4; ///< Indicates the number of devices to which Dynamic Address shall be assigned. + uint32_t roc : 1; ///< Response on Completion, controls whether the response status is sent after the successful completion of the transfer command. (0: Respond status is not required, 1: Respond status is required). + uint32_t toc : 1; ///< Terminate on Completion, controls what bus condition to issue after the transfer command completes. (0: Issue repeated start at the end of transfer. 1: Issue Stop (P) at the end of transfer Note: This field must be set to 1 for ENTDAA. It is meaningful for SETDASA transfer) + } addr; ///< Address assignment command format. + + /** + * @brief Immediate Command + * + * Executes a command with immediate effect, typically for control or configuration purposes. + */ + struct { + uint32_t cmd_attr : 3; ///< Command type (0: regular, 1: immediate, 2: address assignment). + uint32_t tid : 4; ///< Transaction ID, used as an identification tag for this command. The same value shall be reflected in the Response Descriptor + uint32_t cmd : 8; ///< Transfer Command CCC value, specifies CCC code. + uint32_t cp : 1; ///< Command Present, indicates whether the CMD field is valid for CCC transfer + uint32_t dev_indx : 5; ///< Indicates the DAT table index for the slave device being addressed with the transfer. Static and Device addressing related information will be stored to this index in the DAT. This field is reserved in Broadcast CCC transfer. + uint32_t reserved21 : 2; ///< Reserved bits. + uint32_t bc : 3; ///< Byte count (number of bytes transferred in command_h). + uint32_t mode : 3; ///< Data Transfer Speed and Mode. Set the mode and speed for the I3C or I2C transfer. Interpretation of this field depends on whether the Device is in I3C Mode vs. I2C Mode (see the DEVICE field in the DAT Table entry indexed by field DEV_INDEX). + uint32_t rnw : 1; ///< Identifies the direction of this transfer (1: read, 0: write). + uint32_t roc : 1; ///< Response on Completion, controls whether the response status is sent after the successful completion of the transfer command. (0: Respond status is not required, 1: Respond status is required). + uint32_t toc : 1; ///< Terminate on Completion, controls what bus condition to issue after the transfer command completes. (0: Issue repeated start at the end of transfer. 1: Issue Stop (P) at the end of transfer Note: This field must be set to 1 for ENTDAA. It is meaningful for SETDASA transfer) + } immediate; ///< Immediate command format. + + /** + * @brief Regular Transfer Command + * + * Used for standard data transfers on the I3C bus. + */ + struct { + uint32_t cmd_attr : 3; ///< Command type (0: regular, 1: immediate, 2: address assignment). + uint32_t tid : 4; ///< Transaction ID, used as an identification tag for this command. The same value shall be reflected in the Response Descriptor + uint32_t cmd : 8; ///< Transfer Command CCC value, specifies CCC code. + uint32_t cp : 1; ///< Command Present, indicates whether the CMD field is valid for CCC transfer + uint32_t dev_indx : 5; ///< Indicates the DAT table index for the slave device being addressed with the transfer. Static and Device addressing related information will be stored to this index in the DAT. This field is reserved in Broadcast CCC transfer. + uint32_t reserved21 : 5; ///< Reserved bits. + uint32_t mode : 3; ///< Data Transfer Speed and Mode. Set the mode and speed for the I3C or I2C transfer. Interpretation of this field depends on whether the Device is in I3C Mode vs. I2C Mode (see the DEVICE field in the DAT Table entry indexed by field DEV_INDEX). + uint32_t rnw : 1; ///< Identifies the direction of this transfer (1: read, 0: write). + uint32_t roc : 1; ///< Response on Completion, controls whether the response status is sent after the successful completion of the transfer command. (0: Respond status is not required, 1: Respond status is required). + uint32_t toc : 1; ///< Terminate on Completion, controls what bus condition to issue after the transfer command completes. (0: Issue repeated start at the end of transfer. 1: Issue Stop (P) at the end of transfer Note: This field must be set to 1 for ENTDAA. It is meaningful for SETDASA transfer) + } regular; ///< Regular transfer command format. + + /** + * @brief Raw Value Access + * + * Provides direct access to the 32-bit value of the command. + */ + uint32_t val; ///< Raw 32-bit value of the command. + } cmd_l; ///< Low part of the command. + + /** + * @brief Command High Part (cmd_h) + * + * This union defines additional attributes for different types of I3C commands. + */ + union { + /** + * @brief Address Assignment Command High Part + * + * No additional data for address assignment commands. + */ + struct { + uint32_t reserved0 : 32; ///< Reserved bits. + } addr; + + /** + * @brief Immediate Command High Part + * + * Provides up to four bytes of data for the immediate command. + */ + struct { + uint32_t byte1 : 8; ///< First byte of data. + uint32_t byte2 : 8; ///< Second byte of data. + uint32_t byte3 : 8; ///< Third byte of data. + uint32_t byte4 : 8; ///< Fourth byte of data. + } immediate; + + /** + * @brief Regular Transfer Command High Part + * + * Defines the data length for regular transfer commands. + */ + struct { + uint32_t reserved0 : 16; ///< Reserved bits. + uint32_t dl : 16; ///< Data length (number of bytes to transfer). + } regular; + + /** + * @brief Raw Value Access + * + * Provides direct access to the 32-bit value of the high part of the command. + */ + uint32_t val; ///< Raw 32-bit value of the high part of the command. + } cmd_h; ///< High part of the command. +} i3c_master_command_table_t; + +/** + * @brief I3C Master Address Table Entry + * + * This structure represents a single entry in the I3C master address table. + * It is used to store and manage the static and dynamic addresses of devices + * on the I3C bus in different modes, such as SETDASA, ENTDAA, or I2C compatibility. + */ +typedef struct { + union { + /** + * @brief SETDASA Mode + * + * The SETDASA (Set Dynamic Address from Static Address) mode is used + * to assign a dynamic address to a device based on its static address. + */ + struct { + uint32_t static_addr : 7; ///< Static Address of the I3C Target. + uint32_t reserved7 : 9; ///< Reserved bits. + uint32_t dynamic_addr : 8; ///< If used for address assignment by SETDASA CCC, it is the Dynamic Address to be assigned to the I3C device with Static Address. For other transfer, the Dynamic Address is used as the targets’ address. + uint32_t reserved24 : 5; ///< Reserved bits. + uint32_t d : 2; ///< Device NACK Retry Counter. It decides the number of retry when current transfer nacked. + uint32_t mode : 1; ///< Mode indicator (I3C mode = 0). + } setdasa; + + /** + * @brief ENTDAA Mode + * + * The ENTDAA (Enter Dynamic Address Assignment) mode is used for + * dynamically assigning addresses to devices without requiring a static address. + */ + struct { + uint32_t reserved0 : 16; ///< Reserved bits. + uint32_t dynamic_addr : 7; ///< If used for address assignment by ENTDAA CCC, it is the Dynamic Address to be assigned to the I3C device without Static Address. For other transfer, the Dynamic Address is used as the targets’ address. + uint32_t dyn : 1; ///< Parity Bit of 7-bit Dynamic Address. + uint32_t reserved24 : 5; ///< Reserved bits. + uint32_t d : 2; ///< Device NACK Retry Counter. It decides the number of retry when current transfer nacked. + uint32_t mode : 1; ///< Mode indicator (I3C mode = 0). + } entdaa; + + /** + * @brief I2C Compatibility Mode + * + * This mode is used to represent devices operating in I2C mode. + * Only the static address is relevant in this case. + */ + struct { + uint32_t static_addr : 7; ///< Static address of the I2C device (7-bit). + uint32_t reserved7 : 22; ///< Reserved bits. + uint32_t d : 2; ///< Device NACK Retry Counter. It decides the number of retry when the current transfer is nacked. + uint32_t mode : 1; ///< Mode indicator (I2C mode = 1). + } i2c; + + /** + * @brief Raw Value + * + * This provides direct access to the raw 32-bit value of the entry, + * allowing for low-level manipulation or initialization. + */ + uint32_t val; ///< Raw 32-bit value of the address table entry. + } dat; ///< Union of different mode representations. +} i3c_master_address_table_t; + +/** + * @brief I3C master command types + * + * This enumeration defines the types of commands that the I3C master can issue. + * Each command type corresponds to a specific purpose in the I3C communication protocol. + */ +typedef enum { + I3C_MASTER_REGULAR_COMMAND = 0, ///< I3C master sends regular command + I3C_MASTER_IMMEDIATE_COMMAND = 1, ///< I3C master sends immediate command + I3C_MASTER_ADDRESS_ASSIGNMENT_COMMAND = 2, ///< I3C master assigns address command +} i3c_master_command_type_t; + +/** + * @brief I3C master transfer directions + * + * This enumeration defines the direction of data transfer for I3C master operations. + * The transfer direction specifies whether the master sends data to or receives data from the target device. + */ +typedef enum { + I3C_MASTER_WRITE_TRANSFER = 0, ///< I3C master write direction + I3C_MASTER_READ_TRANSFER = 1, ///< I3C master read direction +} i3c_master_transfer_direction_t; + +/** + * @brief I3C master response data + * + * This union represents the response data structure used by the I3C master. + * It includes fields for data length, transaction ID, and error status. + */ +typedef union { + struct { + uint32_t dl : 16; ///< Data Length + uint32_t reserved16 : 8; + uint32_t tid : 4; ///< Transaction ID, used as an identification tag for this command. The same value shall be reflected in the Response Descriptor + uint32_t err_sts : 4; ///< Error state: A 4-bit field indicating the error state of the transaction. + }; + uint32_t val; +} i3c_master_response_data_t; + +#if SOC_I3C_MASTER_SUPPORTED +/** + * @brief I2C group clock source + */ +typedef soc_periph_i3c_master_clk_src_t i3c_master_clock_source_t; +#else +/** + * @brief default type + */ +typedef int i3c_master_clock_source_t; +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 01ec2bf601..8bdbe3c63d 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -91,6 +91,10 @@ if(CONFIG_SOC_I2C_SUPPORTED) list(APPEND srcs "${target_folder}/i2c_periph.c") endif() +if(CONFIG_SOC_I3C_MASTER_SUPPORTED) + list(APPEND srcs "${target_folder}/i3c_master_periph.c") +endif() + if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED) list(APPEND srcs "${target_folder}/temperature_sensor_periph.c") endif() diff --git a/components/soc/esp32p4/i3c_master_periph.c b/components/soc/esp32p4/i3c_master_periph.c new file mode 100644 index 0000000000..8ce351b59f --- /dev/null +++ b/components/soc/esp32p4/i3c_master_periph.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i3c_master_periph.h" +#include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" + +/* + Bunch of constants for every I3C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i3c_master_signal_conn_t i3c_master_periph_signal[SOC_I3C_MASTER_PERIPH_NUM] = { + { + .sda_out_sig = I3C_MST_SDA_PAD_OUT_IDX, + .sda_in_sig = I3C_MST_SDA_PAD_IN_IDX, + .scl_out_sig = I3C_MST_SCL_PAD_OUT_IDX, + .scl_in_sig = I3C_MST_SCL_PAD_IN_IDX, + .irq = ETS_I3C_MST_INTR_SOURCE, + }, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index a5aabc99bc..750bb294da 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -343,6 +343,10 @@ config SOC_SIMD_INSTRUCTION_SUPPORTED bool default y +config SOC_I3C_MASTER_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y @@ -2135,6 +2139,18 @@ config SOC_LCDCAM_CAM_DATA_WIDTH_MAX int default 16 +config SOC_I3C_MASTER_PERIPH_NUM + bool + default y + +config SOC_I3C_MASTER_ADDRESS_TABLE_NUM + int + default 12 + +config SOC_I3C_MASTER_COMMAND_TABLE_NUM + int + default 12 + config SOC_LP_CORE_SUPPORT_ETM bool default y diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 182f4eb66c..65f704344a 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -736,6 +736,19 @@ typedef enum { TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the default choice */ } soc_periph_temperature_sensor_clk_src_t; +//////////////////////////////////////////////////I3C Master/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I3C master + */ +#define SOC_I3C_MASTER_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M} + +typedef enum { + I3C_MASTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, + I3C_MASTER_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, + I3C_MASTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, +} soc_periph_i3c_master_clk_src_t; + //////////////////////////////////////////////////EMAC PTP/////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 0dbaa89fd5..a294d7495e 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -102,6 +102,7 @@ #define SOC_PM_SUPPORTED 1 #define SOC_BITSCRAMBLER_SUPPORTED 1 #define SOC_SIMD_INSTRUCTION_SUPPORTED 1 +#define SOC_I3C_MASTER_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 @@ -794,6 +795,11 @@ #define SOC_LCDCAM_CAM_PERIPH_NUM (1U) #define SOC_LCDCAM_CAM_DATA_WIDTH_MAX (16U) +/*--------------------------- I3C ---------------------------------*/ +#define SOC_I3C_MASTER_PERIPH_NUM (1) +#define SOC_I3C_MASTER_ADDRESS_TABLE_NUM (12) +#define SOC_I3C_MASTER_COMMAND_TABLE_NUM (12) + /*------------------------------------- ULP CAPS -------------------------------------*/ #define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ #define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */ diff --git a/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h index 77e6c083a0..3f9a7fea3f 100644 --- a/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h +++ b/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -129,408 +129,22 @@ typedef union { uint32_t val; } i3c_mst_mem_ibi_data_buf_reg_t; - -/** Group: I3C DEV ADDR TABLE1 LOC REG */ -/** Type of dev_addr_table1_loc register +/** Group: I3C DEV ADDR TABLEn LOC REG */ +/** Type of dev_addr_tablen_loc register * NA */ typedef union { struct { - /** reg_dat_dev1_static_addr : R/W; bitpos: [6:0]; default: 0; + /** reg_dat_devn_static_addr : R/W; bitpos: [6:0]; default: 0; * NA */ - uint32_t reg_dat_dev1_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev1_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev1_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev1_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev1_nack_retry_cnt:2; - /** reg_dat_dev1_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev1_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table1_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE2 LOC REG */ -/** Type of dev_addr_table2_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev2_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev2_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev2_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev2_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev2_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev2_nack_retry_cnt:2; - /** reg_dat_dev2_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev2_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table2_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE3 LOC REG */ -/** Type of dev_addr_table3_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev3_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev3_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev3_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev3_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev3_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev3_nack_retry_cnt:2; - /** reg_dat_dev3_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev3_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table3_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE4 LOC REG */ -/** Type of dev_addr_table4_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev4_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev4_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev4_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev4_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev4_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev4_nack_retry_cnt:2; - /** reg_dat_dev4_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev4_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table4_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE5 LOC REG */ -/** Type of dev_addr_table5_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev5_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev5_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev5_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev5_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev5_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev5_nack_retry_cnt:2; - /** reg_dat_dev5_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev5_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table5_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE6 LOC REG */ -/** Type of dev_addr_table6_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev6_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev6_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev6_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev6_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev6_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev6_nack_retry_cnt:2; - /** reg_dat_dev6_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev6_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table6_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE7 LOC REG */ -/** Type of dev_addr_table7_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev7_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev7_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev7_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev7_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev7_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev7_nack_retry_cnt:2; - /** reg_dat_dev7_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev7_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table7_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE8 LOC REG */ -/** Type of dev_addr_table8_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev8_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev8_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev8_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev8_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev8_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev8_nack_retry_cnt:2; - /** reg_dat_dev8_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev8_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table8_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE9 LOC REG */ -/** Type of dev_addr_table9_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev9_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev9_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev9_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev9_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev9_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev9_nack_retry_cnt:2; - /** reg_dat_dev9_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev9_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table9_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE10 LOC REG */ -/** Type of dev_addr_table10_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev10_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev10_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev10_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev10_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev10_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev10_nack_retry_cnt:2; - /** reg_dat_dev10_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev10_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table10_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE11 LOC REG */ -/** Type of dev_addr_table11_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev11_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev11_static_addr:7; - uint32_t reserved_7:9; - /** reg_dat_dev11_dynamic_addr : R/W; bitpos: [23:16]; default: 0; - * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with - * parity of dynamic address. - */ - uint32_t reg_dat_dev11_dynamic_addr:8; - uint32_t reserved_24:5; - /** reg_dat_dev11_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; - * This field is used to set the Device NACK Retry count for the particular device. If - * the Device NACK's for the device address, the controller automatically retries the - * same device until this count expires. If the Slave does not ACK for the mentioned - * number of retries, then controller generates an error response and move to the Halt - * state. - */ - uint32_t reg_dat_dev11_nack_retry_cnt:2; - /** reg_dat_dev11_i2c : R/W; bitpos: [31]; default: 0; - * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C - * device. - */ - uint32_t reg_dat_dev11_i2c:1; - }; - uint32_t val; -} i3c_mst_mem_dev_addr_table11_loc_reg_t; - - -/** Group: I3C DEV ADDR TABLE12 LOC REG */ -/** Type of dev_addr_table12_loc register - * NA - */ -typedef union { - struct { - /** reg_dat_dev12_static_addr : R/W; bitpos: [6:0]; default: 0; - * NA - */ - uint32_t reg_dat_dev12_static_addr:7; + uint32_t reg_dat_devn_static_addr:7; uint32_t reserved_7:9; /** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0; * Device Dynamic Address with parity, The MSB,bit[23], should be programmed with * parity of dynamic address. */ - uint32_t reg_dat_dev12_dynamic_addr:8; + uint32_t reg_dat_devn_dynamic_addr:8; uint32_t reserved_24:5; /** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0; * This field is used to set the Device NACK Retry count for the particular device. If @@ -539,736 +153,22 @@ typedef union { * number of retries, then controller generates an error response and move to the Halt * state. */ - uint32_t reg_dat_dev12_nack_retry_cnt:2; + uint32_t reg_dat_devn_nack_retry_cnt:2; /** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0; * Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C * device. */ - uint32_t reg_dat_dev12_i2c:1; + uint32_t reg_dat_devn_i2c:1; }; uint32_t val; -} i3c_mst_mem_dev_addr_table12_loc_reg_t; - - -/** Group: I3C DEV CHAR TABLE1 LOC1 REG */ -/** Type of dev_char_table1_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev1_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev1_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table1_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE1 LOC2 REG */ -/** Type of dev_char_table1_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev1_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev1_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table1_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE1 LOC3 REG */ -/** Type of dev_char_table1_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev1_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev1_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table1_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE1 LOC4 REG */ -/** Type of dev_char_table1_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev1_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev1_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table1_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE2 LOC1 REG */ -/** Type of dev_char_table2_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev2_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev2_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table2_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE2 LOC2 REG */ -/** Type of dev_char_table2_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev2_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev2_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table2_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE2 LOC3 REG */ -/** Type of dev_char_table2_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev2_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev2_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table2_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE2 LOC4 REG */ -/** Type of dev_char_table2_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev2_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev2_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table2_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE3 LOC1 REG */ -/** Type of dev_char_table3_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev3_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev3_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table3_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE3 LOC2 REG */ -/** Type of dev_char_table3_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev3_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev3_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table3_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE3 LOC3 REG */ -/** Type of dev_char_table3_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev3_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev3_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table3_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE3 LOC4 REG */ -/** Type of dev_char_table3_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev3_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev3_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table3_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE4 LOC1 REG */ -/** Type of dev_char_table4_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev4_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev4_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table4_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE4 LOC2 REG */ -/** Type of dev_char_table4_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev4_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev4_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table4_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE4 LOC3 REG */ -/** Type of dev_char_table4_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev4_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev4_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table4_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE4 LOC4 REG */ -/** Type of dev_char_table4_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev4_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev4_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table4_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE5 LOC1 REG */ -/** Type of dev_char_table5_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev5_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev5_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table5_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE5 LOC2 REG */ -/** Type of dev_char_table5_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev5_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev5_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table5_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE5 LOC3 REG */ -/** Type of dev_char_table5_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev5_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev5_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table5_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE5 LOC4 REG */ -/** Type of dev_char_table5_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev5_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev5_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table5_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE6 LOC1 REG */ -/** Type of dev_char_table6_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev6_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev6_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table6_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE6 LOC2 REG */ -/** Type of dev_char_table6_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev6_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev6_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table6_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE6 LOC3 REG */ -/** Type of dev_char_table6_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev6_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev6_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table6_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE6 LOC4 REG */ -/** Type of dev_char_table6_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev6_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev6_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table6_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE7 LOC1 REG */ -/** Type of dev_char_table7_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev7_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev7_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table7_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE7 LOC2 REG */ -/** Type of dev_char_table7_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev7_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev7_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table7_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE7 LOC3 REG */ -/** Type of dev_char_table7_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev7_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev7_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table7_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE7 LOC4 REG */ -/** Type of dev_char_table7_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev7_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev7_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table7_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE8 LOC1 REG */ -/** Type of dev_char_table8_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev8_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev8_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table8_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE8 LOC2 REG */ -/** Type of dev_char_table8_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev8_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev8_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table8_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE8 LOC3 REG */ -/** Type of dev_char_table8_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev8_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev8_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table8_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE8 LOC4 REG */ -/** Type of dev_char_table8_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev8_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev8_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table8_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE9 LOC1 REG */ -/** Type of dev_char_table9_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev9_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev9_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table9_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE9 LOC2 REG */ -/** Type of dev_char_table9_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev9_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev9_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table9_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE9 LOC3 REG */ -/** Type of dev_char_table9_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev9_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev9_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table9_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE9 LOC4 REG */ -/** Type of dev_char_table9_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev9_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev9_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table9_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE10 LOC1 REG */ -/** Type of dev_char_table10_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev10_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev10_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table10_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE10 LOC2 REG */ -/** Type of dev_char_table10_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev10_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev10_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table10_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE10 LOC3 REG */ -/** Type of dev_char_table10_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev10_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev10_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table10_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE10 LOC4 REG */ -/** Type of dev_char_table10_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev10_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev10_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table10_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE11 LOC1 REG */ -/** Type of dev_char_table11_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev11_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev11_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table11_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE11 LOC2 REG */ -/** Type of dev_char_table11_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev11_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev11_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table11_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE11 LOC3 REG */ -/** Type of dev_char_table11_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev11_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev11_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table11_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE11 LOC4 REG */ -/** Type of dev_char_table11_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev11_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev11_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table11_loc4_reg_t; - - -/** Group: I3C DEV CHAR TABLE12 LOC1 REG */ -/** Type of dev_char_table12_loc1 register - * NA - */ -typedef union { - struct { - /** dct_dev12_loc1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev12_loc1:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table12_loc1_reg_t; - - -/** Group: I3C DEV CHAR TABLE12 LOC2 REG */ -/** Type of dev_char_table12_loc2 register - * NA - */ -typedef union { - struct { - /** dct_dev12_loc2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev12_loc2:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table12_loc2_reg_t; - - -/** Group: I3C DEV CHAR TABLE12 LOC3 REG */ -/** Type of dev_char_table12_loc3 register - * NA - */ -typedef union { - struct { - /** dct_dev12_loc3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev12_loc3:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table12_loc3_reg_t; - - -/** Group: I3C DEV CHAR TABLE12 LOC4 REG */ -/** Type of dev_char_table12_loc4 register - * NA - */ -typedef union { - struct { - /** dct_dev12_loc4 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dct_dev12_loc4:32; - }; - uint32_t val; -} i3c_mst_mem_dev_char_table12_loc4_reg_t; - +} i3c_mst_mem_dev_addr_tablen_loc_reg_t; + +typedef struct { + volatile uint32_t loc1; + volatile uint32_t loc2; + volatile uint32_t loc3; + volatile uint32_t loc4; +} i3c_mst_mem_dev_char_tablen_reg_t; typedef struct { uint32_t reserved_000[2]; @@ -1280,69 +180,12 @@ typedef struct { uint32_t reserved_01c[9]; volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf; uint32_t reserved_044[31]; - volatile i3c_mst_mem_dev_addr_table1_loc_reg_t dev_addr_table1_loc; - volatile i3c_mst_mem_dev_addr_table2_loc_reg_t dev_addr_table2_loc; - volatile i3c_mst_mem_dev_addr_table3_loc_reg_t dev_addr_table3_loc; - volatile i3c_mst_mem_dev_addr_table4_loc_reg_t dev_addr_table4_loc; - volatile i3c_mst_mem_dev_addr_table5_loc_reg_t dev_addr_table5_loc; - volatile i3c_mst_mem_dev_addr_table6_loc_reg_t dev_addr_table6_loc; - volatile i3c_mst_mem_dev_addr_table7_loc_reg_t dev_addr_table7_loc; - volatile i3c_mst_mem_dev_addr_table8_loc_reg_t dev_addr_table8_loc; - volatile i3c_mst_mem_dev_addr_table9_loc_reg_t dev_addr_table9_loc; - volatile i3c_mst_mem_dev_addr_table10_loc_reg_t dev_addr_table10_loc; - volatile i3c_mst_mem_dev_addr_table11_loc_reg_t dev_addr_table11_loc; - volatile i3c_mst_mem_dev_addr_table12_loc_reg_t dev_addr_table12_loc; + volatile i3c_mst_mem_dev_addr_tablen_loc_reg_t dev_addr_table[12]; uint32_t reserved_0f0[4]; - volatile i3c_mst_mem_dev_char_table1_loc1_reg_t dev_char_table1_loc1; - volatile i3c_mst_mem_dev_char_table1_loc2_reg_t dev_char_table1_loc2; - volatile i3c_mst_mem_dev_char_table1_loc3_reg_t dev_char_table1_loc3; - volatile i3c_mst_mem_dev_char_table1_loc4_reg_t dev_char_table1_loc4; - volatile i3c_mst_mem_dev_char_table2_loc1_reg_t dev_char_table2_loc1; - volatile i3c_mst_mem_dev_char_table2_loc2_reg_t dev_char_table2_loc2; - volatile i3c_mst_mem_dev_char_table2_loc3_reg_t dev_char_table2_loc3; - volatile i3c_mst_mem_dev_char_table2_loc4_reg_t dev_char_table2_loc4; - volatile i3c_mst_mem_dev_char_table3_loc1_reg_t dev_char_table3_loc1; - volatile i3c_mst_mem_dev_char_table3_loc2_reg_t dev_char_table3_loc2; - volatile i3c_mst_mem_dev_char_table3_loc3_reg_t dev_char_table3_loc3; - volatile i3c_mst_mem_dev_char_table3_loc4_reg_t dev_char_table3_loc4; - volatile i3c_mst_mem_dev_char_table4_loc1_reg_t dev_char_table4_loc1; - volatile i3c_mst_mem_dev_char_table4_loc2_reg_t dev_char_table4_loc2; - volatile i3c_mst_mem_dev_char_table4_loc3_reg_t dev_char_table4_loc3; - volatile i3c_mst_mem_dev_char_table4_loc4_reg_t dev_char_table4_loc4; - volatile i3c_mst_mem_dev_char_table5_loc1_reg_t dev_char_table5_loc1; - volatile i3c_mst_mem_dev_char_table5_loc2_reg_t dev_char_table5_loc2; - volatile i3c_mst_mem_dev_char_table5_loc3_reg_t dev_char_table5_loc3; - volatile i3c_mst_mem_dev_char_table5_loc4_reg_t dev_char_table5_loc4; - volatile i3c_mst_mem_dev_char_table6_loc1_reg_t dev_char_table6_loc1; - volatile i3c_mst_mem_dev_char_table6_loc2_reg_t dev_char_table6_loc2; - volatile i3c_mst_mem_dev_char_table6_loc3_reg_t dev_char_table6_loc3; - volatile i3c_mst_mem_dev_char_table6_loc4_reg_t dev_char_table6_loc4; - volatile i3c_mst_mem_dev_char_table7_loc1_reg_t dev_char_table7_loc1; - volatile i3c_mst_mem_dev_char_table7_loc2_reg_t dev_char_table7_loc2; - volatile i3c_mst_mem_dev_char_table7_loc3_reg_t dev_char_table7_loc3; - volatile i3c_mst_mem_dev_char_table7_loc4_reg_t dev_char_table7_loc4; - volatile i3c_mst_mem_dev_char_table8_loc1_reg_t dev_char_table8_loc1; - volatile i3c_mst_mem_dev_char_table8_loc2_reg_t dev_char_table8_loc2; - volatile i3c_mst_mem_dev_char_table8_loc3_reg_t dev_char_table8_loc3; - volatile i3c_mst_mem_dev_char_table8_loc4_reg_t dev_char_table8_loc4; - volatile i3c_mst_mem_dev_char_table9_loc1_reg_t dev_char_table9_loc1; - volatile i3c_mst_mem_dev_char_table9_loc2_reg_t dev_char_table9_loc2; - volatile i3c_mst_mem_dev_char_table9_loc3_reg_t dev_char_table9_loc3; - volatile i3c_mst_mem_dev_char_table9_loc4_reg_t dev_char_table9_loc4; - volatile i3c_mst_mem_dev_char_table10_loc1_reg_t dev_char_table10_loc1; - volatile i3c_mst_mem_dev_char_table10_loc2_reg_t dev_char_table10_loc2; - volatile i3c_mst_mem_dev_char_table10_loc3_reg_t dev_char_table10_loc3; - volatile i3c_mst_mem_dev_char_table10_loc4_reg_t dev_char_table10_loc4; - volatile i3c_mst_mem_dev_char_table11_loc1_reg_t dev_char_table11_loc1; - volatile i3c_mst_mem_dev_char_table11_loc2_reg_t dev_char_table11_loc2; - volatile i3c_mst_mem_dev_char_table11_loc3_reg_t dev_char_table11_loc3; - volatile i3c_mst_mem_dev_char_table11_loc4_reg_t dev_char_table11_loc4; - volatile i3c_mst_mem_dev_char_table12_loc1_reg_t dev_char_table12_loc1; - volatile i3c_mst_mem_dev_char_table12_loc2_reg_t dev_char_table12_loc2; - volatile i3c_mst_mem_dev_char_table12_loc3_reg_t dev_char_table12_loc3; - volatile i3c_mst_mem_dev_char_table12_loc4_reg_t dev_char_table12_loc4; + volatile i3c_mst_mem_dev_char_tablen_reg_t dev_char_table[12]; } i3c_mst_mem_dev_t; +extern i3c_mst_mem_dev_t I3C_MST_MEM; #ifndef __cplusplus _Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure"); diff --git a/components/soc/esp32p4/register/soc/i3c_mst_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_struct.h index f238d6c892..910690e545 100644 --- a/components/soc/esp32p4/register/soc/i3c_mst_struct.h +++ b/components/soc/esp32p4/register/soc/i3c_mst_struct.h @@ -1128,7 +1128,7 @@ typedef union { } i3c_mst_rnd_eco_high_reg_t; -typedef struct { +typedef struct i3c_mst_dev_t { volatile i3c_mst_device_ctrl_reg_t device_ctrl; uint32_t reserved_004[6]; volatile i3c_mst_buffer_thld_ctrl_reg_t buffer_thld_ctrl; @@ -1172,6 +1172,7 @@ typedef struct { volatile i3c_mst_rnd_eco_high_reg_t rnd_eco_high; } i3c_mst_dev_t; +extern i3c_mst_dev_t I3C_MST; #ifndef __cplusplus _Static_assert(sizeof(i3c_mst_dev_t) == 0xbc, "Invalid size of i3c_mst_dev_t structure"); diff --git a/components/soc/esp32p4/register/soc/i3c_slv_struct.h b/components/soc/esp32p4/register/soc/i3c_slv_struct.h index 7df80af894..68c5d3c75b 100644 --- a/components/soc/esp32p4/register/soc/i3c_slv_struct.h +++ b/components/soc/esp32p4/register/soc/i3c_slv_struct.h @@ -539,6 +539,7 @@ typedef struct { volatile i3c_slv_vendorid_reg_t vendorid; } i3c_slv_dev_t; +extern i3c_slv_dev_t I3C_SLV; #ifndef __cplusplus _Static_assert(sizeof(i3c_slv_dev_t) == 0x78, "Invalid size of i3c_slv_dev_t structure"); diff --git a/components/soc/esp32p4/register/soc/reg_base.h b/components/soc/esp32p4/register/soc/reg_base.h index 1f191164bb..09879e6951 100644 --- a/components/soc/esp32p4/register/soc/reg_base.h +++ b/components/soc/esp32p4/register/soc/reg_base.h @@ -104,6 +104,7 @@ #define DR_REG_TWAI1_BASE (DR_REG_HPPERIPH1_BASE + 0x18000) #define DR_REG_TWAI2_BASE (DR_REG_HPPERIPH1_BASE + 0x19000) #define DR_REG_I3C_MST_BASE (DR_REG_HPPERIPH1_BASE + 0x1A000) +#define DR_REG_I3C_MST_MEM_BASE (DR_REG_I3C_MST_BASE) #define DR_REG_I3C_SLV_BASE (DR_REG_HPPERIPH1_BASE + 0x1B000) #define DR_REG_LCDCAM_BASE (DR_REG_HPPERIPH1_BASE + 0x1C000) #define DR_REG_ADC_BASE (DR_REG_HPPERIPH1_BASE + 0x1E000) diff --git a/components/soc/include/soc/i3c_master_periph.h b/components/soc/include/soc/i3c_master_periph.h new file mode 100644 index 0000000000..7c3ab04d01 --- /dev/null +++ b/components/soc/include/soc/i3c_master_periph.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_I3C_MASTER_SUPPORTED + +typedef struct { + const uint8_t sda_out_sig; + const uint8_t sda_in_sig; + const uint8_t scl_out_sig; + const uint8_t scl_in_sig; + const uint8_t irq; +} i3c_master_signal_conn_t; + +extern const i3c_master_signal_conn_t i3c_master_periph_signal[SOC_I3C_MASTER_PERIPH_NUM]; + +#endif + +#ifdef __cplusplus +} +#endif