Merge branch 'fix/sleep_cpu_mspi_freq_mismatch_issue_p4' into 'master'

mspi: fixed cpu and mspi freq mismatch issue when in dfs/sleep on p4

Closes IDF-12068 and PM-333

See merge request espressif/esp-idf!36499

components/esp_hw_support/CMakeLists.txt

@@ -36,7 +36,8 @@ if(NOT non_os_build)
                      "port/esp_clk_tree_common.c"
                      "dma/esp_dma_utils.c"
                      "dma/gdma_link.c"
-                     "spi_bus_lock.c")
+                     "spi_bus_lock.c"
+                     "clk_utils.c")
     if(CONFIG_SOC_GPSPI_SUPPORTED)
         list(APPEND srcs "spi_share_hw_ctrl.c")
     endif()

components/esp_hw_support/clk_utils.c

@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/param.h>
+#include <inttypes.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "esp_check.h"
+#include "esp_log.h"
+#include "soc/soc_caps.h"
+#include "soc/rtc.h"
+#include "hal/mspi_ll.h"
+#include "hal/clk_tree_ll.h"
+#include "esp_private/mspi_timing_tuning.h"
+#include "esp_private/esp_clk_utils.h"
+
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
+{
+#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+    (void) target_cpu_freq;
+    if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) {
+        mspi_timing_change_speed_mode_cache_safe(true);
+    }
+#elif CONFIG_IDF_TARGET_ESP32P4
+    (void) target_cpu_src_freq;
+    /**
+     * Workaround for ESP32P4,
+     * f_cpu >= f_mspi
+     */
+    if (((target_cpu_freq) < CONFIG_ESPTOOLPY_FLASHFREQ_VAL)
+#if CONFIG_SPIRAM
+        || ((target_cpu_freq) < CONFIG_SPIRAM_SPEED)
+#endif
+    ) {
+        mspi_timing_change_speed_mode_cache_safe(true);
+    }
+#else
+    (void) target_cpu_src_freq;
+    (void) target_cpu_freq;
+#endif
+}
+
+void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
+{
+#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+    (void) target_cpu_freq;
+    if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) {
+        mspi_timing_change_speed_mode_cache_safe(false);
+    }
+#elif CONFIG_IDF_TARGET_ESP32P4
+    (void) target_cpu_src_freq;
+    /**
+     * Workaround for ESP32P4,
+     * f_cpu >= f_mspi
+     */
+    if (((target_cpu_freq) >= CONFIG_ESPTOOLPY_FLASHFREQ_VAL)
+#if CONFIG_SPIRAM
+        && ((target_cpu_freq) >= CONFIG_SPIRAM_SPEED)
+#endif
+    ) {
+        mspi_timing_change_speed_mode_cache_safe(false);
+    }
+#else
+    (void) target_cpu_src_freq;
+    (void) target_cpu_freq;
+#endif
+}
+#endif

components/esp_hw_support/include/esp_private/esp_clk_utils.h

@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+#include "soc/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+/**
+ * @brief Sync MSPI speed mode before CPU frequency switching, only needed when frequency is decreasing.
+ *
+ * @param target_cpu_src_freq   Target clock source frequency for CPU frequency switching
+ * @param target_cpu_freq       CPU frequency switching target frequency
+ */
+void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq);
+
+/**
+ * @brief Sync MSPI speed mode after CPU frequency switching, only needed when frequency is upcreasing.
+ *
+ * @param target_cpu_src_freq Target clock source frequency for CPU frequency switching
+ * @param target_cpu_freq     CPU frequency switching target frequency
+ */
+void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq);
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/linker.lf

@@ -13,6 +13,7 @@ entries:
     cpu: esp_cpu_compare_and_set (noflash)
     esp_memory_utils (noflash)
     rtc_clk (noflash)
+    clk_utils (noflash)
     if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y:
         rtc_init:rtc_vddsdio_get_config (noflash)
         rtc_init:rtc_vddsdio_set_config (noflash)

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -386,23 +386,25 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
     //    the return process, which results in dirty cachelines in L1 Cache again.
     pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0);
 
+    if (!dslp) {
 #if CONFIG_SPIRAM
-    psram_ctrlr_ll_wait_all_transaction_done();
+        psram_ctrlr_ll_wait_all_transaction_done();
 #endif
-    s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
+        s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
-    if (s_mpll_freq_mhz_before_sleep) {
+        if (s_mpll_freq_mhz_before_sleep) {
 #if CONFIG_SPIRAM
-        _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
+            _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
-        _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
+            _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
-        if (!s_pmu_sleep_regdma_backup_enabled) {
+            if (!s_pmu_sleep_regdma_backup_enabled) {
-            // MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
+                // MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
-            // If it's a PD_TOP sleep, psram MSPI core clock will be disabled by REGDMA
+                // If it's a PD_TOP sleep, psram MSPI core clock will be disabled by REGDMA
-            // !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
+                // !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
-            _psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
+                _psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
-            _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
+                _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
+            }
+#endif
+            rtc_clk_mpll_disable();
         }
-#endif
-        rtc_clk_mpll_disable();
     }
 
 
@@ -459,7 +461,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
     // Wait eFuse memory update done.
     while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
 
-    if (s_mpll_freq_mhz_before_sleep) {
+    if (s_mpll_freq_mhz_before_sleep && !dslp) {
         rtc_clk_mpll_enable();
         rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
 #if CONFIG_SPIRAM

components/esp_hw_support/sleep_modes.c

@@ -16,6 +16,7 @@
 #include "esp_memory_utils.h"
 #include "esp_sleep.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/esp_clk_utils.h"
 #include "esp_private/esp_sleep_internal.h"
 #include "esp_private/esp_timer_private.h"
 #include "esp_private/rtc_clk.h"
@@ -79,9 +80,6 @@
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_task_wdt.h"
 #include "esp_private/sar_periph_ctrl.h"
-#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
-#include "esp_private/mspi_timing_tuning.h"
-#endif
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
@@ -94,7 +92,6 @@
 #include "esp_private/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/rtc.h"
-#include "esp_private/mspi_timing_tuning.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
@@ -818,9 +815,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_
     }
 #endif
 
-#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-    // Will switch to XTAL turn down MSPI speed
+    uint32_t xtal_freq = rtc_clk_xtal_freq_get();
-    mspi_timing_change_speed_mode_cache_safe(true);
+    esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(xtal_freq, xtal_freq);
 #endif
 
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
@@ -1121,14 +1118,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_
         }
         misc_modules_wake_prepare(sleep_flags);
     }
-
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+    esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(cpu_freq_config.source_freq_mhz, cpu_freq_config.freq_mhz);
-    if (cpu_freq_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) {
-        // Turn up MSPI speed if switch to PLL
-        mspi_timing_change_speed_mode_cache_safe(false);
-    }
 #endif
-
     // re-enable UART output
     resume_uarts();
     return result ? ESP_ERR_SLEEP_REJECT : ESP_OK;

components/esp_pm/pm_impl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -47,9 +47,7 @@
 #include "esp_private/sleep_gpio.h"
 #include "esp_private/sleep_modem.h"
 #include "esp_private/uart_share_hw_ctrl.h"
-#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+#include "esp_private/esp_clk_utils.h"
-#include "esp_private/mspi_timing_tuning.h"
-#endif
 #include "esp_sleep.h"
 #include "esp_memory_utils.h"
 
@@ -669,16 +667,12 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
         if (switch_down) {
             on_freq_update(old_ticks_per_us, new_ticks_per_us);
         }
-#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-        if (new_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) {
+        esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(new_config.source_freq_mhz, new_config.freq_mhz);
-            rtc_clk_cpu_freq_set_config_fast(&new_config);
+#endif
-            mspi_timing_change_speed_mode_cache_safe(false);
-        } else {
-            mspi_timing_change_speed_mode_cache_safe(true);
-            rtc_clk_cpu_freq_set_config_fast(&new_config);
-        }
-#else
         rtc_clk_cpu_freq_set_config_fast(&new_config);
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+        esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(new_config.source_freq_mhz, new_config.freq_mhz);
 #endif
         if (!switch_down) {
             on_freq_update(old_ticks_per_us, new_ticks_per_us);

components/esp_system/port/esp_system_chip.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,10 +9,11 @@
 #include "esp_cpu.h"
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
+#include "hal/clk_tree_ll.h"
+#include "esp_private/esp_clk_utils.h"
 #include "esp_private/rtc_clk.h"
 #include "esp_private/panic_internal.h"
 #include "esp_private/system_internal.h"
-#include "esp_private/mspi_timing_tuning.h"
 #include "esp_heap_caps.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
@@ -36,15 +37,9 @@ void IRAM_ATTR esp_restart_noos_dig(void)
     }
 
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-    /**
+    uint32_t xtal_freq = clk_ll_xtal_load_freq_mhz();
-     * Turn down MSPI speed
+    esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(xtal_freq, xtal_freq);
-     *
+#endif
-     * We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option.
-     * This function will change clock source to a ROM supported one when system restarts.
-     */
-    mspi_timing_change_speed_mode_cache_safe(true);
-#endif  //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-
     // switch to XTAL (otherwise we will keep running from the PLL)
     rtc_clk_cpu_set_to_default_config();
 

components/hal/esp32c5/include/hal/clk_tree_ll.h

@@ -222,6 +222,8 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(v
     return PCR.sysclk_conf.clk_xtal_freq;
 }
 
+#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz()
+
 /**
  * @brief Get SPLL_CLK frequency
  *

components/hal/esp32c61/include/hal/clk_tree_ll.h

@@ -215,6 +215,8 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(v
     return PCR.sysclk_conf.clk_xtal_freq;
 }
 
+#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz()
+
 /**
  * @brief Get SPLL_CLK frequency
  *

components/spi_flash/esp32p4/Kconfig.flash_freq

@@ -14,3 +14,10 @@ choice ESPTOOLPY_FLASHFREQ
     config ESPTOOLPY_FLASHFREQ_20M
         bool "20 MHz"
 endchoice
+
+config ESPTOOLPY_FLASHFREQ_VAL
+    int
+    default 20 if ESPTOOLPY_FLASHFREQ_20M
+    default 40 if ESPTOOLPY_FLASHFREQ_40M
+    default 80 if ESPTOOLPY_FLASHFREQ_80M
+    default 120 if ESPTOOLPY_FLASHFREQ_120M