From 1b3680eff3c8bf2ff7a89f4c415e477e63c752f5 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 11 Apr 2025 20:51:48 +0800 Subject: [PATCH] feat(rtc_time): support rtc time for esp32c61 --- .../esp_rom/esp32c5/include/esp32c5/rom/rtc.h | 3 +-- .../esp32c61/include/esp32c61/rom/rtc.h | 19 +++++++++++++------ .../hal/esp32c61/include/hal/clk_tree_ll.h | 7 +++---- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h index 07c8a166bf..3c5d3750b8 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h @@ -46,7 +46,7 @@ extern "C" { * LP_AON_STORE1_REG RTC_SLOW_CLK calibration value * LP_AON_STORE2_REG Boot time, low word * LP_AON_STORE3_REG Boot time, high word - * LP_AON_STORE4_REG External XTAL frequency + * LP_AON_STORE4_REG Status of whether to disable LOG from ROM at bit[0] * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY * LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC @@ -58,7 +58,6 @@ extern "C" { #define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG #define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG -#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG #define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h index f5b32abb40..a9f62e86a9 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,27 +43,34 @@ extern "C" { * ************************************************************************************* * RTC store registers usage - * LP_AON_STORE0_REG Reserved + * LP_AON_STORE0_REG RTC fix us, high 32 bits * LP_AON_STORE1_REG RTC_SLOW_CLK calibration value * LP_AON_STORE2_REG Boot time, low word * LP_AON_STORE3_REG Boot time, high word - * LP_AON_STORE4_REG External XTAL frequency + * LP_AON_STORE4_REG Status of whether to disable LOG from ROM at bit[0] * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY - * LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC + * LP_AON_STORE7_REG RTC fix us, low 32 bits * LP_AON_STORE8_REG Store light sleep wake stub addr * LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) ************************************************************************************* + * + * Since esp32c61 does not support RTC mem, so use LP_AON store regs to record rtc time: + * + * |------------------------|----------------------------------------| + * | LP_AON_STORE0_REG | LP_AON_STORE7_REG | + * | rtc_fix_us(MSB) | rtc_fix_us(LSB) | + * |------------------------|----------------------------------------| */ +#define RTC_FIX_US_HIGH_REG LP_AON_STORE0_REG #define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG #define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG -#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG #define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG -#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define RTC_FIX_US_LOW_REG LP_AON_STORE7_REG #define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG #define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG diff --git a/components/hal/esp32c61/include/hal/clk_tree_ll.h b/components/hal/esp32c61/include/hal/clk_tree_ll.h index e6eb4f6818..6b1d68d49c 100644 --- a/components/hal/esp32c61/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c61/include/hal/clk_tree_ll.h @@ -556,8 +556,8 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v */ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) { - // TODO IDF-11022 - return; + REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us); + REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32); } /** @@ -567,8 +567,7 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_ */ static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) { - // TODO IDF-11022 - return 0; + return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32); } #ifdef __cplusplus