diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
index 55f28f0330..1ff2f58465 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,7 +21,6 @@
 spi_flash_disable_cache = 0x400001f0;
 spi_flash_restore_cache = 0x400001f4;
 spi_flash_cache_enabled = 0x400001f8;
-spi_flash_enable_cache = 0x400001fc;
 esp_enable_cache_flash_wrap = 0x40000200;
 
 
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
index d78287eb6c..834ef2afb8 100644
--- a/components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
+++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,7 +21,6 @@
 spi_flash_disable_cache = 0x400001e8;
 spi_flash_restore_cache = 0x400001ec;
 spi_flash_cache_enabled = 0x400001f0;
-spi_flash_enable_cache = 0x400001f4;
 esp_enable_cache_flash_wrap = 0x400001f8;
 
 
diff --git a/components/spi_flash/test/test_cache_disabled.c b/components/spi_flash/test/test_cache_disabled.c
index 6025f7ad37..5ca6f3c2b3 100644
--- a/components/spi_flash/test/test_cache_disabled.c
+++ b/components/spi_flash/test/test_cache_disabled.c
@@ -62,10 +62,6 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
 
-#define C6_H2_ROM_IMPL    (CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2))
-
-#if !C6_H2_ROM_IMPL
-//TODO: IDF-6931
 
 // This needs to sufficiently large array, otherwise it may end up in
 // DRAM (e.g. size <= 8 bytes && ARCH == RISCV)
@@ -104,7 +100,6 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="
     xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
     vTaskDelay(1000/portTICK_PERIOD_MS);
 }
-#endif  //#if !C6_H2_ROM_IMPL
 
 #ifndef CONFIG_FREERTOS_UNICORE