diff --git a/components/soc/esp32p4/include/soc/h264_dma_struct.h b/components/soc/esp32p4/include/soc/h264_dma_struct.h index bbc704f034..8153929570 100644 --- a/components/soc/esp32p4/include/soc/h264_dma_struct.h +++ b/components/soc/esp32p4/include/soc/h264_dma_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,852 +10,170 @@ extern "C" { #endif -/** Group: Configuration Registers */ -/** Type of out_conf0_ch0 register - * TX CH0 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch0:1; - /** out_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch0:1; - /** out_check_owner_ch0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch0:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch0:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch0:1; - uint32_t reserved_13:3; - /** out_reorder_en_ch0 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t out_reorder_en_ch0:1; - uint32_t reserved_17:7; - /** out_rst_ch0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch0:1; - /** out_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch0:1; - /** out_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch0:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch0_reg_t; -/** Type of out_push_ch0 register - * TX CH0 outfifo push register +/** Type of out_push register + * TX CHn outfifo push register */ typedef union { struct { - /** outfifo_wdata_ch0 : R/W; bitpos: [9:0]; default: 0; + /** outfifo_wdata : R/W; bitpos: [9:0]; default: 0; * This register stores the data that need to be pushed into DMA Tx FIFO. */ - uint32_t outfifo_wdata_ch0:10; - /** outfifo_push_ch0 : R/W/SC; bitpos: [10]; default: 0; + uint32_t outfifo_wdata:10; + /** outfifo_push : R/W/SC; bitpos: [10]; default: 0; * Set this bit to push data into DMA Tx FIFO. */ - uint32_t outfifo_push_ch0:1; + uint32_t outfifo_push:1; uint32_t reserved_11:21; }; uint32_t val; -} h264_dma_out_push_ch0_reg_t; +} h264_dma_out_push_chn_reg_t; -/** Type of out_link_conf_ch0 register - * TX CH0 out_link dscr ctrl register +/** Type of out_link_conf register + * TX CHn out_link dscr ctrl register */ typedef union { struct { uint32_t reserved_0:20; - /** outlink_stop_ch0 : R/W/SC; bitpos: [20]; default: 0; + /** outlink_stop : R/W/SC; bitpos: [20]; default: 0; * Set this bit to stop dealing with the outlink descriptors. */ - uint32_t outlink_stop_ch0:1; - /** outlink_start_ch0 : R/W/SC; bitpos: [21]; default: 0; + uint32_t outlink_stop:1; + /** outlink_start : R/W/SC; bitpos: [21]; default: 0; * Set this bit to start dealing with the outlink descriptors. */ - uint32_t outlink_start_ch0:1; - /** outlink_restart_ch0 : R/W/SC; bitpos: [22]; default: 0; + uint32_t outlink_start:1; + /** outlink_restart : R/W/SC; bitpos: [22]; default: 0; * Set this bit to restart a new outlink from the last address. */ - uint32_t outlink_restart_ch0:1; - /** outlink_park_ch0 : RO; bitpos: [23]; default: 1; + uint32_t outlink_restart:1; + /** outlink_park : RO; bitpos: [23]; default: 1; * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM * is working. */ - uint32_t outlink_park_ch0:1; + uint32_t outlink_park:1; uint32_t reserved_24:8; }; uint32_t val; -} h264_dma_out_link_conf_ch0_reg_t; +} h264_dma_out_link_conf_chn_reg_t; -/** Type of out_ro_pd_conf_ch0 register - * TX CH0 reorder power config register - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** out_ro_ram_force_pd_ch0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t out_ro_ram_force_pd_ch0:1; - /** out_ro_ram_force_pu_ch0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t out_ro_ram_force_pu_ch0:1; - /** out_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t out_ro_ram_clk_fo_ch0:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_ro_pd_conf_ch0_reg_t; - -/** Type of out_push_ch1 register - * TX CH1 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch1 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch1:10; - /** outfifo_push_ch1 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch1:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch1_reg_t; - -/** Type of out_link_conf_ch1 register - * TX CH1 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch1:1; - /** outlink_start_ch1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch1:1; - /** outlink_restart_ch1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch1:1; - /** outlink_park_ch1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch1:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch1_reg_t; - -/** Type of out_push_ch2 register - * TX CH2 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch2 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch2:10; - /** outfifo_push_ch2 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch2:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch2_reg_t; - -/** Type of out_link_conf_ch2 register - * TX CH2 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch2:1; - /** outlink_start_ch2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch2:1; - /** outlink_restart_ch2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch2:1; - /** outlink_park_ch2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch2:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch2_reg_t; - -/** Type of out_push_ch3 register - * TX CH3 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch3 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch3:10; - /** outfifo_push_ch3 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch3:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch3_reg_t; - -/** Type of out_link_conf_ch3 register - * TX CH3 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch3 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch3:1; - /** outlink_start_ch3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch3:1; - /** outlink_restart_ch3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch3:1; - /** outlink_park_ch3 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch3:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch3_reg_t; - -/** Type of out_push_ch4 register - * TX CH4 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch4 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch4:10; - /** outfifo_push_ch4 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch4:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch4_reg_t; - -/** Type of out_link_conf_ch4 register - * TX CH4 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch4 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch4:1; - /** outlink_start_ch4 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch4:1; - /** outlink_restart_ch4 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch4:1; - /** outlink_park_ch4 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch4:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch4_reg_t; - -/** Type of in_conf0_ch0 register - * RX CH0 config0 register +/** Type of in_conf0 register + * RX CHn config0 register */ typedef union { struct { uint32_t reserved_0:2; - /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; + /** indscr_burst_en : R/W; bitpos: [2]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor * when accessing SRAM. */ - uint32_t indscr_burst_en_ch0:1; - /** in_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0; + uint32_t indscr_burst_en:1; + /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ - uint32_t in_ecc_aes_en_ch0:1; - /** in_check_owner_ch0 : R/W; bitpos: [4]; default: 0; + uint32_t in_ecc_aes_en:1; + /** in_check_owner : R/W; bitpos: [4]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ - uint32_t in_check_owner_ch0:1; + uint32_t in_check_owner:1; uint32_t reserved_5:1; - /** in_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0; + /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0; * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ - uint32_t in_mem_burst_length_ch0:3; + uint32_t in_mem_burst_length:3; uint32_t reserved_9:3; - /** in_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0; + /** in_page_bound_en : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI write data don't cross the address boundary * which define by mem_burst_length */ - uint32_t in_page_bound_en_ch0:1; + uint32_t in_page_bound_en:1; uint32_t reserved_13:11; - /** in_rst_ch0 : R/W; bitpos: [24]; default: 0; + /** in_rst : R/W; bitpos: [24]; default: 0; * Write 1 then write 0 to this bit to reset Rx channel */ - uint32_t in_rst_ch0:1; - /** in_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0; + uint32_t in_rst:1; + /** in_cmd_disable : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ - uint32_t in_cmd_disable_ch0:1; - /** in_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0; + uint32_t in_cmd_disable:1; + /** in_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0; * Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t in_arb_weight_opt_dis_ch0:1; + uint32_t in_arb_weight_opt_dis:1; uint32_t reserved_27:5; }; uint32_t val; -} h264_dma_in_conf0_ch0_reg_t; +} h264_dma_in_conf0_chn_reg_t; -/** Type of in_pop_ch0 register - * RX CH0 INFIFO pop register +/** Type of in_pop register + * RX CHn INFIFO pop register */ typedef union { struct { - /** infifo_rdata_ch0 : RO; bitpos: [10:0]; default: 1024; + /** infifo_rdata : RO; bitpos: [10:0]; default: 1024; * This register stores the data popping from DMA Rx FIFO. */ - uint32_t infifo_rdata_ch0:11; - /** infifo_pop_ch0 : R/W/SC; bitpos: [11]; default: 0; + uint32_t infifo_rdata:11; + /** infifo_pop : R/W/SC; bitpos: [11]; default: 0; * Set this bit to pop data from DMA Rx FIFO. */ - uint32_t infifo_pop_ch0:1; + uint32_t infifo_pop:1; uint32_t reserved_12:20; }; uint32_t val; -} h264_dma_in_pop_ch0_reg_t; +} h264_dma_in_pop_chn_reg_t; -/** Type of in_link_conf_ch0 register - * RX CH0 in_link dscr ctrl register +/** Type of in_link_conf register + * RX CHn in_link dscr ctrl register */ typedef union { struct { uint32_t reserved_0:20; - /** inlink_auto_ret_ch0 : R/W; bitpos: [20]; default: 1; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 1; * Set this bit to return to current inlink descriptor's address, when there are some * errors in current receiving data. */ - uint32_t inlink_auto_ret_ch0:1; - /** inlink_stop_ch0 : R/W/SC; bitpos: [21]; default: 0; + uint32_t inlink_auto_ret:1; + /** inlink_stop : R/W/SC; bitpos: [21]; default: 0; * Set this bit to stop dealing with the inlink descriptors. */ - uint32_t inlink_stop_ch0:1; - /** inlink_start_ch0 : R/W/SC; bitpos: [22]; default: 0; + uint32_t inlink_stop:1; + /** inlink_start : R/W/SC; bitpos: [22]; default: 0; * Set this bit to start dealing with the inlink descriptors. */ - uint32_t inlink_start_ch0:1; - /** inlink_restart_ch0 : R/W/SC; bitpos: [23]; default: 0; + uint32_t inlink_start:1; + /** inlink_restart : R/W/SC; bitpos: [23]; default: 0; * Set this bit to mount a new inlink descriptor. */ - uint32_t inlink_restart_ch0:1; - /** inlink_park_ch0 : RO; bitpos: [24]; default: 1; + uint32_t inlink_restart:1; + /** inlink_park : RO; bitpos: [24]; default: 1; * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is * working. */ - uint32_t inlink_park_ch0:1; + uint32_t inlink_park:1; uint32_t reserved_25:7; }; uint32_t val; -} h264_dma_in_link_conf_ch0_reg_t; +} h264_dma_in_link_conf_chn_reg_t; -/** Type of in_ro_pd_conf_ch0 register - * RX CH0 reorder power config register +/** Type of in_ro_pd_conf register + * RX CHn reorder power config register */ typedef union { struct { uint32_t reserved_0:6; - /** in_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0; + /** in_ro_ram_clk_fo : R/W; bitpos: [6]; default: 0; * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. * 0: A gate-clock will be used when accessing the RAM in DMA. */ - uint32_t in_ro_ram_clk_fo_ch0:1; + uint32_t in_ro_ram_clk_fo:1; uint32_t reserved_7:25; }; uint32_t val; -} h264_dma_in_ro_pd_conf_ch0_reg_t; - -/** Type of in_conf0_ch1 register - * RX CH1 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch1:1; - /** in_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_ch1:1; - /** in_check_owner_ch1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch1:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch1:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch1:1; - uint32_t reserved_13:11; - /** in_rst_ch1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch1:1; - /** in_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch1:1; - /** in_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch1:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch1_reg_t; - -/** Type of in_pop_ch1 register - * RX CH1 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch1 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch1:11; - /** infifo_pop_ch1 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch1:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch1_reg_t; - -/** Type of in_link_conf_ch1 register - * RX CH1 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch1:1; - /** inlink_stop_ch1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch1:1; - /** inlink_start_ch1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch1:1; - /** inlink_restart_ch1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch1:1; - /** inlink_park_ch1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_ch1:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch1_reg_t; - -/** Type of in_conf0_ch2 register - * RX CH2 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch2:1; - /** in_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_ch2:1; - /** in_check_owner_ch2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch2:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch2:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch2:1; - uint32_t reserved_13:11; - /** in_rst_ch2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch2:1; - /** in_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch2:1; - /** in_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch2:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch2_reg_t; - -/** Type of in_pop_ch2 register - * RX CH2 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch2 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch2:11; - /** infifo_pop_ch2 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch2:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch2_reg_t; - -/** Type of in_link_conf_ch2 register - * RX CH2 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch2:1; - /** inlink_stop_ch2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch2:1; - /** inlink_start_ch2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch2:1; - /** inlink_restart_ch2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch2:1; - /** inlink_park_ch2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_ch2:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch2_reg_t; - -/** Type of in_conf0_ch3 register - * RX CH3 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch3:1; - /** in_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_ch3:1; - /** in_check_owner_ch3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch3:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch3:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch3:1; - uint32_t reserved_13:11; - /** in_rst_ch3 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch3:1; - /** in_cmd_disable_ch3 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch3:1; - /** in_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch3:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch3_reg_t; - -/** Type of in_pop_ch3 register - * RX CH3 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch3 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch3:11; - /** infifo_pop_ch3 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch3:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch3_reg_t; - -/** Type of in_link_conf_ch3 register - * RX CH3 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch3 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch3:1; - /** inlink_stop_ch3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch3:1; - /** inlink_start_ch3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch3:1; - /** inlink_restart_ch3 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch3:1; - /** inlink_park_ch3 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_ch3:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch3_reg_t; - -/** Type of in_conf0_ch4 register - * RX CH4 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch4:1; - /** in_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_ch4:1; - /** in_check_owner_ch4 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch4:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch4:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch4:1; - uint32_t reserved_13:11; - /** in_rst_ch4 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch4:1; - /** in_cmd_disable_ch4 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch4:1; - /** in_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch4:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch4_reg_t; - -/** Type of in_pop_ch4 register - * RX CH4 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch4 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch4:11; - /** infifo_pop_ch4 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch4:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch4_reg_t; - -/** Type of in_link_conf_ch4 register - * RX CH4 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch4 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch4:1; - /** inlink_stop_ch4 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch4:1; - /** inlink_start_ch4 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch4:1; - /** inlink_restart_ch4 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch4:1; - /** inlink_park_ch4 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_ch4:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch4_reg_t; +} h264_dma_in_ro_pd_conf_chn_reg_t; /** Type of in_conf0_ch5 register * RX CH5 config0 register @@ -863,33 +181,33 @@ typedef union { typedef union { struct { uint32_t reserved_0:3; - /** in_ecc_aes_en_ch5 : R/W; bitpos: [3]; default: 0; + /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ - uint32_t in_ecc_aes_en_ch5:1; + uint32_t in_ecc_aes_en:1; uint32_t reserved_4:2; - /** in_mem_burst_length_ch5 : R/W; bitpos: [8:6]; default: 0; + /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0; * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ - uint32_t in_mem_burst_length_ch5:3; + uint32_t in_mem_burst_length:3; uint32_t reserved_9:3; - /** in_page_bound_en_ch5 : R/W; bitpos: [12]; default: 0; + /** in_page_bound_en : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI write data don't cross the address boundary * which define by mem_burst_length */ - uint32_t in_page_bound_en_ch5:1; + uint32_t in_page_bound_en:1; uint32_t reserved_13:11; - /** in_rst_ch5 : R/W; bitpos: [24]; default: 0; + /** in_rst : R/W; bitpos: [24]; default: 0; * Write 1 then write 0 to this bit to reset Rx channel */ - uint32_t in_rst_ch5:1; - /** in_cmd_disable_ch5 : R/W; bitpos: [25]; default: 0; + uint32_t in_rst:1; + /** in_cmd_disable : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ - uint32_t in_cmd_disable_ch5:1; + uint32_t in_cmd_disable:1; uint32_t reserved_26:6; }; uint32_t val; @@ -900,14 +218,14 @@ typedef union { */ typedef union { struct { - /** infifo_rdata_ch5 : RO; bitpos: [10:0]; default: 1024; + /** infifo_rdata : RO; bitpos: [10:0]; default: 1024; * This register stores the data popping from DMA Rx FIFO. */ - uint32_t infifo_rdata_ch5:11; - /** infifo_pop_ch5 : R/W/SC; bitpos: [11]; default: 0; + uint32_t infifo_rdata:11; + /** infifo_pop : R/W/SC; bitpos: [11]; default: 0; * Set this bit to pop data from DMA Rx FIFO. */ - uint32_t infifo_pop_ch5:1; + uint32_t infifo_pop:1; uint32_t reserved_12:20; }; uint32_t val; @@ -945,2014 +263,431 @@ typedef union { } h264_dma_rst_conf_reg_t; -/** Group: Interrupt Registers */ -/** Type of out_int_raw_ch0 register - * TX CH0 interrupt raw register +/** Type of out_int_raw register + * TX CHn interrupt raw register */ typedef union { struct { - /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink * descriptor has been transmitted to peripherals for Tx channel 0. */ - uint32_t out_done_ch0_int_raw:1; - /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t done_int_raw:1; + /** eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink * descriptor has been read from memory for Tx channel 0. */ - uint32_t out_eof_ch0_int_raw:1; - /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t eof_int_raw:1; + /** dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when detecting outlink descriptor error, * including owner error, the second and third word error of outlink descriptor for Tx * channel 0. */ - uint32_t out_dscr_err_ch0_int_raw:1; - /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t dscr_err_int_raw:1; + /** total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when data corresponding a outlink * (includes one link descriptor or few link descriptors) is transmitted out for Tx * channel 0. */ - uint32_t out_total_eof_ch0_int_raw:1; - /** outfifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t total_eof_int_raw:1; + /** outfifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when fifo is overflow. */ - uint32_t outfifo_ovf_l1_ch0_int_raw:1; - /** outfifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_l1_int_raw:1; + /** outfifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when fifo is underflow. */ - uint32_t outfifo_udf_l1_ch0_int_raw:1; - /** outfifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + uint32_t outfifo_udf_l1_int_raw:1; + /** outfifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when fifo is overflow. */ - uint32_t outfifo_ovf_l2_ch0_int_raw:1; - /** outfifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + uint32_t outfifo_ovf_l2_int_raw:1; + /** outfifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when fifo is underflow. */ - uint32_t outfifo_udf_l2_ch0_int_raw:1; - /** out_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + uint32_t outfifo_udf_l2_int_raw:1; + /** dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ - uint32_t out_dscr_task_ovf_ch0_int_raw:1; + uint32_t dscr_task_ovf_int_raw:1; uint32_t reserved_9:23; }; uint32_t val; -} h264_dma_out_int_raw_ch0_reg_t; +} h264_dma_out_int_raw_chn_reg_t; -/** Type of out_int_ena_ch0 register - * TX CH0 interrupt ena register +/** Type of out_int_ena register + * TX CHn interrupt ena register */ typedef union { struct { - /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; + /** done_int_ena : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_ch0_int_ena:1; - /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t done_int_ena:1; + /** eof_int_ena : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_ch0_int_ena:1; - /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t eof_int_ena:1; + /** dscr_err_int_ena : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_ch0_int_ena:1; - /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t dscr_err_int_ena:1; + /** total_eof_int_ena : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_ena:1; - /** outfifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t total_eof_int_ena:1; + /** outfifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_ena:1; - /** outfifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_l1_int_ena:1; + /** outfifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_ena:1; - /** outfifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0; + uint32_t outfifo_udf_l1_int_ena:1; + /** outfifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_ena:1; - /** outfifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0; + uint32_t outfifo_ovf_l2_int_ena:1; + /** outfifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_ena:1; - /** out_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [8]; default: 0; + uint32_t outfifo_udf_l2_int_ena:1; + /** dscr_task_ovf_int_ena : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_ena:1; + uint32_t dscr_task_ovf_int_ena:1; uint32_t reserved_9:23; }; uint32_t val; -} h264_dma_out_int_ena_ch0_reg_t; +} h264_dma_out_int_ena_chn_reg_t; -/** Type of out_int_st_ch0 register - * TX CH0 interrupt st register +/** Type of out_int_st register + * TX CHn interrupt st register */ typedef union { struct { - /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0; + /** done_int_st : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_ch0_int_st:1; - /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0; + uint32_t done_int_st:1; + /** eof_int_st : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_ch0_int_st:1; - /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0; + uint32_t eof_int_st:1; + /** dscr_err_int_st : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_ch0_int_st:1; - /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0; + uint32_t dscr_err_int_st:1; + /** total_eof_int_st : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_st:1; - /** outfifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0; + uint32_t total_eof_int_st:1; + /** outfifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_st:1; - /** outfifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_l1_int_st:1; + /** outfifo_udf_l1_int_st : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_st:1; - /** outfifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0; + uint32_t outfifo_udf_l1_int_st:1; + /** outfifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_st:1; - /** outfifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0; + uint32_t outfifo_ovf_l2_int_st:1; + /** outfifo_udf_l2_int_st : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_st:1; - /** out_dscr_task_ovf_ch0_int_st : RO; bitpos: [8]; default: 0; + uint32_t outfifo_udf_l2_int_st:1; + /** dscr_task_ovf_int_st : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_st:1; + uint32_t dscr_task_ovf_int_st:1; uint32_t reserved_9:23; }; uint32_t val; -} h264_dma_out_int_st_ch0_reg_t; +} h264_dma_out_int_st_chn_reg_t; -/** Type of out_int_clr_ch0 register - * TX CH0 interrupt clr register +/** Type of out_int_clr register + * TX CHn interrupt clr register */ typedef union { struct { - /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0; + /** done_int_clr : WT; bitpos: [0]; default: 0; * Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_ch0_int_clr:1; - /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; + uint32_t done_int_clr:1; + /** eof_int_clr : WT; bitpos: [1]; default: 0; * Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_ch0_int_clr:1; - /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0; + uint32_t eof_int_clr:1; + /** dscr_err_int_clr : WT; bitpos: [2]; default: 0; * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_ch0_int_clr:1; - /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0; + uint32_t dscr_err_int_clr:1; + /** total_eof_int_clr : WT; bitpos: [3]; default: 0; * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_clr:1; - /** outfifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0; + uint32_t total_eof_int_clr:1; + /** outfifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0; * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_clr:1; - /** outfifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_l1_int_clr:1; + /** outfifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0; * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_clr:1; - /** outfifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0; + uint32_t outfifo_udf_l1_int_clr:1; + /** outfifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0; * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_clr:1; - /** outfifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0; + uint32_t outfifo_ovf_l2_int_clr:1; + /** outfifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0; * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_clr:1; - /** out_dscr_task_ovf_ch0_int_clr : WT; bitpos: [8]; default: 0; + uint32_t outfifo_udf_l2_int_clr:1; + /** dscr_task_ovf_int_clr : WT; bitpos: [8]; default: 0; * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_clr:1; + uint32_t dscr_task_ovf_int_clr:1; uint32_t reserved_9:23; }; uint32_t val; -} h264_dma_out_int_clr_ch0_reg_t; +} h264_dma_out_int_clr_chn_reg_t; -/** Type of out_int_raw_ch1 register - * TX CH1 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch1_int_raw:1; - /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch1_int_raw:1; - /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch1_int_raw:1; - /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch1_int_raw:1; - /** outfifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch1_int_raw:1; - /** outfifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch1_int_raw:1; - /** outfifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch1_int_raw:1; - /** outfifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch1_int_raw:1; - /** out_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch1_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch1_reg_t; -/** Type of out_int_ena_ch1 register - * TX CH1 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_ena:1; - /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_ena:1; - /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_ena:1; - /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_ena:1; - /** outfifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_ena:1; - /** outfifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_ena:1; - /** outfifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_ena:1; - /** outfifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_ena:1; - /** out_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch1_reg_t; - -/** Type of out_int_st_ch1 register - * TX CH1 interrupt st register - */ -typedef union { - struct { - /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_st:1; - /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_st:1; - /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_st:1; - /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_st:1; - /** outfifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_st:1; - /** outfifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_st:1; - /** outfifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_st:1; - /** outfifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_st:1; - /** out_dscr_task_ovf_ch1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch1_reg_t; - -/** Type of out_int_clr_ch1 register - * TX CH1 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_clr:1; - /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_clr:1; - /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_clr:1; - /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_clr:1; - /** outfifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_clr:1; - /** outfifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_clr:1; - /** outfifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_clr:1; - /** outfifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_clr:1; - /** out_dscr_task_ovf_ch1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch1_reg_t; - -/** Type of out_int_raw_ch2 register - * TX CH2 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch2_int_raw:1; - /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch2_int_raw:1; - /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch2_int_raw:1; - /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch2_int_raw:1; - /** outfifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch2_int_raw:1; - /** outfifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch2_int_raw:1; - /** outfifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch2_int_raw:1; - /** outfifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch2_int_raw:1; - /** out_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch2_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch2_reg_t; - -/** Type of out_int_ena_ch2 register - * TX CH2 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_ena:1; - /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_ena:1; - /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_ena:1; - /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_ena:1; - /** outfifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_ena:1; - /** outfifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_ena:1; - /** outfifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_ena:1; - /** outfifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_ena:1; - /** out_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch2_reg_t; - -/** Type of out_int_st_ch2 register - * TX CH2 interrupt st register - */ -typedef union { - struct { - /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_st:1; - /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_st:1; - /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_st:1; - /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_st:1; - /** outfifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_st:1; - /** outfifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_st:1; - /** outfifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_st:1; - /** outfifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_st:1; - /** out_dscr_task_ovf_ch2_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch2_reg_t; - -/** Type of out_int_clr_ch2 register - * TX CH2 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_clr:1; - /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_clr:1; - /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_clr:1; - /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_clr:1; - /** outfifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_clr:1; - /** outfifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_clr:1; - /** outfifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_clr:1; - /** outfifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_clr:1; - /** out_dscr_task_ovf_ch2_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch2_reg_t; - -/** Type of out_int_raw_ch3 register - * TX CH3 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch3_int_raw:1; - /** out_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch3_int_raw:1; - /** out_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch3_int_raw:1; - /** out_total_eof_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch3_int_raw:1; - /** outfifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch3_int_raw:1; - /** outfifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch3_int_raw:1; - /** outfifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch3_int_raw:1; - /** outfifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch3_int_raw:1; - /** out_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch3_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch3_reg_t; - -/** Type of out_int_ena_ch3 register - * TX CH3 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch3_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_ena:1; - /** out_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_ena:1; - /** out_dscr_err_ch3_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_ena:1; - /** out_total_eof_ch3_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_ena:1; - /** outfifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_ena:1; - /** outfifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_ena:1; - /** outfifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_ena:1; - /** outfifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_ena:1; - /** out_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch3_reg_t; - -/** Type of out_int_st_ch3 register - * TX CH3 interrupt st register - */ -typedef union { - struct { - /** out_done_ch3_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_st:1; - /** out_eof_ch3_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_st:1; - /** out_dscr_err_ch3_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_st:1; - /** out_total_eof_ch3_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_st:1; - /** outfifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_st:1; - /** outfifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_st:1; - /** outfifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_st:1; - /** outfifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_st:1; - /** out_dscr_task_ovf_ch3_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch3_reg_t; - -/** Type of out_int_clr_ch3 register - * TX CH3 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch3_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_clr:1; - /** out_eof_ch3_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_clr:1; - /** out_dscr_err_ch3_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_clr:1; - /** out_total_eof_ch3_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_clr:1; - /** outfifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_clr:1; - /** outfifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_clr:1; - /** outfifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_clr:1; - /** outfifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_clr:1; - /** out_dscr_task_ovf_ch3_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch3_reg_t; - -/** Type of out_int_raw_ch4 register - * TX CH4 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch4_int_raw:1; - /** out_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch4_int_raw:1; - /** out_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch4_int_raw:1; - /** out_total_eof_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch4_int_raw:1; - /** outfifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch4_int_raw:1; - /** outfifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch4_int_raw:1; - /** outfifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch4_int_raw:1; - /** outfifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch4_int_raw:1; - /** out_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch4_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch4_reg_t; - -/** Type of out_int_ena_ch4 register - * TX CH4 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch4_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_ena:1; - /** out_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_ena:1; - /** out_dscr_err_ch4_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_ena:1; - /** out_total_eof_ch4_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_ena:1; - /** outfifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_ena:1; - /** outfifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_ena:1; - /** outfifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_ena:1; - /** outfifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_ena:1; - /** out_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch4_reg_t; - -/** Type of out_int_st_ch4 register - * TX CH4 interrupt st register - */ -typedef union { - struct { - /** out_done_ch4_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_st:1; - /** out_eof_ch4_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_st:1; - /** out_dscr_err_ch4_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_st:1; - /** out_total_eof_ch4_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_st:1; - /** outfifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_st:1; - /** outfifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_st:1; - /** outfifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_st:1; - /** outfifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_st:1; - /** out_dscr_task_ovf_ch4_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch4_reg_t; - -/** Type of out_int_clr_ch4 register - * TX CH4 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch4_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_clr:1; - /** out_eof_ch4_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_clr:1; - /** out_dscr_err_ch4_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_clr:1; - /** out_total_eof_ch4_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_clr:1; - /** outfifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_clr:1; - /** outfifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_clr:1; - /** outfifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_clr:1; - /** outfifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_clr:1; - /** out_dscr_task_ovf_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch4_reg_t; - -/** Type of in_int_raw_ch0 register +/** Type of in_int_raw register * RX CH0 interrupt raw register */ typedef union { struct { - /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been transmitted to peripherals for Rx channel 0. */ - uint32_t in_done_ch0_int_raw:1; - /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t in_done_int_raw:1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received and no data error is detected for Rx channel 0. */ - uint32_t in_suc_eof_ch0_int_raw:1; - /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_raw:1; + /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received and data error is detected */ - uint32_t in_err_eof_ch0_int_raw:1; - /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_raw:1; + /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error, * including owner error, the second and third word error of inlink descriptor for Rx * channel 0. */ - uint32_t in_dscr_err_ch0_int_raw:1; - /** infifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_raw:1; + /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t infifo_ovf_l1_ch0_int_raw:1; - /** infifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + uint32_t infifo_ovf_l1_int_raw:1; + /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t infifo_udf_l1_ch0_int_raw:1; - /** infifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + uint32_t infifo_udf_l1_int_raw:1; + /** infifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t infifo_ovf_l2_ch0_int_raw:1; - /** infifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + uint32_t infifo_ovf_l2_int_raw:1; + /** infifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t infifo_udf_l2_ch0_int_raw:1; - /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + uint32_t infifo_udf_l2_int_raw:1; + /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [8]; default: 0; * The raw interrupt bit turns to high level when the last descriptor is done but fifo * also remain data. */ - uint32_t in_dscr_empty_ch0_int_raw:1; - /** in_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + uint32_t in_dscr_empty_int_raw:1; + /** in_dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ - uint32_t in_dscr_task_ovf_ch0_int_raw:1; + uint32_t in_dscr_task_ovf_int_raw:1; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_in_int_raw_ch0_reg_t; +} h264_dma_in_int_raw_chn_reg_t; -/** Type of in_int_ena_ch0 register +/** Type of in_int_ena register * RX CH0 interrupt ena register */ typedef union { struct { - /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch0_int_ena:1; - /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t in_done_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch0_int_ena:1; - /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_ena:1; + /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_ch0_int_ena:1; - /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_ena:1; + /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_ch0_int_ena:1; - /** infifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_ena:1; + /** infifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch0_int_ena:1; - /** infifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0; + uint32_t infifo_ovf_l1_int_ena:1; + /** infifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch0_int_ena:1; - /** infifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0; + uint32_t infifo_udf_l1_int_ena:1; + /** infifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t infifo_ovf_l2_ch0_int_ena:1; - /** infifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0; + uint32_t infifo_ovf_l2_int_ena:1; + /** infifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t infifo_udf_l2_ch0_int_ena:1; - /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [8]; default: 0; + uint32_t infifo_udf_l2_int_ena:1; + /** in_dscr_empty_int_ena : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_ch0_int_ena:1; - /** in_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [9]; default: 0; + uint32_t in_dscr_empty_int_ena:1; + /** in_dscr_task_ovf_int_ena : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t in_dscr_task_ovf_ch0_int_ena:1; + uint32_t in_dscr_task_ovf_int_ena:1; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_in_int_ena_ch0_reg_t; +} h264_dma_in_int_ena_chn_reg_t; -/** Type of in_int_st_ch0 register +/** Type of in_int_st register * RX CH0 interrupt st register */ typedef union { struct { - /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0; + /** in_done_int_st : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch0_int_st:1; - /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0; + uint32_t in_done_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch0_int_st:1; - /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_st:1; + /** in_err_eof_int_st : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_ch0_int_st:1; - /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_st:1; + /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_ch0_int_st:1; - /** infifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_st:1; + /** infifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch0_int_st:1; - /** infifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0; + uint32_t infifo_ovf_l1_int_st:1; + /** infifo_udf_l1_int_st : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch0_int_st:1; - /** infifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0; + uint32_t infifo_udf_l1_int_st:1; + /** infifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t infifo_ovf_l2_ch0_int_st:1; - /** infifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0; + uint32_t infifo_ovf_l2_int_st:1; + /** infifo_udf_l2_int_st : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t infifo_udf_l2_ch0_int_st:1; - /** in_dscr_empty_ch0_int_st : RO; bitpos: [8]; default: 0; + uint32_t infifo_udf_l2_int_st:1; + /** in_dscr_empty_int_st : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_ch0_int_st:1; - /** in_dscr_task_ovf_ch0_int_st : RO; bitpos: [9]; default: 0; + uint32_t in_dscr_empty_int_st:1; + /** in_dscr_task_ovf_int_st : RO; bitpos: [9]; default: 0; * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t in_dscr_task_ovf_ch0_int_st:1; + uint32_t in_dscr_task_ovf_int_st:1; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_in_int_st_ch0_reg_t; +} h264_dma_in_int_st_chn_reg_t; -/** Type of in_int_clr_ch0 register +/** Type of in_int_clr register * RX CH0 interrupt clr register */ typedef union { struct { - /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0; + /** in_done_int_clr : WT; bitpos: [0]; default: 0; * Set this bit to clear the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch0_int_clr:1; - /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; + uint32_t in_done_int_clr:1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch0_int_clr:1; - /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_clr:1; + /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0; * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_ch0_int_clr:1; - /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_clr:1; + /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0; * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_ch0_int_clr:1; - /** infifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_clr:1; + /** infifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0; * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch0_int_clr:1; - /** infifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0; + uint32_t infifo_ovf_l1_int_clr:1; + /** infifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0; * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch0_int_clr:1; - /** infifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0; + uint32_t infifo_udf_l1_int_clr:1; + /** infifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0; * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t infifo_ovf_l2_ch0_int_clr:1; - /** infifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0; + uint32_t infifo_ovf_l2_int_clr:1; + /** infifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0; * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t infifo_udf_l2_ch0_int_clr:1; - /** in_dscr_empty_ch0_int_clr : WT; bitpos: [8]; default: 0; + uint32_t infifo_udf_l2_int_clr:1; + /** in_dscr_empty_int_clr : WT; bitpos: [8]; default: 0; * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_ch0_int_clr:1; - /** in_dscr_task_ovf_ch0_int_clr : WT; bitpos: [9]; default: 0; + uint32_t in_dscr_empty_int_clr:1; + /** in_dscr_task_ovf_int_clr : WT; bitpos: [9]; default: 0; * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t in_dscr_task_ovf_ch0_int_clr:1; + uint32_t in_dscr_task_ovf_int_clr:1; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_in_int_clr_ch0_reg_t; +} h264_dma_in_int_clr_chn_reg_t; -/** Type of in_int_raw_ch1 register - * RX CH1 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch1_int_raw:1; - /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch1_int_raw:1; - /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch1_int_raw:1; - /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch1_int_raw:1; - /** infifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch1_int_raw:1; - /** infifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch1_int_raw:1; - /** infifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch1_int_raw:1; - /** infifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch1_int_raw:1; - /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch1_int_raw:1; - /** in_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch1_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch1_reg_t; - -/** Type of in_int_ena_ch1 register - * RX CH1 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_ena:1; - /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_ena:1; - /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_ena:1; - /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_ena:1; - /** infifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_ena:1; - /** infifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_ena:1; - /** infifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_ena:1; - /** infifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_ena:1; - /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_ena:1; - /** in_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch1_reg_t; - -/** Type of in_int_st_ch1 register - * RX CH1 interrupt st register - */ -typedef union { - struct { - /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_st:1; - /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_st:1; - /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_st:1; - /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_st:1; - /** infifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_st:1; - /** infifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_st:1; - /** infifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_st:1; - /** infifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_st:1; - /** in_dscr_empty_ch1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_st:1; - /** in_dscr_task_ovf_ch1_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch1_reg_t; - -/** Type of in_int_clr_ch1 register - * RX CH1 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_clr:1; - /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_clr:1; - /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_clr:1; - /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_clr:1; - /** infifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_clr:1; - /** infifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_clr:1; - /** infifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_clr:1; - /** infifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_clr:1; - /** in_dscr_empty_ch1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_clr:1; - /** in_dscr_task_ovf_ch1_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch1_reg_t; - -/** Type of in_int_raw_ch2 register - * RX CH2 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch2_int_raw:1; - /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch2_int_raw:1; - /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch2_int_raw:1; - /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch2_int_raw:1; - /** infifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch2_int_raw:1; - /** infifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch2_int_raw:1; - /** infifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch2_int_raw:1; - /** infifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch2_int_raw:1; - /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch2_int_raw:1; - /** in_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch2_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch2_reg_t; - -/** Type of in_int_ena_ch2 register - * RX CH2 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_ena:1; - /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_ena:1; - /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_ena:1; - /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_ena:1; - /** infifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_ena:1; - /** infifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_ena:1; - /** infifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_ena:1; - /** infifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_ena:1; - /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_ena:1; - /** in_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch2_reg_t; - -/** Type of in_int_st_ch2 register - * RX CH2 interrupt st register - */ -typedef union { - struct { - /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_st:1; - /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_st:1; - /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_st:1; - /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_st:1; - /** infifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_st:1; - /** infifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_st:1; - /** infifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_st:1; - /** infifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_st:1; - /** in_dscr_empty_ch2_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_st:1; - /** in_dscr_task_ovf_ch2_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch2_reg_t; - -/** Type of in_int_clr_ch2 register - * RX CH2 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_clr:1; - /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_clr:1; - /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_clr:1; - /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_clr:1; - /** infifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_clr:1; - /** infifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_clr:1; - /** infifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_clr:1; - /** infifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_clr:1; - /** in_dscr_empty_ch2_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_clr:1; - /** in_dscr_task_ovf_ch2_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch2_reg_t; - -/** Type of in_int_raw_ch3 register - * RX CH3 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch3_int_raw:1; - /** in_suc_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch3_int_raw:1; - /** in_err_eof_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch3_int_raw:1; - /** in_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch3_int_raw:1; - /** infifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch3_int_raw:1; - /** infifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch3_int_raw:1; - /** infifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch3_int_raw:1; - /** infifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch3_int_raw:1; - /** in_dscr_empty_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch3_int_raw:1; - /** in_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch3_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch3_reg_t; - -/** Type of in_int_ena_ch3 register - * RX CH3 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch3_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_ena:1; - /** in_suc_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_ena:1; - /** in_err_eof_ch3_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_ena:1; - /** in_dscr_err_ch3_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_ena:1; - /** infifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_ena:1; - /** infifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_ena:1; - /** infifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_ena:1; - /** infifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_ena:1; - /** in_dscr_empty_ch3_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_ena:1; - /** in_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch3_reg_t; - -/** Type of in_int_st_ch3 register - * RX CH3 interrupt st register - */ -typedef union { - struct { - /** in_done_ch3_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_st:1; - /** in_suc_eof_ch3_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_st:1; - /** in_err_eof_ch3_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_st:1; - /** in_dscr_err_ch3_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_st:1; - /** infifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_st:1; - /** infifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_st:1; - /** infifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_st:1; - /** infifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_st:1; - /** in_dscr_empty_ch3_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_st:1; - /** in_dscr_task_ovf_ch3_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch3_reg_t; - -/** Type of in_int_clr_ch3 register - * RX CH3 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch3_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_clr:1; - /** in_suc_eof_ch3_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_clr:1; - /** in_err_eof_ch3_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_clr:1; - /** in_dscr_err_ch3_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_clr:1; - /** infifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_clr:1; - /** infifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_clr:1; - /** infifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_clr:1; - /** infifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_clr:1; - /** in_dscr_empty_ch3_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_clr:1; - /** in_dscr_task_ovf_ch3_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch3_reg_t; - -/** Type of in_int_raw_ch4 register - * RX CH4 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch4_int_raw:1; - /** in_suc_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch4_int_raw:1; - /** in_err_eof_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch4_int_raw:1; - /** in_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch4_int_raw:1; - /** infifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch4_int_raw:1; - /** infifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch4_int_raw:1; - /** infifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch4_int_raw:1; - /** infifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch4_int_raw:1; - /** in_dscr_empty_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch4_int_raw:1; - /** in_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch4_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch4_reg_t; - -/** Type of in_int_ena_ch4 register - * RX CH4 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch4_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_ena:1; - /** in_suc_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_ena:1; - /** in_err_eof_ch4_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_ena:1; - /** in_dscr_err_ch4_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_ena:1; - /** infifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_ena:1; - /** infifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_ena:1; - /** infifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_ena:1; - /** infifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_ena:1; - /** in_dscr_empty_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_ena:1; - /** in_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch4_reg_t; - -/** Type of in_int_st_ch4 register - * RX CH4 interrupt st register - */ -typedef union { - struct { - /** in_done_ch4_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_st:1; - /** in_suc_eof_ch4_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_st:1; - /** in_err_eof_ch4_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_st:1; - /** in_dscr_err_ch4_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_st:1; - /** infifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_st:1; - /** infifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_st:1; - /** infifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_st:1; - /** infifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_st:1; - /** in_dscr_empty_ch4_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_st:1; - /** in_dscr_task_ovf_ch4_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch4_reg_t; - -/** Type of in_int_clr_ch4 register - * RX CH4 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch4_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_clr:1; - /** in_suc_eof_ch4_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_clr:1; - /** in_err_eof_ch4_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_clr:1; - /** in_dscr_err_ch4_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_clr:1; - /** infifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_clr:1; - /** infifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_clr:1; - /** infifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_clr:1; - /** infifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_clr:1; - /** in_dscr_empty_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_clr:1; - /** in_dscr_task_ovf_ch4_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch4_reg_t; /** Type of in_int_raw_ch5 register * RX CH5 interrupt raw register */ typedef union { struct { - /** in_done_ch5_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been transmitted to peripherals for Rx channel 1. */ - uint32_t in_done_ch5_int_raw:1; - /** in_suc_eof_ch5_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t in_done_int_raw:1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received and no data error is detected for Rx channel 1. */ - uint32_t in_suc_eof_ch5_int_raw:1; - /** infifo_ovf_l1_ch5_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_raw:1; + /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t infifo_ovf_l1_ch5_int_raw:1; - /** infifo_udf_l1_ch5_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t infifo_ovf_l1_int_raw:1; + /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t infifo_udf_l1_ch5_int_raw:1; - /** fetch_mb_col_cnt_ovf_ch5_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t infifo_udf_l1_int_raw:1; + /** fetch_mb_col_cnt_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_raw:1; + uint32_t fetch_mb_col_cnt_ovf_int_raw:1; uint32_t reserved_5:27; }; uint32_t val; @@ -2963,26 +698,26 @@ typedef union { */ typedef union { struct { - /** in_done_ch5_int_ena : R/W; bitpos: [0]; default: 0; + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch5_int_ena:1; - /** in_suc_eof_ch5_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t in_done_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch5_int_ena:1; - /** infifo_ovf_l1_ch5_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_ena:1; + /** infifo_ovf_l1_int_ena : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch5_int_ena:1; - /** infifo_udf_l1_ch5_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t infifo_ovf_l1_int_ena:1; + /** infifo_udf_l1_int_ena : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch5_int_ena:1; - /** fetch_mb_col_cnt_ovf_ch5_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t infifo_udf_l1_int_ena:1; + /** fetch_mb_col_cnt_ovf_int_ena : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_ena:1; + uint32_t fetch_mb_col_cnt_ovf_int_ena:1; uint32_t reserved_5:27; }; uint32_t val; @@ -2993,26 +728,26 @@ typedef union { */ typedef union { struct { - /** in_done_ch5_int_st : RO; bitpos: [0]; default: 0; + /** in_done_int_st : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch5_int_st:1; - /** in_suc_eof_ch5_int_st : RO; bitpos: [1]; default: 0; + uint32_t in_done_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch5_int_st:1; - /** infifo_ovf_l1_ch5_int_st : RO; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_st:1; + /** infifo_ovf_l1_int_st : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch5_int_st:1; - /** infifo_udf_l1_ch5_int_st : RO; bitpos: [3]; default: 0; + uint32_t infifo_ovf_l1_int_st:1; + /** infifo_udf_l1_int_st : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch5_int_st:1; - /** fetch_mb_col_cnt_ovf_ch5_int_st : RO; bitpos: [4]; default: 0; + uint32_t infifo_udf_l1_int_st:1; + /** fetch_mb_col_cnt_ovf_int_st : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_st:1; + uint32_t fetch_mb_col_cnt_ovf_int_st:1; uint32_t reserved_5:27; }; uint32_t val; @@ -3023,1404 +758,316 @@ typedef union { */ typedef union { struct { - /** in_done_ch5_int_clr : WT; bitpos: [0]; default: 0; + /** in_done_int_clr : WT; bitpos: [0]; default: 0; * Set this bit to clear the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_ch5_int_clr:1; - /** in_suc_eof_ch5_int_clr : WT; bitpos: [1]; default: 0; + uint32_t in_done_int_clr:1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_ch5_int_clr:1; - /** infifo_ovf_l1_ch5_int_clr : WT; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_clr:1; + /** infifo_ovf_l1_int_clr : WT; bitpos: [2]; default: 0; * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_l1_ch5_int_clr:1; - /** infifo_udf_l1_ch5_int_clr : WT; bitpos: [3]; default: 0; + uint32_t infifo_ovf_l1_int_clr:1; + /** infifo_udf_l1_int_clr : WT; bitpos: [3]; default: 0; * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_l1_ch5_int_clr:1; - /** fetch_mb_col_cnt_ovf_ch5_int_clr : WT; bitpos: [4]; default: 0; + uint32_t infifo_udf_l1_int_clr:1; + /** fetch_mb_col_cnt_ovf_int_clr : WT; bitpos: [4]; default: 0; * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_clr:1; + uint32_t fetch_mb_col_cnt_ovf_int_clr:1; uint32_t reserved_5:27; }; uint32_t val; } h264_dma_in_int_clr_ch5_reg_t; -/** Group: Status Registers */ -/** Type of outfifo_status_ch0 register - * TX CH0 outfifo status register +/** Type of outfifo_status register + * TX CHn outfifo status register */ typedef union { struct { - /** outfifo_full_l2_ch0 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. + /** outfifo_full_l2 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 2. */ - uint32_t outfifo_full_l2_ch0:1; - /** outfifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + uint32_t outfifo_full_l2:1; + /** outfifo_empty_l2 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 2. */ - uint32_t outfifo_empty_l2_ch0:1; - /** outfifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + uint32_t outfifo_empty_l2:1; + /** outfifo_cnt_l2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. */ - uint32_t outfifo_cnt_l2_ch0:4; - /** outfifo_full_l1_ch0 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 0. + uint32_t outfifo_cnt_l2:4; + /** outfifo_full_l1 : RO; bitpos: [6]; default: 0; + * Tx FIFO full signal for Tx channel 2. */ - uint32_t outfifo_full_l1_ch0:1; - /** outfifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + uint32_t outfifo_full_l1:1; + /** outfifo_empty_l1 : RO; bitpos: [7]; default: 1; + * Tx FIFO empty signal for Tx channel 2. */ - uint32_t outfifo_empty_l1_ch0:1; - /** outfifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + uint32_t outfifo_empty_l1:1; + /** outfifo_cnt_l1 : RO; bitpos: [12:8]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. */ - uint32_t outfifo_cnt_l1_ch0:5; + uint32_t outfifo_cnt_l1:5; uint32_t reserved_13:3; - /** outfifo_full_l3_ch0 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 0. + /** outfifo_full_l3 : RO; bitpos: [16]; default: 0; + * Tx FIFO full signal for Tx channel 2. */ - uint32_t outfifo_full_l3_ch0:1; - /** outfifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + uint32_t outfifo_full_l3:1; + /** outfifo_empty_l3 : RO; bitpos: [17]; default: 1; + * Tx FIFO empty signal for Tx channel 2. */ - uint32_t outfifo_empty_l3_ch0:1; - /** outfifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0; - * The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + uint32_t outfifo_empty_l3:1; + /** outfifo_cnt_l3 : RO; bitpos: [19:18]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. */ - uint32_t outfifo_cnt_l3_ch0:2; + uint32_t outfifo_cnt_l3:2; uint32_t reserved_20:12; }; uint32_t val; -} h264_dma_outfifo_status_ch0_reg_t; +} h264_dma_outfifo_status_reg_t; -/** Type of out_state_ch0 register - * TX CH0 state register +/** Type of out_state register + * TX CHn state register */ typedef union { struct { - /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; + /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; * This register stores the current outlink descriptor's address. */ - uint32_t outlink_dscr_addr_ch0:18; - /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; + uint32_t outlink_dscr_addr:18; + /** out_dscr_state : RO; bitpos: [19:18]; default: 0; * This register stores the current descriptor state machine state. */ - uint32_t out_dscr_state_ch0:2; - /** out_state_ch0 : RO; bitpos: [23:20]; default: 0; + uint32_t out_dscr_state:2; + /** out_state : RO; bitpos: [23:20]; default: 0; * This register stores the current control module state machine state. */ - uint32_t out_state_ch0:4; - /** out_reset_avail_ch0 : RO; bitpos: [24]; default: 1; + uint32_t out_state:4; + /** out_reset_avail : RO; bitpos: [24]; default: 1; * This register indicate that if the channel reset is safety. */ - uint32_t out_reset_avail_ch0:1; + uint32_t out_reset_avail:1; uint32_t reserved_25:7; }; uint32_t val; -} h264_dma_out_state_ch0_reg_t; +} h264_dma_out_state_chn_reg_t; -/** Type of out_eof_des_addr_ch0 register - * TX CH0 eof des addr register +/** Type of out_eof_des_addr register + * TX CHn eof des addr register */ typedef union { struct { - /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch0:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch0_reg_t; - -/** Type of out_dscr_ch0 register - * TX CH0 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch0_reg_t; - -/** Type of out_dscr_bf0_ch0 register - * TX CH0 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch0_reg_t; - -/** Type of out_dscr_bf1_ch0 register - * TX CH0 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch0_reg_t; - -/** Type of out_ro_status_ch0 register - * TX CH0 reorder status register - */ -typedef union { - struct { - /** outfifo_ro_cnt_ch0 : RO; bitpos: [1:0]; default: 0; - * The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. - */ - uint32_t outfifo_ro_cnt_ch0:2; - uint32_t reserved_2:4; - /** out_ro_wr_state_ch0 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t out_ro_wr_state_ch0:2; - /** out_ro_rd_state_ch0 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t out_ro_rd_state_ch0:2; - /** out_pixel_byte_ch0 : RO; bitpos: [13:10]; default: 2; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t out_pixel_byte_ch0:4; - /** out_burst_block_num_ch0 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ - uint32_t out_burst_block_num_ch0:4; - uint32_t reserved_18:14; - }; - uint32_t val; -} h264_dma_out_ro_status_ch0_reg_t; - -/** Type of outfifo_status_ch1 register - * TX CH1 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch1 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l2_ch1:1; - /** outfifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l2_ch1:1; - /** outfifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l2_ch1:4; - /** outfifo_full_l1_ch1 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l1_ch1:1; - /** outfifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l1_ch1:1; - /** outfifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l1_ch1:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch1 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l3_ch1:1; - /** outfifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l3_ch1:1; - /** outfifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l3_ch1:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch1_reg_t; - -/** Type of out_state_ch1 register - * TX CH1 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch1:18; - /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch1:2; - /** out_state_ch1 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch1:4; - /** out_reset_avail_ch1 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_ch1:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_out_state_ch1_reg_t; - -/** Type of out_eof_des_addr_ch1 register - * TX CH1 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch1_reg_t; - -/** Type of out_dscr_ch1 register - * TX CH1 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch1_reg_t; - -/** Type of out_dscr_bf0_ch1 register - * TX CH1 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch1_reg_t; - -/** Type of out_dscr_bf1_ch1 register - * TX CH1 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch1_reg_t; - -/** Type of outfifo_status_ch2 register - * TX CH2 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch2 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch2:1; - /** outfifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch2:1; - /** outfifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch2:4; - /** outfifo_full_l1_ch2 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch2:1; - /** outfifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch2:1; - /** outfifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch2:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch2 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch2:1; - /** outfifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch2:1; - /** outfifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch2:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch2_reg_t; - -/** Type of out_state_ch2 register - * TX CH2 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch2:18; - /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch2:2; - /** out_state_ch2 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch2:4; - /** out_reset_avail_ch2 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_ch2:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_out_state_ch2_reg_t; - -/** Type of out_eof_des_addr_ch2 register - * TX CH2 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; + /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when the EOF bit in this * descriptor is 1. */ - uint32_t out_eof_des_addr_ch2:32; + uint32_t out_eof_des_addr:32; }; uint32_t val; -} h264_dma_out_eof_des_addr_ch2_reg_t; +} h264_dma_out_eof_des_addr_chn_reg_t; -/** Type of out_dscr_ch2 register - * TX CH2 next dscr addr register +/** Type of out_dscr register + * TX CHn next dscr addr register */ typedef union { struct { - /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr : RO; bitpos: [31:0]; default: 0; * The address of the next outlink descriptor address y. */ - uint32_t outlink_dscr_ch2:32; + uint32_t outlink_dscr:32; }; uint32_t val; -} h264_dma_out_dscr_ch2_reg_t; +} h264_dma_out_dscr_chn_reg_t; -/** Type of out_dscr_bf0_ch2 register - * TX CH2 last dscr addr register +/** Type of out_dscr_bf0 register + * TX CHn last dscr addr register */ typedef union { struct { - /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; * The address of the last outlink descriptor's next address y-1. */ - uint32_t outlink_dscr_bf0_ch2:32; + uint32_t outlink_dscr_bf0:32; }; uint32_t val; -} h264_dma_out_dscr_bf0_ch2_reg_t; +} h264_dma_out_dscr_bf0_chn_reg_t; -/** Type of out_dscr_bf1_ch2 register - * TX CH2 second-to-last dscr addr register +/** Type of out_dscr_bf1 register + * TX CHn second-to-last dscr addr register */ typedef union { struct { - /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; * The address of the second-to-last outlink descriptor's next address y-2. */ - uint32_t outlink_dscr_bf1_ch2:32; + uint32_t outlink_dscr_bf1:32; }; uint32_t val; -} h264_dma_out_dscr_bf1_ch2_reg_t; +} h264_dma_out_dscr_bf1_chn_reg_t; -/** Type of outfifo_status_ch3 register - * TX CH3 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch3 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch3:1; - /** outfifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch3:1; - /** outfifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch3:4; - /** outfifo_full_l1_ch3 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch3:1; - /** outfifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch3:1; - /** outfifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch3:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch3 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch3:1; - /** outfifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch3:1; - /** outfifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch3_reg_t; - -/** Type of out_state_ch3 register - * TX CH3 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch3:18; - /** out_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch3:2; - /** out_state_ch3 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch3:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_state_ch3_reg_t; - -/** Type of out_eof_des_addr_ch3 register - * TX CH3 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch3_reg_t; - -/** Type of out_dscr_ch3 register - * TX CH3 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch3_reg_t; - -/** Type of out_dscr_bf0_ch3 register - * TX CH3 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch3_reg_t; - -/** Type of out_dscr_bf1_ch3 register - * TX CH3 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch3_reg_t; - -/** Type of outfifo_status_ch4 register - * TX CH4 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch4 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch4:1; - /** outfifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch4:1; - /** outfifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch4:4; - /** outfifo_full_l1_ch4 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch4:1; - /** outfifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch4:1; - /** outfifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch4:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch4 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch4:1; - /** outfifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch4:1; - /** outfifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch4:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch4_reg_t; - -/** Type of out_state_ch4 register - * TX CH4 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch4:18; - /** out_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch4:2; - /** out_state_ch4 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch4:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_state_ch4_reg_t; - -/** Type of out_eof_des_addr_ch4 register - * TX CH4 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch4_reg_t; - -/** Type of out_dscr_ch4 register - * TX CH4 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch4_reg_t; - -/** Type of out_dscr_bf0_ch4 register - * TX CH4 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch4_reg_t; - -/** Type of out_dscr_bf1_ch4 register - * TX CH4 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch4_reg_t; - -/** Type of infifo_status_ch0 register +/** Type of infifo_status register * RX CH0 INFIFO status register */ typedef union { struct { - /** infifo_full_l2_ch0 : RO; bitpos: [0]; default: 0; + /** infifo_full_l2 : RO; bitpos: [0]; default: 0; * Rx FIFO full signal for Rx channel. */ - uint32_t infifo_full_l2_ch0:1; - /** infifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1; + uint32_t infifo_full_l2:1; + /** infifo_empty_l2 : RO; bitpos: [1]; default: 1; * Rx FIFO empty signal for Rx channel. */ - uint32_t infifo_empty_l2_ch0:1; - /** infifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0; + uint32_t infifo_empty_l2:1; + /** infifo_cnt_l2 : RO; bitpos: [5:2]; default: 0; * The register stores the byte number of the data in Rx FIFO for Rx channel. */ - uint32_t infifo_cnt_l2_ch0:4; - /** infifo_full_l1_ch0 : RO; bitpos: [6]; default: 0; + uint32_t infifo_cnt_l2:4; + /** infifo_full_l1 : RO; bitpos: [6]; default: 0; * Tx FIFO full signal for Tx channel 0. */ - uint32_t infifo_full_l1_ch0:1; - /** infifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1; + uint32_t infifo_full_l1:1; + /** infifo_empty_l1 : RO; bitpos: [7]; default: 1; * Tx FIFO empty signal for Tx channel 0. */ - uint32_t infifo_empty_l1_ch0:1; - /** infifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0; + uint32_t infifo_empty_l1:1; + /** infifo_cnt_l1 : RO; bitpos: [12:8]; default: 0; * The register stores the byte number of the data in Tx FIFO for Tx channel 0. */ - uint32_t infifo_cnt_l1_ch0:5; + uint32_t infifo_cnt_l1:5; uint32_t reserved_13:3; - /** infifo_full_l3_ch0 : RO; bitpos: [16]; default: 0; + /** infifo_full_l3 : RO; bitpos: [16]; default: 0; * Tx FIFO full signal for Tx channel 0. */ - uint32_t infifo_full_l3_ch0:1; - /** infifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1; + uint32_t infifo_full_l3:1; + /** infifo_empty_l3 : RO; bitpos: [17]; default: 1; * Tx FIFO empty signal for Tx channel 0. */ - uint32_t infifo_empty_l3_ch0:1; - /** infifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0; + uint32_t infifo_empty_l3:1; + /** infifo_cnt_l3 : RO; bitpos: [19:18]; default: 0; * The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. */ - uint32_t infifo_cnt_l3_ch0:2; + uint32_t infifo_cnt_l3:2; uint32_t reserved_20:12; }; uint32_t val; -} h264_dma_infifo_status_ch0_reg_t; +} h264_dma_infifo_status_chn_reg_t; -/** Type of in_state_ch0 register +/** Type of in_state register * RX CH0 state register */ typedef union { struct { - /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; + /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; * This register stores the current inlink descriptor's address. */ - uint32_t inlink_dscr_addr_ch0:18; - /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; + uint32_t inlink_dscr_addr:18; + /** in_dscr_state : RO; bitpos: [19:18]; default: 0; * This register stores the current descriptor state machine state. */ - uint32_t in_dscr_state_ch0:2; - /** in_state_ch0 : RO; bitpos: [22:20]; default: 0; + uint32_t in_dscr_state:2; + /** in_state : RO; bitpos: [22:20]; default: 0; * This register stores the current control module state machine state. */ - uint32_t in_state_ch0:3; - /** in_reset_avail_ch0 : RO; bitpos: [23]; default: 1; + uint32_t in_state:3; + /** in_reset_avail : RO; bitpos: [23]; default: 1; * This register indicate that if the channel reset is safety. */ - uint32_t in_reset_avail_ch0:1; + uint32_t in_reset_avail:1; uint32_t reserved_24:8; }; uint32_t val; -} h264_dma_in_state_ch0_reg_t; +} h264_dma_in_state_chn_reg_t; -/** Type of in_suc_eof_des_addr_ch0 register +/** Type of in_suc_eof_des_addr register * RX CH0 eof des addr register */ typedef union { struct { - /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when the EOF bit in this * descriptor is 1. */ - uint32_t in_suc_eof_des_addr_ch0:32; + uint32_t in_suc_eof_des_addr:32; }; uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch0_reg_t; +} h264_dma_in_suc_eof_des_addr_chn_reg_t; -/** Type of in_err_eof_des_addr_ch0 register +/** Type of in_err_eof_des_addr register * RX CH0 err eof des addr register */ typedef union { struct { - /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when there are some * errors in current receiving data. */ - uint32_t in_err_eof_des_addr_ch0:32; + uint32_t in_err_eof_des_addr:32; }; uint32_t val; -} h264_dma_in_err_eof_des_addr_ch0_reg_t; +} h264_dma_in_err_eof_des_addr_chn_reg_t; -/** Type of in_dscr_ch0 register +/** Type of in_dscr register * RX CH0 next dscr addr register */ typedef union { struct { - /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr : RO; bitpos: [31:0]; default: 0; * The address of the next inlink descriptor address x. */ - uint32_t inlink_dscr_ch0:32; + uint32_t inlink_dscr:32; }; uint32_t val; -} h264_dma_in_dscr_ch0_reg_t; +} h264_dma_in_dscr_chn_reg_t; -/** Type of in_dscr_bf0_ch0 register +/** Type of in_dscr_bf0 register * RX CH0 last dscr addr register */ typedef union { struct { - /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; * The address of the last inlink descriptor's next address x-1. */ - uint32_t inlink_dscr_bf0_ch0:32; + uint32_t inlink_dscr_bf0:32; }; uint32_t val; -} h264_dma_in_dscr_bf0_ch0_reg_t; +} h264_dma_in_dscr_bf0_chn_reg_t; -/** Type of in_dscr_bf1_ch0 register +/** Type of in_dscr_bf1 register * RX CH0 second-to-last dscr addr register */ typedef union { struct { - /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; * The address of the second-to-last inlink descriptor's next address x-2. */ - uint32_t inlink_dscr_bf1_ch0:32; + uint32_t inlink_dscr_bf1:32; }; uint32_t val; -} h264_dma_in_dscr_bf1_ch0_reg_t; +} h264_dma_in_dscr_bf1_chn_reg_t; -/** Type of infifo_status_ch1 register - * RX CH1 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch1 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch1:1; - /** infifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch1:1; - /** infifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch1:4; - /** infifo_full_l1_ch1 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch1:1; - /** infifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch1:1; - /** infifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch1:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch1 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch1:1; - /** infifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch1:1; - /** infifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch1:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch1_reg_t; - -/** Type of in_state_ch1 register - * RX CH1 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch1:18; - /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch1:2; - /** in_state_ch1 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch1:3; - /** in_reset_avail_ch1 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch1:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch1_reg_t; - -/** Type of in_suc_eof_des_addr_ch1 register - * RX CH1 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch1_reg_t; - -/** Type of in_err_eof_des_addr_ch1 register - * RX CH1 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch1_reg_t; - -/** Type of in_dscr_ch1 register - * RX CH1 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch1_reg_t; - -/** Type of in_dscr_bf0_ch1 register - * RX CH1 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch1_reg_t; - -/** Type of in_dscr_bf1_ch1 register - * RX CH1 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch1_reg_t; - -/** Type of infifo_status_ch2 register - * RX CH2 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch2 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch2:1; - /** infifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch2:1; - /** infifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch2:4; - /** infifo_full_l1_ch2 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch2:1; - /** infifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch2:1; - /** infifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch2:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch2 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch2:1; - /** infifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch2:1; - /** infifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch2:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch2_reg_t; - -/** Type of in_state_ch2 register - * RX CH2 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch2:18; - /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch2:2; - /** in_state_ch2 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch2:3; - /** in_reset_avail_ch2 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch2:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch2_reg_t; - -/** Type of in_suc_eof_des_addr_ch2 register - * RX CH2 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch2:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch2_reg_t; - -/** Type of in_err_eof_des_addr_ch2 register - * RX CH2 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch2:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch2_reg_t; - -/** Type of in_dscr_ch2 register - * RX CH2 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch2_reg_t; - -/** Type of in_dscr_bf0_ch2 register - * RX CH2 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch2_reg_t; - -/** Type of in_dscr_bf1_ch2 register - * RX CH2 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch2_reg_t; - -/** Type of infifo_status_ch3 register - * RX CH3 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch3 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch3:1; - /** infifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch3:1; - /** infifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch3:4; - /** infifo_full_l1_ch3 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch3:1; - /** infifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch3:1; - /** infifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch3:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch3 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch3:1; - /** infifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch3:1; - /** infifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch3_reg_t; - -/** Type of in_state_ch3 register - * RX CH3 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch3:18; - /** in_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch3:2; - /** in_state_ch3 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch3:3; - /** in_reset_avail_ch3 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch3:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch3_reg_t; - -/** Type of in_suc_eof_des_addr_ch3 register - * RX CH3 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch3_reg_t; - -/** Type of in_err_eof_des_addr_ch3 register - * RX CH3 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch3_reg_t; - -/** Type of in_dscr_ch3 register - * RX CH3 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch3_reg_t; - -/** Type of in_dscr_bf0_ch3 register - * RX CH3 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch3_reg_t; - -/** Type of in_dscr_bf1_ch3 register - * RX CH3 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch3_reg_t; - -/** Type of infifo_status_ch4 register - * RX CH4 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch4 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch4:1; - /** infifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch4:1; - /** infifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch4:4; - /** infifo_full_l1_ch4 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch4:1; - /** infifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch4:1; - /** infifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch4:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch4 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch4:1; - /** infifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch4:1; - /** infifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch4:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch4_reg_t; - -/** Type of in_state_ch4 register - * RX CH4 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch4:18; - /** in_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch4:2; - /** in_state_ch4 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch4:3; - /** in_reset_avail_ch4 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch4:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch4_reg_t; - -/** Type of in_suc_eof_des_addr_ch4 register - * RX CH4 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch4_reg_t; - -/** Type of in_err_eof_des_addr_ch4 register - * RX CH4 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch4_reg_t; - -/** Type of in_dscr_ch4 register - * RX CH4 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch4_reg_t; - -/** Type of in_dscr_bf0_ch4 register - * RX CH4 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch4_reg_t; - -/** Type of in_dscr_bf1_ch4 register - * RX CH4 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch4_reg_t; /** Type of infifo_status_ch5 register * RX CH5 INFIFO status register */ typedef union { struct { - /** infifo_full_l1_ch5 : RO; bitpos: [0]; default: 0; + /** infifo_full_l1 : RO; bitpos: [0]; default: 0; * Tx FIFO full signal for Tx channel 1. */ - uint32_t infifo_full_l1_ch5:1; - /** infifo_empty_l1_ch5 : RO; bitpos: [1]; default: 1; + uint32_t infifo_full_l1:1; + /** infifo_empty_l1 : RO; bitpos: [1]; default: 1; * Tx FIFO empty signal for Tx channel 1. */ - uint32_t infifo_empty_l1_ch5:1; - /** infifo_cnt_l1_ch5 : RO; bitpos: [6:2]; default: 0; + uint32_t infifo_empty_l1:1; + /** infifo_cnt_l1 : RO; bitpos: [6:2]; default: 0; * The register stores the byte number of the data in Tx FIFO for Tx channel 1. */ - uint32_t infifo_cnt_l1_ch5:5; + uint32_t infifo_cnt_l1:5; uint32_t reserved_7:25; }; uint32_t val; @@ -4431,1494 +1078,335 @@ typedef union { */ typedef union { struct { - /** in_state_ch5 : RO; bitpos: [2:0]; default: 0; + /** in_state : RO; bitpos: [2:0]; default: 0; * This register stores the current control module state machine state. */ - uint32_t in_state_ch5:3; - /** in_reset_avail_ch5 : RO; bitpos: [3]; default: 1; + uint32_t in_state:3; + /** in_reset_avail : RO; bitpos: [3]; default: 1; * This register indicate that if the channel reset is safety. */ - uint32_t in_reset_avail_ch5:1; + uint32_t in_reset_avail:1; uint32_t reserved_4:28; }; uint32_t val; } h264_dma_in_state_ch5_reg_t; - -/** Group: out_link addr register */ -/** Type of out_link_addr_ch0 register - * TX CH0 out_link dscr addr register +/** Group: TX CHn config0 register */ +/** Type of out_conf0 register + * TX CHn config0 register */ typedef union { struct { - /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch0:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch0_reg_t; - - -/** Group: tx ch0 arb register */ -/** Type of out_arb_ch0 register - * TX CH0 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch0:4; - /** exter_out_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_out_arb_priority_ch0:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} h264_dma_out_arb_ch0_reg_t; - - -/** Group: TX CH0 test mode register */ -/** Type of out_mode_enable_ch0 register - * tx CH0 mode enable register - */ -typedef union { - struct { - /** out_test_mode_enable_ch0 : R/W; bitpos: [0]; default: 0; - * tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test - * mode - */ - uint32_t out_test_mode_enable_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} h264_dma_out_mode_enable_ch0_reg_t; - -/** Type of out_mode_yuv_ch0 register - * tx CH0 test mode yuv value register - */ -typedef union { - struct { - /** out_test_y_value_ch0 : R/W; bitpos: [7:0]; default: 0; - * tx CH0 test mode y value - */ - uint32_t out_test_y_value_ch0:8; - /** out_test_u_value_ch0 : R/W; bitpos: [15:8]; default: 0; - * tx CH0 test mode u value - */ - uint32_t out_test_u_value_ch0:8; - /** out_test_v_value_ch0 : R/W; bitpos: [23:16]; default: 0; - * tx CH0 test mode v value - */ - uint32_t out_test_v_value_ch0:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_mode_yuv_ch0_reg_t; - - -/** Group: ETM config register */ -/** Type of out_etm_conf_ch0 register - * TX CH0 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch0:1; - /** out_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch0:1; - /** out_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch0:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch0_reg_t; - - -/** Group: TX CH0 debug info */ -/** Type of out_buf_len_ch0 register - * tx CH0 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch0 : RO; bitpos: [12:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch0:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} h264_dma_out_buf_len_ch0_reg_t; - -/** Type of out_fifo_bcnt_ch0 register - * tx CH0 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch0 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch0:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch0_reg_t; - -/** Type of out_push_bytecnt_ch0 register - * tx CH0 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch0 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch0:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch0_reg_t; - -/** Type of out_xaddr_ch0 register - * tx CH0 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch0:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch0_reg_t; - - -/** Group: TX CH1 config0 register */ -/** Type of out_conf0_ch1 register - * TX CH1 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch1 : R/W; bitpos: [0]; default: 0; + /** out_auto_wrback : R/W; bitpos: [0]; default: 0; * Set this bit to enable automatic outlink-writeback when all the data pointed by * outlink descriptor has been received. */ - uint32_t out_auto_wrback_ch1:1; - /** out_eof_mode_ch1 : R/W; bitpos: [1]; default: 1; + uint32_t out_auto_wrback:1; + /** out_eof_mode : R/W; bitpos: [1]; default: 1; * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is * generated when data need to read has been popped from FIFO in DMA */ - uint32_t out_eof_mode_ch1:1; - /** outdscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch1:1; - /** out_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch1:1; - /** out_check_owner_ch1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch1:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 64 bytes - */ - uint32_t out_mem_burst_length_ch1:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch1:1; - uint32_t reserved_13:11; - /** out_rst_ch1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch1:1; - /** out_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch1:1; - /** out_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch1:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch1_reg_t; - - -/** Group: TX CH1 out_link dscr addr register */ -/** Type of out_link_addr_ch1 register - * TX CH1 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch1:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch1_reg_t; - - -/** Group: TX CH1 arb register */ -/** Type of out_arb_ch1 register - * TX CH1 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch1:4; - uint32_t reserved_4:2; - /** inter_out_arb_priority_ch1 : R/W; bitpos: [6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_out_arb_priority_ch1:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_arb_ch1_reg_t; - - -/** Group: TX CH1 ETM config register */ -/** Type of out_etm_conf_ch1 register - * TX CH1 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch1 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch1:1; - /** out_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch1:1; - /** out_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch1:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch1_reg_t; - - -/** Group: TX CH1 debug info */ -/** Type of out_buf_len_ch1 register - * tx CH1 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch1 : RO; bitpos: [12:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch1:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} h264_dma_out_buf_len_ch1_reg_t; - -/** Type of out_fifo_bcnt_ch1 register - * tx CH1 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch1 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch1:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch1_reg_t; - -/** Type of out_push_bytecnt_ch1 register - * tx CH1 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch1 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch1:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch1_reg_t; - -/** Type of out_xaddr_ch1 register - * tx CH1 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch1:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch1_reg_t; - - -/** Group: TX CH2 config0 register */ -/** Type of out_conf0_ch2 register - * TX CH2 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch2:1; - /** out_eof_mode_ch2 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch2:1; - /** outdscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch2:1; - /** out_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch2:1; - /** out_check_owner_ch2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch2:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch2:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch2:1; - uint32_t reserved_13:11; - /** out_rst_ch2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch2:1; - /** out_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch2:1; - /** out_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch2:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch2_reg_t; - - -/** Group: TX CH2 out_link dscr addr register */ -/** Type of out_link_addr_ch2 register - * TX CH2 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch2:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch2_reg_t; - - -/** Group: TX CH2 arb register */ -/** Type of out_arb_ch2 register - * TX CH2 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch2:4; - uint32_t reserved_4:2; - /** inter_out_arb_priority_ch2 : R/W; bitpos: [6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_out_arb_priority_ch2:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_arb_ch2_reg_t; - - -/** Group: TX CH2 ETM config register */ -/** Type of out_etm_conf_ch2 register - * TX CH2 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch2:1; - /** out_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch2:1; - /** out_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch2:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch2_reg_t; - - -/** Group: TX CH2 debug info */ -/** Type of out_buf_len_ch2 register - * tx CH2 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch2 : RO; bitpos: [12:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch2:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} h264_dma_out_buf_len_ch2_reg_t; - -/** Type of out_fifo_bcnt_ch2 register - * tx CH2 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch2 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch2:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch2_reg_t; - -/** Type of out_push_bytecnt_ch2 register - * tx CH2 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch2 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch2_reg_t; - -/** Type of out_xaddr_ch2 register - * tx CH2 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch2:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch2_reg_t; - - -/** Group: TX CH3 config0 register */ -/** Type of out_conf0_ch3 register - * TX CH3 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch3 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch3:1; - /** out_eof_mode_ch3 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch3:1; + uint32_t out_eof_mode:1; /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link * descriptor when accessing internal SRAM. */ uint32_t outdscr_burst_en_ch3:1; - /** out_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0; + /** out_ecc_aes_en : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ - uint32_t out_ecc_aes_en_ch3:1; - /** out_check_owner_ch3 : R/W; bitpos: [4]; default: 0; + uint32_t out_ecc_aes_en:1; + /** out_check_owner : R/W; bitpos: [4]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ - uint32_t out_check_owner_ch3:1; + uint32_t out_check_owner:1; uint32_t reserved_5:1; - /** out_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0; + /** out_mem_burst_length : R/W; bitpos: [8:6]; default: 0; * Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ - uint32_t out_mem_burst_length_ch3:3; + uint32_t out_mem_burst_length:3; uint32_t reserved_9:3; - /** out_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0; + /** out_page_bound_en : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI read data don't cross the address boundary which * define by mem_burst_length */ - uint32_t out_page_bound_en_ch3:1; - uint32_t reserved_13:13; - /** out_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0; + uint32_t out_page_bound_en:1; + uint32_t reserved_13:3; + /** out_reorder_en : R/W; bitpos: [16]; default: 0; + * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ + uint32_t out_reorder_en:1; + uint32_t reserved_17:7; + /** out_rst : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset TX channel + */ + uint32_t out_rst:1; + /** out_cmd_disable : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ + uint32_t out_cmd_disable:1; + /** out_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0; * Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t out_arb_weight_opt_dis_ch3:1; + uint32_t out_arb_weight_opt_dis:1; uint32_t reserved_27:5; }; uint32_t val; -} h264_dma_out_conf0_ch3_reg_t; +} h264_dma_out_conf0_chn_reg_t; -/** Group: TX CH3 out_link dscr addr register */ -/** Type of out_link_addr_ch3 register - * TX CH3 out_link dscr addr register +/** Group: TX CHn out_link dscr addr register */ +/** Type of out_link_addr register + * TX CHn out_link dscr addr register */ typedef union { struct { - /** outlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0; + /** outlink_addr : R/W; bitpos: [31:0]; default: 0; * This register stores the first outlink descriptor's address. */ - uint32_t outlink_addr_ch3:32; + uint32_t outlink_addr:32; }; uint32_t val; -} h264_dma_out_link_addr_ch3_reg_t; +} h264_dma_out_link_addr_chn_reg_t; -/** Group: TX CH3 arb register */ -/** Type of out_arb_ch3 register - * TX CH3 arb register +/** Group: TX CHn arb register */ +/** Type of out_arb register + * TX CHn arb register */ typedef union { struct { - /** out_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1; + /** out_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t out_arb_token_num_ch3:4; - /** exter_out_arb_priority_ch3 : R/W; bitpos: [5:4]; default: 1; + uint32_t out_arb_token_num:4; + /** exter_out_arb_priority : R/W; bitpos: [5:4]; default: 1; * Set the priority of channel */ - uint32_t exter_out_arb_priority_ch3:2; + uint32_t exter_out_arb_priority:2; uint32_t reserved_6:26; }; uint32_t val; -} h264_dma_out_arb_ch3_reg_t; +} h264_dma_out_arb_chn_reg_t; -/** Group: TX CH3 ETM config register */ -/** Type of out_etm_conf_ch3 register - * TX CH3 ETM config register +/** Group: TX CHn ETM config register */ +/** Type of out_etm_conf register + * TX CHn ETM config register */ typedef union { struct { - /** out_etm_en_ch3 : R/W; bitpos: [0]; default: 0; + /** out_etm_en : R/W; bitpos: [0]; default: 0; * Set this bit to 1 to enable ETM task function */ - uint32_t out_etm_en_ch3:1; - /** out_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0; + uint32_t out_etm_en:1; + /** out_etm_loop_en : R/W; bitpos: [1]; default: 0; * when this bit is 1, dscr can be processed after receiving a task */ - uint32_t out_etm_loop_en_ch3:1; - /** out_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1; + uint32_t out_etm_loop_en:1; + /** out_dscr_task_mak : R/W; bitpos: [3:2]; default: 1; * ETM dscr_ready maximum cache numbers */ - uint32_t out_dscr_task_mak_ch3:2; + uint32_t out_dscr_task_mak:2; uint32_t reserved_4:28; }; uint32_t val; -} h264_dma_out_etm_conf_ch3_reg_t; +} h264_dma_out_etm_conf_chn_reg_t; -/** Group: TX CH3 debug info */ -/** Type of out_buf_len_ch3 register - * tx CH3 buf len register +/** Group: TX CHn debug info */ +/** Type of out_buf_len register + * tx CHn buf len register */ typedef union { struct { - /** out_cmdfifo_buf_len_hb_ch3 : RO; bitpos: [12:0]; default: 0; + /** out_cmdfifo_buf_len_hb : RO; bitpos: [12:0]; default: 0; * only for debug */ - uint32_t out_cmdfifo_buf_len_hb_ch3:13; + uint32_t out_cmdfifo_buf_len_hb:13; uint32_t reserved_13:19; }; uint32_t val; -} h264_dma_out_buf_len_ch3_reg_t; +} h264_dma_out_buf_len_chn_reg_t; -/** Type of out_fifo_bcnt_ch3 register - * tx CH3 fifo byte cnt register +/** Type of out_fifo_bcnt register + * tx CHn fifo byte cnt register */ typedef union { struct { - /** out_cmdfifo_outfifo_bcnt_ch3 : RO; bitpos: [9:0]; default: 0; + /** out_cmdfifo_outfifo_bcnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t out_cmdfifo_outfifo_bcnt_ch3:10; + uint32_t out_cmdfifo_outfifo_bcnt:10; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_out_fifo_bcnt_ch3_reg_t; +} h264_dma_out_fifo_bcnt_chn_reg_t; -/** Type of out_push_bytecnt_ch3 register - * tx CH3 push byte cnt register +/** Type of out_push_bytecnt register + * tx CHn push byte cnt register */ typedef union { struct { - /** out_cmdfifo_push_bytecnt_ch3 : RO; bitpos: [7:0]; default: 63; + /** out_cmdfifo_push_bytecnt : RO; bitpos: [7:0]; default: 63; * only for debug */ - uint32_t out_cmdfifo_push_bytecnt_ch3:8; + uint32_t out_cmdfifo_push_bytecnt:8; uint32_t reserved_8:24; }; uint32_t val; -} h264_dma_out_push_bytecnt_ch3_reg_t; +} h264_dma_out_push_bytecnt_chn_reg_t; -/** Type of out_xaddr_ch3 register - * tx CH3 xaddr register +/** Type of out_xaddr register + * tx CHn xaddr register */ typedef union { struct { - /** out_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0; + /** out_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t out_cmdfifo_xaddr_ch3:32; + uint32_t out_cmdfifo_xaddr:32; }; uint32_t val; -} h264_dma_out_xaddr_ch3_reg_t; +} h264_dma_out_xaddr_chn_reg_t; -/** Type of out_block_buf_len_ch3 register - * tx CH3 block buf len register +/** Type of out_block_buf_len register + * tx CHn block buf len register */ typedef union { struct { - /** out_block_buf_len_ch3 : RO; bitpos: [27:0]; default: 0; + /** out_block_buf_len : RO; bitpos: [27:0]; default: 0; * only for debug */ - uint32_t out_block_buf_len_ch3:28; + uint32_t out_block_buf_len:28; uint32_t reserved_28:4; }; uint32_t val; -} h264_dma_out_block_buf_len_ch3_reg_t; - - -/** Group: TX CH4 config0 register */ -/** Type of out_conf0_ch4 register - * TX CH4 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch4 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch4:1; - /** out_eof_mode_ch4 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch4:1; - /** outdscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch4:1; - /** out_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch4:1; - /** out_check_owner_ch4 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch4:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch4:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch4:1; - uint32_t reserved_13:13; - /** out_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch4:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch4_reg_t; - - -/** Group: TX CH4 out_link dscr addr register */ -/** Type of out_link_addr_ch4 register - * TX CH4 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch4:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch4_reg_t; - - -/** Group: TX CH4 arb register */ -/** Type of out_arb_ch4 register - * TX CH4 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch4:4; - /** exter_out_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_out_arb_priority_ch4:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} h264_dma_out_arb_ch4_reg_t; - - -/** Group: TX CH4 ETM config register */ -/** Type of out_etm_conf_ch4 register - * TX CH4 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch4 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch4:1; - /** out_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch4:1; - /** out_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch4:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch4_reg_t; - - -/** Group: TX CH4 debug info */ -/** Type of out_buf_len_ch4 register - * tx CH4 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch4 : RO; bitpos: [12:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch4:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} h264_dma_out_buf_len_ch4_reg_t; - -/** Type of out_fifo_bcnt_ch4 register - * tx CH4 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch4 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch4:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch4_reg_t; - -/** Type of out_push_bytecnt_ch4 register - * tx CH4 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch4 : RO; bitpos: [7:0]; default: 63; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch4:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch4_reg_t; - -/** Type of out_xaddr_ch4 register - * tx CH4 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch4:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch4_reg_t; - -/** Type of out_block_buf_len_ch4 register - * tx CH4 block buf len register - */ -typedef union { - struct { - /** out_block_buf_len_ch4 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_block_buf_len_ch4:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_block_buf_len_ch4_reg_t; +} h264_dma_out_block_buf_len_chn_reg_t; /** Group: RX CH0 in_link dscr addr register */ -/** Type of in_link_addr_ch0 register +/** Type of in_link_addr register * RX CH0 in_link dscr addr register */ typedef union { struct { - /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; + /** inlink_addr : R/W; bitpos: [31:0]; default: 0; * This register stores the first inlink descriptor's address. */ - uint32_t inlink_addr_ch0:32; + uint32_t inlink_addr:32; }; uint32_t val; -} h264_dma_in_link_addr_ch0_reg_t; +} h264_dma_in_link_addr_chn_reg_t; /** Group: RX CH0 arb register */ -/** Type of in_arb_ch0 register +/** Type of in_arb register * RX CH0 arb register */ typedef union { struct { - /** in_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1; + /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t in_arb_token_num_ch0:4; - /** exter_in_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1; + uint32_t in_arb_token_num:4; + /** exter_in_arb_priority : R/W; bitpos: [5:4]; default: 1; * Set the priority of channel */ - uint32_t exter_in_arb_priority_ch0:2; - /** inter_in_arb_priority_ch0 : R/W; bitpos: [8:6]; default: 1; + uint32_t exter_in_arb_priority:2; + /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1; * Set the priority of channel */ - uint32_t inter_in_arb_priority_ch0:3; + uint32_t inter_in_arb_priority:3; uint32_t reserved_9:23; }; uint32_t val; -} h264_dma_in_arb_ch0_reg_t; +} h264_dma_in_arb_chn_reg_t; /** Group: RX CH0 ETM config register */ -/** Type of in_etm_conf_ch0 register +/** Type of in_etm_conf register * RX CH0 ETM config register */ typedef union { struct { - /** in_etm_en_ch0 : R/W; bitpos: [0]; default: 0; + /** in_etm_en : R/W; bitpos: [0]; default: 0; * Set this bit to 1 to enable ETM task function */ - uint32_t in_etm_en_ch0:1; - /** in_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0; + uint32_t in_etm_en:1; + /** in_etm_loop_en : R/W; bitpos: [1]; default: 0; * when this bit is 1, dscr can be processed after receiving a task */ - uint32_t in_etm_loop_en_ch0:1; - /** in_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1; + uint32_t in_etm_loop_en:1; + /** in_dscr_task_mak : R/W; bitpos: [3:2]; default: 1; * ETM dscr_ready maximum cache numbers */ - uint32_t in_dscr_task_mak_ch0:2; + uint32_t in_dscr_task_mak:2; uint32_t reserved_4:28; }; uint32_t val; -} h264_dma_in_etm_conf_ch0_reg_t; +} h264_dma_in_etm_conf_chn_reg_t; /** Group: RX CH0 debug info */ -/** Type of in_fifo_cnt_ch0 register +/** Type of in_fifo_cnt register * rx CH0 fifo cnt register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch0 : RO; bitpos: [9:0]; default: 0; + /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_infifo_cnt_ch0:10; + uint32_t in_cmdfifo_infifo_cnt:10; uint32_t reserved_10:22; }; uint32_t val; -} h264_dma_in_fifo_cnt_ch0_reg_t; +} h264_dma_in_fifo_cnt_chn_reg_t; -/** Type of in_pop_data_cnt_ch0 register +/** Type of in_pop_data_cnt register * rx CH0 pop data cnt register */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch0 : RO; bitpos: [7:0]; default: 7; + /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 7; * only for debug */ - uint32_t in_cmdfifo_pop_data_cnt_ch0:8; + uint32_t in_cmdfifo_pop_data_cnt:8; uint32_t reserved_8:24; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch0_reg_t; +} h264_dma_in_pop_data_cnt_chn_reg_t; -/** Type of in_xaddr_ch0 register +/** Type of in_xaddr register * rx CH0 xaddr register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0; + /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_xaddr_ch0:32; + uint32_t in_cmdfifo_xaddr:32; }; uint32_t val; -} h264_dma_in_xaddr_ch0_reg_t; +} h264_dma_in_xaddr_chn_reg_t; -/** Type of in_buf_hb_rcv_ch0 register +/** Type of in_buf_hb_rcv register * rx CH0 buf len hb rcv register */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch0 : RO; bitpos: [28:0]; default: 0; + /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_buf_hb_rcv_ch0:29; + uint32_t in_cmdfifo_buf_hb_rcv:29; uint32_t reserved_29:3; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch0_reg_t; - - -/** Group: RX CH1 in_link dscr addr register */ -/** Type of in_link_addr_ch1 register - * RX CH1 in_link dscr addr register - */ -typedef union { - struct { - /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_ch1:32; - }; - uint32_t val; -} h264_dma_in_link_addr_ch1_reg_t; - - -/** Group: RX CH1 arb register */ -/** Type of in_arb_ch1 register - * RX CH1 arb register - */ -typedef union { - struct { - /** in_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_ch1:4; - /** exter_in_arb_priority_ch1 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_in_arb_priority_ch1:2; - /** inter_in_arb_priority_ch1 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_in_arb_priority_ch1:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_in_arb_ch1_reg_t; - - -/** Group: RX CH1 ETM config register */ -/** Type of in_etm_conf_ch1 register - * RX CH1 ETM config register - */ -typedef union { - struct { - /** in_etm_en_ch1 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t in_etm_en_ch1:1; - /** in_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t in_etm_loop_en_ch1:1; - /** in_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t in_dscr_task_mak_ch1:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_in_etm_conf_ch1_reg_t; - - -/** Group: RX CH1 debug info */ -/** Type of in_fifo_cnt_ch1 register - * rx CH1 fifo cnt register - */ -typedef union { - struct { - /** in_cmdfifo_infifo_cnt_ch1 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_infifo_cnt_ch1:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_fifo_cnt_ch1_reg_t; - -/** Type of in_pop_data_cnt_ch1 register - * rx CH1 pop data cnt register - */ -typedef union { - struct { - /** in_cmdfifo_pop_data_cnt_ch1 : RO; bitpos: [7:0]; default: 7; - * only for debug - */ - uint32_t in_cmdfifo_pop_data_cnt_ch1:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_in_pop_data_cnt_ch1_reg_t; - -/** Type of in_xaddr_ch1 register - * rx CH1 xaddr register - */ -typedef union { - struct { - /** in_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_xaddr_ch1:32; - }; - uint32_t val; -} h264_dma_in_xaddr_ch1_reg_t; - -/** Type of in_buf_hb_rcv_ch1 register - * rx CH1 buf len hb rcv register - */ -typedef union { - struct { - /** in_cmdfifo_buf_hb_rcv_ch1 : RO; bitpos: [28:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_buf_hb_rcv_ch1:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_dma_in_buf_hb_rcv_ch1_reg_t; - - -/** Group: RX CH2 in_link dscr addr register */ -/** Type of in_link_addr_ch2 register - * RX CH2 in_link dscr addr register - */ -typedef union { - struct { - /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_ch2:32; - }; - uint32_t val; -} h264_dma_in_link_addr_ch2_reg_t; - - -/** Group: RX CH2 arb register */ -/** Type of in_arb_ch2 register - * RX CH2 arb register - */ -typedef union { - struct { - /** in_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_ch2:4; - uint32_t reserved_4:2; - /** inter_in_arb_priority_ch2 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_in_arb_priority_ch2:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_in_arb_ch2_reg_t; - - -/** Group: RX CH2 ETM config register */ -/** Type of in_etm_conf_ch2 register - * RX CH2 ETM config register - */ -typedef union { - struct { - /** in_etm_en_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t in_etm_en_ch2:1; - /** in_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t in_etm_loop_en_ch2:1; - /** in_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t in_dscr_task_mak_ch2:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_in_etm_conf_ch2_reg_t; - - -/** Group: RX CH2 debug info */ -/** Type of in_fifo_cnt_ch2 register - * rx CH2 fifo cnt register - */ -typedef union { - struct { - /** in_cmdfifo_infifo_cnt_ch2 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_infifo_cnt_ch2:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_fifo_cnt_ch2_reg_t; - -/** Type of in_pop_data_cnt_ch2 register - * rx CH2 pop data cnt register - */ -typedef union { - struct { - /** in_cmdfifo_pop_data_cnt_ch2 : RO; bitpos: [7:0]; default: 7; - * only for debug - */ - uint32_t in_cmdfifo_pop_data_cnt_ch2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_in_pop_data_cnt_ch2_reg_t; - -/** Type of in_xaddr_ch2 register - * rx CH2 xaddr register - */ -typedef union { - struct { - /** in_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_xaddr_ch2:32; - }; - uint32_t val; -} h264_dma_in_xaddr_ch2_reg_t; - -/** Type of in_buf_hb_rcv_ch2 register - * rx CH2 buf len hb rcv register - */ -typedef union { - struct { - /** in_cmdfifo_buf_hb_rcv_ch2 : RO; bitpos: [28:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_buf_hb_rcv_ch2:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_dma_in_buf_hb_rcv_ch2_reg_t; - - -/** Group: RX CH3 in_link dscr addr register */ -/** Type of in_link_addr_ch3 register - * RX CH3 in_link dscr addr register - */ -typedef union { - struct { - /** inlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_ch3:32; - }; - uint32_t val; -} h264_dma_in_link_addr_ch3_reg_t; - - -/** Group: RX CH3 arb register */ -/** Type of in_arb_ch3 register - * RX CH3 arb register - */ -typedef union { - struct { - /** in_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_ch3:4; - uint32_t reserved_4:2; - /** inter_in_arb_priority_ch3 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_in_arb_priority_ch3:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_in_arb_ch3_reg_t; - - -/** Group: RX CH3 ETM config register */ -/** Type of in_etm_conf_ch3 register - * RX CH3 ETM config register - */ -typedef union { - struct { - /** in_etm_en_ch3 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t in_etm_en_ch3:1; - /** in_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t in_etm_loop_en_ch3:1; - /** in_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t in_dscr_task_mak_ch3:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_in_etm_conf_ch3_reg_t; - - -/** Group: RX CH3 debug info */ -/** Type of in_fifo_cnt_ch3 register - * rx CH3 fifo cnt register - */ -typedef union { - struct { - /** in_cmdfifo_infifo_cnt_ch3 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_infifo_cnt_ch3:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_fifo_cnt_ch3_reg_t; - -/** Type of in_pop_data_cnt_ch3 register - * rx CH3 pop data cnt register - */ -typedef union { - struct { - /** in_cmdfifo_pop_data_cnt_ch3 : RO; bitpos: [7:0]; default: 7; - * only for debug - */ - uint32_t in_cmdfifo_pop_data_cnt_ch3:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_in_pop_data_cnt_ch3_reg_t; - -/** Type of in_xaddr_ch3 register - * rx CH3 xaddr register - */ -typedef union { - struct { - /** in_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_xaddr_ch3:32; - }; - uint32_t val; -} h264_dma_in_xaddr_ch3_reg_t; - -/** Type of in_buf_hb_rcv_ch3 register - * rx CH3 buf len hb rcv register - */ -typedef union { - struct { - /** in_cmdfifo_buf_hb_rcv_ch3 : RO; bitpos: [28:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_buf_hb_rcv_ch3:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_dma_in_buf_hb_rcv_ch3_reg_t; - - -/** Group: RX CH4 in_link dscr addr register */ -/** Type of in_link_addr_ch4 register - * RX CH4 in_link dscr addr register - */ -typedef union { - struct { - /** inlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_ch4:32; - }; - uint32_t val; -} h264_dma_in_link_addr_ch4_reg_t; - - -/** Group: RX CH4 arb register */ -/** Type of in_arb_ch4 register - * RX CH4 arb register - */ -typedef union { - struct { - /** in_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_ch4:4; - /** exter_in_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_in_arb_priority_ch4:2; - /** inter_in_arb_priority_ch4 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_in_arb_priority_ch4:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_in_arb_ch4_reg_t; - - -/** Group: RX CH4 ETM config register */ -/** Type of in_etm_conf_ch4 register - * RX CH4 ETM config register - */ -typedef union { - struct { - /** in_etm_en_ch4 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t in_etm_en_ch4:1; - /** in_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t in_etm_loop_en_ch4:1; - /** in_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t in_dscr_task_mak_ch4:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_in_etm_conf_ch4_reg_t; - - -/** Group: RX CH4 debug info */ -/** Type of in_fifo_cnt_ch4 register - * rx CH4 fifo cnt register - */ -typedef union { - struct { - /** in_cmdfifo_infifo_cnt_ch4 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_infifo_cnt_ch4:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_fifo_cnt_ch4_reg_t; - -/** Type of in_pop_data_cnt_ch4 register - * rx CH4 pop data cnt register - */ -typedef union { - struct { - /** in_cmdfifo_pop_data_cnt_ch4 : RO; bitpos: [7:0]; default: 7; - * only for debug - */ - uint32_t in_cmdfifo_pop_data_cnt_ch4:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_in_pop_data_cnt_ch4_reg_t; - -/** Type of in_xaddr_ch4 register - * rx CH4 xaddr register - */ -typedef union { - struct { - /** in_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_xaddr_ch4:32; - }; - uint32_t val; -} h264_dma_in_xaddr_ch4_reg_t; - -/** Type of in_buf_hb_rcv_ch4 register - * rx CH4 buf len hb rcv register - */ -typedef union { - struct { - /** in_cmdfifo_buf_hb_rcv_ch4 : RO; bitpos: [28:0]; default: 0; - * only for debug - */ - uint32_t in_cmdfifo_buf_hb_rcv_ch4:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_dma_in_buf_hb_rcv_ch4_reg_t; - +} h264_dma_in_buf_hb_rcv_chn_reg_t; /** Group: RX CH5 config1 register */ /** Type of in_conf1_ch5 register @@ -5926,10 +1414,10 @@ typedef union { */ typedef union { struct { - /** block_start_addr_ch5 : R/W; bitpos: [31:0]; default: 0; + /** block_start_addr : R/W; bitpos: [31:0]; default: 0; * RX Channel 5 destination start address */ - uint32_t block_start_addr_ch5:32; + uint32_t block_start_addr:32; }; uint32_t val; } h264_dma_in_conf1_ch5_reg_t; @@ -5941,14 +1429,14 @@ typedef union { */ typedef union { struct { - /** block_row_length_12line_ch5 : R/W; bitpos: [15:0]; default: 30720; + /** block_row_length_12line : R/W; bitpos: [15:0]; default: 30720; * The number of bytes contained in a row block 12line in RX channel 5 */ - uint32_t block_row_length_12line_ch5:16; - /** block_row_length_4line_ch5 : R/W; bitpos: [31:16]; default: 15360; + uint32_t block_row_length_12line:16; + /** block_row_length_4line : R/W; bitpos: [31:16]; default: 15360; * The number of bytes contained in a row block 4line in RX channel 5 */ - uint32_t block_row_length_4line_ch5:16; + uint32_t block_row_length_4line:16; }; uint32_t val; } h264_dma_in_conf2_ch5_reg_t; @@ -5960,14 +1448,14 @@ typedef union { */ typedef union { struct { - /** block_length_12line_ch5 : R/W; bitpos: [13:0]; default: 256; + /** block_length_12line : R/W; bitpos: [13:0]; default: 256; * The number of bytes contained in a block 12line */ - uint32_t block_length_12line_ch5:14; - /** block_length_4line_ch5 : R/W; bitpos: [27:14]; default: 128; + uint32_t block_length_12line:14; + /** block_length_4line : R/W; bitpos: [27:14]; default: 128; * The number of bytes contained in a block 4line */ - uint32_t block_length_4line_ch5:14; + uint32_t block_length_4line:14; uint32_t reserved_28:4; }; uint32_t val; @@ -5980,15 +1468,15 @@ typedef union { */ typedef union { struct { - /** in_arb_token_num_ch5 : R/W; bitpos: [3:0]; default: 1; + /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t in_arb_token_num_ch5:4; + uint32_t in_arb_token_num:4; uint32_t reserved_4:2; - /** inter_in_arb_priority_ch5 : R/W; bitpos: [8:6]; default: 1; + /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1; * Set the priority of channel */ - uint32_t inter_in_arb_priority_ch5:3; + uint32_t inter_in_arb_priority:3; uint32_t reserved_9:23; }; uint32_t val; @@ -6001,10 +1489,10 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch5 : RO; bitpos: [9:0]; default: 0; + /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_infifo_cnt_ch5:10; + uint32_t in_cmdfifo_infifo_cnt:10; uint32_t reserved_10:22; }; uint32_t val; @@ -6015,10 +1503,10 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch5 : RO; bitpos: [7:0]; default: 255; + /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 255; * only for debug */ - uint32_t in_cmdfifo_pop_data_cnt_ch5:8; + uint32_t in_cmdfifo_pop_data_cnt:8; uint32_t reserved_8:24; }; uint32_t val; @@ -6029,10 +1517,10 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_xaddr_ch5 : RO; bitpos: [31:0]; default: 0; + /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_xaddr_ch5:32; + uint32_t in_cmdfifo_xaddr:32; }; uint32_t val; } h264_dma_in_xaddr_ch5_reg_t; @@ -6042,10 +1530,10 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch5 : RO; bitpos: [28:0]; default: 0; + /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_buf_hb_rcv_ch5:29; + uint32_t in_cmdfifo_buf_hb_rcv:29; uint32_t reserved_29:3; }; uint32_t val; @@ -6133,153 +1621,51 @@ typedef union { /** Group: dscr addr range register */ -/** Type of inter_mem_start_addr0 register - * Start address of inter memory range0 register +/** Type of mem_start_addr register + * Start address of inter memory range register */ typedef union { struct { - /** access_inter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944; + /** access_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; * The start address of accessible address space. */ - uint32_t access_inter_mem_start_addr0:32; + uint32_t access_mem_start_addr:32; }; uint32_t val; -} h264_dma_inter_mem_start_addr0_reg_t; +} h264_dma_mem_start_addr_reg_t; -/** Type of inter_mem_end_addr0 register - * end address of inter memory range0 register +/** Type of mem_end_addr register + * end address of inter memory range register */ typedef union { struct { - /** access_inter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103; + /** access_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; * The end address of accessible address space. The access address beyond this range * would lead to descriptor error. */ - uint32_t access_inter_mem_end_addr0:32; + uint32_t access_mem_end_addr:32; }; uint32_t val; -} h264_dma_inter_mem_end_addr0_reg_t; +} h264_dma_mem_end_addr_reg_t; -/** Type of inter_mem_start_addr1 register - * Start address of inter memory range1 register - */ -typedef union { - struct { - /** access_inter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_inter_mem_start_addr1:32; - }; - uint32_t val; -} h264_dma_inter_mem_start_addr1_reg_t; - -/** Type of inter_mem_end_addr1 register - * end address of inter memory range1 register - */ -typedef union { - struct { - /** access_inter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_inter_mem_end_addr1:32; - }; - uint32_t val; -} h264_dma_inter_mem_end_addr1_reg_t; - -/** Type of exter_mem_start_addr0 register - * Start address of exter memory range0 register - */ -typedef union { - struct { - /** access_exter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_exter_mem_start_addr0:32; - }; - uint32_t val; -} h264_dma_exter_mem_start_addr0_reg_t; - -/** Type of exter_mem_end_addr0 register - * end address of exter memory range0 register - */ -typedef union { - struct { - /** access_exter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_exter_mem_end_addr0:32; - }; - uint32_t val; -} h264_dma_exter_mem_end_addr0_reg_t; - -/** Type of exter_mem_start_addr1 register - * Start address of exter memory range1 register - */ -typedef union { - struct { - /** access_exter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_exter_mem_start_addr1:32; - }; - uint32_t val; -} h264_dma_exter_mem_start_addr1_reg_t; - -/** Type of exter_mem_end_addr1 register - * end address of exter memory range1 register - */ -typedef union { - struct { - /** access_exter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_exter_mem_end_addr1:32; - }; - uint32_t val; -} h264_dma_exter_mem_end_addr1_reg_t; - - -/** Group: out arb config register */ -/** Type of out_arb_config register +/** Group: arb config register */ +/** Type of arb_config register * reserved */ typedef union { struct { - /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; + /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; * Set the max number of timeout count of arbiter */ - uint32_t out_arb_timeout_num:16; - /** out_weight_en : R/W; bitpos: [16]; default: 0; + uint32_t arb_timeout_num:16; + /** weight_en : R/W; bitpos: [16]; default: 0; * reserved */ - uint32_t out_weight_en:1; + uint32_t weight_en:1; uint32_t reserved_17:15; }; uint32_t val; -} h264_dma_out_arb_config_reg_t; - - -/** Group: in arb config register */ -/** Type of in_arb_config register - * reserved - */ -typedef union { - struct { - /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t in_arb_timeout_num:16; - /** in_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t in_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} h264_dma_in_arb_config_reg_t; +} h264_dma_arb_config_reg_t; /** Group: date register */ @@ -6384,293 +1770,102 @@ typedef union { typedef struct { - volatile h264_dma_out_conf0_ch0_reg_t out_conf0_ch0; - volatile h264_dma_out_int_raw_ch0_reg_t out_int_raw_ch0; - volatile h264_dma_out_int_ena_ch0_reg_t out_int_ena_ch0; - volatile h264_dma_out_int_st_ch0_reg_t out_int_st_ch0; - volatile h264_dma_out_int_clr_ch0_reg_t out_int_clr_ch0; - volatile h264_dma_outfifo_status_ch0_reg_t outfifo_status_ch0; - volatile h264_dma_out_push_ch0_reg_t out_push_ch0; - volatile h264_dma_out_link_conf_ch0_reg_t out_link_conf_ch0; - volatile h264_dma_out_link_addr_ch0_reg_t out_link_addr_ch0; - volatile h264_dma_out_state_ch0_reg_t out_state_ch0; - volatile h264_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0; - volatile h264_dma_out_dscr_ch0_reg_t out_dscr_ch0; - volatile h264_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0; - volatile h264_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0; - uint32_t reserved_038; - volatile h264_dma_out_arb_ch0_reg_t out_arb_ch0; - volatile h264_dma_out_ro_status_ch0_reg_t out_ro_status_ch0; - volatile h264_dma_out_ro_pd_conf_ch0_reg_t out_ro_pd_conf_ch0; - uint32_t reserved_048[2]; - volatile h264_dma_out_mode_enable_ch0_reg_t out_mode_enable_ch0; - volatile h264_dma_out_mode_yuv_ch0_reg_t out_mode_yuv_ch0; - uint32_t reserved_058[4]; - volatile h264_dma_out_etm_conf_ch0_reg_t out_etm_conf_ch0; - uint32_t reserved_06c; - volatile h264_dma_out_buf_len_ch0_reg_t out_buf_len_ch0; - volatile h264_dma_out_fifo_bcnt_ch0_reg_t out_fifo_bcnt_ch0; - volatile h264_dma_out_push_bytecnt_ch0_reg_t out_push_bytecnt_ch0; - volatile h264_dma_out_xaddr_ch0_reg_t out_xaddr_ch0; - uint32_t reserved_080[32]; - volatile h264_dma_out_conf0_ch1_reg_t out_conf0_ch1; - volatile h264_dma_out_int_raw_ch1_reg_t out_int_raw_ch1; - volatile h264_dma_out_int_ena_ch1_reg_t out_int_ena_ch1; - volatile h264_dma_out_int_st_ch1_reg_t out_int_st_ch1; - volatile h264_dma_out_int_clr_ch1_reg_t out_int_clr_ch1; - volatile h264_dma_outfifo_status_ch1_reg_t outfifo_status_ch1; - volatile h264_dma_out_push_ch1_reg_t out_push_ch1; - volatile h264_dma_out_link_conf_ch1_reg_t out_link_conf_ch1; - volatile h264_dma_out_link_addr_ch1_reg_t out_link_addr_ch1; - volatile h264_dma_out_state_ch1_reg_t out_state_ch1; - volatile h264_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1; - volatile h264_dma_out_dscr_ch1_reg_t out_dscr_ch1; - volatile h264_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1; - volatile h264_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1; - uint32_t reserved_138; - volatile h264_dma_out_arb_ch1_reg_t out_arb_ch1; - uint32_t reserved_140[10]; - volatile h264_dma_out_etm_conf_ch1_reg_t out_etm_conf_ch1; - uint32_t reserved_16c; - volatile h264_dma_out_buf_len_ch1_reg_t out_buf_len_ch1; - volatile h264_dma_out_fifo_bcnt_ch1_reg_t out_fifo_bcnt_ch1; - volatile h264_dma_out_push_bytecnt_ch1_reg_t out_push_bytecnt_ch1; - volatile h264_dma_out_xaddr_ch1_reg_t out_xaddr_ch1; - uint32_t reserved_180[32]; - volatile h264_dma_out_conf0_ch2_reg_t out_conf0_ch2; - volatile h264_dma_out_int_raw_ch2_reg_t out_int_raw_ch2; - volatile h264_dma_out_int_ena_ch2_reg_t out_int_ena_ch2; - volatile h264_dma_out_int_st_ch2_reg_t out_int_st_ch2; - volatile h264_dma_out_int_clr_ch2_reg_t out_int_clr_ch2; - volatile h264_dma_outfifo_status_ch2_reg_t outfifo_status_ch2; - volatile h264_dma_out_push_ch2_reg_t out_push_ch2; - volatile h264_dma_out_link_conf_ch2_reg_t out_link_conf_ch2; - volatile h264_dma_out_link_addr_ch2_reg_t out_link_addr_ch2; - volatile h264_dma_out_state_ch2_reg_t out_state_ch2; - volatile h264_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2; - volatile h264_dma_out_dscr_ch2_reg_t out_dscr_ch2; - volatile h264_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2; - volatile h264_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2; - uint32_t reserved_238; - volatile h264_dma_out_arb_ch2_reg_t out_arb_ch2; - uint32_t reserved_240[10]; - volatile h264_dma_out_etm_conf_ch2_reg_t out_etm_conf_ch2; - uint32_t reserved_26c; - volatile h264_dma_out_buf_len_ch2_reg_t out_buf_len_ch2; - volatile h264_dma_out_fifo_bcnt_ch2_reg_t out_fifo_bcnt_ch2; - volatile h264_dma_out_push_bytecnt_ch2_reg_t out_push_bytecnt_ch2; - volatile h264_dma_out_xaddr_ch2_reg_t out_xaddr_ch2; - uint32_t reserved_280[32]; - volatile h264_dma_out_conf0_ch3_reg_t out_conf0_ch3; - volatile h264_dma_out_int_raw_ch3_reg_t out_int_raw_ch3; - volatile h264_dma_out_int_ena_ch3_reg_t out_int_ena_ch3; - volatile h264_dma_out_int_st_ch3_reg_t out_int_st_ch3; - volatile h264_dma_out_int_clr_ch3_reg_t out_int_clr_ch3; - volatile h264_dma_outfifo_status_ch3_reg_t outfifo_status_ch3; - volatile h264_dma_out_push_ch3_reg_t out_push_ch3; - volatile h264_dma_out_link_conf_ch3_reg_t out_link_conf_ch3; - volatile h264_dma_out_link_addr_ch3_reg_t out_link_addr_ch3; - volatile h264_dma_out_state_ch3_reg_t out_state_ch3; - volatile h264_dma_out_eof_des_addr_ch3_reg_t out_eof_des_addr_ch3; - volatile h264_dma_out_dscr_ch3_reg_t out_dscr_ch3; - volatile h264_dma_out_dscr_bf0_ch3_reg_t out_dscr_bf0_ch3; - volatile h264_dma_out_dscr_bf1_ch3_reg_t out_dscr_bf1_ch3; + volatile h264_dma_out_conf0_chn_reg_t conf0; + volatile h264_dma_out_int_raw_chn_reg_t int_raw; + volatile h264_dma_out_int_ena_chn_reg_t int_ena; + volatile h264_dma_out_int_st_chn_reg_t int_st; + volatile h264_dma_out_int_clr_chn_reg_t int_clr; + volatile h264_dma_outfifo_status_reg_t outfifo_status; + volatile h264_dma_out_push_chn_reg_t push; + volatile h264_dma_out_link_conf_chn_reg_t link_conf; + volatile h264_dma_out_link_addr_chn_reg_t link_addr; + volatile h264_dma_out_state_chn_reg_t state; + volatile h264_dma_out_eof_des_addr_chn_reg_t eof_des_addr; + volatile h264_dma_out_dscr_chn_reg_t dscr; + volatile h264_dma_out_dscr_bf0_chn_reg_t dscr_bf0; + volatile h264_dma_out_dscr_bf1_chn_reg_t dscr_bf1; uint32_t reserved_338; - volatile h264_dma_out_arb_ch3_reg_t out_arb_ch3; + volatile h264_dma_out_arb_chn_reg_t arb; uint32_t reserved_340[10]; - volatile h264_dma_out_etm_conf_ch3_reg_t out_etm_conf_ch3; + volatile h264_dma_out_etm_conf_chn_reg_t etm_conf; uint32_t reserved_36c; - volatile h264_dma_out_buf_len_ch3_reg_t out_buf_len_ch3; - volatile h264_dma_out_fifo_bcnt_ch3_reg_t out_fifo_bcnt_ch3; - volatile h264_dma_out_push_bytecnt_ch3_reg_t out_push_bytecnt_ch3; - volatile h264_dma_out_xaddr_ch3_reg_t out_xaddr_ch3; - volatile h264_dma_out_block_buf_len_ch3_reg_t out_block_buf_len_ch3; + volatile h264_dma_out_buf_len_chn_reg_t buf_len; + volatile h264_dma_out_fifo_bcnt_chn_reg_t fifo_bcnt; + volatile h264_dma_out_push_bytecnt_chn_reg_t push_bytecnt; + volatile h264_dma_out_xaddr_chn_reg_t xaddr; + volatile h264_dma_out_block_buf_len_chn_reg_t block_buf_len; // Please note that this reg only exists on out[3] and out[4] uint32_t reserved_384[31]; - volatile h264_dma_out_conf0_ch4_reg_t out_conf0_ch4; - volatile h264_dma_out_int_raw_ch4_reg_t out_int_raw_ch4; - volatile h264_dma_out_int_ena_ch4_reg_t out_int_ena_ch4; - volatile h264_dma_out_int_st_ch4_reg_t out_int_st_ch4; - volatile h264_dma_out_int_clr_ch4_reg_t out_int_clr_ch4; - volatile h264_dma_outfifo_status_ch4_reg_t outfifo_status_ch4; - volatile h264_dma_out_push_ch4_reg_t out_push_ch4; - volatile h264_dma_out_link_conf_ch4_reg_t out_link_conf_ch4; - volatile h264_dma_out_link_addr_ch4_reg_t out_link_addr_ch4; - volatile h264_dma_out_state_ch4_reg_t out_state_ch4; - volatile h264_dma_out_eof_des_addr_ch4_reg_t out_eof_des_addr_ch4; - volatile h264_dma_out_dscr_ch4_reg_t out_dscr_ch4; - volatile h264_dma_out_dscr_bf0_ch4_reg_t out_dscr_bf0_ch4; - volatile h264_dma_out_dscr_bf1_ch4_reg_t out_dscr_bf1_ch4; - uint32_t reserved_438; - volatile h264_dma_out_arb_ch4_reg_t out_arb_ch4; - uint32_t reserved_440[10]; - volatile h264_dma_out_etm_conf_ch4_reg_t out_etm_conf_ch4; - uint32_t reserved_46c; - volatile h264_dma_out_buf_len_ch4_reg_t out_buf_len_ch4; - volatile h264_dma_out_fifo_bcnt_ch4_reg_t out_fifo_bcnt_ch4; - volatile h264_dma_out_push_bytecnt_ch4_reg_t out_push_bytecnt_ch4; - volatile h264_dma_out_xaddr_ch4_reg_t out_xaddr_ch4; - volatile h264_dma_out_block_buf_len_ch4_reg_t out_block_buf_len_ch4; - uint32_t reserved_484[31]; - volatile h264_dma_in_conf0_ch0_reg_t in_conf0_ch0; - volatile h264_dma_in_int_raw_ch0_reg_t in_int_raw_ch0; - volatile h264_dma_in_int_ena_ch0_reg_t in_int_ena_ch0; - volatile h264_dma_in_int_st_ch0_reg_t in_int_st_ch0; - volatile h264_dma_in_int_clr_ch0_reg_t in_int_clr_ch0; - volatile h264_dma_infifo_status_ch0_reg_t infifo_status_ch0; - volatile h264_dma_in_pop_ch0_reg_t in_pop_ch0; - volatile h264_dma_in_link_conf_ch0_reg_t in_link_conf_ch0; - volatile h264_dma_in_link_addr_ch0_reg_t in_link_addr_ch0; - volatile h264_dma_in_state_ch0_reg_t in_state_ch0; - volatile h264_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0; - volatile h264_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0; - volatile h264_dma_in_dscr_ch0_reg_t in_dscr_ch0; - volatile h264_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0; - volatile h264_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0; +} h264_dma_out_chn_regs_t; + +typedef struct { + volatile h264_dma_in_conf0_chn_reg_t conf0; + volatile h264_dma_in_int_raw_chn_reg_t int_raw; + volatile h264_dma_in_int_ena_chn_reg_t int_ena; + volatile h264_dma_in_int_st_chn_reg_t int_st; + volatile h264_dma_in_int_clr_chn_reg_t int_clr; + volatile h264_dma_infifo_status_chn_reg_t infifo_status; + volatile h264_dma_in_pop_chn_reg_t pop; + volatile h264_dma_in_link_conf_chn_reg_t link_conf; + volatile h264_dma_in_link_addr_chn_reg_t link_addr; + volatile h264_dma_in_state_chn_reg_t state; + volatile h264_dma_in_suc_eof_des_addr_chn_reg_t suc_eof_des_addr; + volatile h264_dma_in_err_eof_des_addr_chn_reg_t err_eof_des_addr; + volatile h264_dma_in_dscr_chn_reg_t dscr; + volatile h264_dma_in_dscr_bf0_chn_reg_t dscr_bf0; + volatile h264_dma_in_dscr_bf1_chn_reg_t dscr_bf1; uint32_t reserved_53c; - volatile h264_dma_in_arb_ch0_reg_t in_arb_ch0; + volatile h264_dma_in_arb_chn_reg_t arb; uint32_t reserved_544; - volatile h264_dma_in_ro_pd_conf_ch0_reg_t in_ro_pd_conf_ch0; + volatile h264_dma_in_ro_pd_conf_chn_reg_t ro_pd_conf; uint32_t reserved_54c[8]; - volatile h264_dma_in_etm_conf_ch0_reg_t in_etm_conf_ch0; + volatile h264_dma_in_etm_conf_chn_reg_t etm_conf; uint32_t reserved_570[4]; - volatile h264_dma_in_fifo_cnt_ch0_reg_t in_fifo_cnt_ch0; - volatile h264_dma_in_pop_data_cnt_ch0_reg_t in_pop_data_cnt_ch0; - volatile h264_dma_in_xaddr_ch0_reg_t in_xaddr_ch0; - volatile h264_dma_in_buf_hb_rcv_ch0_reg_t in_buf_hb_rcv_ch0; + volatile h264_dma_in_fifo_cnt_chn_reg_t fifo_cnt; + volatile h264_dma_in_pop_data_cnt_chn_reg_t pop_data_cnt; + volatile h264_dma_in_xaddr_chn_reg_t xaddr; + volatile h264_dma_in_buf_hb_rcv_chn_reg_t buf_hb_rcv; uint32_t reserved_590[28]; - volatile h264_dma_in_conf0_ch1_reg_t in_conf0_ch1; - volatile h264_dma_in_int_raw_ch1_reg_t in_int_raw_ch1; - volatile h264_dma_in_int_ena_ch1_reg_t in_int_ena_ch1; - volatile h264_dma_in_int_st_ch1_reg_t in_int_st_ch1; - volatile h264_dma_in_int_clr_ch1_reg_t in_int_clr_ch1; - volatile h264_dma_infifo_status_ch1_reg_t infifo_status_ch1; - volatile h264_dma_in_pop_ch1_reg_t in_pop_ch1; - volatile h264_dma_in_link_conf_ch1_reg_t in_link_conf_ch1; - volatile h264_dma_in_link_addr_ch1_reg_t in_link_addr_ch1; - volatile h264_dma_in_state_ch1_reg_t in_state_ch1; - volatile h264_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1; - volatile h264_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1; - volatile h264_dma_in_dscr_ch1_reg_t in_dscr_ch1; - volatile h264_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1; - volatile h264_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1; - uint32_t reserved_63c; - volatile h264_dma_in_arb_ch1_reg_t in_arb_ch1; - uint32_t reserved_644; - volatile h264_dma_in_etm_conf_ch1_reg_t in_etm_conf_ch1; - uint32_t reserved_64c[13]; - volatile h264_dma_in_fifo_cnt_ch1_reg_t in_fifo_cnt_ch1; - volatile h264_dma_in_pop_data_cnt_ch1_reg_t in_pop_data_cnt_ch1; - volatile h264_dma_in_xaddr_ch1_reg_t in_xaddr_ch1; - volatile h264_dma_in_buf_hb_rcv_ch1_reg_t in_buf_hb_rcv_ch1; - uint32_t reserved_690[28]; - volatile h264_dma_in_conf0_ch2_reg_t in_conf0_ch2; - volatile h264_dma_in_int_raw_ch2_reg_t in_int_raw_ch2; - volatile h264_dma_in_int_ena_ch2_reg_t in_int_ena_ch2; - volatile h264_dma_in_int_st_ch2_reg_t in_int_st_ch2; - volatile h264_dma_in_int_clr_ch2_reg_t in_int_clr_ch2; - volatile h264_dma_infifo_status_ch2_reg_t infifo_status_ch2; - volatile h264_dma_in_pop_ch2_reg_t in_pop_ch2; - volatile h264_dma_in_link_conf_ch2_reg_t in_link_conf_ch2; - volatile h264_dma_in_link_addr_ch2_reg_t in_link_addr_ch2; - volatile h264_dma_in_state_ch2_reg_t in_state_ch2; - volatile h264_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2; - volatile h264_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2; - volatile h264_dma_in_dscr_ch2_reg_t in_dscr_ch2; - volatile h264_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2; - volatile h264_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2; - uint32_t reserved_73c; - volatile h264_dma_in_arb_ch2_reg_t in_arb_ch2; - uint32_t reserved_744; - volatile h264_dma_in_etm_conf_ch2_reg_t in_etm_conf_ch2; - uint32_t reserved_74c[13]; - volatile h264_dma_in_fifo_cnt_ch2_reg_t in_fifo_cnt_ch2; - volatile h264_dma_in_pop_data_cnt_ch2_reg_t in_pop_data_cnt_ch2; - volatile h264_dma_in_xaddr_ch2_reg_t in_xaddr_ch2; - volatile h264_dma_in_buf_hb_rcv_ch2_reg_t in_buf_hb_rcv_ch2; - uint32_t reserved_790[28]; - volatile h264_dma_in_conf0_ch3_reg_t in_conf0_ch3; - volatile h264_dma_in_int_raw_ch3_reg_t in_int_raw_ch3; - volatile h264_dma_in_int_ena_ch3_reg_t in_int_ena_ch3; - volatile h264_dma_in_int_st_ch3_reg_t in_int_st_ch3; - volatile h264_dma_in_int_clr_ch3_reg_t in_int_clr_ch3; - volatile h264_dma_infifo_status_ch3_reg_t infifo_status_ch3; - volatile h264_dma_in_pop_ch3_reg_t in_pop_ch3; - volatile h264_dma_in_link_conf_ch3_reg_t in_link_conf_ch3; - volatile h264_dma_in_link_addr_ch3_reg_t in_link_addr_ch3; - volatile h264_dma_in_state_ch3_reg_t in_state_ch3; - volatile h264_dma_in_suc_eof_des_addr_ch3_reg_t in_suc_eof_des_addr_ch3; - volatile h264_dma_in_err_eof_des_addr_ch3_reg_t in_err_eof_des_addr_ch3; - volatile h264_dma_in_dscr_ch3_reg_t in_dscr_ch3; - volatile h264_dma_in_dscr_bf0_ch3_reg_t in_dscr_bf0_ch3; - volatile h264_dma_in_dscr_bf1_ch3_reg_t in_dscr_bf1_ch3; - uint32_t reserved_83c; - volatile h264_dma_in_arb_ch3_reg_t in_arb_ch3; - uint32_t reserved_844; - volatile h264_dma_in_etm_conf_ch3_reg_t in_etm_conf_ch3; - uint32_t reserved_84c[13]; - volatile h264_dma_in_fifo_cnt_ch3_reg_t in_fifo_cnt_ch3; - volatile h264_dma_in_pop_data_cnt_ch3_reg_t in_pop_data_cnt_ch3; - volatile h264_dma_in_xaddr_ch3_reg_t in_xaddr_ch3; - volatile h264_dma_in_buf_hb_rcv_ch3_reg_t in_buf_hb_rcv_ch3; - uint32_t reserved_890[28]; - volatile h264_dma_in_conf0_ch4_reg_t in_conf0_ch4; - volatile h264_dma_in_int_raw_ch4_reg_t in_int_raw_ch4; - volatile h264_dma_in_int_ena_ch4_reg_t in_int_ena_ch4; - volatile h264_dma_in_int_st_ch4_reg_t in_int_st_ch4; - volatile h264_dma_in_int_clr_ch4_reg_t in_int_clr_ch4; - volatile h264_dma_infifo_status_ch4_reg_t infifo_status_ch4; - volatile h264_dma_in_pop_ch4_reg_t in_pop_ch4; - volatile h264_dma_in_link_conf_ch4_reg_t in_link_conf_ch4; - volatile h264_dma_in_link_addr_ch4_reg_t in_link_addr_ch4; - volatile h264_dma_in_state_ch4_reg_t in_state_ch4; - volatile h264_dma_in_suc_eof_des_addr_ch4_reg_t in_suc_eof_des_addr_ch4; - volatile h264_dma_in_err_eof_des_addr_ch4_reg_t in_err_eof_des_addr_ch4; - volatile h264_dma_in_dscr_ch4_reg_t in_dscr_ch4; - volatile h264_dma_in_dscr_bf0_ch4_reg_t in_dscr_bf0_ch4; - volatile h264_dma_in_dscr_bf1_ch4_reg_t in_dscr_bf1_ch4; - uint32_t reserved_93c; - volatile h264_dma_in_arb_ch4_reg_t in_arb_ch4; - uint32_t reserved_944; - volatile h264_dma_in_etm_conf_ch4_reg_t in_etm_conf_ch4; - uint32_t reserved_94c[13]; - volatile h264_dma_in_fifo_cnt_ch4_reg_t in_fifo_cnt_ch4; - volatile h264_dma_in_pop_data_cnt_ch4_reg_t in_pop_data_cnt_ch4; - volatile h264_dma_in_xaddr_ch4_reg_t in_xaddr_ch4; - volatile h264_dma_in_buf_hb_rcv_ch4_reg_t in_buf_hb_rcv_ch4; - uint32_t reserved_990[28]; - volatile h264_dma_in_conf0_ch5_reg_t in_conf0_ch5; - volatile h264_dma_in_conf1_ch5_reg_t in_conf1_ch5; - volatile h264_dma_in_conf2_ch5_reg_t in_conf2_ch5; - volatile h264_dma_in_conf3_ch5_reg_t in_conf3_ch5; - volatile h264_dma_in_int_raw_ch5_reg_t in_int_raw_ch5; - volatile h264_dma_in_int_ena_ch5_reg_t in_int_ena_ch5; - volatile h264_dma_in_int_st_ch5_reg_t in_int_st_ch5; - volatile h264_dma_in_int_clr_ch5_reg_t in_int_clr_ch5; - volatile h264_dma_infifo_status_ch5_reg_t infifo_status_ch5; - volatile h264_dma_in_pop_ch5_reg_t in_pop_ch5; - volatile h264_dma_in_state_ch5_reg_t in_state_ch5; +} h264_dma_in_chn_regs_t; + +typedef struct { + volatile h264_dma_in_conf0_ch5_reg_t conf0; + volatile h264_dma_in_conf1_ch5_reg_t conf1; + volatile h264_dma_in_conf2_ch5_reg_t conf2; + volatile h264_dma_in_conf3_ch5_reg_t conf3; + volatile h264_dma_in_int_raw_ch5_reg_t int_raw; + volatile h264_dma_in_int_ena_ch5_reg_t int_ena; + volatile h264_dma_in_int_st_ch5_reg_t int_st; + volatile h264_dma_in_int_clr_ch5_reg_t int_clr; + volatile h264_dma_infifo_status_ch5_reg_t infifo_status; + volatile h264_dma_in_pop_ch5_reg_t pop; + volatile h264_dma_in_state_ch5_reg_t state; uint32_t reserved_a2c[5]; - volatile h264_dma_in_arb_ch5_reg_t in_arb_ch5; + volatile h264_dma_in_arb_ch5_reg_t arb; uint32_t reserved_a44[15]; - volatile h264_dma_in_fifo_cnt_ch5_reg_t in_fifo_cnt_ch5; - volatile h264_dma_in_pop_data_cnt_ch5_reg_t in_pop_data_cnt_ch5; - volatile h264_dma_in_xaddr_ch5_reg_t in_xaddr_ch5; - volatile h264_dma_in_buf_hb_rcv_ch5_reg_t in_buf_hb_rcv_ch5; + volatile h264_dma_in_fifo_cnt_ch5_reg_t fifo_cnt; + volatile h264_dma_in_pop_data_cnt_ch5_reg_t pop_data_cnt; + volatile h264_dma_in_xaddr_ch5_reg_t xaddr; + volatile h264_dma_in_buf_hb_rcv_ch5_reg_t buf_hb_rcv; uint32_t reserved_a90[28]; +} h264_dma_in_ch5_regs_t; + +typedef struct { + volatile h264_dma_mem_start_addr_reg_t start; + volatile h264_dma_mem_end_addr_reg_t end; +} h264_dma_mem_addr_reg_t; + +typedef struct { + volatile h264_dma_out_chn_regs_t dma_out_ch[5]; + volatile h264_dma_in_chn_regs_t dma_in_ch[5]; + volatile h264_dma_in_ch5_regs_t dma_in_ch5; volatile h264_dma_inter_axi_err_reg_t inter_axi_err; volatile h264_dma_exter_axi_err_reg_t exter_axi_err; volatile h264_dma_rst_conf_reg_t rst_conf; - volatile h264_dma_inter_mem_start_addr0_reg_t inter_mem_start_addr0; - volatile h264_dma_inter_mem_end_addr0_reg_t inter_mem_end_addr0; - volatile h264_dma_inter_mem_start_addr1_reg_t inter_mem_start_addr1; - volatile h264_dma_inter_mem_end_addr1_reg_t inter_mem_end_addr1; + volatile h264_dma_mem_addr_reg_t inter_mem_addr[2]; uint32_t reserved_b1c; - volatile h264_dma_exter_mem_start_addr0_reg_t exter_mem_start_addr0; - volatile h264_dma_exter_mem_end_addr0_reg_t exter_mem_end_addr0; - volatile h264_dma_exter_mem_start_addr1_reg_t exter_mem_start_addr1; - volatile h264_dma_exter_mem_end_addr1_reg_t exter_mem_end_addr1; - volatile h264_dma_out_arb_config_reg_t out_arb_config; - volatile h264_dma_in_arb_config_reg_t in_arb_config; + volatile h264_dma_mem_addr_reg_t exter_mem_addr[2]; + volatile h264_dma_arb_config_reg_t out_arb_config; + volatile h264_dma_arb_config_reg_t in_arb_config; uint32_t reserved_b38; volatile h264_dma_date_reg_t date; uint32_t reserved_b40[4]; diff --git a/components/soc/esp32p4/include/soc/h264_struct.h b/components/soc/esp32p4/include/soc/h264_struct.h index c21ac4ef22..f45ebac784 100644 --- a/components/soc/esp32p4/include/soc/h264_struct.h +++ b/components/soc/esp32p4/include/soc/h264_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,1029 +63,286 @@ typedef union { uint32_t val; } h264_gop_conf_reg_t; -/** Type of a_sys_mb_res register +/** Type of sys_mb_res register * Video A horizontal and vertical MB resolution register. */ typedef union { struct { - /** a_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; + /** sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; * Configures video A vertical MB resolution. */ - uint32_t a_sys_total_mb_y:7; - /** a_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; + uint32_t sys_total_mb_y:7; + /** sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; * Configures video A horizontal MB resolution. */ - uint32_t a_sys_total_mb_x:7; + uint32_t sys_total_mb_x:7; uint32_t reserved_14:18; }; uint32_t val; -} h264_a_sys_mb_res_reg_t; +} h264_sys_mb_res_reg_t; -/** Type of a_sys_conf register +/** Type of sys_conf register * Video A system level configuration register. */ typedef union { struct { - /** a_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; + /** db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; * Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of * written db temp+1) is greater than this filed in first MB line, trigger * H264_DB_TMP_READY_INT. Min is 3. */ - uint32_t a_db_tmp_ready_trigger_mb_num:7; - /** a_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; + uint32_t db_tmp_ready_trigger_mb_num:7; + /** rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; * Configures when to trigger video A H264_REC_READY_INT. When the MB line number of * generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. * Min is 4. */ - uint32_t a_rec_ready_trigger_mb_lines:7; - /** a_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; + uint32_t rec_ready_trigger_mb_lines:7; + /** intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; * Configures video A intra cost offset when I MB compared with P MB. */ - uint32_t a_intra_cost_cmp_offset:16; + uint32_t intra_cost_cmp_offset:16; uint32_t reserved_30:2; }; uint32_t val; -} h264_a_sys_conf_reg_t; +} h264_sys_conf_reg_t; -/** Type of a_deci_score register +/** Type of deci_score register * Video A luma and chroma MB decimate score Register. */ typedef union { struct { - /** a_c_deci_score : R/W; bitpos: [9:0]; default: 0; + /** c_deci_score : R/W; bitpos: [9:0]; default: 0; * Configures video A chroma MB decimate score. When chroma score is smaller than it, * chroma decimate will be enable. */ - uint32_t a_c_deci_score:10; - /** a_l_deci_score : R/W; bitpos: [19:10]; default: 0; + uint32_t c_deci_score:10; + /** l_deci_score : R/W; bitpos: [19:10]; default: 0; * Configures video A luma MB decimate score. When luma score is smaller than it, luma * decimate will be enable. */ - uint32_t a_l_deci_score:10; + uint32_t l_deci_score:10; uint32_t reserved_20:12; }; uint32_t val; -} h264_a_deci_score_reg_t; +} h264_deci_score_reg_t; -/** Type of a_deci_score_offset register +/** Type of deci_score_offset register * Video A luma and chroma MB decimate score offset Register. */ typedef union { struct { - /** a_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; + /** i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; * Configures video A i16x16 MB decimate score offset. This offset will be added to * i16x16 MB score. */ - uint32_t a_i16x16_deci_score_offset:6; - /** a_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; + uint32_t i16x16_deci_score_offset:6; + /** i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; * Configures video A I chroma MB decimate score offset. This offset will be added to * I chroma MB score. */ - uint32_t a_i_chroma_deci_score_offset:6; - /** a_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; + uint32_t i_chroma_deci_score_offset:6; + /** p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; * Configures video A p16x16 MB decimate score offset. This offset will be added to * p16x16 MB score. */ - uint32_t a_p16x16_deci_score_offset:6; - /** a_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; + uint32_t p16x16_deci_score_offset:6; + /** p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; * Configures video A p chroma MB decimate score offset. This offset will be added to * p chroma MB score. */ - uint32_t a_p_chroma_deci_score_offset:6; + uint32_t p_chroma_deci_score_offset:6; uint32_t reserved_24:8; }; uint32_t val; -} h264_a_deci_score_offset_reg_t; +} h264_deci_score_offset_reg_t; -/** Type of a_rc_conf0 register +/** Type of rc_conf0 register * Video A rate control configuration register0. */ typedef union { struct { - /** a_qp : R/W; bitpos: [5:0]; default: 0; + /** qp : R/W; bitpos: [5:0]; default: 0; * Configures video A frame level initial luma QP value. */ - uint32_t a_qp:6; - /** a_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; + uint32_t qp:6; + /** rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; * Configures video A parameter U value. U = int((float) u << 8). */ - uint32_t a_rate_ctrl_u:16; - /** a_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; + uint32_t rate_ctrl_u:16; + /** mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; * Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro * block rate ctrl\\1:Close the macro block rate ctrl. */ - uint32_t a_mb_rate_ctrl_en:1; + uint32_t mb_rate_ctrl_en:1; uint32_t reserved_23:9; }; uint32_t val; -} h264_a_rc_conf0_reg_t; +} h264_rc_conf0_reg_t; -/** Type of a_rc_conf1 register +/** Type of rc_conf1 register * Video A rate control configuration register1. */ typedef union { struct { - /** a_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; + /** chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; * Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma * QP(after map) + reg_chroma_dc_qp_delta. */ - uint32_t a_chroma_dc_qp_delta:3; - /** a_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; + uint32_t chroma_dc_qp_delta:3; + /** chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; * Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma * QP + reg_chroma_qp_delta. */ - uint32_t a_chroma_qp_delta:4; - /** a_qp_min : R/W; bitpos: [12:7]; default: 0; + uint32_t chroma_qp_delta:4; + /** qp_min : R/W; bitpos: [12:7]; default: 0; * Configures video A allowed luma QP min value. */ - uint32_t a_qp_min:6; - /** a_qp_max : R/W; bitpos: [18:13]; default: 0; + uint32_t qp_min:6; + /** qp_max : R/W; bitpos: [18:13]; default: 0; * Configures video A allowed luma QP max value. */ - uint32_t a_qp_max:6; - /** a_mad_frame_pred : R/W; bitpos: [30:19]; default: 0; + uint32_t qp_max:6; + /** mad_frame_pred : R/W; bitpos: [30:19]; default: 0; * Configures vdieo A frame level predicted MB MAD value. */ - uint32_t a_mad_frame_pred:12; + uint32_t mad_frame_pred:12; uint32_t reserved_31:1; }; uint32_t val; -} h264_a_rc_conf1_reg_t; +} h264_rc_conf1_reg_t; -/** Type of a_db_bypass register +/** Type of db_bypass register * Video A Deblocking bypass register */ typedef union { struct { - /** a_bypass_db_filter : R/W; bitpos: [0]; default: 0; + /** bypass_db_filter : R/W; bitpos: [0]; default: 0; * Configures whether or not to bypass video A deblcoking filter. \\0: Open the * deblock filter\\1: Close the deblock filter */ - uint32_t a_bypass_db_filter:1; + uint32_t bypass_db_filter:1; uint32_t reserved_1:31; }; uint32_t val; -} h264_a_db_bypass_reg_t; +} h264_db_bypass_reg_t; -/** Type of a_roi_region0 register - * Video A H264 ROI region0 range configure register. +/** Type of roi_region register + * Video A H264 ROI region range configure register. */ typedef union { struct { - /** a_roi_region0_x : R/W; bitpos: [6:0]; default: 0; + /** roi_region_x : R/W; bitpos: [6:0]; default: 0; * Configures the horizontal start macroblocks of region 0 in Video A. */ - uint32_t a_roi_region0_x:7; - /** a_roi_region0_y : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region_x:7; + /** roi_region_y : R/W; bitpos: [13:7]; default: 0; * Configures the vertical start macroblocks of region 0 in Video A. */ - uint32_t a_roi_region0_y:7; - /** a_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region_y:7; + /** roi_region_x_len : R/W; bitpos: [20:14]; default: 0; * Configures the number of macroblocks in horizontal direction of the region 0 in * Video A. */ - uint32_t a_roi_region0_x_len:7; - /** a_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region_x_len:7; + /** roi_region_y_len : R/W; bitpos: [27:21]; default: 0; * Configures the number of macroblocks in vertical direction of the region 0 in * Video A. */ - uint32_t a_roi_region0_y_len:7; - /** a_roi_region0_en : R/W; bitpos: [28]; default: 0; + uint32_t roi_region_y_len:7; + /** roi_region_en : R/W; bitpos: [28]; default: 0; * Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open * ROI. */ - uint32_t a_roi_region0_en:1; + uint32_t roi_region_en:1; uint32_t reserved_29:3; }; uint32_t val; -} h264_a_roi_region0_reg_t; +} h264_roi_region_reg_t; -/** Type of a_roi_region1 register - * Video A H264 ROI region1 range configure register. - */ -typedef union { - struct { - /** a_roi_region1_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 1 in Video A. - */ - uint32_t a_roi_region1_x:7; - /** a_roi_region1_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 1 in Video A. - */ - uint32_t a_roi_region1_y:7; - /** a_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 1 in - * Video A. - */ - uint32_t a_roi_region1_x_len:7; - /** a_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 1 in - * Video A. - */ - uint32_t a_roi_region1_y_len:7; - /** a_roi_region1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region1_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region1_reg_t; - -/** Type of a_roi_region2 register - * Video A H264 ROI region2 range configure register. - */ -typedef union { - struct { - /** a_roi_region2_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 2 in Video A. - */ - uint32_t a_roi_region2_x:7; - /** a_roi_region2_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 2 in Video A. - */ - uint32_t a_roi_region2_y:7; - /** a_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 2 in - * Video A. - */ - uint32_t a_roi_region2_x_len:7; - /** a_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 2 in - * Video A. - */ - uint32_t a_roi_region2_y_len:7; - /** a_roi_region2_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region2_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region2_reg_t; - -/** Type of a_roi_region3 register - * Video A H264 ROI region3 range configure register. - */ -typedef union { - struct { - /** a_roi_region3_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 3 in Video A. - */ - uint32_t a_roi_region3_x:7; - /** a_roi_region3_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 3 in Video A. - */ - uint32_t a_roi_region3_y:7; - /** a_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 3 in - * video A. - */ - uint32_t a_roi_region3_x_len:7; - /** a_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 3 in - * video A. - */ - uint32_t a_roi_region3_y_len:7; - /** a_roi_region3_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region3_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region3_reg_t; - -/** Type of a_roi_region4 register - * Video A H264 ROI region4 range configure register. - */ -typedef union { - struct { - /** a_roi_region4_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 4 in Video A. - */ - uint32_t a_roi_region4_x:7; - /** a_roi_region4_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 4 in Video A. - */ - uint32_t a_roi_region4_y:7; - /** a_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 4 in - * video A. - */ - uint32_t a_roi_region4_x_len:7; - /** a_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 4 in - * video A. - */ - uint32_t a_roi_region4_y_len:7; - /** a_roi_region4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region4_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region4_reg_t; - -/** Type of a_roi_region5 register - * Video A H264 ROI region5 range configure register. - */ -typedef union { - struct { - /** a_roi_region5_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 5 video A. - */ - uint32_t a_roi_region5_x:7; - /** a_roi_region5_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 5 video A. - */ - uint32_t a_roi_region5_y:7; - /** a_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 5 - * video A. - */ - uint32_t a_roi_region5_x_len:7; - /** a_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 5 in - * video A. - */ - uint32_t a_roi_region5_y_len:7; - /** a_roi_region5_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region5_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region5_reg_t; - -/** Type of a_roi_region6 register - * Video A H264 ROI region6 range configure register. - */ -typedef union { - struct { - /** a_roi_region6_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 6 video A. - */ - uint32_t a_roi_region6_x:7; - /** a_roi_region6_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 6 in video A. - */ - uint32_t a_roi_region6_y:7; - /** a_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 6 in - * video A. - */ - uint32_t a_roi_region6_x_len:7; - /** a_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 6 in - * video A. - */ - uint32_t a_roi_region6_y_len:7; - /** a_roi_region6_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region6_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region6_reg_t; - -/** Type of a_roi_region7 register - * Video A H264 ROI region7 range configure register. - */ -typedef union { - struct { - /** a_roi_region7_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 7 in video A. - */ - uint32_t a_roi_region7_x:7; - /** a_roi_region7_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 7 in video A. - */ - uint32_t a_roi_region7_y:7; - /** a_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 7 in - * video A. - */ - uint32_t a_roi_region7_x_len:7; - /** a_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 7 in - * video A. - */ - uint32_t a_roi_region7_y_len:7; - /** a_roi_region7_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t a_roi_region7_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region7_reg_t; - -/** Type of a_roi_region0_3_qp register +/** Type of roi_region0_3_qp register * Video A H264 ROI region0, region1,region2,region3 QP register. */ typedef union { struct { - /** a_roi_region0_qp : R/W; bitpos: [6:0]; default: 0; + /** roi_region0_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 ROI region0 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region0_qp:7; - /** a_roi_region1_qp : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region0_qp:7; + /** roi_region1_qp : R/W; bitpos: [13:7]; default: 0; * Configure H264 ROI region1 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region1_qp:7; - /** a_roi_region2_qp : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region1_qp:7; + /** roi_region2_qp : R/W; bitpos: [20:14]; default: 0; * Configure H264 ROI region2 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region2_qp:7; - /** a_roi_region3_qp : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region2_qp:7; + /** roi_region3_qp : R/W; bitpos: [27:21]; default: 0; * Configure H264 ROI region3 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region3_qp:7; + uint32_t roi_region3_qp:7; uint32_t reserved_28:4; }; uint32_t val; -} h264_a_roi_region0_3_qp_reg_t; +} h264_roi_region0_3_qp_reg_t; -/** Type of a_roi_region4_7_qp register +/** Type of roi_region4_7_qp register * Video A H264 ROI region4, region5,region6,region7 QP register. */ typedef union { struct { - /** a_roi_region4_qp : R/W; bitpos: [6:0]; default: 0; + /** roi_region4_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 ROI region4 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region4_qp:7; - /** a_roi_region5_qp : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region4_qp:7; + /** roi_region5_qp : R/W; bitpos: [13:7]; default: 0; * Configure H264 ROI region5 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region5_qp:7; - /** a_roi_region6_qp : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region5_qp:7; + /** roi_region6_qp : R/W; bitpos: [20:14]; default: 0; * Configure H264 ROI region6 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region6_qp:7; - /** a_roi_region7_qp : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region6_qp:7; + /** roi_region7_qp : R/W; bitpos: [27:21]; default: 0; * Configure H264 ROI region7 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region7_qp:7; + uint32_t roi_region7_qp:7; uint32_t reserved_28:4; }; uint32_t val; -} h264_a_roi_region4_7_qp_reg_t; +} h264_roi_region4_7_qp_reg_t; -/** Type of a_no_roi_region_qp_offset register +/** Type of no_roi_region_qp_offset register * Video A H264 no roi region QP register. */ typedef union { struct { - /** a_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; + /** no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 no region qp in video A, delta qp. */ - uint32_t a_no_roi_region_qp:7; + uint32_t no_roi_region_qp:7; uint32_t reserved_7:25; }; uint32_t val; -} h264_a_no_roi_region_qp_offset_reg_t; +} h264_no_roi_region_qp_offset_reg_t; -/** Type of a_roi_config register +/** Type of roi_config register * Video A H264 ROI configure register. */ typedef union { struct { - /** a_roi_en : R/W; bitpos: [0]; default: 0; + /** roi_en : R/W; bitpos: [0]; default: 0; * Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. */ - uint32_t a_roi_en:1; - /** a_roi_mode : R/W; bitpos: [1]; default: 0; + uint32_t roi_en:1; + /** roi_mode : R/W; bitpos: [1]; default: 0; * Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. */ - uint32_t a_roi_mode:1; + uint32_t roi_mode:1; uint32_t reserved_2:30; }; uint32_t val; -} h264_a_roi_config_reg_t; - -/** Type of b_sys_mb_res register - * Video B horizontal and vertical MB resolution register. - */ -typedef union { - struct { - /** b_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; - * Configures video B vertical MB resolution. - */ - uint32_t b_sys_total_mb_y:7; - /** b_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; - * Configures video B horizontal MB resolution. - */ - uint32_t b_sys_total_mb_x:7; - uint32_t reserved_14:18; - }; - uint32_t val; -} h264_b_sys_mb_res_reg_t; - -/** Type of b_sys_conf register - * Video B system level configuration register. - */ -typedef union { - struct { - /** b_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; - * Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of - * written db temp+1) is greater than this filed in first MB line, trigger - * H264_DB_TMP_READY_INT. Min is 3. - */ - uint32_t b_db_tmp_ready_trigger_mb_num:7; - /** b_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; - * Configures when to trigger video B H264_REC_READY_INT. When the MB line number of - * generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. - * Min is 4. - */ - uint32_t b_rec_ready_trigger_mb_lines:7; - /** b_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; - * Configures video B intra cost offset when I MB compared with P MB. - */ - uint32_t b_intra_cost_cmp_offset:16; - uint32_t reserved_30:2; - }; - uint32_t val; -} h264_b_sys_conf_reg_t; - -/** Type of b_deci_score register - * Video B luma and chroma MB decimate score Register. - */ -typedef union { - struct { - /** b_c_deci_score : R/W; bitpos: [9:0]; default: 0; - * Configures video B chroma MB decimate score. When chroma score is smaller than it, - * chroma decimate will be enable. - */ - uint32_t b_c_deci_score:10; - /** b_l_deci_score : R/W; bitpos: [19:10]; default: 0; - * Configures video B luma MB decimate score. When luma score is smaller than it, luma - * decimate will be enable. - */ - uint32_t b_l_deci_score:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_b_deci_score_reg_t; - -/** Type of b_deci_score_offset register - * Video B luma and chroma MB decimate score offset Register. - */ -typedef union { - struct { - /** b_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; - * Configures video B i16x16 MB decimate score offset. This offset will be added to - * i16x16 MB score. - */ - uint32_t b_i16x16_deci_score_offset:6; - /** b_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; - * Configures video B I chroma MB decimate score offset. This offset will be added to - * I chroma MB score. - */ - uint32_t b_i_chroma_deci_score_offset:6; - /** b_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; - * Configures video B p16x16 MB decimate score offset. This offset will be added to - * p16x16 MB score. - */ - uint32_t b_p16x16_deci_score_offset:6; - /** b_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; - * Configures video B p chroma MB decimate score offset. This offset will be added to - * p chroma MB score. - */ - uint32_t b_p_chroma_deci_score_offset:6; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_b_deci_score_offset_reg_t; - -/** Type of b_rc_conf0 register - * Video B rate control configuration register0. - */ -typedef union { - struct { - /** b_qp : R/W; bitpos: [5:0]; default: 0; - * Configures video B frame level initial luma QP value. - */ - uint32_t b_qp:6; - /** b_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; - * Configures video B parameter U value. U = int((float) u << 8). - */ - uint32_t b_rate_ctrl_u:16; - /** b_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; - * Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro - * block rate ctrl\\1:Close the macro block rate ctrl. - */ - uint32_t b_mb_rate_ctrl_en:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} h264_b_rc_conf0_reg_t; - -/** Type of b_rc_conf1 register - * Video B rate control configuration register1. - */ -typedef union { - struct { - /** b_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; - * Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma - * QP(after map) + reg_chroma_dc_qp_delta. - */ - uint32_t b_chroma_dc_qp_delta:3; - /** b_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; - * Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma - * QP + reg_chroma_qp_delta. - */ - uint32_t b_chroma_qp_delta:4; - /** b_qp_min : R/W; bitpos: [12:7]; default: 0; - * Configures video B allowed luma QP min value. - */ - uint32_t b_qp_min:6; - /** b_qp_max : R/W; bitpos: [18:13]; default: 0; - * Configures video B allowed luma QP max value. - */ - uint32_t b_qp_max:6; - /** b_mad_frame_pred : R/W; bitpos: [30:19]; default: 0; - * Configures vdieo B frame level predicted MB MAD value. - */ - uint32_t b_mad_frame_pred:12; - uint32_t reserved_31:1; - }; - uint32_t val; -} h264_b_rc_conf1_reg_t; - -/** Type of b_db_bypass register - * Video B Deblocking bypass register - */ -typedef union { - struct { - /** b_bypass_db_filter : R/W; bitpos: [0]; default: 0; - * Configures whether or not to bypass video B deblcoking filter. \\0: Open the - * deblock filter\\1: Close the deblock filter - */ - uint32_t b_bypass_db_filter:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} h264_b_db_bypass_reg_t; - -/** Type of b_roi_region0 register - * Video B H264 ROI region0 range configure register. - */ -typedef union { - struct { - /** b_roi_region0_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 0 in Video B. - */ - uint32_t b_roi_region0_x:7; - /** b_roi_region0_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 0 in Video B. - */ - uint32_t b_roi_region0_y:7; - /** b_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 0 in - * Video B. - */ - uint32_t b_roi_region0_x_len:7; - /** b_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 0 in - * Video B. - */ - uint32_t b_roi_region0_y_len:7; - /** b_roi_region0_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region0_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region0_reg_t; - -/** Type of b_roi_region1 register - * Video B H264 ROI region1 range configure register. - */ -typedef union { - struct { - /** b_roi_region1_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 1 in Video B. - */ - uint32_t b_roi_region1_x:7; - /** b_roi_region1_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 1 in Video B. - */ - uint32_t b_roi_region1_y:7; - /** b_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 1 in - * Video B. - */ - uint32_t b_roi_region1_x_len:7; - /** b_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 1 in - * Video B. - */ - uint32_t b_roi_region1_y_len:7; - /** b_roi_region1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region1_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region1_reg_t; - -/** Type of b_roi_region2 register - * Video B H264 ROI region2 range configure register. - */ -typedef union { - struct { - /** b_roi_region2_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 2 in Video B. - */ - uint32_t b_roi_region2_x:7; - /** b_roi_region2_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 2 in Video B. - */ - uint32_t b_roi_region2_y:7; - /** b_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 2 in - * Video B. - */ - uint32_t b_roi_region2_x_len:7; - /** b_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 2 in - * Video B. - */ - uint32_t b_roi_region2_y_len:7; - /** b_roi_region2_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region2_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region2_reg_t; - -/** Type of b_roi_region3 register - * Video B H264 ROI region3 range configure register. - */ -typedef union { - struct { - /** b_roi_region3_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 3 in Video B. - */ - uint32_t b_roi_region3_x:7; - /** b_roi_region3_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 3 in Video B. - */ - uint32_t b_roi_region3_y:7; - /** b_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 3 in - * video B. - */ - uint32_t b_roi_region3_x_len:7; - /** b_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 3 in - * video B. - */ - uint32_t b_roi_region3_y_len:7; - /** b_roi_region3_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region3_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region3_reg_t; - -/** Type of b_roi_region4 register - * Video B H264 ROI region4 range configure register. - */ -typedef union { - struct { - /** b_roi_region4_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 4 in Video B. - */ - uint32_t b_roi_region4_x:7; - /** b_roi_region4_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 4 in Video B. - */ - uint32_t b_roi_region4_y:7; - /** b_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 4 in - * video B. - */ - uint32_t b_roi_region4_x_len:7; - /** b_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 4 in - * video B. - */ - uint32_t b_roi_region4_y_len:7; - /** b_roi_region4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region4_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region4_reg_t; - -/** Type of b_roi_region5 register - * Video B H264 ROI region5 range configure register. - */ -typedef union { - struct { - /** b_roi_region5_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 5 video B. - */ - uint32_t b_roi_region5_x:7; - /** b_roi_region5_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 5 video B. - */ - uint32_t b_roi_region5_y:7; - /** b_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 5 - * video B. - */ - uint32_t b_roi_region5_x_len:7; - /** b_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 5 in - * video B. - */ - uint32_t b_roi_region5_y_len:7; - /** b_roi_region5_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region5_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region5_reg_t; - -/** Type of b_roi_region6 register - * Video B H264 ROI region6 range configure register. - */ -typedef union { - struct { - /** b_roi_region6_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 6 video B. - */ - uint32_t b_roi_region6_x:7; - /** b_roi_region6_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 6 in video B. - */ - uint32_t b_roi_region6_y:7; - /** b_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 6 in - * video B. - */ - uint32_t b_roi_region6_x_len:7; - /** b_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 6 in - * video B. - */ - uint32_t b_roi_region6_y_len:7; - /** b_roi_region6_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region6_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region6_reg_t; - -/** Type of b_roi_region7 register - * Video B H264 ROI region7 range configure register. - */ -typedef union { - struct { - /** b_roi_region7_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 7 in video B. - */ - uint32_t b_roi_region7_x:7; - /** b_roi_region7_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 7 in video B. - */ - uint32_t b_roi_region7_y:7; - /** b_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 7 in - * video B. - */ - uint32_t b_roi_region7_x_len:7; - /** b_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 7 in - * video B. - */ - uint32_t b_roi_region7_y_len:7; - /** b_roi_region7_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open - * ROI. - */ - uint32_t b_roi_region7_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region7_reg_t; - -/** Type of b_roi_region0_3_qp register - * Video B H264 ROI region0, region1,region2,region3 QP register. - */ -typedef union { - struct { - /** b_roi_region0_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 ROI region0 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region0_qp:7; - /** b_roi_region1_qp : R/W; bitpos: [13:7]; default: 0; - * Configure H264 ROI region1 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region1_qp:7; - /** b_roi_region2_qp : R/W; bitpos: [20:14]; default: 0; - * Configure H264 ROI region2 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region2_qp:7; - /** b_roi_region3_qp : R/W; bitpos: [27:21]; default: 0; - * Configure H264 ROI region3 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region3_qp:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_b_roi_region0_3_qp_reg_t; - -/** Type of b_roi_region4_7_qp register - * Video B H264 ROI region4, region5,region6,region7 QP register. - */ -typedef union { - struct { - /** b_roi_region4_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 ROI region4 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region4_qp:7; - /** b_roi_region5_qp : R/W; bitpos: [13:7]; default: 0; - * Configure H264 ROI region5 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region5_qp:7; - /** b_roi_region6_qp : R/W; bitpos: [20:14]; default: 0; - * Configure H264 ROI region6 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region6_qp:7; - /** b_roi_region7_qp : R/W; bitpos: [27:21]; default: 0; - * Configure H264 ROI region7 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region7_qp:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_b_roi_region4_7_qp_reg_t; - -/** Type of b_no_roi_region_qp_offset register - * Video B H264 no roi region QP register. - */ -typedef union { - struct { - /** b_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 no region qp in video B, delta qp. - */ - uint32_t b_no_roi_region_qp:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_b_no_roi_region_qp_offset_reg_t; - -/** Type of b_roi_config register - * Video B H264 ROI configure register. - */ -typedef union { - struct { - /** b_roi_en : R/W; bitpos: [0]; default: 0; - * Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. - */ - uint32_t b_roi_en:1; - /** b_roi_mode : R/W; bitpos: [1]; default: 0; - * Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. - */ - uint32_t b_roi_mode:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} h264_b_roi_config_reg_t; +} h264_roi_config_reg_t; /** Type of slice_header_remain register * Frame Slice Header remain bit register. @@ -1134,31 +391,18 @@ typedef union { uint32_t val; } h264_bs_threshold_reg_t; -/** Type of slice_header_byte0 register - * Frame Slice Header byte low 32 bit register. +/** Type of slice_header_byte register + * Frame Slice Header byte 32 bit register. */ typedef union { struct { - /** slice_byte_lsb : R/W; bitpos: [31:0]; default: 0; - * Configures Slice Header low 32 bit + /** byte : R/W; bitpos: [31:0]; default: 0; + * Configures Slice Header 32 bit */ - uint32_t slice_byte_lsb:32; + uint32_t byte:32; }; uint32_t val; -} h264_slice_header_byte0_reg_t; - -/** Type of slice_header_byte1 register - * Frame Slice Header byte high 32 bit register. - */ -typedef union { - struct { - /** slice_byte_msb : R/W; bitpos: [31:0]; default: 0; - * Configures Slice Header high 32 bit - */ - uint32_t slice_byte_msb:32; - }; - uint32_t val; -} h264_slice_header_byte1_reg_t; +} h264_slice_header_reg_t; /** Type of conf register * General configuration register. @@ -1742,55 +986,32 @@ typedef union { } h264_date_reg_t; +typedef struct { + volatile h264_sys_mb_res_reg_t sys_mb_res; + volatile h264_sys_conf_reg_t sys_conf; + volatile h264_deci_score_reg_t deci_score; + volatile h264_deci_score_offset_reg_t deci_score_offset; + volatile h264_rc_conf0_reg_t rc_conf0; + volatile h264_rc_conf1_reg_t rc_conf1; + volatile h264_db_bypass_reg_t db_bypass; + volatile h264_roi_region_reg_t roi_region[8]; + volatile h264_roi_region0_3_qp_reg_t roi_region0_3_qp; + volatile h264_roi_region4_7_qp_reg_t roi_region4_7_qp; + volatile h264_no_roi_region_qp_offset_reg_t no_roi_region_qp_offset; + volatile h264_roi_config_reg_t roi_config; +} h264_ctrl_regs_t; + typedef struct { volatile h264_sys_ctrl_reg_t sys_ctrl; volatile h264_gop_conf_reg_t gop_conf; - volatile h264_a_sys_mb_res_reg_t a_sys_mb_res; - volatile h264_a_sys_conf_reg_t a_sys_conf; - volatile h264_a_deci_score_reg_t a_deci_score; - volatile h264_a_deci_score_offset_reg_t a_deci_score_offset; - volatile h264_a_rc_conf0_reg_t a_rc_conf0; - volatile h264_a_rc_conf1_reg_t a_rc_conf1; - volatile h264_a_db_bypass_reg_t a_db_bypass; - volatile h264_a_roi_region0_reg_t a_roi_region0; - volatile h264_a_roi_region1_reg_t a_roi_region1; - volatile h264_a_roi_region2_reg_t a_roi_region2; - volatile h264_a_roi_region3_reg_t a_roi_region3; - volatile h264_a_roi_region4_reg_t a_roi_region4; - volatile h264_a_roi_region5_reg_t a_roi_region5; - volatile h264_a_roi_region6_reg_t a_roi_region6; - volatile h264_a_roi_region7_reg_t a_roi_region7; - volatile h264_a_roi_region0_3_qp_reg_t a_roi_region0_3_qp; - volatile h264_a_roi_region4_7_qp_reg_t a_roi_region4_7_qp; - volatile h264_a_no_roi_region_qp_offset_reg_t a_no_roi_region_qp_offset; - volatile h264_a_roi_config_reg_t a_roi_config; - volatile h264_b_sys_mb_res_reg_t b_sys_mb_res; - volatile h264_b_sys_conf_reg_t b_sys_conf; - volatile h264_b_deci_score_reg_t b_deci_score; - volatile h264_b_deci_score_offset_reg_t b_deci_score_offset; - volatile h264_b_rc_conf0_reg_t b_rc_conf0; - volatile h264_b_rc_conf1_reg_t b_rc_conf1; - volatile h264_b_db_bypass_reg_t b_db_bypass; - volatile h264_b_roi_region0_reg_t b_roi_region0; - volatile h264_b_roi_region1_reg_t b_roi_region1; - volatile h264_b_roi_region2_reg_t b_roi_region2; - volatile h264_b_roi_region3_reg_t b_roi_region3; - volatile h264_b_roi_region4_reg_t b_roi_region4; - volatile h264_b_roi_region5_reg_t b_roi_region5; - volatile h264_b_roi_region6_reg_t b_roi_region6; - volatile h264_b_roi_region7_reg_t b_roi_region7; - volatile h264_b_roi_region0_3_qp_reg_t b_roi_region0_3_qp; - volatile h264_b_roi_region4_7_qp_reg_t b_roi_region4_7_qp; - volatile h264_b_no_roi_region_qp_offset_reg_t b_no_roi_region_qp_offset; - volatile h264_b_roi_config_reg_t b_roi_config; + volatile h264_ctrl_regs_t ctrl[2]; volatile h264_rc_status0_reg_t rc_status0; volatile h264_rc_status1_reg_t rc_status1; volatile h264_rc_status2_reg_t rc_status2; volatile h264_slice_header_remain_reg_t slice_header_remain; volatile h264_slice_header_byte_length_reg_t slice_header_byte_length; volatile h264_bs_threshold_reg_t bs_threshold; - volatile h264_slice_header_byte0_reg_t slice_header_byte0; - volatile h264_slice_header_byte1_reg_t slice_header_byte1; + volatile h264_slice_header_reg_t slice_header[2]; volatile h264_int_raw_reg_t int_raw; volatile h264_int_st_reg_t int_st; volatile h264_int_ena_reg_t int_ena;