diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 0de00bb51c..2408d0a093 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -13,7 +13,6 @@
 #include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/rtc.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/gpio_hal.h"
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/usb/cdc_acm.h"
diff --git a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
index 43eed52043..26fe72b1e3 100644
--- a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
+++ b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
@@ -16,6 +16,7 @@
 #include "esp_system.h"
 #include "soc/uart_struct.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/uart_share_hw_ctrl.h"
 #include "esp_rom_gpio.h"
 #include "hal/gpio_hal.h"
 #include "hal/uart_ll.h"
@@ -678,7 +679,10 @@ static void uart_aut_baud_det_init(int rxd_io_num)
     gpio_set_direction(rxd_io_num, GPIO_MODE_INPUT_OUTPUT);
     esp_rom_gpio_connect_out_signal(rxd_io_num, i2c_periph_signal[0].scl_out_sig, 0, 0);
     esp_rom_gpio_connect_in_signal(rxd_io_num, UART_PERIPH_SIGNAL(1, SOC_UART_RX_PIN_IDX), 0);
-    periph_module_enable(PERIPH_UART1_MODULE);
+    HP_UART_BUS_CLK_ATOMIC() {
+        uart_ll_enable_bus_clock(1, true);
+        uart_ll_reset_register(1);
+    }
     /* Reset all the bits */
     uart_ll_disable_intr_mask(&UART1, ~0);
     uart_ll_clr_intsts_mask(&UART1, ~0);
@@ -710,7 +714,9 @@ static void i2c_scl_freq_cal(void)
 
     printf("\nSCL high period %.3f (us), SCL low_period %.3f (us)\n\n", (float)(i2c_cource_clk_period * high_period_cnt), (float)(i2c_cource_clk_period * low_period_cnt));
     uart_ll_set_autobaud_en(&UART1, false);
-    periph_module_disable(PERIPH_UART1_MODULE);
+    HP_UART_BUS_CLK_ATOMIC() {
+        uart_ll_enable_bus_clock(1, false);
+    }
 }
 
 TEST_CASE("I2C SCL freq test (local test)", "[i2c][ignore]")
diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c
index 056c97fc68..9c60cfe7e2 100644
--- a/components/esp_driver_gpio/src/dedic_gpio.c
+++ b/components/esp_driver_gpio/src/dedic_gpio.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -28,6 +28,8 @@
 #include "soc/dedic_gpio_periph.h"
 #if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
 #include "soc/dedic_gpio_struct.h"
+#endif
+#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
 #include "hal/dedic_gpio_ll.h"
 #endif
 
@@ -84,7 +86,11 @@ static esp_err_t dedic_gpio_build_platform(int core_id)
                 s_platform[core_id]->dev = &DEDIC_GPIO;
 #endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
 #if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-                periph_module_enable(dedic_gpio_periph_signals.module); // enable APB clock to peripheral
+                // enable dedicated GPIO register clock
+                PERIPH_RCC_ATOMIC() {
+                    dedic_gpio_ll_enable_bus_clock(true);
+                    dedic_gpio_ll_reset_register();
+                }
 #endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
             }
         }
@@ -107,7 +113,10 @@ static void dedic_gpio_break_platform(uint32_t core_id)
             free(s_platform[core_id]);
             s_platform[core_id] = NULL;
 #if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-            periph_module_disable(dedic_gpio_periph_signals.module); // disable module if no GPIO channel is being used
+            // disable the register clock if no GPIO channel is in use
+            PERIPH_RCC_ATOMIC() {
+                dedic_gpio_ll_enable_bus_clock(false);
+            }
 #endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
         }
         _lock_release(&s_platform_mutexlock[core_id]);
diff --git a/components/esp_driver_sdio/src/sdio_slave.c b/components/esp_driver_sdio/src/sdio_slave.c
index 1689f97f18..ccc56d9ae9 100644
--- a/components/esp_driver_sdio/src/sdio_slave.c
+++ b/components/esp_driver_sdio/src/sdio_slave.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -83,6 +83,7 @@ The driver of FIFOs works as below:
 #include "freertos/FreeRTOS.h"
 #include "soc/soc_memory_layout.h"
 #include "soc/gpio_periph.h"
+#include "soc/soc_caps.h"
 #include "esp_cpu.h"
 #include "freertos/semphr.h"
 #include "esp_private/periph_ctrl.h"
@@ -100,6 +101,12 @@ static const char TAG[] = "sdio_slave";
 #define SDIO_SLAVE_LOGE(s, ...) ESP_LOGE(TAG, "%s(%d): "s, __FUNCTION__,__LINE__,##__VA_ARGS__)
 #define SDIO_SLAVE_LOGW(s, ...) ESP_LOGW(TAG, "%s: "s, __FUNCTION__,##__VA_ARGS__)
 
+#if !SOC_RCC_IS_INDEPENDENT
+#define SDIO_SLAVE_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define SDIO_SLAVE_RCC_ATOMIC()
+#endif
+
 // sdio_slave_buf_handle_t is of type recv_desc_t*;
 typedef struct recv_desc_s {
     union {
@@ -304,9 +311,11 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)
     }
     configure_pin(slot->d3_gpio, slot->func, pullup);
 
-    //enable module and config
-    periph_module_reset(PERIPH_SDIO_SLAVE_MODULE);
-    periph_module_enable(PERIPH_SDIO_SLAVE_MODULE);
+    //enable register clock
+    SDIO_SLAVE_RCC_ATOMIC() {
+        sdio_slave_ll_enable_bus_clock(true);
+        sdio_slave_ll_reset_register();
+    }
 
     sdio_slave_hal_hw_init(context.hal);
     return ESP_OK;
@@ -333,6 +342,11 @@ static void sdio_slave_hw_deinit(void)
     recover_pin(slot->d1_gpio, slot->func);
     recover_pin(slot->d2_gpio, slot->func);
     recover_pin(slot->d3_gpio, slot->func);
+
+    //disable register clock
+    SDIO_SLAVE_RCC_ATOMIC() {
+        sdio_slave_ll_enable_bus_clock(false);
+    }
 }
 
 esp_err_t sdio_slave_initialize(sdio_slave_config_t *config)
diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c
index 1a06b8c0a2..68353afca5 100644
--- a/components/esp_driver_spi/src/gpspi/spi_common.c
+++ b/components/esp_driver_spi/src/gpspi/spi_common.c
@@ -970,7 +970,9 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t
         ret = false;
     } else {
         //Reset DMA
-        periph_module_reset(PERIPH_SPI_DMA_MODULE);
+        SPI_COMMON_RCC_CLOCK_ATOMIC() {
+            spi_dma_ll_reset_register(dmachan);
+        }
         ret = true;
     }
     portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
@@ -988,7 +990,9 @@ void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
     dmaworkaround_channels_busy[dmachan - 1] = 0;
     if (dmaworkaround_waiting_for_chan == dmachan) {
         //Reset DMA
-        periph_module_reset(PERIPH_SPI_DMA_MODULE);
+        SPI_COMMON_RCC_CLOCK_ATOMIC() {
+            spi_dma_ll_reset_register(dmachan);
+        }
         dmaworkaround_waiting_for_chan = 0;
         //Call callback
         dmaworkaround_cb(dmaworkaround_cb_arg);
diff --git a/components/esp_hw_support/include/esp_private/periph_ctrl.h b/components/esp_hw_support/include/esp_private/periph_ctrl.h
index 99ee3d6d99..4f714c987b 100644
--- a/components/esp_hw_support/include/esp_private/periph_ctrl.h
+++ b/components/esp_hw_support/include/esp_private/periph_ctrl.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
 #include <stdint.h>
+#include "sdkconfig.h"
 #include "soc/periph_defs.h"
 
 #ifdef __cplusplus
@@ -68,6 +69,24 @@ void periph_rcc_exit(void);
 /*************************************************************************************************************
  * @note The following APIs are no longer supported since ESP32P4, please use the RCC lock macros instead.
  *************************************************************************************************************/
+// allow the following targets to use the legacy periph_module_xyz APIs, to maintain backward compatibility,
+// because periph_module_xyz is also used outside of the ESP-IDF
+#if defined(CONFIG_IDF_TARGET_ESP32)   || \
+    defined(CONFIG_IDF_TARGET_ESP32S2) || \
+    defined(CONFIG_IDF_TARGET_ESP32S3) || \
+    defined(CONFIG_IDF_TARGET_ESP32C2) || \
+    defined(CONFIG_IDF_TARGET_ESP32C3) || \
+    defined(CONFIG_IDF_TARGET_ESP32C6) || \
+    defined(CONFIG_IDF_TARGET_ESP32H2)
+#define __PERIPH_CTRL_ALLOW_LEGACY_API
+#endif
+
+#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
+#define __PERIPH_CTRL_DEPRECATE_ATTR
+#else
+#define __PERIPH_CTRL_DEPRECATE_ATTR __attribute__((deprecated("This function is not functional on "CONFIG_IDF_TARGET)))
+#endif
+
 /**
  * @brief Enable peripheral module by un-gating the clock and de-asserting the reset signal.
  *
@@ -77,6 +96,7 @@ void periph_rcc_exit(void);
  *       @c periph_module_disable() has to be called the same number of times,
  *       in order to put the peripheral into disabled state.
  */
+__PERIPH_CTRL_DEPRECATE_ATTR
 void periph_module_enable(periph_module_t periph);
 
 /**
@@ -88,6 +108,7 @@ void periph_module_enable(periph_module_t periph);
  *       @c periph_module_disable() has to be called the same number of times,
  *       in order to put the peripheral into disabled state.
  */
+__PERIPH_CTRL_DEPRECATE_ATTR
 void periph_module_disable(periph_module_t periph);
 
 /**
@@ -97,6 +118,7 @@ void periph_module_disable(periph_module_t periph);
  *
  * @note Calling this function does not enable or disable the clock for the module.
  */
+__PERIPH_CTRL_DEPRECATE_ATTR
 void periph_module_reset(periph_module_t periph);
 
 /**
@@ -131,6 +153,8 @@ void wifi_module_enable(void);
  */
 void wifi_module_disable(void);
 
+#undef __PERIPH_CTRL_DEPRECATE_ATTR
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c
index 94d64f61ca..daf0a99192 100644
--- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c
+++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c
@@ -36,7 +36,6 @@
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
 #include "esp_private/system_internal.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/uart_hal.h"
 #endif
 
diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c
index e56d0e12a3..87642de1d7 100644
--- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c
+++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c
@@ -36,7 +36,6 @@
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
 #include "esp_private/system_internal.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/uart_hal.h"
 #endif
 
diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c
index 69e8f05b0f..3734807b88 100644
--- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c
+++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c
@@ -36,7 +36,6 @@
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
 #include "esp_private/system_internal.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/uart_hal.h"
 #endif
 
diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c
index 864dbf24a9..f27af1d5dc 100644
--- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c
+++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c
@@ -37,7 +37,6 @@
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
 #include "esp_private/system_internal.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/uart_hal.h"
 #endif
 
diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c
index 3f089170ae..19749c11ba 100644
--- a/components/esp_hw_support/modem_clock.c
+++ b/components/esp_hw_support/modem_clock.c
@@ -12,7 +12,6 @@
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "freertos/FreeRTOS.h"
-#include "hal/clk_gate_ll.h"
 #include "esp_private/esp_modem_clock.h"
 #include "esp_private/esp_pmu.h"
 #include "esp_sleep.h"
diff --git a/components/esp_hw_support/periph_ctrl.c b/components/esp_hw_support/periph_ctrl.c
index a560cd2990..51aeb2ae48 100644
--- a/components/esp_hw_support/periph_ctrl.c
+++ b/components/esp_hw_support/periph_ctrl.c
@@ -1,13 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "freertos/FreeRTOS.h"
-#include "hal/clk_gate_ll.h"
 #include "esp_attr.h"
 #include "esp_private/periph_ctrl.h"
 #include "soc/soc_caps.h"
+#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
+#include "hal/clk_gate_ll.h"
+#endif
 
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT
 #include "esp_private/esp_modem_clock.h"
@@ -55,6 +57,7 @@ void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
 
 void periph_module_enable(periph_module_t periph)
 {
+#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
     assert(periph < PERIPH_MODULE_MAX);
     portENTER_CRITICAL_SAFE(&periph_spinlock);
     if (ref_counts[periph] == 0) {
@@ -62,10 +65,12 @@ void periph_module_enable(periph_module_t periph)
     }
     ref_counts[periph]++;
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
+#endif
 }
 
 void periph_module_disable(periph_module_t periph)
 {
+#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
     assert(periph < PERIPH_MODULE_MAX);
     portENTER_CRITICAL_SAFE(&periph_spinlock);
     ref_counts[periph]--;
@@ -73,14 +78,17 @@ void periph_module_disable(periph_module_t periph)
         periph_ll_disable_clk_set_rst(periph);
     }
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
+#endif
 }
 
 void periph_module_reset(periph_module_t periph)
 {
+#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
     assert(periph < PERIPH_MODULE_MAX);
     portENTER_CRITICAL_SAFE(&periph_spinlock);
     periph_ll_reset(periph);
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
+#endif
 }
 
 #if !SOC_IEEE802154_BLE_ONLY
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index b4dc4592b8..cedc40284b 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -48,7 +48,6 @@
 #if SOC_TOUCH_SENSOR_SUPPORTED
 #include "hal/touch_sensor_hal.h"
 #endif
-#include "hal/clk_gate_ll.h"
 
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
index 65f4443d99..7da508fde7 100644
--- a/components/esp_system/port/soc/esp32s2/clk.c
+++ b/components/esp_system/port/soc/esp32s2/clk.c
@@ -26,7 +26,6 @@
 #include "esp_private/esp_clk.h"
 #include "bootloader_clock.h"
 #include "soc/syscon_reg.h"
-#include "hal/clk_gate_ll.h"
 
 static const char *TAG = "clk";
 
diff --git a/components/hal/esp32/include/hal/sdio_slave_ll.h b/components/hal/esp32/include/hal/sdio_slave_ll.h
index 695c647941..2c94f217e7 100644
--- a/components/hal/esp32/include/hal/sdio_slave_ll.h
+++ b/components/hal/esp32/include/hal/sdio_slave_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,7 @@
 #include "soc/host_reg.h"
 #include "soc/hinf_struct.h"
 #include "soc/lldesc.h"
+#include "soc/dport_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -35,7 +36,6 @@ extern "C" {
 /// Get address of the only HINF registers for ESP32
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
 
-
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
  *
@@ -75,6 +75,36 @@ typedef enum {
     SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
 } sdio_slave_ll_slvint_t;
 
+/**
+ * @brief Enable the bus clock for the SDIO slave module
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void _sdio_slave_ll_enable_bus_clock(bool enable)
+{
+    uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
+    reg_val &= ~DPORT_WIFI_CLK_SDIOSLAVE_EN;
+    reg_val |= enable << 4;
+    DPORT_WRITE_PERI_REG(DPORT_WIFI_CLK_EN_REG, reg_val);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define sdio_slave_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sdio_slave_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the SDIO slave module
+ */
+static inline void _sdio_slave_ll_reset_register(void)
+{
+    DPORT_WRITE_PERI_REG(DPORT_CORE_RST_EN_REG, DPORT_SDIO_RST);
+    DPORT_WRITE_PERI_REG(DPORT_CORE_RST_EN_REG, 0);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define sdio_slave_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sdio_slave_ll_reset_register(__VA_ARGS__)
+
 /**
  * Initialize the hardware.
  *
@@ -104,31 +134,31 @@ static inline void sdio_slave_ll_init(slc_dev_t *slc)
  */
 static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
 {
-    switch(timing) {
-        case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
-            host->conf.frc_sdio20 = 0x1f;
-            host->conf.frc_sdio11 = 0;
-            host->conf.frc_pos_samp = 0x1f;
-            host->conf.frc_neg_samp = 0;
-            break;
-        case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
-            host->conf.frc_sdio20 = 0x1f;
-            host->conf.frc_sdio11 = 0;
-            host->conf.frc_pos_samp = 0;
-            host->conf.frc_neg_samp = 0x1f;
-            break;
-        case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
-            host->conf.frc_sdio20 = 0;
-            host->conf.frc_sdio11 = 0x1f;
-            host->conf.frc_pos_samp = 0x1f;
-            host->conf.frc_neg_samp = 0;
-            break;
-        case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
-            host->conf.frc_sdio20 = 0;
-            host->conf.frc_sdio11 = 0x1f;
-            host->conf.frc_pos_samp = 0;
-            host->conf.frc_neg_samp = 0x1f;
-            break;
+    switch (timing) {
+    case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
     }
 }
 
@@ -267,7 +297,7 @@ static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
  */
 static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
 {
-    slc->slc0_int_ena.rx_eof = (ena? 1: 0);
+    slc->slc0_int_ena.rx_eof = (ena ? 1 : 0);
 }
 
 /**
@@ -411,9 +441,9 @@ static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
  * @param pos Position of the register, 0-63 except 24-27.
  * @return address of the register.
  */
-static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
+static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t *host, int pos)
 {
-    return (intptr_t )&(host->conf_w0) + pos + (pos>23?4:0) + (pos>31?12:0);
+    return (intptr_t) & (host->conf_w0) + pos + (pos > 23 ? 4 : 0) + (pos > 31 ? 12 : 0);
 }
 
 /**
@@ -425,7 +455,7 @@ static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
  */
 static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
 {
-    return *(uint8_t*)sdio_slave_ll_host_get_w_reg(host, pos);
+    return *(uint8_t *)sdio_slave_ll_host_get_w_reg(host, pos);
 }
 
 /**
@@ -435,9 +465,9 @@ static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
  * @param pos Position of the register, 0-63, except 24-27.
  * @param reg Value to set.
  */
-static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t reg)
+static inline void sdio_slave_ll_host_set_reg(host_dev_t *host, int pos, uint8_t reg)
 {
-    uint32_t* addr = (uint32_t*)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
+    uint32_t *addr = (uint32_t *)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
     uint32_t shift = (pos % 4) * 8;
     *addr &= ~(0xff << shift);
     *addr |= ((uint32_t)reg << shift);
@@ -449,7 +479,7 @@ static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t
  * @param host Address of the host registers
  * @return Enabled interrupts
  */
-static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
+static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t *host)
 {
     return (sdio_slave_hostint_t)host->slc0_func1_int_ena.val;
 }
@@ -470,7 +500,7 @@ static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_sl
  * @param host Address of the host registers
  * @param mask Mask of interrupts to clear.
  */
-static inline void sdio_slave_ll_host_intr_clear(host_dev_t* host, const sdio_slave_hostint_t *mask)
+static inline void sdio_slave_ll_host_intr_clear(host_dev_t *host, const sdio_slave_hostint_t *mask)
 {
     host->slc0_int_clr.val = (*mask);
 }
@@ -488,7 +518,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_
 }
 
 /**
- * Enable some of the slave interrups (send from host)
+ * Enable some of the slave interrupts (send from host)
  *
  * @param slc Address of the SLC registers
  * @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h
index 1b8eea8ed7..9ab400ee3f 100644
--- a/components/hal/esp32/include/hal/spi_ll.h
+++ b/components/hal/esp32/include/hal/spi_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -260,7 +260,7 @@ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw)
 /**
  * Reset SPI DMA TX FIFO
  *
- * On ESP32, this function is not seperated
+ * On ESP32, this function is not separated
  *
  * @param hw Beginning address of the peripheral registers.
  */
@@ -273,7 +273,7 @@ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw)
 /**
  * Reset SPI DMA RX FIFO
  *
- * On ESP32, this function is not seperated
+ * On ESP32, this function is not separated
  *
  * @param hw Beginning address of the peripheral registers.
  */
@@ -626,7 +626,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
  * Get the frequency of given dividers. Don't use in app.
  *
  * @param fapb APB clock of the system.
- * @param pre Pre devider.
+ * @param pre Pre divider.
  * @param n main divider.
  *
  * @return Frequency of given dividers.
@@ -637,10 +637,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
 }
 
 /**
- * Calculate the nearest frequency avaliable for master.
+ * Calculate the nearest frequency available for master.
  *
  * @param fapb APB clock of the system.
- * @param hz Frequncy desired.
+ * @param hz Frequency desired.
  * @param duty_cycle Duty cycle desired.
  * @param out_reg Output address to store the calculated clock configurations for the return frequency.
  *
@@ -720,7 +720,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
  *
  * @param hw Beginning address of the peripheral registers.
  * @param fapb APB clock of the system.
- * @param hz Frequncy desired.
+ * @param hz Frequency desired.
  * @param duty_cycle Duty cycle desired.
  *
  * @return Actual frequency that is used.
@@ -1079,7 +1079,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
+__attribute__((always_inline))
 static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
+    (void)host_id; // has only one spi_dma
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
 }
diff --git a/components/hal/esp32/include/hal/uhci_ll.h b/components/hal/esp32/include/hal/uhci_ll.h
new file mode 100644
index 0000000000..c6c1b84e10
--- /dev/null
+++ b/components/hal/esp32/include/hal/uhci_ll.h
@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for UHCI register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+#include <stdio.h>
+#include "hal/uhci_types.h"
+#include "soc/uhci_struct.h"
+#include "soc/dport_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable the bus clock for UHCI module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
+{
+    uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
+    if (group_id == 0) {
+        reg_val &= ~DPORT_UHCI0_CLK_EN;
+        reg_val |= enable << 8;
+    } else {
+        reg_val &= ~DPORT_UHCI1_CLK_EN;
+        reg_val |= enable << 12;
+    }
+    DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the UHCI module
+ *
+ * @param group_id Group ID
+ */
+static inline void _uhci_ll_reset_register(int group_id)
+{
+    if (group_id == 0) {
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
+    } else {
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c3/include/hal/uhci_ll.h b/components/hal/esp32c3/include/hal/uhci_ll.h
index 2a507a30f9..22d2652156 100644
--- a/components/hal/esp32c3/include/hal/uhci_ll.h
+++ b/components/hal/esp32c3/include/hal/uhci_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,11 +7,11 @@
 // The LL layer for UHCI register operations.
 // Note that most of the register operations in this layer are non-atomic operations.
 
-
 #pragma once
 #include <stdio.h>
 #include "hal/uhci_types.h"
 #include "soc/uhci_struct.h"
+#include "soc/system_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -26,6 +26,38 @@ typedef enum {
     UHCI_RX_EOF_MAX       = 0x7,
 } uhci_rxeof_cfg_t;
 
+/**
+ * @brief Enable the bus clock for UHCI module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    SYSTEM.perip_clk_en0.reg_uhci0_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the UHCI module
+ *
+ * @param group_id Group ID
+ */
+static inline void _uhci_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    SYSTEM.perip_rst_en0.reg_uhci0_rst = 1;
+    SYSTEM.perip_rst_en0.reg_uhci0_rst = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
+
 static inline void uhci_ll_init(uhci_dev_t *hw)
 {
     typeof(hw->conf0) conf0_reg;
@@ -38,8 +70,8 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
 
 static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
 {
-    hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
-    hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
+    hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
+    hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
 }
 
 static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@@ -118,7 +150,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
     return hw->int_st.val;
 }
 
-
 static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
 {
     if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
diff --git a/components/hal/esp32c6/include/hal/sdio_slave_ll.h b/components/hal/esp32c6/include/hal/sdio_slave_ll.h
index 7319cbe20a..97c4b54410 100644
--- a/components/hal/esp32c6/include/hal/sdio_slave_ll.h
+++ b/components/hal/esp32c6/include/hal/sdio_slave_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,7 @@
 #include "soc/host_reg.h"
 #include "soc/hinf_struct.h"
 #include "soc/lldesc.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -35,7 +36,6 @@ extern "C" {
 /// Get address of the only HINF registers
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
 
-
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
  *
@@ -75,6 +75,25 @@ typedef enum {
     SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
 } sdio_slave_ll_slvint_t;
 
+/**
+ * @brief Enable the bus clock for the SDIO slave module
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void sdio_slave_ll_enable_bus_clock(bool enable)
+{
+    PCR.sdio_slave_conf.sdio_slave_clk_en = enable;
+}
+
+/**
+ * @brief Reset the SDIO slave module
+ */
+static inline void sdio_slave_ll_reset_register(void)
+{
+    PCR.sdio_slave_conf.sdio_slave_rst_en = 1;
+    PCR.sdio_slave_conf.sdio_slave_rst_en = 0;
+}
+
 /**
  * Initialize the hardware.
  *
@@ -104,31 +123,31 @@ static inline void sdio_slave_ll_init(slc_dev_t *slc)
  */
 static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
 {
-    switch(timing) {
-        case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
-            host->conf.frc_sdio20 = 0x1f;
-            host->conf.frc_sdio11 = 0;
-            host->conf.frc_pos_samp = 0x1f;
-            host->conf.frc_neg_samp = 0;
-            break;
-        case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
-            host->conf.frc_sdio20 = 0x1f;
-            host->conf.frc_sdio11 = 0;
-            host->conf.frc_pos_samp = 0;
-            host->conf.frc_neg_samp = 0x1f;
-            break;
-        case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
-            host->conf.frc_sdio20 = 0;
-            host->conf.frc_sdio11 = 0x1f;
-            host->conf.frc_pos_samp = 0x1f;
-            host->conf.frc_neg_samp = 0;
-            break;
-        case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
-            host->conf.frc_sdio20 = 0;
-            host->conf.frc_sdio11 = 0x1f;
-            host->conf.frc_pos_samp = 0;
-            host->conf.frc_neg_samp = 0x1f;
-            break;
+    switch (timing) {
+    case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
     }
 }
 
@@ -267,7 +286,7 @@ static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
  */
 static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
 {
-    slc->slc0int_ena.slc0_rx_eof_int_ena = (ena? 1: 0);
+    slc->slc0int_ena.slc0_rx_eof_int_ena = (ena ? 1 : 0);
 }
 
 /**
@@ -411,9 +430,9 @@ static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
  * @param pos Position of the register, 0-63 except 24-27.
  * @return address of the register.
  */
-static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
+static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t *host, int pos)
 {
-    return (intptr_t )&(host->conf_w0) + pos + (pos>23?4:0) + (pos>31?12:0);
+    return (intptr_t) & (host->conf_w0) + pos + (pos > 23 ? 4 : 0) + (pos > 31 ? 12 : 0);
 }
 
 /**
@@ -425,7 +444,7 @@ static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
  */
 static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
 {
-    return *(uint8_t*)sdio_slave_ll_host_get_w_reg(host, pos);
+    return *(uint8_t *)sdio_slave_ll_host_get_w_reg(host, pos);
 }
 
 /**
@@ -435,9 +454,9 @@ static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
  * @param pos Position of the register, 0-63, except 24-27.
  * @param reg Value to set.
  */
-static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t reg)
+static inline void sdio_slave_ll_host_set_reg(host_dev_t *host, int pos, uint8_t reg)
 {
-    uint32_t* addr = (uint32_t*)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
+    uint32_t *addr = (uint32_t *)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
     uint32_t shift = (pos % 4) * 8;
     *addr &= ~(0xff << shift);
     *addr |= ((uint32_t)reg << shift);
@@ -449,7 +468,7 @@ static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t
  * @param host Address of the host registers
  * @return Enabled interrupts
  */
-static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
+static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t *host)
 {
     return (sdio_slave_hostint_t)host->slc0host_func1_int_ena.val;
 }
@@ -470,7 +489,7 @@ static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_sl
  * @param host Address of the host registers
  * @param mask Mask of interrupts to clear.
  */
-static inline void sdio_slave_ll_host_intr_clear(host_dev_t* host, const sdio_slave_hostint_t *mask)
+static inline void sdio_slave_ll_host_intr_clear(host_dev_t *host, const sdio_slave_hostint_t *mask)
 {
     host->slc0host_int_clr.val = (*mask);
 }
@@ -488,7 +507,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_
 }
 
 /**
- * Enable some of the slave interrups (send from host)
+ * Enable some of the slave interrupts (send from host)
  *
  * @param slc Address of the SLC registers
  * @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h
deleted file mode 100644
index caf46ad96e..0000000000
--- a/components/hal/esp32p4/include/hal/clk_gate_ll.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/periph_defs.h"
-#include "soc/soc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_clkrst_reg.h"
-#include "esp_attr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
-{
-    switch (periph) {
-    case PERIPH_EMAC_MODULE:
-        return LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN;
-    case PERIPH_I3C_MODULE:
-        return HP_SYS_CLKRST_REG_I3C_MST_CLK_EN;
-    case PERIPH_SARADC_MODULE:
-        return HP_SYS_CLKRST_REG_ADC_CLK_EN;
-    case PERIPH_PVT_MODULE:
-        return HP_SYS_CLKRST_REG_PVT_CLK_EN;
-    case PERIPH_AES_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN;
-    case PERIPH_DS_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN;
-    case PERIPH_ECC_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN;
-    case PERIPH_HMAC_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN;
-    case PERIPH_RSA_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN;
-    case PERIPH_SEC_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN;
-    case PERIPH_SHA_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN;
-    case PERIPH_ECDSA_MODULE:
-        return HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN;
-    case PERIPH_ISP_MODULE:
-        return HP_SYS_CLKRST_REG_ISP_CLK_EN;
-    default:
-        return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable)
-{
-    uint32_t ret;
-    switch (periph) {
-    case PERIPH_PVT_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_PVT_TOP;
-    case PERIPH_ISP_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_ISP;
-    case PERIPH_UHCI_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UHCI;
-    case PERIPH_I3C_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_I3CMST | HP_SYS_CLKRST_REG_RST_EN_I3CSLV;
-    case PERIPH_SARADC_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_ADC;
-    case PERIPH_AES_MODULE:
-        ret = HP_SYS_CLKRST_REG_RST_EN_AES;
-        if (enable == true) {
-            // Clear reset on digital signature, otherwise AES unit is held in reset
-            ret |= HP_SYS_CLKRST_REG_RST_EN_DS;
-        }
-        return ret;
-    case PERIPH_DS_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_DS;
-    case PERIPH_ECC_MODULE:
-        ret = HP_SYS_CLKRST_REG_RST_EN_ECC;
-        if (enable == true) {
-            ret |= HP_SYS_CLKRST_REG_RST_EN_ECDSA;
-        }
-        return ret;
-    case PERIPH_HMAC_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_HMAC;
-    case PERIPH_RSA_MODULE:
-        ret = HP_SYS_CLKRST_REG_RST_EN_RSA;
-        if (enable == true) {
-            // Clear reset on digital signature, and ECDSA, otherwise RSA is held in reset
-            ret |= HP_SYS_CLKRST_REG_RST_EN_DS | HP_SYS_CLKRST_REG_RST_EN_ECDSA;
-        }
-        return ret;
-    case PERIPH_SEC_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_SEC;
-    case PERIPH_SHA_MODULE:
-        ret = HP_SYS_CLKRST_REG_RST_EN_SHA;
-        if (enable == true) {
-            // Clear reset on digital signature, HMAC and ECDSA, otherwise SHA is held in reset
-            ret |= (HP_SYS_CLKRST_REG_RST_EN_HMAC | HP_SYS_CLKRST_REG_RST_EN_DS | HP_SYS_CLKRST_REG_RST_EN_ECDSA);
-        }
-        return ret;
-    case PERIPH_ECDSA_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_ECDSA;
-    case PERIPH_EMAC_MODULE:
-        return LP_CLKRST_RST_EN_EMAC;
-    default:
-        return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
-{
-    switch (periph) {
-    case PERIPH_I3C_MODULE:
-    case PERIPH_SARADC_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL22_REG;
-    case PERIPH_PVT_MODULE:
-    case PERIPH_AES_MODULE:
-    case PERIPH_DS_MODULE:
-    case PERIPH_ECC_MODULE:
-    case PERIPH_HMAC_MODULE:
-    case PERIPH_RSA_MODULE:
-    case PERIPH_SEC_MODULE:
-    case PERIPH_SHA_MODULE:
-    case PERIPH_ECDSA_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL24_REG;
-    case PERIPH_ISP_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL25_REG;
-    case PERIPH_EMAC_MODULE:
-        return LP_CLKRST_HP_CLK_CTRL_REG;
-    default:
-        abort();
-        return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
-{
-    switch (periph) {
-    case PERIPH_PVT_MODULE:
-    case PERIPH_ISP_MODULE:
-        return HP_SYS_CLKRST_HP_RST_EN0_REG;
-    case PERIPH_UHCI_MODULE:
-    case PERIPH_I3C_MODULE:
-    case PERIPH_SARADC_MODULE:
-    case PERIPH_AES_MODULE:
-    case PERIPH_DS_MODULE:
-    case PERIPH_ECC_MODULE:
-    case PERIPH_HMAC_MODULE:
-    case PERIPH_RSA_MODULE:
-    case PERIPH_SEC_MODULE:
-    case PERIPH_SHA_MODULE:
-    case PERIPH_ECDSA_MODULE:
-        return HP_SYS_CLKRST_HP_RST_EN2_REG;
-    case PERIPH_EMAC_MODULE:
-        return LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG;
-    default:
-        abort();
-        return 0;
-    }
-}
-
-static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
-}
-
-static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
-{
-    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline void periph_ll_reset(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
-{
-    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
index 20bbdb0827..c02b97c595 100644
--- a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,29 @@ extern "C" {
 #include <stdbool.h>
 #include "hal/misc.h"
 #include "soc/dedic_gpio_struct.h"
+#include "soc/system_reg.h"
+
+static inline void _dedic_gpio_ll_enable_bus_clock(bool enable)
+{
+    uint32_t reg_val = READ_PERI_REG(DPORT_CPU_PERI_CLK_EN_REG);
+    reg_val &= ~DPORT_CLK_EN_DEDICATED_GPIO_M;
+    reg_val |= enable << DPORT_CLK_EN_DEDICATED_GPIO_S;
+    WRITE_PERI_REG(DPORT_CPU_PERI_CLK_EN_REG, reg_val);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dedic_gpio_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _dedic_gpio_ll_enable_bus_clock(__VA_ARGS__)
+
+static inline void _dedic_gpio_ll_reset_register(void)
+{
+    WRITE_PERI_REG(DPORT_CPU_PERI_RST_EN_REG, DPORT_RST_EN_DEDICATED_GPIO_M);
+    WRITE_PERI_REG(DPORT_CPU_PERI_RST_EN_REG, 0);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dedic_gpio_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _dedic_gpio_ll_reset_register(__VA_ARGS__)
 
 static inline void dedic_gpio_ll_enable_instruction_access_out(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
 {
diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_ll.h
new file mode 100644
index 0000000000..f6e019b686
--- /dev/null
+++ b/components/hal/esp32s3/include/hal/dedic_gpio_ll.h
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/system_struct.h"
+
+static inline void _dedic_gpio_ll_enable_bus_clock(bool enable)
+{
+    SYSTEM.cpu_peri_clk_en.clk_en_dedicated_gpio = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dedic_gpio_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _dedic_gpio_ll_enable_bus_clock(__VA_ARGS__)
+
+static inline void _dedic_gpio_ll_reset_register(void)
+{
+    SYSTEM.cpu_peri_rst_en.rst_en_dedicated_gpio = 1;
+    SYSTEM.cpu_peri_rst_en.rst_en_dedicated_gpio = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dedic_gpio_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _dedic_gpio_ll_reset_register(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s3/include/hal/uhci_ll.h b/components/hal/esp32s3/include/hal/uhci_ll.h
index 65286ec7e7..94c539787c 100644
--- a/components/hal/esp32s3/include/hal/uhci_ll.h
+++ b/components/hal/esp32s3/include/hal/uhci_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,11 +7,11 @@
 // The LL layer for UHCI register operations.
 // Note that most of the register operations in this layer are non-atomic operations.
 
-
 #pragma once
 #include <stdio.h>
 #include "hal/uhci_types.h"
 #include "soc/uhci_struct.h"
+#include "soc/system_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -26,6 +26,38 @@ typedef enum {
     UHCI_RX_EOF_MAX       = 0x7,
 } uhci_rxeof_cfg_t;
 
+/**
+ * @brief Enable the bus clock for UHCI module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    SYSTEM.perip_clk_en0.uhci0_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the UHCI module
+ *
+ * @param group_id Group ID
+ */
+static inline void _uhci_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    SYSTEM.perip_rst_en0.uhci0_rst = 1;
+    SYSTEM.perip_rst_en0.uhci0_rst = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
+
 static inline void uhci_ll_init(uhci_dev_t *hw)
 {
     typeof(hw->conf0) conf0_reg;
@@ -38,9 +70,9 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
 
 static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
 {
-    hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
-    hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
-    hw->conf0.uart2_ce = (uart_num == 2)? 1: 0;
+    hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
+    hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
+    hw->conf0.uart2_ce = (uart_num == 2) ? 1 : 0;
 }
 
 static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@@ -119,7 +151,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
     return hw->int_st.val;
 }
 
-
 static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
 {
     if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
index 4564581967..ee30352c4b 100644
--- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
+++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
@@ -12,7 +12,6 @@
 #include "esp_efuse_chip.h"
 #include "esp_private/esp_crypto_lock_internal.h"
 #include "esp_random.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/ecc_ll.h"
 #include "hal/ecdsa_hal.h"
 #include "hal/ecdsa_ll.h"
@@ -97,7 +96,7 @@ static void test_ecdsa_corrupt_data(bool is_p256, uint8_t* sha, uint8_t* r_le, u
         len = 24;
     }
 
-    // Randomly select a bit and corrupt its correpsonding value
+    // Randomly select a bit and corrupt its corresponding value
     uint16_t r_bit = esp_random() % len * 8;
 
     printf("Corrupting SHA bit %d...\n", r_bit);
diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/include/soc/uhci_struct.h
index c89e06a18c..8751b6ad19 100644
--- a/components/soc/esp32c3/include/soc/uhci_struct.h
+++ b/components/soc/esp32c3/include/soc/uhci_struct.h
@@ -215,7 +215,6 @@ typedef volatile struct uhci_dev_s {
     uint32_t date;                                     /*a*/
 } uhci_dev_t;
 extern uhci_dev_t UHCI0;
-extern uhci_dev_t UHCI1;
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld
index 191e7120c0..331affba60 100644
--- a/components/soc/esp32c3/ld/esp32c3.peripherals.ld
+++ b/components/soc/esp32c3/ld/esp32c3.peripherals.ld
@@ -16,7 +16,6 @@ PROVIDE ( HINF = 0x6000B000 );
 PROVIDE ( I2S0  = 0x6002d000 );
 PROVIDE ( I2C0  = 0x60013000 );
 PROVIDE ( UHCI0  = 0x60014000 );
-PROVIDE ( UHCI1  = 0x6000c000 );
 PROVIDE ( HOST = 0x60015000 );
 PROVIDE ( RMT = 0x60016000 );
 PROVIDE ( RMTMEM = 0x60016400 );
diff --git a/components/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/esp32s3/include/soc/uhci_struct.h
index 6fdd2cad1f..f7308abbf0 100644
--- a/components/soc/esp32s3/include/soc/uhci_struct.h
+++ b/components/soc/esp32s3/include/soc/uhci_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UHCI_STRUCT_H_
 #define _SOC_UHCI_STRUCT_H_
 
@@ -233,7 +225,6 @@ typedef volatile struct uhci_dev_s {
     uint32_t date;
 } uhci_dev_t;
 extern uhci_dev_t UHCI0;
-extern uhci_dev_t UHCI1;
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld
index 0b6d8881a2..abf6f87b83 100644
--- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld
+++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld
@@ -19,7 +19,6 @@ PROVIDE ( I2S1 = 0x6002D000 );
 PROVIDE ( UART1 = 0x60010000 );
 PROVIDE ( I2C0 = 0x60013000 );
 PROVIDE ( UHCI0 = 0x60014000 );
-PROVIDE ( UHCI1 = 0x60014000 );
 PROVIDE ( HOST = 0x60015000 );
 PROVIDE ( RMT = 0x60016000 );
 PROVIDE ( RMTMEM = 0x60016800 );
diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt
index c51569dc22..c1528ca06c 100644
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@@ -714,7 +714,6 @@ components/soc/esp32s3/include/soc/uart_pins.h
 components/soc/esp32s3/include/soc/uart_reg.h
 components/soc/esp32s3/include/soc/uart_struct.h
 components/soc/esp32s3/include/soc/uhci_reg.h
-components/soc/esp32s3/include/soc/uhci_struct.h
 components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
 components/soc/esp32s3/include/soc/usb_wrap_reg.h
 components/soc/esp32s3/include/soc/usb_wrap_struct.h