diff --git a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h
index eb98a8ebc4..a49f74d367 100644
--- a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h
+++ b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h
@@ -79,7 +79,6 @@ typedef enum {
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
     RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core (hp system)*/
     DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core (hp system)*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core (hp system)*/
     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core (hp system)*/
@@ -121,7 +120,6 @@ typedef enum {
     EXT_EVENT1_TRIG = BIT1,
     GPIO_TRIG       = BIT2,
     TIMER_EXPIRE    = BIT3,
-    SDIO_TRIG       = BIT4,
     MAC_TRIG        = BIT5,
     UART0_TRIG      = BIT6,
     UART1_TRIG      = BIT7,
@@ -140,7 +138,6 @@ typedef enum {
     EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
     GPIO_TRIG_EN       = GPIO_TRIG,
     TIMER_EXPIRE_EN    = TIMER_EXPIRE,
-    SDIO_TRIG_EN       = SDIO_TRIG,
     MAC_TRIG_EN        = MAC_TRIG,
     UART0_TRIG_EN      = UART0_TRIG,
     UART1_TRIG_EN      = UART1_TRIG,
diff --git a/components/esp_rom/include/esp32c61/rom/rtc.h b/components/esp_rom/include/esp32c61/rom/rtc.h
index e0a775d302..fc3e04e161 100644
--- a/components/esp_rom/include/esp32c61/rom/rtc.h
+++ b/components/esp_rom/include/esp32c61/rom/rtc.h
@@ -80,7 +80,6 @@ typedef enum {
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
     RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core (hp system)*/
     DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core (hp system)*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core (hp system)*/
     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core (hp system)*/
@@ -101,7 +100,6 @@ typedef enum {
 ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
 ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
 ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
-ESP_STATIC_ASSERT((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
@@ -123,7 +121,6 @@ typedef enum {
     EXT_EVENT1_TRIG = BIT1,
     GPIO_TRIG       = BIT2,
     TIMER_EXPIRE    = BIT3,
-    SDIO_TRIG       = BIT4,
     MAC_TRIG        = BIT5,
     UART0_TRIG      = BIT6,
     UART1_TRIG      = BIT7,
@@ -142,7 +139,6 @@ typedef enum {
     EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
     GPIO_TRIG_EN       = GPIO_TRIG,
     TIMER_EXPIRE_EN    = TIMER_EXPIRE,
-    SDIO_TRIG_EN       = SDIO_TRIG,
     MAC_TRIG_EN        = MAC_TRIG,
     UART0_TRIG_EN      = UART0_TRIG,
     UART1_TRIG_EN      = UART1_TRIG,
diff --git a/components/esp_system/port/soc/esp32c61/reset_reason.c b/components/esp_system/port/soc/esp32c61/reset_reason.c
index 84d8798417..458cb0f585 100644
--- a/components/esp_system/port/soc/esp32c61/reset_reason.c
+++ b/components/esp_system/port/soc/esp32c61/reset_reason.c
@@ -62,9 +62,6 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     case RESET_REASON_CPU0_JTAG:
         return ESP_RST_JTAG;
 
-    case RESET_REASON_CORE_SDIO:
-        return ESP_RST_SDIO;
-
     default:
         return ESP_RST_UNKNOWN;
     }
diff --git a/components/soc/esp32c61/include/soc/reset_reasons.h b/components/soc/esp32c61/include/soc/reset_reasons.h
index 074d599720..d9e12683d2 100644
--- a/components/soc/esp32c61/include/soc/reset_reasons.h
+++ b/components/soc/esp32c61/include/soc/reset_reasons.h
@@ -32,7 +32,6 @@ typedef enum {
     RESET_REASON_CHIP_BROWN_OUT  = 0x01, // VDD voltage is not stable and resets the chip
     RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
     RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
-    RESET_REASON_CORE_SDIO       = 0x06, // SDIO module resets the digital core (hp system)
     RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core (hp system)
     RESET_REASON_CORE_MWDT1      = 0x08, // Main watch dog 1 resets digital core (hp system)
     RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core (hp system)