diff --git a/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c b/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c index c5c3e645c8..937414c6e7 100644 --- a/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c +++ b/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c @@ -52,7 +52,7 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = { { .regn_num = 1, .regn_start_addr = SOC_PERIPHERAL_LOW, - .regn_end_addr = (DR_REG_INTERRUPT_MATRIX_BASE - 0x4), + .regn_end_addr = (DR_REG_INTMTX_BASE - 0x4), .regn_pms = 0x6, .filter_enable = 1, }, diff --git a/components/hal/include/hal/interrupt_plic_ll.h b/components/hal/include/hal/interrupt_plic_ll.h index 3862df0734..ab6993c1d1 100644 --- a/components/hal/include/hal/interrupt_plic_ll.h +++ b/components/hal/include/hal/interrupt_plic_ll.h @@ -27,7 +27,7 @@ extern "C" { */ FORCE_INLINE_ATTR void interrupt_plic_ll_route(int intr_src, int intr_num) { - REG_WRITE(DR_REG_INTERRUPT_MATRIX_BASE + 4 * intr_src, intr_num); + REG_WRITE(DR_REG_INTMTX_BASE + 4 * intr_src, intr_num); } diff --git a/components/soc/esp32c5/register/soc/reg_base.h b/components/soc/esp32c5/register/soc/reg_base.h index b2516ec71c..e5df7a8592 100644 --- a/components/soc/esp32c5/register/soc/reg_base.h +++ b/components/soc/esp32c5/register/soc/reg_base.h @@ -26,8 +26,8 @@ #define DR_REG_TWAI1_BASE 0x6000D000 #define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_MCPWM_BASE 0x60014000 diff --git a/components/soc/esp32c5/system_retention_periph.c b/components/soc/esp32c5/system_retention_periph.c index 9f9abd98d8..b8c4e1c675 100644 --- a/components/soc/esp32c5/system_retention_periph.c +++ b/components/soc/esp32c5/system_retention_periph.c @@ -19,9 +19,9 @@ #include "soc/interrupt_matrix_reg.h" /* Interrupt Matrix Registers Context */ -#define N_REGS_INTR_MATRIX() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1) +#define N_REGS_INTR_MATRIX() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTMTX_BASE) / 4) + 1) const regdma_entries_config_t intr_matrix_regs_retention[] = { - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTMTX_BASE, DR_REG_INTMTX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ }; _Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions"); diff --git a/components/soc/esp32c6/include/soc/interrupt_reg.h b/components/soc/esp32c6/include/soc/interrupt_reg.h index e111811dbf..80265c4f69 100644 --- a/components/soc/esp32c6/include/soc/interrupt_reg.h +++ b/components/soc/esp32c6/include/soc/interrupt_reg.h @@ -42,4 +42,4 @@ #define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) #endif -#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h index a2e729de2b..ae4b390503 100644 --- a/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h @@ -13,7 +13,7 @@ extern "C" { /** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0) /** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -25,7 +25,7 @@ extern "C" { /** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x4) /** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -37,7 +37,7 @@ extern "C" { /** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8) /** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -49,7 +49,7 @@ extern "C" { /** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) +#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc) /** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -61,7 +61,7 @@ extern "C" { /** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) +#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10) /** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -73,7 +73,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) +#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14) /** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -85,7 +85,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) +#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x18) /** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -97,7 +97,7 @@ extern "C" { /** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) +#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x1c) /** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -109,7 +109,7 @@ extern "C" { /** INTMTX_CORE0_COEX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) +#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x20) /** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -121,7 +121,7 @@ extern "C" { /** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x24) /** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -133,7 +133,7 @@ extern "C" { /** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x28) /** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -145,7 +145,7 @@ extern "C" { /** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) +#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c) /** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -157,7 +157,7 @@ extern "C" { /** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30) /** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -169,7 +169,7 @@ extern "C" { /** INTMTX_CORE0_PMU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) +#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34) /** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -181,7 +181,7 @@ extern "C" { /** INTMTX_CORE0_EFUSE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) +#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38) /** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -193,7 +193,7 @@ extern "C" { /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c) /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -205,7 +205,7 @@ extern "C" { /** INTMTX_CORE0_LP_UART_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) +#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40) /** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -217,7 +217,7 @@ extern "C" { /** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) +#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x44) /** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -229,7 +229,7 @@ extern "C" { /** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) +#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48) /** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -241,7 +241,7 @@ extern "C" { /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c) /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -253,7 +253,7 @@ extern "C" { /** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50) /** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -265,7 +265,7 @@ extern "C" { /** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54) /** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -277,7 +277,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x58) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -289,7 +289,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x5c) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -301,7 +301,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x60) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -313,7 +313,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x64) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -325,7 +325,7 @@ extern "C" { /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68) /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -337,7 +337,7 @@ extern "C" { /** INTMTX_CORE0_TRACE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) +#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c) /** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -349,7 +349,7 @@ extern "C" { /** INTMTX_CORE0_CACHE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) +#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70) /** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -361,7 +361,7 @@ extern "C" { /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74) /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -373,7 +373,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x78) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -385,7 +385,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x7c) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -397,7 +397,7 @@ extern "C" { /** INTMTX_CORE0_PAU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) +#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80) /** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -409,7 +409,7 @@ extern "C" { /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84) /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -421,7 +421,7 @@ extern "C" { /** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88) /** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -433,7 +433,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c) /** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -445,7 +445,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90) /** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -457,7 +457,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94) /** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -469,7 +469,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98) /** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -481,7 +481,7 @@ extern "C" { /** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) +#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c) /** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -493,7 +493,7 @@ extern "C" { /** INTMTX_CORE0_MSPI_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) +#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0) /** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -505,7 +505,7 @@ extern "C" { /** INTMTX_CORE0_I2S_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) +#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4) /** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -517,7 +517,7 @@ extern "C" { /** INTMTX_CORE0_UHCI0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) +#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8) /** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -529,7 +529,7 @@ extern "C" { /** INTMTX_CORE0_UART0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) +#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac) /** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -541,7 +541,7 @@ extern "C" { /** INTMTX_CORE0_UART1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) +#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0) /** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -553,7 +553,7 @@ extern "C" { /** INTMTX_CORE0_LEDC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) +#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4) /** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -565,7 +565,7 @@ extern "C" { /** INTMTX_CORE0_CAN0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) +#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8) /** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -577,7 +577,7 @@ extern "C" { /** INTMTX_CORE0_CAN1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) +#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc) /** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -589,7 +589,7 @@ extern "C" { /** INTMTX_CORE0_USB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) +#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0) /** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -601,7 +601,7 @@ extern "C" { /** INTMTX_CORE0_RMT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) +#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4) /** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -613,7 +613,7 @@ extern "C" { /** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8) /** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -625,7 +625,7 @@ extern "C" { /** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) +#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc) /** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -637,7 +637,7 @@ extern "C" { /** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) +#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0) /** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -649,7 +649,7 @@ extern "C" { /** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4) /** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -661,7 +661,7 @@ extern "C" { /** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) +#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8) /** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -673,7 +673,7 @@ extern "C" { /** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) +#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc) /** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -685,7 +685,7 @@ extern "C" { /** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0) /** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -697,7 +697,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4) /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -709,7 +709,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8) /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -721,7 +721,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec) /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -733,7 +733,7 @@ extern "C" { /** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) +#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0) /** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -745,7 +745,7 @@ extern "C" { /** INTMTX_CORE0_PWM_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) +#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4) /** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -757,7 +757,7 @@ extern "C" { /** INTMTX_CORE0_PCNT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) +#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8) /** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -769,7 +769,7 @@ extern "C" { /** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) +#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc) /** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -781,7 +781,7 @@ extern "C" { /** INTMTX_CORE0_SLC0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) +#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100) /** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -793,7 +793,7 @@ extern "C" { /** INTMTX_CORE0_SLC1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) +#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x104) /** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -805,7 +805,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x108) /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -817,7 +817,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10c) /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -829,7 +829,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x110) /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -841,7 +841,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114) +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x114) /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -853,7 +853,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118) +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x118) /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -865,7 +865,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c) +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x11c) /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -877,7 +877,7 @@ extern "C" { /** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120) +#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x120) /** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -889,7 +889,7 @@ extern "C" { /** INTMTX_CORE0_AES_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124) +#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x124) /** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -901,7 +901,7 @@ extern "C" { /** INTMTX_CORE0_SHA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128) +#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x128) /** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -913,7 +913,7 @@ extern "C" { /** INTMTX_CORE0_RSA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c) +#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x12c) /** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -925,7 +925,7 @@ extern "C" { /** INTMTX_CORE0_ECC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130) +#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x130) /** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * Need add description */ @@ -937,7 +937,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_0_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134) +#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x134) /** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; * Need add description */ @@ -949,7 +949,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_1_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138) +#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x138) /** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; * Need add description */ @@ -961,7 +961,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_2_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c) +#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x13c) /** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; * Need add description */ @@ -973,7 +973,7 @@ extern "C" { /** INTMTX_CORE0_CLOCK_GATE_REG register * register description */ -#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140) +#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x140) /** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; * Need add description */ @@ -985,7 +985,7 @@ extern "C" { /** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register * register description */ -#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) +#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc) /** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144; * Need add description */ diff --git a/components/soc/esp32c6/register/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h index 603ccc602e..3e7a47af40 100644 --- a/components/soc/esp32c6/register/soc/reg_base.h +++ b/components/soc/esp32c6/register/soc/reg_base.h @@ -26,7 +26,7 @@ #define DR_REG_TWAI1_BASE 0x6000D000 #define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTMTX_BASE 0x60010000 #define DR_REG_ATOMIC_BASE 0x60011000 #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 diff --git a/components/soc/esp32c6/system_retention_periph.c b/components/soc/esp32c6/system_retention_periph.c index 8d1a56ea7f..25f1b093d3 100644 --- a/components/soc/esp32c6/system_retention_periph.c +++ b/components/soc/esp32c6/system_retention_periph.c @@ -19,9 +19,9 @@ #include "soc/interrupt_matrix_reg.h" /* Interrupt Matrix Registers Context */ -#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1) +#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTMTX_BASE) / 4) + 1) const regdma_entries_config_t intr_matrix_regs_retention[] = { - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTMTX_BASE, DR_REG_INTMTX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ }; _Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions"); diff --git a/components/soc/esp32c61/include/soc/interrupt_reg.h b/components/soc/esp32c61/include/soc/interrupt_reg.h index 6fe29fee6a..7dffc583d0 100644 --- a/components/soc/esp32c61/include/soc/interrupt_reg.h +++ b/components/soc/esp32c61/include/soc/interrupt_reg.h @@ -15,4 +15,4 @@ #define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index ca6ee32e03..bf56d907e3 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -24,7 +24,7 @@ #define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h index 67732ccf6a..8188103611 100644 --- a/components/soc/esp32c61/register/soc/reg_base.h +++ b/components/soc/esp32c61/register/soc/reg_base.h @@ -19,7 +19,7 @@ #define DR_REG_I2S_BASE 0x6000C000 #define DR_REG_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTMTX_BASE 0x60010000 #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_PVT_MONITOR_BASE 0x60019000 #define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 diff --git a/components/soc/esp32h2/include/soc/interrupt_reg.h b/components/soc/esp32h2/include/soc/interrupt_reg.h index 4faef7949b..7e870b5410 100644 --- a/components/soc/esp32h2/include/soc/interrupt_reg.h +++ b/components/soc/esp32h2/include/soc/interrupt_reg.h @@ -21,4 +21,4 @@ #define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG #define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG #define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) -#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h index c526cacc8b..e6d7cec9c7 100644 --- a/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h @@ -14,7 +14,7 @@ extern "C" { /** INTMTX_CORE0_PMU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) +#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0) /** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PMU_INTR mapping register */ @@ -26,7 +26,7 @@ extern "C" { /** INTMTX_CORE0_EFUSE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) +#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4) /** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_EFUSE_INTR mapping register */ @@ -38,7 +38,7 @@ extern "C" { /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8) /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_RTC_TIMER_INTR mapping register */ @@ -50,7 +50,7 @@ extern "C" { /** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc) /** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_BLE_TIMER_INTR mapping register */ @@ -62,7 +62,7 @@ extern "C" { /** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) +#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10) /** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_WDT_INTR mapping register */ @@ -74,7 +74,7 @@ extern "C" { /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14) /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_PERI_TIMEOUT_INTR mapping register */ @@ -86,7 +86,7 @@ extern "C" { /** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x18) /** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_APM_M0_INTR mapping register */ @@ -98,7 +98,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x1c) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_0 mapping register */ @@ -110,7 +110,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x20) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_1 mapping register */ @@ -122,7 +122,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x24) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_2 mapping register */ @@ -134,7 +134,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x28) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_3 mapping register */ @@ -146,7 +146,7 @@ extern "C" { /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c) /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ASSIST_DEBUG_INTR mapping register */ @@ -158,7 +158,7 @@ extern "C" { /** INTMTX_CORE0_TRACE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) +#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30) /** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TRACE_INTR mapping register */ @@ -170,7 +170,7 @@ extern "C" { /** INTMTX_CORE0_CACHE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) +#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34) /** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CACHE_INTR mapping register */ @@ -182,7 +182,7 @@ extern "C" { /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38) /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_PERI_TIMEOUT_INTR mapping register */ @@ -194,7 +194,7 @@ extern "C" { /** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) +#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c) /** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_MAC_INTR mapping register */ @@ -206,7 +206,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) +#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40) /** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_BB_INTR mapping register */ @@ -218,7 +218,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) +#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x44) /** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_BB_NMI mapping register */ @@ -230,7 +230,7 @@ extern "C" { /** INTMTX_CORE0_COEX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) +#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48) /** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_COEX_INTR mapping register */ @@ -242,7 +242,7 @@ extern "C" { /** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c) /** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BLE_TIMER_INTR mapping register */ @@ -254,7 +254,7 @@ extern "C" { /** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50) /** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BLE_SEC_INTR mapping register */ @@ -266,7 +266,7 @@ extern "C" { /** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54) /** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ZB_MAC_INTR mapping register */ @@ -278,7 +278,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x58) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPIO_INTERRUPT_PRO mapping register */ @@ -290,7 +290,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x5c) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPIO_INTERRUPT_PRO_NMI mapping register */ @@ -302,7 +302,7 @@ extern "C" { /** INTMTX_CORE0_PAU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) +#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60) /** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PAU_INTR mapping register */ @@ -314,7 +314,7 @@ extern "C" { /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64) /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_PERI_TIMEOUT_INTR mapping register */ @@ -326,7 +326,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68) /** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M0_INTR mapping register */ @@ -338,7 +338,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c) /** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M1_INTR mapping register */ @@ -350,7 +350,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70) /** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M2_INTR mapping register */ @@ -362,7 +362,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74) /** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M3_INTR mapping register */ @@ -374,7 +374,7 @@ extern "C" { /** INTMTX_CORE0_MSPI_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) +#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78) /** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_MSPI_INTR mapping register */ @@ -386,7 +386,7 @@ extern "C" { /** INTMTX_CORE0_I2S_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) +#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c) /** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2S_INTR mapping register */ @@ -398,7 +398,7 @@ extern "C" { /** INTMTX_CORE0_UHCI0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) +#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80) /** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UHCI0_INTR mapping register */ @@ -410,7 +410,7 @@ extern "C" { /** INTMTX_CORE0_UART0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) +#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84) /** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UART0_INTR mapping register */ @@ -422,7 +422,7 @@ extern "C" { /** INTMTX_CORE0_UART1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) +#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88) /** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UART1_INTR mapping register */ @@ -434,7 +434,7 @@ extern "C" { /** INTMTX_CORE0_LEDC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) +#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c) /** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LEDC_INTR mapping register */ @@ -446,7 +446,7 @@ extern "C" { /** INTMTX_CORE0_CAN0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) +#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90) /** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CAN0_INTR mapping register */ @@ -458,7 +458,7 @@ extern "C" { /** INTMTX_CORE0_USB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) +#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94) /** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_USB_INTR mapping register */ @@ -470,7 +470,7 @@ extern "C" { /** INTMTX_CORE0_RMT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) +#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98) /** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_RMT_INTR mapping register */ @@ -482,7 +482,7 @@ extern "C" { /** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c) /** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2C_EXT0_INTR mapping register */ @@ -494,7 +494,7 @@ extern "C" { /** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0) /** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2C_EXT1_INTR mapping register */ @@ -506,7 +506,7 @@ extern "C" { /** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) +#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4) /** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG0_T0_INTR mapping register */ @@ -518,7 +518,7 @@ extern "C" { /** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8) /** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG0_WDT_INTR mapping register */ @@ -530,7 +530,7 @@ extern "C" { /** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) +#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac) /** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG1_T0_INTR mapping register */ @@ -542,7 +542,7 @@ extern "C" { /** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0) /** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG1_WDT_INTR mapping register */ @@ -554,7 +554,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4) /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET0_INTR mapping register */ @@ -566,7 +566,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8) /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET1_INTR mapping register */ @@ -578,7 +578,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc) /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET2_INTR mapping register */ @@ -590,7 +590,7 @@ extern "C" { /** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) +#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0) /** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_APB_ADC_INTR mapping register */ @@ -602,7 +602,7 @@ extern "C" { /** INTMTX_CORE0_PWM_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) +#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4) /** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PWM_INTR mapping register */ @@ -614,7 +614,7 @@ extern "C" { /** INTMTX_CORE0_PCNT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) +#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8) /** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PCNT_INTR mapping register */ @@ -626,7 +626,7 @@ extern "C" { /** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc) /** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PARL_IO_TX_INTR mapping register */ @@ -638,7 +638,7 @@ extern "C" { /** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0) /** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PARL_IO_RX_INTR mapping register */ @@ -650,7 +650,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4) /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH0_INTR mapping register */ @@ -662,7 +662,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8) /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH1_INTR mapping register */ @@ -674,7 +674,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc) /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH2_INTR mapping register */ @@ -686,7 +686,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0) /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH0_INTR mapping register */ @@ -698,7 +698,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4) /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH1_INTR mapping register */ @@ -710,7 +710,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8) /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH2_INTR mapping register */ @@ -722,7 +722,7 @@ extern "C" { /** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) +#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec) /** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPSPI2_INTR mapping register */ @@ -734,7 +734,7 @@ extern "C" { /** INTMTX_CORE0_AES_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) +#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0) /** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_AES_INTR mapping register */ @@ -746,7 +746,7 @@ extern "C" { /** INTMTX_CORE0_SHA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) +#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4) /** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SHA_INTR mapping register */ @@ -758,7 +758,7 @@ extern "C" { /** INTMTX_CORE0_RSA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) +#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8) /** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_RSA_INTR mapping register */ @@ -770,7 +770,7 @@ extern "C" { /** INTMTX_CORE0_ECC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) +#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc) /** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ECC_INTR mapping register */ @@ -782,7 +782,7 @@ extern "C" { /** INTMTX_CORE0_ECDSA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) +#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100) /** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ECDSA_INTR mapping register */ @@ -794,7 +794,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_0_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) +#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x104) /** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 0~31 mapping register */ @@ -806,7 +806,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_1_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) +#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x108) /** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 32~63 mapping register */ @@ -818,7 +818,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_2_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) +#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x10c) /** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 64~95 mapping register */ @@ -830,7 +830,7 @@ extern "C" { /** INTMTX_CORE0_CLOCK_GATE_REG register * register description */ -#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) +#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x110) /** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; * Clock register */ @@ -842,7 +842,7 @@ extern "C" { /** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register * register description */ -#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) +#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc) /** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784; * Version control register */ diff --git a/components/soc/esp32h2/register/soc/reg_base.h b/components/soc/esp32h2/register/soc/reg_base.h index 1a5a0e4f0a..db76fc37f1 100644 --- a/components/soc/esp32h2/register/soc/reg_base.h +++ b/components/soc/esp32h2/register/soc/reg_base.h @@ -20,7 +20,7 @@ #define DR_REG_I2S_BASE 0x6000D000 #define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTMTX_BASE 0x60010000 #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_MCPWM_BASE 0x60014000 diff --git a/components/soc/esp32h2/system_retention_periph.c b/components/soc/esp32h2/system_retention_periph.c index 3ef3b168bc..463a401f92 100644 --- a/components/soc/esp32h2/system_retention_periph.c +++ b/components/soc/esp32h2/system_retention_periph.c @@ -19,9 +19,9 @@ #include "soc/interrupt_matrix_reg.h" /* Interrupt Matrix Registers Context */ -#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1) +#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTMTX_BASE) / 4) + 1) const regdma_entries_config_t intr_matrix_regs_retention[] = { - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTMTX_BASE, DR_REG_INTMTX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ }; _Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions"); diff --git a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h index 79f21ccb00..020976f85f 100644 --- a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h @@ -13,7 +13,7 @@ extern "C" { /** INTMTX_CORE0_PMU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) +#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0) /** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PMU_INTR mapping register */ @@ -25,7 +25,7 @@ extern "C" { /** INTMTX_CORE0_EFUSE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) +#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4) /** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_EFUSE_INTR mapping register */ @@ -37,7 +37,7 @@ extern "C" { /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8) /** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_RTC_TIMER_INTR mapping register */ @@ -49,7 +49,7 @@ extern "C" { /** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc) /** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_BLE_TIMER_INTR mapping register */ @@ -61,7 +61,7 @@ extern "C" { /** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) +#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10) /** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_WDT_INTR mapping register */ @@ -73,7 +73,7 @@ extern "C" { /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14) /** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_PERI_TIMEOUT_INTR mapping register */ @@ -85,7 +85,7 @@ extern "C" { /** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x18) /** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LP_APM_M0_INTR mapping register */ @@ -97,7 +97,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x1c) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_0 mapping register */ @@ -109,7 +109,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x20) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_1 mapping register */ @@ -121,7 +121,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x24) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_2 mapping register */ @@ -133,7 +133,7 @@ extern "C" { /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x28) /** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_INTR_FROM_CPU_3 mapping register */ @@ -145,7 +145,7 @@ extern "C" { /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c) /** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ASSIST_DEBUG_INTR mapping register */ @@ -157,7 +157,7 @@ extern "C" { /** INTMTX_CORE0_TRACE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) +#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30) /** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TRACE_INTR mapping register */ @@ -169,7 +169,7 @@ extern "C" { /** INTMTX_CORE0_CACHE_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) +#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34) /** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CACHE_INTR mapping register */ @@ -181,7 +181,7 @@ extern "C" { /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38) /** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CPU_PERI_TIMEOUT_INTR mapping register */ @@ -193,7 +193,7 @@ extern "C" { /** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) +#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c) /** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_MAC_INTR mapping register */ @@ -205,7 +205,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) +#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40) /** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_BB_INTR mapping register */ @@ -217,7 +217,7 @@ extern "C" { /** INTMTX_CORE0_BT_BB_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) +#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x44) /** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BT_BB_NMI mapping register */ @@ -229,7 +229,7 @@ extern "C" { /** INTMTX_CORE0_COEX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) +#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48) /** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_COEX_INTR mapping register */ @@ -241,7 +241,7 @@ extern "C" { /** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c) /** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BLE_TIMER_INTR mapping register */ @@ -253,7 +253,7 @@ extern "C" { /** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50) /** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_BLE_SEC_INTR mapping register */ @@ -265,7 +265,7 @@ extern "C" { /** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54) /** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ZB_MAC_INTR mapping register */ @@ -277,7 +277,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x58) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPIO_INTERRUPT_PRO mapping register */ @@ -289,7 +289,7 @@ extern "C" { /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register * register description */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x5c) /** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPIO_INTERRUPT_PRO_NMI mapping register */ @@ -301,7 +301,7 @@ extern "C" { /** INTMTX_CORE0_PAU_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) +#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60) /** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PAU_INTR mapping register */ @@ -313,7 +313,7 @@ extern "C" { /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64) /** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_PERI_TIMEOUT_INTR mapping register */ @@ -325,7 +325,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68) /** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M0_INTR mapping register */ @@ -337,7 +337,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c) /** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M1_INTR mapping register */ @@ -349,7 +349,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70) /** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M2_INTR mapping register */ @@ -361,7 +361,7 @@ extern "C" { /** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74) /** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_HP_APM_M3_INTR mapping register */ @@ -373,7 +373,7 @@ extern "C" { /** INTMTX_CORE0_MSPI_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) +#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78) /** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_MSPI_INTR mapping register */ @@ -385,7 +385,7 @@ extern "C" { /** INTMTX_CORE0_I2S1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) +#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c) /** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2S1_INTR mapping register */ @@ -397,7 +397,7 @@ extern "C" { /** INTMTX_CORE0_UHCI0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) +#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80) /** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UHCI0_INTR mapping register */ @@ -409,7 +409,7 @@ extern "C" { /** INTMTX_CORE0_UART0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) +#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84) /** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UART0_INTR mapping register */ @@ -421,7 +421,7 @@ extern "C" { /** INTMTX_CORE0_UART1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) +#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88) /** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_UART1_INTR mapping register */ @@ -433,7 +433,7 @@ extern "C" { /** INTMTX_CORE0_LEDC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) +#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c) /** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_LEDC_INTR mapping register */ @@ -445,7 +445,7 @@ extern "C" { /** INTMTX_CORE0_CAN0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) +#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90) /** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_CAN0_INTR mapping register */ @@ -457,7 +457,7 @@ extern "C" { /** INTMTX_CORE0_USB_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) +#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94) /** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_USB_INTR mapping register */ @@ -469,7 +469,7 @@ extern "C" { /** INTMTX_CORE0_RMT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) +#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98) /** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_RMT_INTR mapping register */ @@ -481,7 +481,7 @@ extern "C" { /** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c) /** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2C_EXT0_INTR mapping register */ @@ -493,7 +493,7 @@ extern "C" { /** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0) /** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_I2C_EXT1_INTR mapping register */ @@ -505,7 +505,7 @@ extern "C" { /** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) +#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4) /** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG0_T0_INTR mapping register */ @@ -517,7 +517,7 @@ extern "C" { /** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8) /** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG0_WDT_INTR mapping register */ @@ -529,7 +529,7 @@ extern "C" { /** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) +#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac) /** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG1_T0_INTR mapping register */ @@ -541,7 +541,7 @@ extern "C" { /** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0) /** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_TG1_WDT_INTR mapping register */ @@ -553,7 +553,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4) /** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET0_INTR mapping register */ @@ -565,7 +565,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8) /** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET1_INTR mapping register */ @@ -577,7 +577,7 @@ extern "C" { /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc) /** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SYSTIMER_TARGET2_INTR mapping register */ @@ -589,7 +589,7 @@ extern "C" { /** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) +#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0) /** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_APB_ADC_INTR mapping register */ @@ -601,7 +601,7 @@ extern "C" { /** INTMTX_CORE0_PWM_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) +#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4) /** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PWM_INTR mapping register */ @@ -613,7 +613,7 @@ extern "C" { /** INTMTX_CORE0_PCNT_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) +#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8) /** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PCNT_INTR mapping register */ @@ -625,7 +625,7 @@ extern "C" { /** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc) /** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PARL_IO_TX_INTR mapping register */ @@ -637,7 +637,7 @@ extern "C" { /** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0) /** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_PARL_IO_RX_INTR mapping register */ @@ -649,7 +649,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4) /** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH0_INTR mapping register */ @@ -661,7 +661,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8) /** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH1_INTR mapping register */ @@ -673,7 +673,7 @@ extern "C" { /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc) /** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_IN_CH2_INTR mapping register */ @@ -685,7 +685,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0) /** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH0_INTR mapping register */ @@ -697,7 +697,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4) /** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH1_INTR mapping register */ @@ -709,7 +709,7 @@ extern "C" { /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8) /** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_DMA_OUT_CH2_INTR mapping register */ @@ -721,7 +721,7 @@ extern "C" { /** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) +#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec) /** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_GPSPI2_INTR mapping register */ @@ -733,7 +733,7 @@ extern "C" { /** INTMTX_CORE0_AES_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) +#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0) /** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_AES_INTR mapping register */ @@ -745,7 +745,7 @@ extern "C" { /** INTMTX_CORE0_SHA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) +#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4) /** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_SHA_INTR mapping register */ @@ -757,7 +757,7 @@ extern "C" { /** INTMTX_CORE0_RSA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) +#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8) /** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_RSA_INTR mapping register */ @@ -769,7 +769,7 @@ extern "C" { /** INTMTX_CORE0_ECC_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) +#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc) /** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ECC_INTR mapping register */ @@ -781,7 +781,7 @@ extern "C" { /** INTMTX_CORE0_ECDSA_INTR_MAP_REG register * register description */ -#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) +#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100) /** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; * CORE0_ECDSA_INTR mapping register */ @@ -793,7 +793,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_0_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) +#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x104) /** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 0~31 mapping register */ @@ -805,7 +805,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_1_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) +#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x108) /** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 32~63 mapping register */ @@ -817,7 +817,7 @@ extern "C" { /** INTMTX_CORE0_INT_STATUS_REG_2_REG register * register description */ -#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) +#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x10c) /** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; * Status register for interrupt sources 64~95 mapping register */ @@ -829,7 +829,7 @@ extern "C" { /** INTMTX_CORE0_CLOCK_GATE_REG register * register description */ -#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) +#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x110) /** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; * Clock register */ @@ -841,7 +841,7 @@ extern "C" { /** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register * register description */ -#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) +#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc) /** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784; * Version control register */ diff --git a/components/soc/esp32h21/register/soc/interrupt_reg.h b/components/soc/esp32h21/register/soc/interrupt_reg.h index 9d685cddd6..3a631a9839 100644 --- a/components/soc/esp32h21/register/soc/interrupt_reg.h +++ b/components/soc/esp32h21/register/soc/interrupt_reg.h @@ -21,4 +21,4 @@ #define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG #define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG #define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) -#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h index 16e579ec62..916f629504 100644 --- a/components/soc/esp32h21/register/soc/reg_base.h +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -22,7 +22,7 @@ #define DR_REG_I2S0_BASE 0x6000D000 #define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTMTX_BASE 0x60010000 #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_MCPWM0_BASE 0x60014000 diff --git a/components/soc/esp32p4/register/soc/reg_base.h b/components/soc/esp32p4/register/soc/reg_base.h index 0cd0e31006..1f191164bb 100644 --- a/components/soc/esp32p4/register/soc/reg_base.h +++ b/components/soc/esp32p4/register/soc/reg_base.h @@ -178,7 +178,7 @@ #define DR_REG_TIMERGROUP1_BASE DR_REG_TIMG1_BASE #define DR_REG_I2S_BASE DR_REG_I2S0_BASE #define DR_REG_USB_SERIAL_JTAG_BASE DR_REG_USB2JTAG_BASE -#define DR_REG_INTERRUPT_MATRIX_BASE DR_REG_INTR_BASE +#define DR_REG_INTMTX_BASE DR_REG_INTR_BASE #define DR_REG_SOC_ETM_BASE DR_REG_ETM_BASE #define DR_REG_MCPWM_BASE DR_REG_MCPWM0_BASE #define DR_REG_PARL_IO_BASE DR_REG_PARIO_BASE