fix(soc): Add the unavailable TRM mentioned RNG_DATA_REG register for C2 and C3

components/soc/esp32c2/include/soc/wdev_reg.h

@@ -7,6 +7,7 @@
 #pragma once
 
 #include "soc.h"
+#include "soc/syscon_reg.h"
 
 /* Hardware random number generator register */
-#define WDEV_RND_REG 0x600260b0
+#define WDEV_RND_REG RNG_DATA_REG

components/soc/esp32c2/register/soc/syscon_reg.h

@@ -503,6 +503,8 @@ en only when have access the rom have clock.*/
 #define SYSCON_RND_DATA_V  0xFFFFFFFF
 #define SYSCON_RND_DATA_S  0
 
+#define RNG_DATA_REG SYSCON_RND_DATA_REG
+
 #define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0xB4)
 /* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
 /*description: reg_peri_backup_ena.*/

components/soc/esp32c3/include/soc/wdev_reg.h

@@ -1,20 +1,13 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
 #include "soc.h"
+#include "soc/syscon_reg.h"
 
 /* Hardware random number generator register */
-#define WDEV_RND_REG 0x600260b0
+#define WDEV_RND_REG RNG_DATA_REG

components/soc/esp32c3/register/soc/syscon_reg.h

@@ -497,6 +497,8 @@ extern "C" {
 #define SYSCON_RND_DATA_V  0xFFFFFFFF
 #define SYSCON_RND_DATA_S  0
 
+#define RNG_DATA_REG SYSCON_RND_DATA_REG
+
 #define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0x0B4)
 /* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
 /*description: */