diff --git a/components/soc/esp32/adc_periph.c b/components/soc/esp32/adc_periph.c index 4e2d22da4e..78243a6439 100644 --- a/components/soc/esp32/adc_periph.c +++ b/components/soc/esp32/adc_periph.c @@ -1,25 +1,21 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/adc_periph.h" /* Store IO number corresponding to the ADC channel number. */ const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { /* ADC1 */ - {ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM, - ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, -1, -1}, + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM, + ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, -1, -1 + }, /* ADC2 */ - {ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM, - ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM} + { + ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM, + ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM + } }; diff --git a/components/soc/esp32/dport_access.c b/components/soc/esp32/dport_access.c index 95cebd9c42..eb21d398fe 100644 --- a/components/soc/esp32/dport_access.c +++ b/components/soc/esp32/dport_access.c @@ -17,17 +17,17 @@ IRAM_ATTR uint32_t esp_dport_access_reg_read(uint32_t reg) #else uint32_t apb; unsigned int intLvl; - __asm__ __volatile__ (\ - "rsil %[LVL], "XTSTR(SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL)"\n"\ - "movi %[APB], "XTSTR(0x3ff40078)"\n"\ - "l32i %[APB], %[APB], 0\n"\ - "l32i %[REG], %[REG], 0\n"\ - "wsr %[LVL], "XTSTR(PS)"\n"\ - "rsync\n"\ - : [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\ - : \ - : "memory" \ - ); + __asm__ __volatile__(\ + "rsil %[LVL], "XTSTR(SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL)"\n"\ + "movi %[APB], "XTSTR(0x3ff40078)"\n"\ + "l32i %[APB], %[APB], 0\n"\ + "l32i %[REG], %[REG], 0\n"\ + "wsr %[LVL], "XTSTR(PS)"\n"\ + "rsync\n"\ + : [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\ + : \ + : "memory" \ + ); return reg; #endif } @@ -38,14 +38,14 @@ IRAM_ATTR uint32_t esp_dport_access_sequence_reg_read(uint32_t reg) return _DPORT_REG_READ(reg); #else uint32_t apb; - __asm__ __volatile__ (\ - "movi %[APB], "XTSTR(0x3ff40078)"\n"\ - "l32i %[APB], %[APB], 0\n"\ - "l32i %[REG], %[REG], 0\n"\ - : [APB]"=a"(apb), [REG]"+a"(reg)\ - : \ - : "memory" \ - ); + __asm__ __volatile__(\ + "movi %[APB], "XTSTR(0x3ff40078)"\n"\ + "l32i %[APB], %[APB], 0\n"\ + "l32i %[REG], %[REG], 0\n"\ + : [APB]"=a"(apb), [REG]"+a"(reg)\ + : \ + : "memory" \ + ); return reg; #endif } diff --git a/components/soc/esp32/include/soc/bb_reg.h b/components/soc/esp32/include/soc/bb_reg.h index 62828b89e5..51ae751d0f 100644 --- a/components/soc/esp32/include/soc/bb_reg.h +++ b/components/soc/esp32/include/soc/bb_reg.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_BB_REG_H_ #define _SOC_BB_REG_H_ @@ -37,5 +29,4 @@ #define BB_DC_EST_FORCE_PD_V 1 #define BB_DC_EST_FORCE_PD_S 0 - #endif /* _SOC_BB_REG_H_ */ diff --git a/components/soc/esp32/include/soc/boot_mode.h b/components/soc/esp32/include/soc/boot_mode.h index 5106e10cfb..28ab835864 100644 --- a/components/soc/esp32/include/soc/boot_mode.h +++ b/components/soc/esp32/include/soc/boot_mode.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_BOOT_MODE_H_ #define _SOC_BOOT_MODE_H_ @@ -18,80 +10,78 @@ #include "soc.h" /*SPI Boot*/ -#define IS_1XXXX(v) (((v)&0x10)==0x10) +#define IS_1XXXX(v) (((v)&0x10)==0x10) /*HSPI Boot*/ -#define IS_010XX(v) (((v)&0x1c)==0x08) +#define IS_010XX(v) (((v)&0x1c)==0x08) /*Download Boot, SDIO/UART0/UART1*/ -#define IS_00XXX(v) (((v)&0x18)==0x00) +#define IS_00XXX(v) (((v)&0x18)==0x00) /*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ -#define IS_00X00(v) (((v)&0x1b)==0x00) +#define IS_00X00(v) (((v)&0x1b)==0x00) /*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ -#define IS_00X01(v) (((v)&0x1b)==0x01) +#define IS_00X01(v) (((v)&0x1b)==0x01) /*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ -#define IS_00X10(v) (((v)&0x1b)==0x02) +#define IS_00X10(v) (((v)&0x1b)==0x02) /*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ -#define IS_00X11(v) (((v)&0x1b)==0x03) +#define IS_00X11(v) (((v)&0x1b)==0x03) /*ATE/ANALOG Mode*/ -#define IS_01110(v) (((v)&0x1f)==0x0e) +#define IS_01110(v) (((v)&0x1f)==0x0e) /*Diagnostic Mode+UART0 download Mode*/ -#define IS_01111(v) (((v)&0x1f)==0x0f) +#define IS_01111(v) (((v)&0x1f)==0x0f) /*legacy SPI Boot*/ -#define IS_01100(v) (((v)&0x1f)==0x0c) +#define IS_01100(v) (((v)&0x1f)==0x0c) /*SDIO_Slave download Mode V1.1*/ -#define IS_01101(v) (((v)&0x1f)==0x0d) - - +#define IS_01101(v) (((v)&0x1f)==0x0d) #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP)) /*do not include download mode*/ -#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET()) +#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET()) /*all spi boot including spi/hspi/legacy*/ -#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) +#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) /*all faster spi boot including spi/hspi*/ -#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET())) +#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET())) /*all spi boot including spi/legacy*/ -#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) +#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) /*all spi boot including hspi/legacy*/ -#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET()) +#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET()) /*all sdio V2 of failing edge input, failing edge output*/ -#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET()) +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET()) /*all sdio V2 of failing edge input, raising edge output*/ -#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET()) +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET()) /*all sdio V2 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET()) /*all sdio V2 of raising edge input, raising edge output*/ -#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET()) /*all sdio V1 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET()) /*do not include download mode*/ -#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET()) +#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET()) /*joint download boot*/ -#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET()) +#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET()) /*ATE mode*/ -#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET()) +#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET()) /*A bit to control flash boot print*/ #define ETS_IS_PRINT_BOOT() (BOOT_MODE_GET() & 0x2) diff --git a/components/soc/esp32/include/soc/clk_tree_defs.h b/components/soc/esp32/include/soc/clk_tree_defs.h index c0b0a8d194..ffdf27170b 100644 --- a/components/soc/esp32/include/soc/clk_tree_defs.h +++ b/components/soc/esp32/include/soc/clk_tree_defs.h @@ -411,7 +411,6 @@ typedef enum { ADC_RTC_CLK_SRC_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the default clock choice */ } soc_periph_adc_rtc_clk_src_t; - //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// /** @@ -446,7 +445,6 @@ typedef enum { LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ } soc_periph_ledc_clk_src_legacy_t; - //////////////////////////////////////////////////SDMMC/////////////////////////////////////////////////////////////// /** @@ -476,7 +474,6 @@ typedef enum { CLKOUT_SIG_INVALID = 0xFF, } soc_clkout_sig_id_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32/include/soc/clkout_channel.h b/components/soc/esp32/include/soc/clkout_channel.h index b660ac1ac3..89548d2f45 100644 --- a/components/soc/esp32/include/soc/clkout_channel.h +++ b/components/soc/esp32/include/soc/clkout_channel.h @@ -36,7 +36,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : -1) #define IS_VALID_CLKOUT_IO(gpio_num) ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO)) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32/include/soc/dac_channel.h b/components/soc/esp32/include/soc/dac_channel.h index 71733e7625..d37ddb2007 100644 --- a/components/soc/esp32/include/soc/dac_channel.h +++ b/components/soc/esp32/include/soc/dac_channel.h @@ -6,7 +6,6 @@ #pragma once - #define DAC_GPIO25_CHANNEL DAC_CHAN_0 #define DAC_CHAN0_GPIO_NUM 25 #define DAC_CHANNEL_1_GPIO_NUM DAC_CHAN0_GPIO_NUM //`DAC_CHANNEL_1_GPIO_NUM` is defined for DAC legacy driver, indicating the first DAC channel. diff --git a/components/soc/esp32/include/soc/dport_access.h b/components/soc/esp32/include/soc/dport_access.h index 972cbf49a4..2c5f71b502 100644 --- a/components/soc/esp32/include/soc/dport_access.h +++ b/components/soc/esp32/include/soc/dport_access.h @@ -108,23 +108,23 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg); void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); #if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND - #define DPORT_INTERRUPT_DISABLE() - #define DPORT_INTERRUPT_RESTORE() - #define DPORT_REG_READ(reg) _DPORT_REG_READ(reg) - #define DPORT_SEQUENCE_REG_READ(reg) _DPORT_REG_READ(reg) +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() +#define DPORT_REG_READ(reg) _DPORT_REG_READ(reg) +#define DPORT_SEQUENCE_REG_READ(reg) _DPORT_REG_READ(reg) #else - #define DPORT_REG_READ(reg) esp_dport_access_reg_read(reg) - #define DPORT_SEQUENCE_REG_READ(reg) esp_dport_access_sequence_reg_read(reg) - #ifndef XTSTR - #define _XTSTR(x) # x - #define XTSTR(x) _XTSTR(x) - #endif +#define DPORT_REG_READ(reg) esp_dport_access_reg_read(reg) +#define DPORT_SEQUENCE_REG_READ(reg) esp_dport_access_sequence_reg_read(reg) +#ifndef XTSTR +#define _XTSTR(x) # x +#define XTSTR(x) _XTSTR(x) +#endif - #define DPORT_INTERRUPT_DISABLE() unsigned intLvl = __extension__({ unsigned __tmp; \ +#define DPORT_INTERRUPT_DISABLE() unsigned intLvl = __extension__({ unsigned __tmp; \ __asm__ __volatile__("rsil %0, " XTSTR(SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL) "\n" \ : "=a" (__tmp) : : "memory" ); \ __tmp;}) - #define DPORT_INTERRUPT_RESTORE() do{ unsigned __tmp = (intLvl); \ +#define DPORT_INTERRUPT_RESTORE() do{ unsigned __tmp = (intLvl); \ __asm__ __volatile__("wsr.ps %0 ; rsync\n" \ : : "a" (__tmp) : "memory" ); \ }while(0) diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index b4bebe9702..f4d026b0cf 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -8,7 +8,6 @@ #include "esp_bit_defs.h" - #ifdef __cplusplus extern "C" { #endif @@ -58,7 +57,6 @@ extern "C" { //MMU entry num, 384 entries that are used in IDF for Flash #define SOC_MMU_ENTRY_NUM 384 - #define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 #define SOC_MMU_IBUS_VADDR_BASE 0x40000000 @@ -88,9 +86,6 @@ extern "C" { #define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (SOC_DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) #define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (SOC_DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) - - - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32/include/soc/gpio_pins.h b/components/soc/esp32/include/soc/gpio_pins.h index 226a4bd0bf..aeac077069 100644 --- a/components/soc/esp32/include/soc/gpio_pins.h +++ b/components/soc/esp32/include/soc/gpio_pins.h @@ -10,7 +10,6 @@ extern "C" { #endif - #define GPIO_MATRIX_CONST_ONE_INPUT (0x38) #define GPIO_MATRIX_CONST_ZERO_INPUT (0x30) diff --git a/components/soc/esp32/include/soc/pid.h b/components/soc/esp32/include/soc/pid.h index bd4e9f26d2..a38c0329b1 100644 --- a/components/soc/esp32/include/soc/pid.h +++ b/components/soc/esp32/include/soc/pid.h @@ -1,65 +1,57 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_PID_H_ #define _SOC_PID_H_ #define PROPID_GEN_BASE 0x3FF1F000 //Bits 1..7: 1 if interrupt will be triggering PID change -#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000) +#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000) //Vectors for the various interrupt handlers -#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004) -#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008) -#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C) -#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010) -#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014) -#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018) -#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C) +#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004) +#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008) +#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C) +#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010) +#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014) +#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018) +#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C) //Delay, in CPU cycles, before switching to new PID -#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020) -#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024) +#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020) +#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024) //Last detected interrupt. Set by hw on int. -#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028) +#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028) //PID/prev int data for each int -#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C) -#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030) -#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034) -#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038) -#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C) -#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040) -#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044) -#define PROPID_FROM_PID_MASK 0x7 -#define PROPID_FROM_PID_S 0 -#define PROPID_FROM_INT_MASK 0xF -#define PROPID_FROM_INT_S 3 +#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C) +#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030) +#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034) +#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038) +#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C) +#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040) +#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044) +#define PROPID_FROM_PID_MASK 0x7 +#define PROPID_FROM_PID_S 0 +#define PROPID_FROM_INT_MASK 0xF +#define PROPID_FROM_INT_S 3 //PID to be set after confirm routine -#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048) +#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048) //Write to kick off PID change -#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c) +#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c) //current PID? -#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050) +#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050) //Write to mask NMI -#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054) +#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054) //Write to unmask NMI -#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058) -#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c) +#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058) +#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c) //Debug regs -#define PROPID_PID ((PROPID_GEN_BASE)+0x060) -#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064) +#define PROPID_PID ((PROPID_GEN_BASE)+0x060) +#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064) #endif /* _SOC_PID_H_ */ diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 1491f79609..340a2a4623 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -19,14 +19,12 @@ #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) - #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) - #ifndef __ASSEMBLER__ #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 27707e7635..60b621eeba 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -318,7 +318,6 @@ #define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - // Peripheral supports DIO, DOUT, QIO, or QOUT #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;}) @@ -356,7 +355,6 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ - /*-------------------------- SPIRAM CAPS -------------------------------------*/ #define SOC_SPIRAM_SUPPORTED 1 @@ -383,7 +381,6 @@ /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (4096) - /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_192 (1) diff --git a/components/soc/esp32/include/soc/soc_pins.h b/components/soc/esp32/include/soc/soc_pins.h index c26f3ca425..0d0107e6e6 100644 --- a/components/soc/esp32/include/soc/soc_pins.h +++ b/components/soc/esp32/include/soc/soc_pins.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* * Pin definition header file. The long term plan is to have a single soc_pins.h for all diff --git a/components/soc/esp32/include/soc/uart_pins.h b/components/soc/esp32/include/soc/uart_pins.h index c84d399768..70252cba08 100644 --- a/components/soc/esp32/include/soc/uart_pins.h +++ b/components/soc/esp32/include/soc/uart_pins.h @@ -1,16 +1,8 @@ -// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32/include/soc/wdev_reg.h b/components/soc/esp32/include/soc/wdev_reg.h index 93b60b2733..aa2a1628fd 100644 --- a/components/soc/esp32/include/soc/wdev_reg.h +++ b/components/soc/esp32/include/soc/wdev_reg.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32/ledc_periph.c b/components/soc/esp32/ledc_periph.c index 2039d62532..d3b2fca798 100644 --- a/components/soc/esp32/ledc_periph.c +++ b/components/soc/esp32/ledc_periph.c @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/ledc_periph.h" #include "soc/gpio_sig_map.h" @@ -20,9 +12,9 @@ */ const ledc_signal_conn_t ledc_periph_signal[2] = { { - .sig_out0_idx = LEDC_HS_SIG_OUT0_IDX, + .sig_out0_idx = LEDC_HS_SIG_OUT0_IDX, }, { - .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, } }; diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h index 9b9f1a46f3..21fbf24382 100644 --- a/components/soc/esp32c2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h @@ -268,7 +268,6 @@ typedef enum { GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */ } soc_periph_glitch_filter_clk_src_t; - //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c2/include/soc/clkout_channel.h b/components/soc/esp32c2/include/soc/clkout_channel.h index 719893aee4..7b185e0c2c 100644 --- a/components/soc/esp32c2/include/soc/clkout_channel.h +++ b/components/soc/esp32c2/include/soc/clkout_channel.h @@ -26,7 +26,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index 61dd8e67ab..c8f481cd09 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -5,7 +5,6 @@ */ #pragma once - #include #include "esp_bit_defs.h" @@ -21,7 +20,6 @@ extern "C" { #define SOC_MMU_PAGE_SIZE 0x10000 #endif - /*IRAM0 is connected with Cache IBUS0*/ #define SOC_IRAM0_ADDRESS_LOW 0x4037C000 #define SOC_IRAM0_ADDRESS_HIGH 0x403C0000 @@ -58,7 +56,7 @@ extern "C" { * valid bit + value bits * valid bit is BIT(6), so value bits are 0x3f */ -#define SOC_MMU_VALID_VAL_MASK 0x3f +#define SOC_MMU_VALID_VAL_MASK 0x3f /** * Max MMU available paddr page num. @@ -134,7 +132,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32c2/include/soc/gpio_pins.h b/components/soc/esp32c2/include/soc/gpio_pins.h index 57ccedaeb9..e3a704eca2 100644 --- a/components/soc/esp32c2/include/soc/gpio_pins.h +++ b/components/soc/esp32c2/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32c2/include/soc/regi2c_defs.h b/components/soc/esp32c2/include/soc/regi2c_defs.h index 99d0e2b5f9..cb2698641b 100644 --- a/components/soc/esp32c2/include/soc/regi2c_defs.h +++ b/components/soc/esp32c2/include/soc/regi2c_defs.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #include "esp_bit_defs.h" @@ -22,7 +21,6 @@ #define ANA_I2C_SAR_FORCE_PD BIT(18) #define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - #define ANA_CONFIG2_REG 0x6004E848 #define ANA_CONFIG2_M BIT(18) diff --git a/components/soc/esp32c2/include/soc/reset_reasons.h b/components/soc/esp32c2/include/soc/reset_reasons.h index ed9226159a..ffe7ac60b5 100644 --- a/components/soc/esp32c2/include/soc/reset_reasons.h +++ b/components/soc/esp32c2/include/soc/reset_reasons.h @@ -43,7 +43,6 @@ typedef enum { RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index a24a2b197e..a1d7b8fa47 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -23,7 +23,6 @@ 0 \ ) - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) diff --git a/components/soc/esp32c2/ledc_periph.c b/components/soc/esp32c2/ledc_periph.c index a401e1f80a..bba8416cf4 100644 --- a/components/soc/esp32c2/ledc_periph.c +++ b/components/soc/esp32c2/ledc_periph.c @@ -11,7 +11,7 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { + { .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + } }; diff --git a/components/soc/esp32c2/uart_periph.c b/components/soc/esp32c2/uart_periph.c index e43bcd0daf..b20c532922 100644 --- a/components/soc/esp32c2/uart_periph.c +++ b/components/soc/esp32c2/uart_periph.c @@ -10,7 +10,7 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { + { .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, diff --git a/components/soc/esp32c3/include/soc/boot_mode.h b/components/soc/esp32c3/include/soc/boot_mode.h index 648d0a4386..5ff864913d 100644 --- a/components/soc/esp32c3/include/soc/boot_mode.h +++ b/components/soc/esp32c3/include/soc/boot_mode.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_BOOT_MODE_H_ #define _SOC_BOOT_MODE_H_ @@ -47,8 +39,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32c3/include/soc/clk_tree_defs.h b/components/soc/esp32c3/include/soc/clk_tree_defs.h index 901f3fa513..a36eceeac5 100644 --- a/components/soc/esp32c3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c3/include/soc/clk_tree_defs.h @@ -340,7 +340,6 @@ typedef enum { ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ } soc_periph_adc_digi_clk_src_t; - //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c3/include/soc/clkout_channel.h b/components/soc/esp32c3/include/soc/clkout_channel.h index 719893aee4..7b185e0c2c 100644 --- a/components/soc/esp32c3/include/soc/clkout_channel.h +++ b/components/soc/esp32c3/include/soc/clkout_channel.h @@ -26,7 +26,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index d78731f148..a40c540251 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -14,7 +14,7 @@ extern "C" { /*IRAM0 is connected with Cache IBUS0*/ #define SOC_IRAM0_ADDRESS_LOW 0x4037C000 #define SOC_IRAM0_ADDRESS_HIGH 0x403E0000 -#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x42800000 /*DRAM0 is connected with Cache DBUS0*/ @@ -102,7 +102,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32c3/include/soc/gpio_num.h b/components/soc/esp32c3/include/soc/gpio_num.h index 7db274eed1..01084fce8a 100644 --- a/components/soc/esp32c3/include/soc/gpio_num.h +++ b/components/soc/esp32c3/include/soc/gpio_num.h @@ -10,7 +10,6 @@ extern "C" { #endif - /** * @brief GPIO number */ diff --git a/components/soc/esp32c3/include/soc/gpio_pins.h b/components/soc/esp32c3/include/soc/gpio_pins.h index 133acc2eef..5064ad2754 100644 --- a/components/soc/esp32c3/include/soc/gpio_pins.h +++ b/components/soc/esp32c3/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32c3/include/soc/regi2c_defs.h b/components/soc/esp32c3/include/soc/regi2c_defs.h index 142851b6f9..874da75e26 100644 --- a/components/soc/esp32c3/include/soc/regi2c_defs.h +++ b/components/soc/esp32c3/include/soc/regi2c_defs.h @@ -20,7 +20,6 @@ #define ANA_I2C_SAR_FORCE_PD BIT(18) #define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - #define ANA_CONFIG2_REG 0x6000E048 #define ANA_CONFIG2_M BIT(18) diff --git a/components/soc/esp32c3/include/soc/reset_reasons.h b/components/soc/esp32c3/include/soc/reset_reasons.h index c624619bb3..a05cdd1361 100644 --- a/components/soc/esp32c3/include/soc/reset_reasons.h +++ b/components/soc/esp32c3/include/soc/reset_reasons.h @@ -1,16 +1,8 @@ -// Copyright 2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -57,7 +49,6 @@ typedef enum { RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c3/ledc_periph.c b/components/soc/esp32c3/ledc_periph.c index 13f87e5c86..0ea7d06015 100644 --- a/components/soc/esp32c3/ledc_periph.c +++ b/components/soc/esp32c3/ledc_periph.c @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/ledc_periph.h" #include "soc/gpio_sig_map.h" @@ -19,7 +11,7 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { + { .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + } }; diff --git a/components/soc/esp32c3/uart_periph.c b/components/soc/esp32c3/uart_periph.c index 73eb978cbe..72b8852608 100644 --- a/components/soc/esp32c3/uart_periph.c +++ b/components/soc/esp32c3/uart_periph.c @@ -10,7 +10,7 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { + { .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, diff --git a/components/soc/esp32c5/etm_periph.c b/components/soc/esp32c5/etm_periph.c index 7b268c443a..0084a78164 100644 --- a/components/soc/esp32c5/etm_periph.c +++ b/components/soc/esp32c5/etm_periph.c @@ -18,19 +18,19 @@ static const regdma_entries_config_t etm_regdma_entries[] = { // restore stage: store the enabled channels [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), - SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), - SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, // backup stage: save configuration registers // restore stage: restore the configuration registers [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), - SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, }; diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c index ee82803157..7fae53a02e 100644 --- a/components/soc/esp32c5/gdma_periph.c +++ b/components/soc/esp32c5/gdma_periph.c @@ -49,18 +49,22 @@ const gdma_signal_conn_t gdma_periph_signals = { static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ - G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - g0p0_regs_map0[0], g0p0_regs_map0[1], \ - g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ - G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - g0p0_regs_map1[0], g0p0_regs_map1[1], \ - g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AHB_DMA Channel (Group0, Pair1) Registers Context @@ -83,18 +87,22 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - g0p1_regs_map0[0], g0p1_regs_map0[1], \ - g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - g0p1_regs_map1[0], g0p1_regs_map1[1], \ - g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AHB_DMA Channel (Group0, Pair2) Registers Context @@ -118,36 +126,40 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0}; static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - } + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } } }; diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c index bd702887f8..fb20be89e3 100644 --- a/components/soc/esp32c5/i2c_periph.c +++ b/components/soc/esp32c5/i2c_periph.c @@ -10,8 +10,7 @@ /* Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc */ -typedef enum -{ +typedef enum { LP_I2C_MUX_FUNC = 0, LP_GPIO_MUX_FUNC = 1, LP_IO_MUX_FUNC_NUM = 2, @@ -54,16 +53,26 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c0_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { diff --git a/components/soc/esp32c5/include/soc/clkout_channel.h b/components/soc/esp32c5/include/soc/clkout_channel.h index 719893aee4..7b185e0c2c 100644 --- a/components/soc/esp32c5/include/soc/clkout_channel.h +++ b/components/soc/esp32c5/include/soc/clkout_channel.h @@ -26,7 +26,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32c5/include/soc/ext_mem_defs.h b/components/soc/esp32c5/include/soc/ext_mem_defs.h index de680754ad..51f3778e2d 100644 --- a/components/soc/esp32c5/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c5/include/soc/ext_mem_defs.h @@ -19,7 +19,6 @@ extern "C" { #define SOC_MMU_PAGE_SIZE 0x10000 #endif - #define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) @@ -114,7 +113,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32c5/include/soc/gpio_pins.h b/components/soc/esp32c5/include/soc/gpio_pins.h index 783e712a31..88c26b35a2 100644 --- a/components/soc/esp32c5/include/soc/gpio_pins.h +++ b/components/soc/esp32c5/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32c5/include/soc/interrupt_reg.h b/components/soc/esp32c5/include/soc/interrupt_reg.h index 4bfbc07b86..74cf892ebe 100644 --- a/components/soc/esp32c5/include/soc/interrupt_reg.h +++ b/components/soc/esp32c5/include/soc/interrupt_reg.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "soc/clic_reg.h" #include "soc/soc_caps.h" diff --git a/components/soc/esp32c5/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/include/soc/regi2c_dig_reg.h index 16b1ebd10a..a11d489e38 100644 --- a/components/soc/esp32c5/include/soc/regi2c_dig_reg.h +++ b/components/soc/esp32c5/include/soc/regi2c_dig_reg.h @@ -59,6 +59,6 @@ #define I2C_DIG_REG_XPD_DIG_REG_MSB 3 #define I2C_DIG_REG_XPD_DIG_REG_LSB 3 -#define I2C_DIG_REG_SCK_DCAP 14 -#define I2C_DIG_REG_SCK_DCAP_MSB 7 -#define I2C_DIG_REG_SCK_DCAP_LSB 0 +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h index 8822b2573a..f433a48b62 100644 --- a/components/soc/esp32c5/include/soc/reset_reasons.h +++ b/components/soc/esp32c5/include/soc/reset_reasons.h @@ -22,7 +22,6 @@ extern "C" { #endif - /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter @@ -50,7 +49,6 @@ typedef enum { RESET_REASON_CPU0_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this) } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c5/ledc_periph.c b/components/soc/esp32c5/ledc_periph.c index 1279e25dce..5a55b87b28 100644 --- a/components/soc/esp32c5/ledc_periph.c +++ b/components/soc/esp32c5/ledc_periph.c @@ -44,38 +44,42 @@ static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0}; static const regdma_entries_config_t ledc_common_regdma_entries[] = { // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), - LEDC_INT_ENA_REG, 0, - (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), - .owner = LEDC_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), - LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, - LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, - ledc_common_regs_map[0], ledc_common_regs_map[1], - ledc_common_regs_map[2], ledc_common_regs_map[3]), - .owner = LEDC_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, }; #define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ - LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ - LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ } #define LEDC_CHANNEL_RETENTION_REGS_CNT 2 static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; #define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ @@ -85,14 +89,14 @@ static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ 1, 0, 0), \ .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ - LEDC_DUTY_START_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ - LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ - LEDC_PARA_UP_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \ LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \ 1, 0, 0), \ @@ -119,48 +123,48 @@ static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANN const ledc_reg_retention_info_t ledc_reg_retention_info = { .common = { - .regdma_entry_array = ledc_common_regdma_entries, - .array_size = ARRAY_SIZE(ledc_common_regdma_entries), - }, - .timer[0] = { - .regdma_entry_array = ledc_timer0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), - }, - .timer[1] = { - .regdma_entry_array = ledc_timer1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), - }, - .timer[2] = { - .regdma_entry_array = ledc_timer2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), - }, - .timer[3] = { - .regdma_entry_array = ledc_timer3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), - }, - .channel[0] = { - .regdma_entry_array = ledc_channel0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), - }, - .channel[1] = { - .regdma_entry_array = ledc_channel1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), - }, - .channel[2] = { - .regdma_entry_array = ledc_channel2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), - }, - .channel[3] = { - .regdma_entry_array = ledc_channel3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), - }, - .channel[4] = { - .regdma_entry_array = ledc_channel4_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), - }, - .channel[5] = { - .regdma_entry_array = ledc_channel5_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), - }, - .module_id = SLEEP_RETENTION_MODULE_LEDC, + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, }; diff --git a/components/soc/esp32c5/mcpwm_periph.c b/components/soc/esp32c5/mcpwm_periph.c index b7f1d71308..aff88c7ab2 100644 --- a/components/soc/esp32c5/mcpwm_periph.c +++ b/components/soc/esp32c5/mcpwm_periph.c @@ -103,19 +103,25 @@ static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0} static const regdma_entries_config_t mcpwm_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, // restore stage: trigger a forced update of all active registers - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) }, + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, }; const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = { diff --git a/components/soc/esp32c5/parlio_periph.c b/components/soc/esp32c5/parlio_periph.c index bd17bfceb1..3d323084ba 100644 --- a/components/soc/esp32c5/parlio_periph.c +++ b/components/soc/esp32c5/parlio_periph.c @@ -62,12 +62,14 @@ static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; static const regdma_entries_config_t parlio_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = { [0] = { diff --git a/components/soc/esp32c5/pcnt_periph.c b/components/soc/esp32c5/pcnt_periph.c index c96644dae1..834053942f 100644 --- a/components/soc/esp32c5/pcnt_periph.c +++ b/components/soc/esp32c5/pcnt_periph.c @@ -82,12 +82,14 @@ static const uint32_t pcnt_regs_map[4] = {0x1f040fff, 0x0, 0x0, 0x0}; static const regdma_entries_config_t pcnt_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ - PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ - PCNT_RETENTION_REGS_CNT, 0, 0, \ - pcnt_regs_map[0], pcnt_regs_map[1], \ - pcnt_regs_map[2], pcnt_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ + PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ + PCNT_RETENTION_REGS_CNT, 0, 0, \ + pcnt_regs_map[0], pcnt_regs_map[1], \ + pcnt_regs_map[2], pcnt_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = { diff --git a/components/soc/esp32c5/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/register/soc/gpio_ext_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_ext_reg.h rename to components/soc/esp32c5/register/soc/gpio_ext_reg.h diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/register/soc/gpio_ext_struct.h similarity index 88% rename from components/soc/esp32c5/include/soc/gpio_ext_struct.h rename to components/soc/esp32c5/register/soc/gpio_ext_struct.h index adf51ea44a..19b033c2b6 100644 --- a/components/soc/esp32c5/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c5/register/soc/gpio_ext_struct.h @@ -19,13 +19,12 @@ typedef union { /** clk_en : R/W; bitpos: [0]; default: 0; * Clock enable bit of configuration registers for sigma delta modulation. */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } gpio_ext_clock_gate_reg_t; - /** Group: SDM Configure Registers */ /** Type of sigmadelta_misc register * MISC Register @@ -37,8 +36,8 @@ typedef union { * 0: Not enable\\ * 1: Enable\\%\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. */ - uint32_t sigmadelta_clk_en:1; - uint32_t reserved_1:31; + uint32_t sigmadelta_clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } gpio_ext_sigmadelta_misc_reg_t; @@ -51,17 +50,16 @@ typedef union { /** sdn_in : R/W; bitpos: [7:0]; default: 0; * Configures the duty cycle of sigma delta modulation output. \\ */ - uint32_t sdn_in:8; + uint32_t sdn_in: 8; /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; * Configures the divider value to divide IO MUX operating clock. \\ */ - uint32_t sdn_prescale:8; - uint32_t reserved_16:16; + uint32_t sdn_prescale: 8; + uint32_t reserved_16: 16; }; uint32_t val; } gpio_ext_sigmadeltan_reg_t; - /** Group: Configure Registers */ /** Type of pad_comp_config_0 register * Configuration register for zero-crossing detection @@ -73,14 +71,14 @@ typedef union { * 0: Disable\\ * 1: Enable\\ */ - uint32_t xpd_comp_0:1; + uint32_t xpd_comp_0: 1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; * Configures the reference voltage for analog PAD voltage comparator.. \\ * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be * used as a regular GPIO\\ * 1: Reference voltage is the voltage on the GPIO8 PAD\\ */ - uint32_t mode_comp_0:1; + uint32_t mode_comp_0: 1; /** dref_comp_0 : R/W; bitpos: [4:2]; default: 0; * Configures the internal reference voltage for analog PAD voltage coparator. \\ * 0: Internal reference voltage is 0 * VDDPST1\\ @@ -89,8 +87,8 @@ typedef union { * 6: Internal reference voltage is 0.6 * VDDPST1\\ * 7: Internal reference voltage is 0.7 * VDDPST1\\ */ - uint32_t dref_comp_0:3; - uint32_t reserved_5:27; + uint32_t dref_comp_0: 3; + uint32_t reserved_5: 27; }; uint32_t val; } gpio_ext_pad_comp_config_0_reg_t; @@ -105,7 +103,7 @@ typedef union { * comparator.\\ * Measurement unit: IO MUX operating clock cycle\\ */ - uint32_t zero_det_filter_cnt_0:32; + uint32_t zero_det_filter_cnt_0: 32; }; uint32_t val; } gpio_ext_pad_comp_filter_0_reg_t; @@ -119,23 +117,22 @@ typedef union { * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. * CLK_OUT_out1 can be found in peripheral output signals. */ - uint32_t clk_out1:5; + uint32_t clk_out1: 5; /** clk_out2 : R/W; bitpos: [9:5]; default: 0; * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. * CLK_OUT_out2 can be found in peripheral output signals. */ - uint32_t clk_out2:5; + uint32_t clk_out2: 5; /** clk_out3 : R/W; bitpos: [14:10]; default: 0; * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. * CLK_OUT_out3 can be found in peripheral output signals. */ - uint32_t clk_out3:5; - uint32_t reserved_15:17; + uint32_t clk_out3: 5; + uint32_t reserved_15: 17; }; uint32_t val; } gpio_ext_pin_ctrl_reg_t; - /** Group: Glitch filter Configure Registers */ /** Type of glitch_filter_chn register * Glitch Filter Configure Register of Channeln @@ -147,7 +144,7 @@ typedef union { * 0: Not enable\\ * 1: Enable\\ */ - uint32_t filter_chn_en:1; + uint32_t filter_chn_en: 1; /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0; * Configures to select the input GPIO for Glitch Filter. \\ * 0: Select GPIO0\\ @@ -157,26 +154,25 @@ typedef union { * 28: Select GPIO28\\ * 29 ~ 63: Reserved\\ */ - uint32_t filter_chn_input_io_num:6; - uint32_t reserved_7:1; + uint32_t filter_chn_input_io_num: 6; + uint32_t reserved_7: 1; /** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be * less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\ * Measurement unit: IO MUX operating clock cycle\\ */ - uint32_t filter_chn_window_thres:6; + uint32_t filter_chn_window_thres: 6; /** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width * is 0 ~ 63. \\ * Measurement unit: IO MUX operating clock cycle\\ */ - uint32_t filter_chn_window_width:6; - uint32_t reserved_20:12; + uint32_t filter_chn_window_width: 6; + uint32_t reserved_20: 12; }; uint32_t val; } gpio_ext_glitch_filter_chn_reg_t; - /** Group: Etm Configure Registers */ /** Type of etm_event_chn_cfg register * Etm Config register of Channeln @@ -192,15 +188,15 @@ typedef union { * 28: Select GPIO28\\ * 29 ~ 63: Reserved\\ */ - uint32_t etm_chn_event_sel:6; - uint32_t reserved_6:1; + uint32_t etm_chn_event_sel: 6; + uint32_t reserved_6: 1; /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; * Configures whether or not to enable ETM event send.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_chn_event_en:1; - uint32_t reserved_8:24; + uint32_t etm_chn_event_en: 1; + uint32_t reserved_8: 24; }; uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; @@ -226,14 +222,14 @@ typedef union { * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO * choose a etm task channel. */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_3:2; + uint32_t etm_task_gpio0_sel: 3; + uint32_t reserved_3: 2; /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; * Configures whether or not to enable GPIO$n to response ETM task.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_task_gpio0_en:1; + uint32_t etm_task_gpio0_en: 1; /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; * Configures to select an ETM task channel for GPIO$n.\\ * 0: Select channel 0\\ @@ -250,14 +246,14 @@ typedef union { * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO * choose a etm task channel. */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_9:2; + uint32_t etm_task_gpio1_sel: 3; + uint32_t reserved_9: 2; /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; * Configures whether or not to enable GPIO$n to response ETM task.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_task_gpio1_en:1; + uint32_t etm_task_gpio1_en: 1; /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; * Configures to select an ETM task channel for GPIO$n.\\ * 0: Select channel 0\\ @@ -274,14 +270,14 @@ typedef union { * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO * choose a etm task channel. */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_15:2; + uint32_t etm_task_gpio2_sel: 3; + uint32_t reserved_15: 2; /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable GPIO$n to response ETM task.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_task_gpio2_en:1; + uint32_t etm_task_gpio2_en: 1; /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; * Configures to select an ETM task channel for GPIO$n.\\ * 0: Select channel 0\\ @@ -298,14 +294,14 @@ typedef union { * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO * choose a etm task channel. */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_21:2; + uint32_t etm_task_gpio3_sel: 3; + uint32_t reserved_21: 2; /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; * Configures whether or not to enable GPIO$n to response ETM task.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_task_gpio3_en:1; + uint32_t etm_task_gpio3_en: 1; /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; * Configures to select an ETM task channel for GPIO$n.\\ * 0: Select channel 0\\ @@ -322,21 +318,19 @@ typedef union { * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO * choose a etm task channel. */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_27:2; + uint32_t etm_task_gpio4_sel: 3; + uint32_t reserved_27: 2; /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; * Configures whether or not to enable GPIO$n to response ETM task.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_task_gpio4_en:1; - uint32_t reserved_30:2; + uint32_t etm_task_gpio4_en: 1; + uint32_t reserved_30: 2; }; uint32_t val; } gpio_ext_etm_task_pn_cfg_reg_t; - - /** Group: Interrupt Registers */ /** Type of int_raw register * GPIO_EXT interrupt raw register @@ -346,16 +340,16 @@ typedef union { /** comp_neg_0_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; * analog comparator pos edge interrupt raw */ - uint32_t comp_neg_0_int_raw:1; + uint32_t comp_neg_0_int_raw: 1; /** comp_pos_0_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; * analog comparator neg edge interrupt raw */ - uint32_t comp_pos_0_int_raw:1; + uint32_t comp_pos_0_int_raw: 1; /** comp_all_0_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; * analog comparator neg or pos edge interrupt raw */ - uint32_t comp_all_0_int_raw:1; - uint32_t reserved_3:29; + uint32_t comp_all_0_int_raw: 1; + uint32_t reserved_3: 29; }; uint32_t val; } gpio_ext_int_raw_reg_t; @@ -368,16 +362,16 @@ typedef union { /** comp_neg_0_int_st : RO; bitpos: [0]; default: 0; * analog comparator pos edge interrupt status */ - uint32_t comp_neg_0_int_st:1; + uint32_t comp_neg_0_int_st: 1; /** comp_pos_0_int_st : RO; bitpos: [1]; default: 0; * analog comparator neg edge interrupt status */ - uint32_t comp_pos_0_int_st:1; + uint32_t comp_pos_0_int_st: 1; /** comp_all_0_int_st : RO; bitpos: [2]; default: 0; * analog comparator neg or pos edge interrupt status */ - uint32_t comp_all_0_int_st:1; - uint32_t reserved_3:29; + uint32_t comp_all_0_int_st: 1; + uint32_t reserved_3: 29; }; uint32_t val; } gpio_ext_int_st_reg_t; @@ -390,16 +384,16 @@ typedef union { /** comp_neg_0_int_ena : R/W; bitpos: [0]; default: 1; * analog comparator pos edge interrupt enable */ - uint32_t comp_neg_0_int_ena:1; + uint32_t comp_neg_0_int_ena: 1; /** comp_pos_0_int_ena : R/W; bitpos: [1]; default: 1; * analog comparator neg edge interrupt enable */ - uint32_t comp_pos_0_int_ena:1; + uint32_t comp_pos_0_int_ena: 1; /** comp_all_0_int_ena : R/W; bitpos: [2]; default: 1; * analog comparator neg or pos edge interrupt enable */ - uint32_t comp_all_0_int_ena:1; - uint32_t reserved_3:29; + uint32_t comp_all_0_int_ena: 1; + uint32_t reserved_3: 29; }; uint32_t val; } gpio_ext_int_ena_reg_t; @@ -412,21 +406,20 @@ typedef union { /** comp_neg_0_int_clr : WT; bitpos: [0]; default: 0; * analog comparator pos edge interrupt clear */ - uint32_t comp_neg_0_int_clr:1; + uint32_t comp_neg_0_int_clr: 1; /** comp_pos_0_int_clr : WT; bitpos: [1]; default: 0; * analog comparator neg edge interrupt clear */ - uint32_t comp_pos_0_int_clr:1; + uint32_t comp_pos_0_int_clr: 1; /** comp_all_0_int_clr : WT; bitpos: [2]; default: 0; * analog comparator neg or pos edge interrupt clear */ - uint32_t comp_all_0_int_clr:1; - uint32_t reserved_3:29; + uint32_t comp_all_0_int_clr: 1; + uint32_t reserved_3: 29; }; uint32_t val; } gpio_ext_int_clr_reg_t; - /** Group: Version Register */ /** Type of version register * Version Control Register @@ -436,8 +429,8 @@ typedef union { /** date : R/W; bitpos: [27:0]; default: 36774208; * Version control register. */ - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } gpio_ext_version_reg_t; diff --git a/components/soc/esp32c5/rmt_periph.c b/components/soc/esp32c5/rmt_periph.c index aa92c87aea..6916399d77 100644 --- a/components/soc/esp32c5/rmt_periph.c +++ b/components/soc/esp32c5/rmt_periph.c @@ -50,10 +50,10 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { // restore stage: restore the configuration registers [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_RMT_LINK(0x00), - RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, - RMT_RETENTION_REGS_CNT, 0, 0, - rmt_regs_map[0], rmt_regs_map[1], - rmt_regs_map[2], rmt_regs_map[3]), + RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, + RMT_RETENTION_REGS_CNT, 0, 0, + rmt_regs_map[0], rmt_regs_map[1], + rmt_regs_map[2], rmt_regs_map[3]), .owner = ENTRY(0) | ENTRY(2), }, }; diff --git a/components/soc/esp32c5/system_retention_periph.c b/components/soc/esp32c5/system_retention_periph.c index fbface5460..9f9abd98d8 100644 --- a/components/soc/esp32c5/system_retention_periph.c +++ b/components/soc/esp32c5/system_retention_periph.c @@ -63,8 +63,10 @@ const regdma_entries_config_t iomux_regs_retention[] = { [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_REGS_CNT, 0, 0, - gpio_regs_map[0], gpio_regs_map[1], gpio_regs_map[2], gpio_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, \ + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_REGS_CNT, 0, 0, + gpio_regs_map[0], gpio_regs_map[1], gpio_regs_map[2], gpio_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) + }, \ }; _Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions"); @@ -90,36 +92,36 @@ const regdma_entries_config_t flash_spimem_regs_retention[] = { [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLOCK_GATE_REG(0), N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Note: spimem register should set update reg to make the configuration take effect */ - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CALI_UPDATE, SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CALI_UPDATE, SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions"); /* Systimer Registers Context */ #define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) const regdma_entries_config_t systimer_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ - [1] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */ - [9] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [10] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [11] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [12] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [13] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [14] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [15] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [16] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [16] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */ [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* Systimer intr enable */ diff --git a/components/soc/esp32c5/temperature_sensor_periph.c b/components/soc/esp32c5/temperature_sensor_periph.c index 45410347bd..37e0e7e501 100644 --- a/components/soc/esp32c5/temperature_sensor_periph.c +++ b/components/soc/esp32c5/temperature_sensor_periph.c @@ -29,8 +29,10 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S #define TEMPERATURE_SENSOR_RETENTION_MAP_BASE APB_SARADC_INT_ENA_REG static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; static const regdma_entries_config_t temperature_sensor_regs_entries[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { diff --git a/components/soc/esp32c5/timer_periph.c b/components/soc/esp32c5/timer_periph.c index bb8ce80fed..c3a4d8d109 100644 --- a/components/soc/esp32c5/timer_periph.c +++ b/components/soc/esp32c5/timer_periph.c @@ -39,36 +39,36 @@ const regdma_entries_config_t tg0_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; @@ -77,36 +77,36 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; diff --git a/components/soc/esp32c5/uart_periph.c b/components/soc/esp32c5/uart_periph.c index b98467fc4b..507f3241d8 100644 --- a/components/soc/esp32c5/uart_periph.c +++ b/components/soc/esp32c5/uart_periph.c @@ -10,7 +10,8 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { // HP UART0 + { + // HP UART0 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, @@ -43,7 +44,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART0_INTR_SOURCE, }, - { // HP UART1 + { + // HP UART1 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U1TXD_GPIO_NUM, @@ -76,7 +78,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART1_INTR_SOURCE, }, - { // LP UART0 + { + // LP UART0 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = LP_U0TXD_GPIO_NUM, diff --git a/components/soc/esp32c5/wdt_periph.c b/components/soc/esp32c5/wdt_periph.c index f615401cfa..8d082d6e92 100644 --- a/components/soc/esp32c5/wdt_periph.c +++ b/components/soc/esp32c5/wdt_periph.c @@ -9,21 +9,21 @@ #define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { diff --git a/components/soc/esp32c6/etm_periph.c b/components/soc/esp32c6/etm_periph.c index 7b268c443a..0084a78164 100644 --- a/components/soc/esp32c6/etm_periph.c +++ b/components/soc/esp32c6/etm_periph.c @@ -18,19 +18,19 @@ static const regdma_entries_config_t etm_regdma_entries[] = { // restore stage: store the enabled channels [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), - SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), - SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, // backup stage: save configuration registers // restore stage: restore the configuration registers [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), - SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, }; diff --git a/components/soc/esp32c6/gdma_periph.c b/components/soc/esp32c6/gdma_periph.c index 4e2790c1af..ca0e57f25a 100644 --- a/components/soc/esp32c6/gdma_periph.c +++ b/components/soc/esp32c6/gdma_periph.c @@ -39,12 +39,14 @@ const gdma_signal_conn_t gdma_periph_signals = { #define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ - G0P0_RETENTION_REGS_CNT, 0, 0, \ - g0p0_regs_map[0], g0p0_regs_map[1], \ - g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* GDMA Channel (Group0, Pair1) Registers Context @@ -57,12 +59,14 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { #define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ - G0P1_RETENTION_REGS_CNT, 0, 0, \ - g0p1_regs_map[0], g0p1_regs_map[1], \ - g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* GDMA Channel (Group0, Pair2) Registers Context @@ -78,36 +82,40 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - }, + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, } }; diff --git a/components/soc/esp32c6/i2c_periph.c b/components/soc/esp32c6/i2c_periph.c index c2a39d3c9c..96e46a6529 100644 --- a/components/soc/esp32c6/i2c_periph.c +++ b/components/soc/esp32c6/i2c_periph.c @@ -45,16 +45,26 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c0_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { diff --git a/components/soc/esp32c6/ieee802154_periph.c b/components/soc/esp32c6/ieee802154_periph.c index 275c83bc59..6e9f436aba 100644 --- a/components/soc/esp32c6/ieee802154_periph.c +++ b/components/soc/esp32c6/ieee802154_periph.c @@ -7,6 +7,6 @@ #include "soc/ieee802154_periph.h" const ieee802154_conn_t ieee802154_periph = { - .module = PERIPH_IEEE802154_MODULE, - .irq_id = ETS_ZB_MAC_SOURCE, + .module = PERIPH_IEEE802154_MODULE, + .irq_id = ETS_ZB_MAC_SOURCE, }; diff --git a/components/soc/esp32c6/include/modem/modem_lpcon_struct.h b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h index eafb7933e6..c06ddd5521 100644 --- a/components/soc/esp32c6/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h @@ -12,146 +12,145 @@ extern "C" { typedef union { struct { - uint32_t clk_en:1; - uint32_t clk_debug_ena:1; - uint32_t reserved_2:30; + uint32_t clk_en: 1; + uint32_t clk_debug_ena: 1; + uint32_t reserved_2: 30; }; uint32_t val; } modem_lpcon_test_conf_reg_t; typedef union { struct { - uint32_t clk_lp_timer_sel_osc_slow:1; - uint32_t clk_lp_timer_sel_osc_fast:1; - uint32_t clk_lp_timer_sel_xtal:1; - uint32_t clk_lp_timer_sel_xtal32k:1; - uint32_t clk_lp_timer_div_num:12; - uint32_t reserved_16:16; + uint32_t clk_lp_timer_sel_osc_slow: 1; + uint32_t clk_lp_timer_sel_osc_fast: 1; + uint32_t clk_lp_timer_sel_xtal: 1; + uint32_t clk_lp_timer_sel_xtal32k: 1; + uint32_t clk_lp_timer_div_num: 12; + uint32_t reserved_16: 16; }; uint32_t val; } modem_lpcon_lp_timer_conf_reg_t; typedef union { struct { - uint32_t clk_coex_lp_sel_osc_slow:1; - uint32_t clk_coex_lp_sel_osc_fast:1; - uint32_t clk_coex_lp_sel_xtal:1; - uint32_t clk_coex_lp_sel_xtal32k:1; - uint32_t clk_coex_lp_div_num:12; - uint32_t reserved_16:16; + uint32_t clk_coex_lp_sel_osc_slow: 1; + uint32_t clk_coex_lp_sel_osc_fast: 1; + uint32_t clk_coex_lp_sel_xtal: 1; + uint32_t clk_coex_lp_sel_xtal32k: 1; + uint32_t clk_coex_lp_div_num: 12; + uint32_t reserved_16: 16; }; uint32_t val; } modem_lpcon_coex_lp_clk_conf_reg_t; typedef union { struct { - uint32_t clk_wifipwr_lp_sel_osc_slow:1; - uint32_t clk_wifipwr_lp_sel_osc_fast:1; - uint32_t clk_wifipwr_lp_sel_xtal:1; - uint32_t clk_wifipwr_lp_sel_xtal32k:1; - uint32_t clk_wifipwr_lp_div_num:12; - uint32_t reserved_16:16; + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal: 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num: 12; + uint32_t reserved_16: 16; }; uint32_t val; } modem_lpcon_wifi_lp_clk_conf_reg_t; typedef union { struct { - uint32_t clk_i2c_mst_sel_160m:1; - uint32_t reserved_1:31; + uint32_t clk_i2c_mst_sel_160m: 1; + uint32_t reserved_1: 31; }; uint32_t val; } modem_lpcon_i2c_mst_clk_conf_reg_t; typedef union { struct { - uint32_t clk_modem_32k_sel:2; - uint32_t reserved_2:30; + uint32_t clk_modem_32k_sel: 2; + uint32_t reserved_2: 30; }; uint32_t val; } modem_lpcon_modem_32k_clk_conf_reg_t; typedef union { struct { - uint32_t clk_wifipwr_en:1; - uint32_t clk_coex_en:1; - uint32_t clk_i2c_mst_en:1; - uint32_t clk_lp_timer_en:1; - uint32_t reserved_4:28; + uint32_t clk_wifipwr_en: 1; + uint32_t clk_coex_en: 1; + uint32_t clk_i2c_mst_en: 1; + uint32_t clk_lp_timer_en: 1; + uint32_t reserved_4: 28; }; uint32_t val; } modem_lpcon_clk_conf_reg_t; typedef union { struct { - uint32_t clk_wifipwr_fo:1; - uint32_t clk_coex_fo:1; - uint32_t clk_i2c_mst_fo:1; - uint32_t clk_lp_timer_fo:1; - uint32_t clk_bcmem_fo:1; - uint32_t clk_i2c_mst_mem_fo:1; - uint32_t clk_chan_freq_mem_fo:1; - uint32_t clk_pbus_mem_fo:1; - uint32_t clk_agc_mem_fo:1; - uint32_t clk_dc_mem_fo:1; - uint32_t reserved_10:22; + uint32_t clk_wifipwr_fo: 1; + uint32_t clk_coex_fo: 1; + uint32_t clk_i2c_mst_fo: 1; + uint32_t clk_lp_timer_fo: 1; + uint32_t clk_bcmem_fo: 1; + uint32_t clk_i2c_mst_mem_fo: 1; + uint32_t clk_chan_freq_mem_fo: 1; + uint32_t clk_pbus_mem_fo: 1; + uint32_t clk_agc_mem_fo: 1; + uint32_t clk_dc_mem_fo: 1; + uint32_t reserved_10: 22; }; uint32_t val; } modem_lpcon_clk_conf_force_on_reg_t; typedef union { struct { - uint32_t reserved_0:16; - uint32_t clk_wifipwr_st_map:4; - uint32_t clk_coex_st_map:4; - uint32_t clk_i2c_mst_st_map:4; - uint32_t clk_lp_apb_st_map:4; + uint32_t reserved_0: 16; + uint32_t clk_wifipwr_st_map: 4; + uint32_t clk_coex_st_map: 4; + uint32_t clk_i2c_mst_st_map: 4; + uint32_t clk_lp_apb_st_map: 4; }; uint32_t val; } modem_lpcon_clk_conf_power_st_reg_t; typedef union { struct { - uint32_t rst_wifipwr:1; - uint32_t rst_coex:1; - uint32_t rst_i2c_mst:1; - uint32_t rst_lp_timer:1; - uint32_t reserved_4:28; + uint32_t rst_wifipwr: 1; + uint32_t rst_coex: 1; + uint32_t rst_i2c_mst: 1; + uint32_t rst_lp_timer: 1; + uint32_t reserved_4: 28; }; uint32_t val; } modem_lpcon_rst_conf_reg_t; typedef union { struct { - uint32_t dc_mem_force_pu:1; - uint32_t dc_mem_force_pd:1; - uint32_t agc_mem_force_pu:1; - uint32_t agc_mem_force_pd:1; - uint32_t pbus_mem_force_pu:1; - uint32_t pbus_mem_force_pd:1; - uint32_t bc_mem_force_pu:1; - uint32_t bc_mem_force_pd:1; - uint32_t i2c_mst_mem_force_pu:1; - uint32_t i2c_mst_mem_force_pd:1; - uint32_t chan_freq_mem_force_pu:1; - uint32_t chan_freq_mem_force_pd:1; - uint32_t modem_pwr_mem_wp:3; - uint32_t modem_pwr_mem_wa:3; - uint32_t modem_pwr_mem_ra:2; - uint32_t reserved_20:12; + uint32_t dc_mem_force_pu: 1; + uint32_t dc_mem_force_pd: 1; + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t bc_mem_force_pu: 1; + uint32_t bc_mem_force_pd: 1; + uint32_t i2c_mst_mem_force_pu: 1; + uint32_t i2c_mst_mem_force_pd: 1; + uint32_t chan_freq_mem_force_pu: 1; + uint32_t chan_freq_mem_force_pd: 1; + uint32_t modem_pwr_mem_wp: 3; + uint32_t modem_pwr_mem_wa: 3; + uint32_t modem_pwr_mem_ra: 2; + uint32_t reserved_20: 12; }; uint32_t val; } modem_lpcon_mem_conf_reg_t; typedef union { struct { - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } modem_lpcon_date_reg_t; - typedef struct { volatile modem_lpcon_test_conf_reg_t test_conf; volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf; diff --git a/components/soc/esp32c6/include/modem/modem_syscon_struct.h b/components/soc/esp32c6/include/modem/modem_syscon_struct.h index bb95c39ed9..4aedfac18f 100644 --- a/components/soc/esp32c6/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32c6/include/modem/modem_syscon_struct.h @@ -12,175 +12,174 @@ extern "C" { typedef union { struct { - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } modem_syscon_test_conf_reg_t; typedef union { struct { - uint32_t reserved_0:21; - uint32_t clk_data_dump_mux:1; - uint32_t clk_etm_en:1; - uint32_t clk_zb_apb_en:1; - uint32_t clk_zb_mac_en:1; - uint32_t clk_modem_sec_ecb_en:1; - uint32_t clk_modem_sec_ccm_en:1; - uint32_t clk_modem_sec_bah_en:1; - uint32_t clk_modem_sec_apb_en:1; - uint32_t clk_modem_sec_en:1; - uint32_t clk_ble_timer_en:1; - uint32_t clk_data_dump_en:1; + uint32_t reserved_0: 21; + uint32_t clk_data_dump_mux: 1; + uint32_t clk_etm_en: 1; + uint32_t clk_zb_apb_en: 1; + uint32_t clk_zb_mac_en: 1; + uint32_t clk_modem_sec_ecb_en: 1; + uint32_t clk_modem_sec_ccm_en: 1; + uint32_t clk_modem_sec_bah_en: 1; + uint32_t clk_modem_sec_apb_en: 1; + uint32_t clk_modem_sec_en: 1; + uint32_t clk_ble_timer_en: 1; + uint32_t clk_data_dump_en: 1; }; uint32_t val; } modem_syscon_clk_conf_reg_t; typedef union { struct { - uint32_t reserved_0:22; - uint32_t clk_etm_fo:1; - uint32_t clk_zb_apb_fo:1; - uint32_t clk_zb_mac_fo:1; - uint32_t clk_modem_sec_ecb_fo:1; - uint32_t clk_modem_sec_ccm_fo:1; - uint32_t clk_modem_sec_bah_fo:1; - uint32_t clk_modem_sec_apb_fo:1; - uint32_t clk_modem_sec_fo:1; - uint32_t clk_ble_timer_fo:1; - uint32_t clk_data_dump_fo:1; + uint32_t reserved_0: 22; + uint32_t clk_etm_fo: 1; + uint32_t clk_zb_apb_fo: 1; + uint32_t clk_zb_mac_fo: 1; + uint32_t clk_modem_sec_ecb_fo: 1; + uint32_t clk_modem_sec_ccm_fo: 1; + uint32_t clk_modem_sec_bah_fo: 1; + uint32_t clk_modem_sec_apb_fo: 1; + uint32_t clk_modem_sec_fo: 1; + uint32_t clk_ble_timer_fo: 1; + uint32_t clk_data_dump_fo: 1; }; uint32_t val; } modem_syscon_clk_conf_force_on_reg_t; typedef union { struct { - uint32_t reserved_0:8; - uint32_t clk_zb_st_map:4; - uint32_t clk_fe_st_map:4; - uint32_t clk_bt_st_map:4; - uint32_t clk_wifi_st_map:4; - uint32_t clk_modem_peri_st_map:4; - uint32_t clk_modem_apb_st_map:4; + uint32_t reserved_0: 8; + uint32_t clk_zb_st_map: 4; + uint32_t clk_fe_st_map: 4; + uint32_t clk_bt_st_map: 4; + uint32_t clk_wifi_st_map: 4; + uint32_t clk_modem_peri_st_map: 4; + uint32_t clk_modem_apb_st_map: 4; }; uint32_t val; } modem_syscon_clk_conf_power_st_reg_t; typedef union { struct { - uint32_t reserved_0:8; - uint32_t rst_wifibb:1; - uint32_t reserved_9:1; - uint32_t rst_wifimac:1; - uint32_t reserved_11:3; - uint32_t rst_fe:1; - uint32_t rst_btmac_apb:1; - uint32_t rst_btmac:1; - uint32_t rst_btbb_apb:1; - uint32_t rst_btbb:1; - uint32_t reserved_19:3; - uint32_t rst_etm:1; - uint32_t reserved_23:1; - uint32_t rst_zbmac:1; - uint32_t rst_modem_ecb:1; - uint32_t rst_modem_ccm:1; - uint32_t rst_modem_bah:1; - uint32_t reserved_28:1; - uint32_t rst_modem_sec:1; - uint32_t rst_ble_timer:1; - uint32_t rst_data_dump:1; + uint32_t reserved_0: 8; + uint32_t rst_wifibb: 1; + uint32_t reserved_9: 1; + uint32_t rst_wifimac: 1; + uint32_t reserved_11: 3; + uint32_t rst_fe: 1; + uint32_t rst_btmac_apb: 1; + uint32_t rst_btmac: 1; + uint32_t rst_btbb_apb: 1; + uint32_t rst_btbb: 1; + uint32_t reserved_19: 3; + uint32_t rst_etm: 1; + uint32_t reserved_23: 1; + uint32_t rst_zbmac: 1; + uint32_t rst_modem_ecb: 1; + uint32_t rst_modem_ccm: 1; + uint32_t rst_modem_bah: 1; + uint32_t reserved_28: 1; + uint32_t rst_modem_sec: 1; + uint32_t rst_ble_timer: 1; + uint32_t rst_data_dump: 1; }; uint32_t val; } modem_syscon_modem_rst_conf_reg_t; typedef union { struct { - uint32_t clk_wifibb_22m_en:1; - uint32_t clk_wifibb_40m_en:1; - uint32_t clk_wifibb_44m_en:1; - uint32_t clk_wifibb_80m_en:1; - uint32_t clk_wifibb_40x_en:1; - uint32_t clk_wifibb_80x_en:1; - uint32_t clk_wifibb_40x1_en:1; - uint32_t clk_wifibb_80x1_en:1; - uint32_t clk_wifibb_160x1_en:1; - uint32_t clk_wifimac_en:1; - uint32_t clk_wifi_apb_en:1; - uint32_t clk_fe_20m_en:1; - uint32_t clk_fe_40m_en:1; - uint32_t clk_fe_80m_en:1; - uint32_t clk_fe_160m_en:1; - uint32_t clk_fe_cal_160m_en:1; - uint32_t clk_fe_apb_en:1; - uint32_t clk_bt_apb_en:1; - uint32_t clk_bt_en:1; - uint32_t clk_wifibb_480m_en:1; - uint32_t clk_fe_480m_en:1; - uint32_t clk_fe_anamode_40m_en:1; - uint32_t clk_fe_anamode_80m_en:1; - uint32_t clk_fe_anamode_160m_en:1; - uint32_t reserved_24:8; + uint32_t clk_wifibb_22m_en: 1; + uint32_t clk_wifibb_40m_en: 1; + uint32_t clk_wifibb_44m_en: 1; + uint32_t clk_wifibb_80m_en: 1; + uint32_t clk_wifibb_40x_en: 1; + uint32_t clk_wifibb_80x_en: 1; + uint32_t clk_wifibb_40x1_en: 1; + uint32_t clk_wifibb_80x1_en: 1; + uint32_t clk_wifibb_160x1_en: 1; + uint32_t clk_wifimac_en: 1; + uint32_t clk_wifi_apb_en: 1; + uint32_t clk_fe_20m_en: 1; + uint32_t clk_fe_40m_en: 1; + uint32_t clk_fe_80m_en: 1; + uint32_t clk_fe_160m_en: 1; + uint32_t clk_fe_cal_160m_en: 1; + uint32_t clk_fe_apb_en: 1; + uint32_t clk_bt_apb_en: 1; + uint32_t clk_bt_en: 1; + uint32_t clk_wifibb_480m_en: 1; + uint32_t clk_fe_480m_en: 1; + uint32_t clk_fe_anamode_40m_en: 1; + uint32_t clk_fe_anamode_80m_en: 1; + uint32_t clk_fe_anamode_160m_en: 1; + uint32_t reserved_24: 8; }; uint32_t val; } modem_syscon_clk_conf1_reg_t; typedef union { struct { - uint32_t clk_wifibb_22m_fo:1; - uint32_t clk_wifibb_40m_fo:1; - uint32_t clk_wifibb_44m_fo:1; - uint32_t clk_wifibb_80m_fo:1; - uint32_t clk_wifibb_40x_fo:1; - uint32_t clk_wifibb_80x_fo:1; - uint32_t clk_wifibb_40x1_fo:1; - uint32_t clk_wifibb_80x1_fo:1; - uint32_t clk_wifibb_160x1_fo:1; - uint32_t clk_wifimac_fo:1; - uint32_t clk_wifi_apb_fo:1; - uint32_t clk_fe_20m_fo:1; - uint32_t clk_fe_40m_fo:1; - uint32_t clk_fe_80m_fo:1; - uint32_t clk_fe_160m_fo:1; - uint32_t clk_fe_cal_160m_fo:1; - uint32_t clk_fe_apb_fo:1; - uint32_t clk_bt_apb_fo:1; - uint32_t clk_bt_fo:1; - uint32_t clk_wifibb_480m_fo:1; - uint32_t clk_fe_480m_fo:1; - uint32_t clk_fe_anamode_40m_fo:1; - uint32_t clk_fe_anamode_80m_fo:1; - uint32_t clk_fe_anamode_160m_fo:1; - uint32_t reserved_24:8; + uint32_t clk_wifibb_22m_fo: 1; + uint32_t clk_wifibb_40m_fo: 1; + uint32_t clk_wifibb_44m_fo: 1; + uint32_t clk_wifibb_80m_fo: 1; + uint32_t clk_wifibb_40x_fo: 1; + uint32_t clk_wifibb_80x_fo: 1; + uint32_t clk_wifibb_40x1_fo: 1; + uint32_t clk_wifibb_80x1_fo: 1; + uint32_t clk_wifibb_160x1_fo: 1; + uint32_t clk_wifimac_fo: 1; + uint32_t clk_wifi_apb_fo: 1; + uint32_t clk_fe_20m_fo: 1; + uint32_t clk_fe_40m_fo: 1; + uint32_t clk_fe_80m_fo: 1; + uint32_t clk_fe_160m_fo: 1; + uint32_t clk_fe_cal_160m_fo: 1; + uint32_t clk_fe_apb_fo: 1; + uint32_t clk_bt_apb_fo: 1; + uint32_t clk_bt_fo: 1; + uint32_t clk_wifibb_480m_fo: 1; + uint32_t clk_fe_480m_fo: 1; + uint32_t clk_fe_anamode_40m_fo: 1; + uint32_t clk_fe_anamode_80m_fo: 1; + uint32_t clk_fe_anamode_160m_fo: 1; + uint32_t reserved_24: 8; }; uint32_t val; } modem_syscon_clk_conf1_force_on_reg_t; typedef union { struct { - uint32_t wifi_bb_cfg:32; + uint32_t wifi_bb_cfg: 32; }; uint32_t val; } modem_syscon_wifi_bb_cfg_reg_t; typedef union { struct { - uint32_t modem_mem_wp:3; - uint32_t modem_mem_wa:3; - uint32_t modem_mem_ra:2; - uint32_t reserved_8:24; + uint32_t modem_mem_wp: 3; + uint32_t modem_mem_wa: 3; + uint32_t modem_mem_ra: 2; + uint32_t reserved_8: 24; }; uint32_t val; } modem_syscon_mem_conf_reg_t; typedef union { struct { - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } modem_syscon_date_reg_t; - typedef struct { volatile modem_syscon_test_conf_reg_t test_conf; volatile modem_syscon_clk_conf_reg_t clk_conf; diff --git a/components/soc/esp32c6/include/soc/boot_mode.h b/components/soc/esp32c6/include/soc/boot_mode.h index 3921a29c56..9baf2fbd83 100644 --- a/components/soc/esp32c6/include/soc/boot_mode.h +++ b/components/soc/esp32c6/include/soc/boot_mode.h @@ -39,8 +39,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32c6/include/soc/clkout_channel.h b/components/soc/esp32c6/include/soc/clkout_channel.h index 719893aee4..7b185e0c2c 100644 --- a/components/soc/esp32c6/include/soc/clkout_channel.h +++ b/components/soc/esp32c6/include/soc/clkout_channel.h @@ -26,7 +26,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32c6/include/soc/ext_mem_defs.h b/components/soc/esp32c6/include/soc/ext_mem_defs.h index 90c47de89d..91e58aa92c 100644 --- a/components/soc/esp32c6/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c6/include/soc/ext_mem_defs.h @@ -19,7 +19,6 @@ extern "C" { #define SOC_MMU_PAGE_SIZE 0x10000 #endif - #define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) @@ -127,7 +126,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32c6/include/soc/gpio_pins.h b/components/soc/esp32c6/include/soc/gpio_pins.h index 78af5a05dc..71184c2051 100644 --- a/components/soc/esp32c6/include/soc/gpio_pins.h +++ b/components/soc/esp32c6/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/regi2c_defs.h b/components/soc/esp32c6/include/soc/regi2c_defs.h index 38db4f1595..d6e4837c87 100644 --- a/components/soc/esp32c6/include/soc/regi2c_defs.h +++ b/components/soc/esp32c6/include/soc/regi2c_defs.h @@ -14,7 +14,6 @@ #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24)) - #define ANA_CONFIG_REG 0x600AF81C #define ANA_CONFIG_S (8) #define ANA_CONFIG_M (0x3FF) @@ -22,7 +21,6 @@ #define ANA_I2C_SAR_FORCE_PD BIT(18) #define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - #define ANA_CONFIG2_REG 0x600AF820 #define ANA_CONFIG2_M BIT(18) diff --git a/components/soc/esp32c6/include/soc/regi2c_dig_reg.h b/components/soc/esp32c6/include/soc/regi2c_dig_reg.h index b71845476e..e3c9a53bb4 100644 --- a/components/soc/esp32c6/include/soc/regi2c_dig_reg.h +++ b/components/soc/esp32c6/include/soc/regi2c_dig_reg.h @@ -59,6 +59,6 @@ #define I2C_DIG_REG_XPD_DIG_REG_MSB 3 #define I2C_DIG_REG_XPD_DIG_REG_LSB 3 -#define I2C_DIG_REG_SCK_DCAP 14 -#define I2C_DIG_REG_SCK_DCAP_MSB 7 -#define I2C_DIG_REG_SCK_DCAP_LSB 0 +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c6/include/soc/reset_reasons.h b/components/soc/esp32c6/include/soc/reset_reasons.h index b6b0e33ae3..f934df203c 100644 --- a/components/soc/esp32c6/include/soc/reset_reasons.h +++ b/components/soc/esp32c6/include/soc/reset_reasons.h @@ -22,7 +22,6 @@ extern "C" { #endif - /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter @@ -49,7 +48,6 @@ typedef enum { RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index cccfc360ba..de1278b668 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -555,7 +555,6 @@ /* macro redefine for pass esp_wifi headers md5sum check */ #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE - #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/include/soc/regi2c_dig_reg.h b/components/soc/esp32c61/include/soc/regi2c_dig_reg.h index 9e2bd628ca..3a3f7edb0a 100644 --- a/components/soc/esp32c61/include/soc/regi2c_dig_reg.h +++ b/components/soc/esp32c61/include/soc/regi2c_dig_reg.h @@ -59,6 +59,6 @@ #define I2C_DIG_REG_XPD_DIG_REG_MSB 3 #define I2C_DIG_REG_XPD_DIG_REG_LSB 3 -#define I2C_DIG_REG_SCK_DCAP 14 -#define I2C_DIG_REG_SCK_DCAP_MSB 7 -#define I2C_DIG_REG_SCK_DCAP_LSB 0 +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c61/include/soc/regi2c_saradc.h b/components/soc/esp32c61/include/soc/regi2c_saradc.h index 0a80bbbc53..a49ca32d8f 100644 --- a/components/soc/esp32c61/include/soc/regi2c_saradc.h +++ b/components/soc/esp32c61/include/soc/regi2c_saradc.h @@ -18,8 +18,6 @@ #define I2C_SAR_ADC 0X69 #define I2C_SAR_ADC_HOSTID 0 - - #define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 #define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 #define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 @@ -80,7 +78,6 @@ #define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 #define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 - #define POWER_GLITCH_DREF_VDET_PERIF 11 #define POWER_GLITCH_DREF_VDET_PERIF_MSB 2 #define POWER_GLITCH_DREF_VDET_PERIF_LSB 0 diff --git a/components/soc/esp32c61/include/soc/reset_reasons.h b/components/soc/esp32c61/include/soc/reset_reasons.h index e2a7c55024..aa4c02a307 100644 --- a/components/soc/esp32c61/include/soc/reset_reasons.h +++ b/components/soc/esp32c61/include/soc/reset_reasons.h @@ -22,7 +22,6 @@ extern "C" { #endif - /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter @@ -50,7 +49,6 @@ typedef enum { RESET_REASON_CPU_LOCKUP = 0x1A, // CPU lockup resets } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index eeff6bf032..f477774007 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -198,13 +198,13 @@ #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ - #define SOC_RTCIO_PIN_COUNT 7 - #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, +#define SOC_RTCIO_PIN_COUNT 7 +#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) * when the pins are switched to RTC function. */ - #define SOC_RTCIO_HOLD_SUPPORTED 1 - #define SOC_RTCIO_WAKE_SUPPORTED 1 +#define SOC_RTCIO_HOLD_SUPPORTED 1 +#define SOC_RTCIO_WAKE_SUPPORTED 1 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ diff --git a/components/soc/esp32c61/ledc_periph.c b/components/soc/esp32c61/ledc_periph.c index 3fed785c27..7273244c17 100644 --- a/components/soc/esp32c61/ledc_periph.c +++ b/components/soc/esp32c61/ledc_periph.c @@ -44,38 +44,42 @@ static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0}; static const regdma_entries_config_t ledc_common_regdma_entries[] = { // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), - LEDC_INT_ENA_REG, 0, - (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), - .owner = LEDC_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), - LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, - LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, - ledc_common_regs_map[0], ledc_common_regs_map[1], - ledc_common_regs_map[2], ledc_common_regs_map[3]), - .owner = LEDC_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, }; #define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ - LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ - LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ } #define LEDC_CHANNEL_RETENTION_REGS_CNT 2 static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; #define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ @@ -85,14 +89,14 @@ static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ 1, 0, 0), \ .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ - LEDC_DUTY_START_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ - LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ - LEDC_PARA_UP_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \ LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \ 1, 0, 0), \ @@ -119,48 +123,48 @@ static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANN const ledc_reg_retention_info_t ledc_reg_retention_info = { .common = { - .regdma_entry_array = ledc_common_regdma_entries, - .array_size = ARRAY_SIZE(ledc_common_regdma_entries), - }, - .timer[0] = { - .regdma_entry_array = ledc_timer0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), - }, - .timer[1] = { - .regdma_entry_array = ledc_timer1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), - }, - .timer[2] = { - .regdma_entry_array = ledc_timer2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), - }, - .timer[3] = { - .regdma_entry_array = ledc_timer3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), - }, - .channel[0] = { - .regdma_entry_array = ledc_channel0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), - }, - .channel[1] = { - .regdma_entry_array = ledc_channel1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), - }, - .channel[2] = { - .regdma_entry_array = ledc_channel2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), - }, - .channel[3] = { - .regdma_entry_array = ledc_channel3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), - }, - .channel[4] = { - .regdma_entry_array = ledc_channel4_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), - }, - .channel[5] = { - .regdma_entry_array = ledc_channel5_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), - }, - .module_id = SLEEP_RETENTION_MODULE_LEDC, + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, }; diff --git a/components/soc/esp32c61/system_retention_periph.c b/components/soc/esp32c61/system_retention_periph.c index b9ae7fb1a7..f695bec2ba 100644 --- a/components/soc/esp32c61/system_retention_periph.c +++ b/components/soc/esp32c61/system_retention_periph.c @@ -84,36 +84,36 @@ const regdma_entries_config_t flash_spimem_regs_retention[] = { [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLOCK_GATE_REG(0), N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Note: spimem register should set update reg to make the configuration take effect */ - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CALI_UPDATE, SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) } + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CALI_UPDATE, SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) } }; _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions"); /* Systimer Registers Context */ #define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) const regdma_entries_config_t systimer_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ - [1] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */ - [9] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [10] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [11] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [12] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [13] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [14] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [15] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [16] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [16] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */ [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* Systimer intr enable */ diff --git a/components/soc/esp32c61/temperature_sensor_periph.c b/components/soc/esp32c61/temperature_sensor_periph.c index ee85209076..dc94673872 100644 --- a/components/soc/esp32c61/temperature_sensor_periph.c +++ b/components/soc/esp32c61/temperature_sensor_periph.c @@ -29,8 +29,10 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S #define TEMPERATURE_SENSOR_RETENTION_MAP_BASE SARADC_INT_ENA_REG static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; static const regdma_entries_config_t temperature_sensor_regs_entries[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { diff --git a/components/soc/esp32c61/timer_periph.c b/components/soc/esp32c61/timer_periph.c index 07b8e599c5..30cabb8420 100644 --- a/components/soc/esp32c61/timer_periph.c +++ b/components/soc/esp32c61/timer_periph.c @@ -39,36 +39,36 @@ const regdma_entries_config_t tg0_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; @@ -77,36 +77,36 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; diff --git a/components/soc/esp32c61/uart_periph.c b/components/soc/esp32c61/uart_periph.c index a4e8c50841..475d06d902 100644 --- a/components/soc/esp32c61/uart_periph.c +++ b/components/soc/esp32c61/uart_periph.c @@ -11,7 +11,8 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { // HP UART0 + { + // HP UART0 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, @@ -44,7 +45,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART0_INTR_SOURCE, }, - { // HP UART1 + { + // HP UART1 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U1TXD_GPIO_NUM, @@ -76,7 +78,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { }, .irq = ETS_UART1_INTR_SOURCE, }, - { // HP UART2 + { + // HP UART2 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U2TXD_GPIO_NUM, diff --git a/components/soc/esp32c61/wdt_periph.c b/components/soc/esp32c61/wdt_periph.c index f615401cfa..8d082d6e92 100644 --- a/components/soc/esp32c61/wdt_periph.c +++ b/components/soc/esp32c61/wdt_periph.c @@ -9,21 +9,21 @@ #define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { diff --git a/components/soc/esp32h2/etm_periph.c b/components/soc/esp32h2/etm_periph.c index 7b268c443a..0084a78164 100644 --- a/components/soc/esp32h2/etm_periph.c +++ b/components/soc/esp32h2/etm_periph.c @@ -18,19 +18,19 @@ static const regdma_entries_config_t etm_regdma_entries[] = { // restore stage: store the enabled channels [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), - SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), - SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, // backup stage: save configuration registers // restore stage: restore the configuration registers [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), - SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), .owner = ENTRY(0) | ENTRY(2), }, }; diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c index 5e55ca93e8..9e6cc78c86 100644 --- a/components/soc/esp32h2/gdma_periph.c +++ b/components/soc/esp32h2/gdma_periph.c @@ -39,12 +39,14 @@ const gdma_signal_conn_t gdma_periph_signals = { #define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ - G0P0_RETENTION_REGS_CNT, 0, 0, \ - g0p0_regs_map[0], g0p0_regs_map[1], \ - g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* GDMA Channel (Group0, Pair1) Registers Context @@ -57,12 +59,14 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { #define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ - G0P1_RETENTION_REGS_CNT, 0, 0, \ - g0p1_regs_map[0], g0p1_regs_map[1], \ - g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* GDMA Channel (Group0, Pair2) Registers Context @@ -78,36 +82,40 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - } + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } } }; diff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c index 5afb3995eb..ffda3bf9f8 100644 --- a/components/soc/esp32h2/i2c_periph.c +++ b/components/soc/esp32h2/i2c_periph.c @@ -42,32 +42,52 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c0_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; #define I2C1_RETENTION_REGS_CNT 18 #define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c1_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { diff --git a/components/soc/esp32h2/ieee802154_periph.c b/components/soc/esp32h2/ieee802154_periph.c index 58cce6d7bb..104bc61c12 100644 --- a/components/soc/esp32h2/ieee802154_periph.c +++ b/components/soc/esp32h2/ieee802154_periph.c @@ -7,6 +7,6 @@ #include "soc/ieee802154_periph.h" const ieee802154_conn_t ieee802154_periph = { - .module = PERIPH_IEEE802154_MODULE, - .irq_id = ETS_ZB_MAC_INTR_SOURCE, + .module = PERIPH_IEEE802154_MODULE, + .irq_id = ETS_ZB_MAC_INTR_SOURCE, }; diff --git a/components/soc/esp32h2/include/modem/modem_lpcon_struct.h b/components/soc/esp32h2/include/modem/modem_lpcon_struct.h index 6e57c6f5f4..c6dbbea741 100644 --- a/components/soc/esp32h2/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32h2/include/modem/modem_lpcon_struct.h @@ -12,96 +12,95 @@ extern "C" { typedef union { struct { - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } modem_lpcon_test_conf_reg_t; typedef union { struct { - uint32_t clk_coex_lp_sel_osc_slow:1; - uint32_t clk_coex_lp_sel_osc_fast:1; - uint32_t clk_coex_lp_sel_xtal:1; - uint32_t clk_coex_lp_sel_xtal32k:1; - uint32_t clk_coex_lp_div_num:12; - uint32_t reserved_16:16; + uint32_t clk_coex_lp_sel_osc_slow: 1; + uint32_t clk_coex_lp_sel_osc_fast: 1; + uint32_t clk_coex_lp_sel_xtal: 1; + uint32_t clk_coex_lp_sel_xtal32k: 1; + uint32_t clk_coex_lp_div_num: 12; + uint32_t reserved_16: 16; }; uint32_t val; } modem_lpcon_coex_lp_clk_conf_reg_t; typedef union { struct { - uint32_t reserved_0:1; - uint32_t clk_coex_en:1; - uint32_t clk_i2c_mst_en:1; - uint32_t reserved_3:2; - uint32_t clk_fe_mem_en:1; - uint32_t reserved_6:26; + uint32_t reserved_0: 1; + uint32_t clk_coex_en: 1; + uint32_t clk_i2c_mst_en: 1; + uint32_t reserved_3: 2; + uint32_t clk_fe_mem_en: 1; + uint32_t reserved_6: 26; }; uint32_t val; } modem_lpcon_clk_conf_reg_t; typedef union { struct { - uint32_t reserved_0:1; - uint32_t clk_coex_fo:1; - uint32_t clk_i2c_mst_fo:1; - uint32_t reserved_3:2; - uint32_t clk_fe_mem_fo:1; - uint32_t reserved_6:26; + uint32_t reserved_0: 1; + uint32_t clk_coex_fo: 1; + uint32_t clk_i2c_mst_fo: 1; + uint32_t reserved_3: 2; + uint32_t clk_fe_mem_fo: 1; + uint32_t reserved_6: 26; }; uint32_t val; } modem_lpcon_clk_conf_force_on_reg_t; typedef union { struct { - uint32_t pwr_tick_target:6; - uint32_t reserved_6:26; + uint32_t pwr_tick_target: 6; + uint32_t reserved_6: 26; }; uint32_t val; } modem_lpcon_tick_conf_reg_t; typedef union { struct { - uint32_t reserved_0:1; - uint32_t rst_coex:1; - uint32_t rst_i2c_mst:1; - uint32_t reserved_3:29; + uint32_t reserved_0: 1; + uint32_t rst_coex: 1; + uint32_t rst_i2c_mst: 1; + uint32_t reserved_3: 29; }; uint32_t val; } modem_lpcon_rst_conf_reg_t; typedef union { struct { - uint32_t reserved_0:2; - uint32_t agc_mem_force_pu:1; - uint32_t agc_mem_force_pd:1; - uint32_t pbus_mem_force_pu:1; - uint32_t pbus_mem_force_pd:1; - uint32_t reserved_6:2; - uint32_t i2c_mst_mem_force_pu:1; - uint32_t i2c_mst_mem_force_pd:1; - uint32_t chan_freq_mem_force_pu:1; - uint32_t chan_freq_mem_force_pd:1; - uint32_t modem_pwr_mem_wp:3; - uint32_t modem_pwr_mem_wa:3; - uint32_t modem_pwr_mem_ra:2; - uint32_t modem_pwr_mem_rm:4; - uint32_t reserved_24:8; + uint32_t reserved_0: 2; + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t reserved_6: 2; + uint32_t i2c_mst_mem_force_pu: 1; + uint32_t i2c_mst_mem_force_pd: 1; + uint32_t chan_freq_mem_force_pu: 1; + uint32_t chan_freq_mem_force_pd: 1; + uint32_t modem_pwr_mem_wp: 3; + uint32_t modem_pwr_mem_wa: 3; + uint32_t modem_pwr_mem_ra: 2; + uint32_t modem_pwr_mem_rm: 4; + uint32_t reserved_24: 8; }; uint32_t val; } modem_lpcon_mem_conf_reg_t; typedef union { struct { - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } modem_lpcon_date_reg_t; - typedef struct { volatile modem_lpcon_test_conf_reg_t test_conf; volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf; diff --git a/components/soc/esp32h2/include/modem/modem_syscon_struct.h b/components/soc/esp32h2/include/modem/modem_syscon_struct.h index 99bd8a5ce6..d8f271bf1b 100644 --- a/components/soc/esp32h2/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32h2/include/modem/modem_syscon_struct.h @@ -12,112 +12,111 @@ extern "C" { typedef union { struct { - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } modem_syscon_test_conf_reg_t; typedef union { struct { - uint32_t reserved_0:21; - uint32_t clk_etm_en:1; - uint32_t clk_zb_apb_en:1; - uint32_t clk_zb_mac_en:1; - uint32_t clk_modem_sec_ecb_en:1; - uint32_t clk_modem_sec_ccm_en:1; - uint32_t clk_modem_sec_bah_en:1; - uint32_t clk_modem_sec_apb_en:1; - uint32_t clk_modem_sec_en:1; - uint32_t clk_ble_timer_apb_en:1; - uint32_t clk_ble_timer_en:1; - uint32_t clk_data_dump_en:1; + uint32_t reserved_0: 21; + uint32_t clk_etm_en: 1; + uint32_t clk_zb_apb_en: 1; + uint32_t clk_zb_mac_en: 1; + uint32_t clk_modem_sec_ecb_en: 1; + uint32_t clk_modem_sec_ccm_en: 1; + uint32_t clk_modem_sec_bah_en: 1; + uint32_t clk_modem_sec_apb_en: 1; + uint32_t clk_modem_sec_en: 1; + uint32_t clk_ble_timer_apb_en: 1; + uint32_t clk_ble_timer_en: 1; + uint32_t clk_data_dump_en: 1; }; uint32_t val; } modem_syscon_clk_conf_reg_t; typedef union { struct { - uint32_t reserved_0:22; - uint32_t clk_etm_fo:1; - uint32_t reserved_23:1; - uint32_t clk_zb_fo:1; - uint32_t reserved_25:4; - uint32_t clk_modem_sec_fo:1; - uint32_t clk_ble_timer_fo:1; - uint32_t clk_data_dump_fo:1; + uint32_t reserved_0: 22; + uint32_t clk_etm_fo: 1; + uint32_t reserved_23: 1; + uint32_t clk_zb_fo: 1; + uint32_t reserved_25: 4; + uint32_t clk_modem_sec_fo: 1; + uint32_t clk_ble_timer_fo: 1; + uint32_t clk_data_dump_fo: 1; }; uint32_t val; } modem_syscon_clk_conf_force_on_reg_t; typedef union { struct { - uint32_t reserved_0:14; - uint32_t rst_fe:1; - uint32_t rst_btmac_apb:1; - uint32_t rst_btmac:1; - uint32_t rst_btbb_apb:1; - uint32_t rst_btbb:1; - uint32_t reserved_19:3; - uint32_t rst_etm:1; - uint32_t reserved_23:1; - uint32_t rst_zbmac:1; - uint32_t rst_modem_ecb:1; - uint32_t rst_modem_ccm:1; - uint32_t rst_modem_bah:1; - uint32_t reserved_28:1; - uint32_t rst_modem_sec:1; - uint32_t rst_ble_timer:1; - uint32_t rst_data_dump:1; + uint32_t reserved_0: 14; + uint32_t rst_fe: 1; + uint32_t rst_btmac_apb: 1; + uint32_t rst_btmac: 1; + uint32_t rst_btbb_apb: 1; + uint32_t rst_btbb: 1; + uint32_t reserved_19: 3; + uint32_t rst_etm: 1; + uint32_t reserved_23: 1; + uint32_t rst_zbmac: 1; + uint32_t rst_modem_ecb: 1; + uint32_t rst_modem_ccm: 1; + uint32_t rst_modem_bah: 1; + uint32_t reserved_28: 1; + uint32_t rst_modem_sec: 1; + uint32_t rst_ble_timer: 1; + uint32_t rst_data_dump: 1; }; uint32_t val; } modem_syscon_modem_rst_conf_reg_t; typedef union { struct { - uint32_t reserved_0:12; - uint32_t clk_fe_16m_en:1; - uint32_t clk_fe_32m_en:1; - uint32_t clk_fe_sdm_en:1; - uint32_t clk_fe_adc_en:1; - uint32_t clk_fe_apb_en:1; - uint32_t clk_bt_apb_en:1; - uint32_t clk_bt_en:1; - uint32_t reserved_19:13; + uint32_t reserved_0: 12; + uint32_t clk_fe_16m_en: 1; + uint32_t clk_fe_32m_en: 1; + uint32_t clk_fe_sdm_en: 1; + uint32_t clk_fe_adc_en: 1; + uint32_t clk_fe_apb_en: 1; + uint32_t clk_bt_apb_en: 1; + uint32_t clk_bt_en: 1; + uint32_t reserved_19: 13; }; uint32_t val; } modem_syscon_clk_conf1_reg_t; typedef union { struct { - uint32_t reserved_0:16; - uint32_t clk_fe_fo:1; - uint32_t reserved_17:1; - uint32_t clk_bt_fo:1; - uint32_t reserved_19:13; + uint32_t reserved_0: 16; + uint32_t clk_fe_fo: 1; + uint32_t reserved_17: 1; + uint32_t clk_bt_fo: 1; + uint32_t reserved_19: 13; }; uint32_t val; } modem_syscon_clk_conf1_force_on_reg_t; typedef union { struct { - uint32_t modem_mem_wp:3; - uint32_t modem_mem_wa:3; - uint32_t modem_mem_ra:2; - uint32_t reserved_8:24; + uint32_t modem_mem_wp: 3; + uint32_t modem_mem_wa: 3; + uint32_t modem_mem_ra: 2; + uint32_t reserved_8: 24; }; uint32_t val; } modem_syscon_mem_conf_reg_t; typedef union { struct { - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } modem_syscon_date_reg_t; - typedef struct { volatile modem_syscon_test_conf_reg_t test_conf; volatile modem_syscon_clk_conf_reg_t clk_conf; diff --git a/components/soc/esp32h2/include/soc/boot_mode.h b/components/soc/esp32h2/include/soc/boot_mode.h index f782959272..3ce2db3b4d 100644 --- a/components/soc/esp32h2/include/soc/boot_mode.h +++ b/components/soc/esp32h2/include/soc/boot_mode.h @@ -39,8 +39,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32h2/include/soc/clkout_channel.h b/components/soc/esp32h2/include/soc/clkout_channel.h index 719893aee4..7b185e0c2c 100644 --- a/components/soc/esp32h2/include/soc/clkout_channel.h +++ b/components/soc/esp32h2/include/soc/clkout_channel.h @@ -26,7 +26,6 @@ typedef enum clock_out_channel { (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) - #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index fb6e1f7278..2b4dd3cd12 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -19,7 +19,6 @@ extern "C" { #define SOC_MMU_PAGE_SIZE 0x10000 #endif - #define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) @@ -127,7 +126,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32h2/include/soc/gpio_pins.h b/components/soc/esp32h2/include/soc/gpio_pins.h index 853aba1421..d99bc9be90 100644 --- a/components/soc/esp32h2/include/soc/gpio_pins.h +++ b/components/soc/esp32h2/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h index 8c8477c51c..01faf4437c 100644 --- a/components/soc/esp32h2/include/soc/periph_defs.h +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -44,7 +44,7 @@ typedef enum { PERIPH_SARADC_MODULE, PERIPH_TEMPSENSOR_MODULE, PERIPH_ASSIST_DEBUG_MODULE, -/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ PERIPH_BT_MODULE, PERIPH_IEEE802154_MODULE, PERIPH_COEX_MODULE, @@ -53,7 +53,7 @@ typedef enum { PERIPH_MODEM_ETM_MODULE, PERIPH_MODEM_ADC_COMMON_FE_MODULE, PERIPH_MODULE_MAX -/* !!! Don't append soc modules here !!! */ + /* !!! Don't append soc modules here !!! */ } periph_module_t; #define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE diff --git a/components/soc/esp32h2/include/soc/regi2c_defs.h b/components/soc/esp32h2/include/soc/regi2c_defs.h index 799f0e0b80..b4d6651968 100644 --- a/components/soc/esp32h2/include/soc/regi2c_defs.h +++ b/components/soc/esp32h2/include/soc/regi2c_defs.h @@ -21,7 +21,6 @@ #define ANA_I2C_SAR_FORCE_PD BIT(18) #define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - // I2C_MST_ANA_CONF2_REG #define ANA_CONFIG2_M BIT(18) diff --git a/components/soc/esp32h2/include/soc/reset_reasons.h b/components/soc/esp32h2/include/soc/reset_reasons.h index 24ce66c9a4..dbb2735ae8 100644 --- a/components/soc/esp32h2/include/soc/reset_reasons.h +++ b/components/soc/esp32h2/include/soc/reset_reasons.h @@ -22,7 +22,6 @@ extern "C" { #endif - /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter @@ -49,7 +48,6 @@ typedef enum { RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/ledc_periph.c b/components/soc/esp32h2/ledc_periph.c index e20f002e5a..2f40e4dc76 100644 --- a/components/soc/esp32h2/ledc_periph.c +++ b/components/soc/esp32h2/ledc_periph.c @@ -11,9 +11,9 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { + { .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + } }; /** @@ -31,7 +31,7 @@ const ledc_signal_conn_t ledc_periph_signal[1] = { * LEDC_CONF_REG, * * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore. - * We won't start a fade automatically after wake-up. + * We won't start a fade automatically after wake-up. * Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep. * * Note 2: For timer/channel registers to get synced, update bits need to be set @@ -42,56 +42,60 @@ const ledc_signal_conn_t ledc_periph_signal[1] = { #define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8) static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0}; static const regdma_entries_config_t ledc_common_regdma_entries[] = { - // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). + // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), - LEDC_INT_ENA_REG, 0, - (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), - .owner = LEDC_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), - LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, - LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, - ledc_common_regs_map[0], ledc_common_regs_map[1], - ledc_common_regs_map[2], ledc_common_regs_map[3]), - .owner = LEDC_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, }; #define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ - LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ - LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ } #define LEDC_CHANNEL_RETENTION_REGS_CNT 2 static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; #define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \ .owner = LEDC_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ 1, 0, 0), \ .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ - LEDC_DUTY_START_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ - LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ - LEDC_PARA_UP_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ } static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0); @@ -107,49 +111,49 @@ static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANN static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5); const ledc_reg_retention_info_t ledc_reg_retention_info = { - .common = { - .regdma_entry_array = ledc_common_regdma_entries, - .array_size = ARRAY_SIZE(ledc_common_regdma_entries), - }, - .timer[0] = { - .regdma_entry_array = ledc_timer0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), - }, - .timer[1] = { - .regdma_entry_array = ledc_timer1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), - }, - .timer[2] = { - .regdma_entry_array = ledc_timer2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), - }, - .timer[3] = { - .regdma_entry_array = ledc_timer3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), - }, - .channel[0] = { - .regdma_entry_array = ledc_channel0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), - }, - .channel[1] = { - .regdma_entry_array = ledc_channel1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), - }, - .channel[2] = { - .regdma_entry_array = ledc_channel2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), - }, - .channel[3] = { - .regdma_entry_array = ledc_channel3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), - }, - .channel[4] = { - .regdma_entry_array = ledc_channel4_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), - }, - .channel[5] = { - .regdma_entry_array = ledc_channel5_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), - }, - .module_id = SLEEP_RETENTION_MODULE_LEDC, + .common = { + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, }; diff --git a/components/soc/esp32h2/mcpwm_periph.c b/components/soc/esp32h2/mcpwm_periph.c index 9879e557f4..0f8161570b 100644 --- a/components/soc/esp32h2/mcpwm_periph.c +++ b/components/soc/esp32h2/mcpwm_periph.c @@ -103,19 +103,25 @@ static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0}; static const regdma_entries_config_t mcpwm_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, // restore stage: trigger a forced update of all active registers - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) }, + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, }; const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = { diff --git a/components/soc/esp32h2/parlio_periph.c b/components/soc/esp32h2/parlio_periph.c index bd17bfceb1..3d323084ba 100644 --- a/components/soc/esp32h2/parlio_periph.c +++ b/components/soc/esp32h2/parlio_periph.c @@ -62,12 +62,14 @@ static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; static const regdma_entries_config_t parlio_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = { [0] = { diff --git a/components/soc/esp32h2/pcnt_periph.c b/components/soc/esp32h2/pcnt_periph.c index 14c52fc0d6..5fee4252ff 100644 --- a/components/soc/esp32h2/pcnt_periph.c +++ b/components/soc/esp32h2/pcnt_periph.c @@ -77,12 +77,14 @@ static const uint32_t pcnt_regs_map[4] = {0x1040fff, 0x0, 0x0, 0x0}; static const regdma_entries_config_t pcnt_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ - PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ - PCNT_RETENTION_REGS_CNT, 0, 0, \ - pcnt_regs_map[0], pcnt_regs_map[1], \ - pcnt_regs_map[2], pcnt_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ + PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ + PCNT_RETENTION_REGS_CNT, 0, 0, \ + pcnt_regs_map[0], pcnt_regs_map[1], \ + pcnt_regs_map[2], pcnt_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = { diff --git a/components/soc/esp32h2/rmt_periph.c b/components/soc/esp32h2/rmt_periph.c index c08da463f2..d7148c1ddc 100644 --- a/components/soc/esp32h2/rmt_periph.c +++ b/components/soc/esp32h2/rmt_periph.c @@ -50,10 +50,10 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { // restore stage: restore the configuration registers [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_RMT_LINK(0x00), - RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, - RMT_RETENTION_REGS_CNT, 0, 0, - rmt_regs_map[0], rmt_regs_map[1], - rmt_regs_map[2], rmt_regs_map[3]), + RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, + RMT_RETENTION_REGS_CNT, 0, 0, + rmt_regs_map[0], rmt_regs_map[1], + rmt_regs_map[2], rmt_regs_map[3]), .owner = ENTRY(0) | ENTRY(2), }, }; diff --git a/components/soc/esp32h2/system_retention_periph.c b/components/soc/esp32h2/system_retention_periph.c index 436840e682..3ef3b168bc 100644 --- a/components/soc/esp32h2/system_retention_periph.c +++ b/components/soc/esp32h2/system_retention_periph.c @@ -84,29 +84,29 @@ _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_ /* Systimer Registers Context */ #define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) const regdma_entries_config_t systimer_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ - [1] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */ + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */ - [9] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [10] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [11] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [12] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [13] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [14] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [15] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [16] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [16] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */ [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* Systimer intr enable */ diff --git a/components/soc/esp32h2/temperature_sensor_periph.c b/components/soc/esp32h2/temperature_sensor_periph.c index 348567d3f2..a4cc33aa6f 100644 --- a/components/soc/esp32h2/temperature_sensor_periph.c +++ b/components/soc/esp32h2/temperature_sensor_periph.c @@ -9,7 +9,6 @@ #include "soc/temperature_sensor_periph.h" #include "soc/apb_saradc_reg.h" - const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { /*Offset reg_val min max error */ {-2, 5, 50, 125, 3}, @@ -30,8 +29,10 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S #define TEMPERATURE_SENSOR_RETENTION_MAP_BASE APB_SARADC_INT_ENA_REG static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; static const regdma_entries_config_t temperature_sensor_regs_entries[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ }; const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { diff --git a/components/soc/esp32h2/timer_periph.c b/components/soc/esp32h2/timer_periph.c index bb8ce80fed..c3a4d8d109 100644 --- a/components/soc/esp32h2/timer_periph.c +++ b/components/soc/esp32h2/timer_periph.c @@ -39,36 +39,36 @@ const regdma_entries_config_t tg0_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; @@ -77,36 +77,36 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: wait for the capture done [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, }; diff --git a/components/soc/esp32h2/uart_periph.c b/components/soc/esp32h2/uart_periph.c index 857eeb65e5..2a65a8650e 100644 --- a/components/soc/esp32h2/uart_periph.c +++ b/components/soc/esp32h2/uart_periph.c @@ -11,7 +11,7 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { + { .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, diff --git a/components/soc/esp32h2/wdt_periph.c b/components/soc/esp32h2/wdt_periph.c index f615401cfa..8d082d6e92 100644 --- a/components/soc/esp32h2/wdt_periph.c +++ b/components/soc/esp32h2/wdt_periph.c @@ -9,21 +9,21 @@ #define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { diff --git a/components/soc/esp32p4/etm_periph.c b/components/soc/esp32p4/etm_periph.c index f7b28b02bf..5e24359e30 100644 --- a/components/soc/esp32p4/etm_periph.c +++ b/components/soc/esp32p4/etm_periph.c @@ -18,19 +18,19 @@ static const regdma_entries_config_t etm_regdma_entries[] = { // restore stage: store the enabled channels [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), - SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), .owner = ENTRY(0), }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), - SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), .owner = ENTRY(0), }, // backup stage: save configuration registers // restore stage: restore the configuration registers [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), - SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), .owner = ENTRY(0), }, }; diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c index 61d00e6f86..eb8970b30c 100644 --- a/components/soc/esp32p4/gdma_periph.c +++ b/components/soc/esp32p4/gdma_periph.c @@ -66,18 +66,22 @@ const gdma_signal_conn_t gdma_periph_signals = { static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \ - ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \ - ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \ + ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \ + ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AHB_DMA Channel (Group0, Pair1) Registers Context @@ -99,18 +103,22 @@ static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604}; static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \ - ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \ - ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \ + ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \ + ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AHB_DMA Channel (Group0, Pair2) Registers Context @@ -132,18 +140,22 @@ static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c}; static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \ - ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \ - ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \ + ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \ + ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AXI_DMA Channel (Group1, Pair0) Registers Context @@ -164,18 +176,22 @@ static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ - axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ - axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY}, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ + axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ + axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AXI_DMA Channel (Group1, Pair1) Registers Context @@ -196,18 +212,22 @@ static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ - axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ - axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ + axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ + axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; /* AXI_DMA Channel (Group1, Pair2) Registers Context @@ -228,53 +248,57 @@ static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ - axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ - axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ + axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ + axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { [0] = { - ahb_dma_g0p0_regs_retention, - ARRAY_SIZE(ahb_dma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH0, - }, + ahb_dma_g0p0_regs_retention, + ARRAY_SIZE(ahb_dma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH0, + }, [1] = { - ahb_dma_g0p1_regs_retention, - ARRAY_SIZE(ahb_dma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH1, - }, + ahb_dma_g0p1_regs_retention, + ARRAY_SIZE(ahb_dma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH1, + }, [2] = { - ahb_dma_g0p2_regs_retention, - ARRAY_SIZE(ahb_dma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH2, - }, + ahb_dma_g0p2_regs_retention, + ARRAY_SIZE(ahb_dma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH2, + }, }, [1] = { [0] = { - axi_dma_g1p0_regs_retention, - ARRAY_SIZE(axi_dma_g1p0_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH0, - }, + axi_dma_g1p0_regs_retention, + ARRAY_SIZE(axi_dma_g1p0_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH0, + }, [1] = { - axi_dma_g1p1_regs_retention, - ARRAY_SIZE(axi_dma_g1p1_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH1, - }, + axi_dma_g1p1_regs_retention, + ARRAY_SIZE(axi_dma_g1p1_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH1, + }, [2] = { - axi_dma_g1p2_regs_retention, - ARRAY_SIZE(axi_dma_g1p2_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH2, - }, + axi_dma_g1p2_regs_retention, + ARRAY_SIZE(axi_dma_g1p2_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH2, + }, } }; diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c index 699e5890de..b895c9f362 100644 --- a/components/soc/esp32p4/i2c_periph.c +++ b/components/soc/esp32p4/i2c_periph.c @@ -48,32 +48,52 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c0_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ - .owner = ENTRY(0) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) + }, \ }; #define I2C1_RETENTION_REGS_CNT 18 #define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const regdma_entries_config_t i2c1_regs_retention[] = { - [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ - .owner = ENTRY(0) }, \ - [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ - .owner = ENTRY(0) }, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ + .owner = ENTRY(0) + }, \ + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) + }, \ + [4] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) + }, \ }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { diff --git a/components/soc/esp32p4/i2s_periph.c b/components/soc/esp32p4/i2s_periph.c index 76d39c7435..4391c6e05e 100644 --- a/components/soc/esp32p4/i2s_periph.c +++ b/components/soc/esp32p4/i2s_periph.c @@ -85,7 +85,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { }; const i2s_signal_conn_t lp_i2s_periph_signal[SOC_LP_I2S_NUM] = { - [0] = { + [0] = { .mck_out_sig = -1, .mck_in_sig = -1, diff --git a/components/soc/esp32p4/include/soc/boot_mode.h b/components/soc/esp32p4/include/soc/boot_mode.h index d532dc1bc9..644f860dee 100644 --- a/components/soc/esp32p4/include/soc/boot_mode.h +++ b/components/soc/esp32p4/include/soc/boot_mode.h @@ -39,8 +39,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h index 2099d5a582..0e732e554d 100644 --- a/components/soc/esp32p4/include/soc/clkout_channel.h +++ b/components/soc/esp32p4/include/soc/clkout_channel.h @@ -21,7 +21,6 @@ typedef enum clock_out_channel { CLKOUT_CHANNEL_MAX, } clock_out_channel_t; - #define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel) ((channel == CLKOUT_CHANNEL_1) ? DBG_CH0_CLK_IDX : \ (channel == CLKOUT_CHANNEL_2) ? DBG_CH1_CLK_IDX : SIG_GPIO_OUT_IDX) diff --git a/components/soc/esp32p4/include/soc/ext_mem_defs.h b/components/soc/esp32p4/include/soc/ext_mem_defs.h index c305e72453..64ca55c935 100644 --- a/components/soc/esp32p4/include/soc/ext_mem_defs.h +++ b/components/soc/esp32p4/include/soc/ext_mem_defs.h @@ -54,7 +54,6 @@ extern "C" { #define SOC_ADDRESS_IN_DRAM_FLASH(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM_FLASH, vaddr) #define SOC_ADDRESS_IN_DRAM_PSRAM(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM_PSRAM, vaddr) - #define SOC_MMU_FLASH_VALID BIT(12) #define SOC_MMU_FLASH_INVALID 0 #define SOC_MMU_PSRAM_VALID BIT(11) @@ -126,7 +125,6 @@ extern "C" { #define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) #endif - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h index baaf358edf..0bfcb59834 100644 --- a/components/soc/esp32p4/include/soc/gpio_pins.h +++ b/components/soc/esp32p4/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/interrupt_reg.h b/components/soc/esp32p4/include/soc/interrupt_reg.h index 2f2aabe539..1eb016ab24 100644 --- a/components/soc/esp32p4/include/soc/interrupt_reg.h +++ b/components/soc/esp32p4/include/soc/interrupt_reg.h @@ -25,7 +25,6 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_THRESH_REG (rv_utils_get_core_id() == 0 ? INTERRUPT_CURRENT_CORE_INT_THRESH_REG : INTERRUPT_OTHER_CORE_INT_THRESH_REG) #define INTERRUPT_CORE1_CPU_INT_THRESH_REG (rv_utils_get_core_id() == 1 ? INTERRUPT_CURRENT_CORE_INT_THRESH_REG : INTERRUPT_OTHER_CORE_INT_THRESH_REG) - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/lp_gpio_pins.h b/components/soc/esp32p4/include/soc/lp_gpio_pins.h index 3c9d05556d..281506fcbf 100644 --- a/components/soc/esp32p4/include/soc/lp_gpio_pins.h +++ b/components/soc/esp32p4/include/soc/lp_gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h index 583beb13c4..061bcaf3b4 100644 --- a/components/soc/esp32p4/include/soc/regi2c_defs.h +++ b/components/soc/esp32p4/include/soc/regi2c_defs.h @@ -13,7 +13,6 @@ #define ANA_I2C_SAR_FORCE_PD BIT(18) - #define ANA_CONFIG2_REG 0x50124020 #define ANA_CONFIG2_M BIT(18) diff --git a/components/soc/esp32p4/include/soc/regi2c_dig_reg.h b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h index aca6b3e778..390f7baf11 100644 --- a/components/soc/esp32p4/include/soc/regi2c_dig_reg.h +++ b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h @@ -68,5 +68,5 @@ #define I2C_DIG_REG_XPD_DIG_REG_LSB 3 #define I2C_DIG_REG_SCK_DCAP 14 -#define I2C_DIG_REG_SCK_DCAP_MSB 7 -#define I2C_DIG_REG_SCK_DCAP_LSB 0 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32p4/include/soc/regi2c_saradc.h b/components/soc/esp32p4/include/soc/regi2c_saradc.h index 88fa3640bc..725992d692 100644 --- a/components/soc/esp32p4/include/soc/regi2c_saradc.h +++ b/components/soc/esp32p4/include/soc/regi2c_saradc.h @@ -54,7 +54,6 @@ #define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 #define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - #define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5 #define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2 #define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0 diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h index 4e6952d555..1472f32231 100644 --- a/components/soc/esp32p4/include/soc/reset_reasons.h +++ b/components/soc/esp32p4/include/soc/reset_reasons.h @@ -48,7 +48,6 @@ typedef enum { RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this) } soc_reset_reason_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 6779cc7390..53b28f587f 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -100,7 +100,6 @@ #define SOC_DEEP_SLEEP_SUPPORTED 1 #define SOC_PM_SUPPORTED 1 - /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c index 11a073f72b..dfce02a609 100644 --- a/components/soc/esp32p4/ledc_periph.c +++ b/components/soc/esp32p4/ledc_periph.c @@ -44,38 +44,42 @@ static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0}; static const regdma_entries_config_t ledc_common_regdma_entries[] = { // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), - LEDC_INT_ENA_REG, 0, - (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1), - .owner = LEDC_RETENTION_ENTRY }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), - LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, - LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, - ledc_common_regs_map[0], ledc_common_regs_map[1], - ledc_common_regs_map[2], ledc_common_regs_map[3]), - .owner = LEDC_RETENTION_ENTRY }, + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, }; #define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ - LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ - 1, 0, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ - LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ } #define LEDC_CHANNEL_RETENTION_REGS_CNT 2 static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; #define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ @@ -85,14 +89,14 @@ static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0}; LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ 1, 0, 0), \ .owner = LEDC_RETENTION_ENTRY }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ - LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ - LEDC_DUTY_START_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ - LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ - LEDC_PARA_UP_CH##chan##_M, 1, 0), \ - .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \ LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \ 1, 0, 0), \ @@ -120,57 +124,57 @@ static const regdma_entries_config_t ledc_channel6_regdma_entries[] = LEDC_CHANN static const regdma_entries_config_t ledc_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(7); const ledc_reg_retention_info_t ledc_reg_retention_info = { - .common = { - .regdma_entry_array = ledc_common_regdma_entries, - .array_size = ARRAY_SIZE(ledc_common_regdma_entries), - }, - .timer[0] = { - .regdma_entry_array = ledc_timer0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), - }, - .timer[1] = { - .regdma_entry_array = ledc_timer1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), - }, - .timer[2] = { - .regdma_entry_array = ledc_timer2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), - }, - .timer[3] = { - .regdma_entry_array = ledc_timer3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), - }, - .channel[0] = { - .regdma_entry_array = ledc_channel0_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), - }, - .channel[1] = { - .regdma_entry_array = ledc_channel1_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), - }, - .channel[2] = { - .regdma_entry_array = ledc_channel2_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), - }, - .channel[3] = { - .regdma_entry_array = ledc_channel3_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), - }, - .channel[4] = { - .regdma_entry_array = ledc_channel4_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), - }, - .channel[5] = { - .regdma_entry_array = ledc_channel5_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), - }, + .common = { + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, .channel[6] = { - .regdma_entry_array = ledc_channel6_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel6_regdma_entries), - }, + .regdma_entry_array = ledc_channel6_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel6_regdma_entries), + }, .channel[7] = { - .regdma_entry_array = ledc_channel7_regdma_entries, - .array_size = ARRAY_SIZE(ledc_channel7_regdma_entries), - }, - .module_id = SLEEP_RETENTION_MODULE_LEDC, + .regdma_entry_array = ledc_channel7_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel7_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, }; diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c index 62ab0ed295..b5f823986a 100644 --- a/components/soc/esp32p4/parlio_periph.c +++ b/components/soc/esp32p4/parlio_periph.c @@ -78,12 +78,14 @@ static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; static const regdma_entries_config_t parlio_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, - PARLIO_RETENTION_REGS_CNT, 0, 0, - parlio_regs_map[0], parlio_regs_map[1], - parlio_regs_map[2], parlio_regs_map[3]), - .owner = ENTRY(0)}, + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, + PARLIO_RETENTION_REGS_CNT, 0, 0, + parlio_regs_map[0], parlio_regs_map[1], + parlio_regs_map[2], parlio_regs_map[3]), + .owner = ENTRY(0) + }, }; const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = { [0] = { diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c index 4b1cbcac5c..d10e7974fa 100644 --- a/components/soc/esp32p4/pcnt_periph.c +++ b/components/soc/esp32p4/pcnt_periph.c @@ -83,12 +83,14 @@ static const uint32_t pcnt_regs_map[4] = {0x1f040fff, 0x0, 0x0, 0x0}; static const regdma_entries_config_t pcnt_regs_retention[] = { // backup stage: save configuration registers // restore stage: restore the configuration registers - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ - PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ - PCNT_RETENTION_REGS_CNT, 0, 0, \ - pcnt_regs_map[0], pcnt_regs_map[1], \ - pcnt_regs_map[2], pcnt_regs_map[3]), \ - .owner = ENTRY(0)}, \ + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \ + PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \ + PCNT_RETENTION_REGS_CNT, 0, 0, \ + pcnt_regs_map[0], pcnt_regs_map[1], \ + pcnt_regs_map[2], pcnt_regs_map[3]), \ + .owner = ENTRY(0) + }, \ }; const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = { diff --git a/components/soc/esp32p4/include/soc/emac_ptp_struct.h b/components/soc/esp32p4/register/soc/emac_ptp_struct.h similarity index 94% rename from components/soc/esp32p4/include/soc/emac_ptp_struct.h rename to components/soc/esp32p4/register/soc/emac_ptp_struct.h index ef01da6f8a..d5af2bf890 100644 --- a/components/soc/esp32p4/include/soc/emac_ptp_struct.h +++ b/components/soc/esp32p4/register/soc/emac_ptp_struct.h @@ -12,7 +12,7 @@ extern "C" { #endif typedef struct emac_ptp_dev_s { - volatile union{ + volatile union { struct { uint32_t en_timestamp : 1; /* Timestamp Enable */ uint32_t ts_fine_coarse_update : 1; /* Timestamp Fine or Coarse Update */ @@ -41,66 +41,66 @@ typedef struct emac_ptp_dev_s { }; uint32_t val; } timestamp_ctrl; - volatile union{ + volatile union { struct { uint32_t sub_second_incre_value : 8; /* Sub-second Increment Value */ uint32_t reserved : 24; /* Reserved */ }; uint32_t val; } sub_sec_incre; - volatile union{ + volatile union { struct { uint32_t ts_second : 32; /* Timestamp Second */ }; uint32_t val; } sys_seconds; - volatile union{ + volatile union { struct { uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */ uint32_t reserved: 1; /* Reserved */ }; uint32_t val; } sys_nanosec; - volatile union{ + volatile union { struct { uint32_t ts_second : 32; /* Timestamp Second */ }; uint32_t val; } sys_seconds_update; - volatile union{ + volatile union { struct { uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */ uint32_t add_sub : 1; /* Add or Subtract Time */ }; uint32_t val; } sys_nanosec_update; - volatile union{ + volatile union { struct { uint32_t ts_addend_val: 32; /* Timestamp Addend Register */ }; uint32_t val; } timestamp_addend; - volatile union{ + volatile union { struct { uint32_t tgt_time_second_val : 32; /* Target Time Seconds Register */ }; uint32_t val; } tgt_seconds; - volatile union{ + volatile union { struct { uint32_t tgt_ts_low_reg : 31; /* Target Timestamp Low Register */ uint32_t tgt_time_reg_busy : 1; /* Target Time Register Busy */ }; uint32_t val; } tgt_nanosec; - volatile union{ + volatile union { struct { uint32_t ts_higher_word : 16; /* Timestamp Higher Word Register */ uint32_t reserved : 16; /* Reserved */ }; uint32_t val; } sys_seconds_high; - volatile union{ + volatile union { struct { uint32_t ts_secons_ovf : 1; /* Timestamp Seconds Overflow */ uint32_t ts_tgt_time_reach : 1; /* Timestamp Target Time Reached */ @@ -121,7 +121,7 @@ typedef struct emac_ptp_dev_s { }; uint32_t val; } status; - volatile union{ + volatile union { struct { uint32_t pps_cmd0 : 4; /* Flexible PPS0 Output Control */ uint32_t en_pps0 : 1; /* Flexible PPS Output Mode Enable */ @@ -142,20 +142,20 @@ typedef struct emac_ptp_dev_s { }; uint32_t val; } pps_ctrl; - volatile union{ + volatile union { struct { uint32_t aux_ts_low : 31; /* Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */ uint32_t reserved : 1; /* Reserved */ }; uint32_t val; } aux_nanosec; - volatile union{ + volatile union { struct { uint32_t aux_tx_high : 32; /* Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */ }; uint32_t val; } aux_seconds; - volatile union{ + volatile union { struct { uint32_t av_ethertype_val : 16; /* AV EtherType Value */ uint32_t ac_queue_pri : 3; /* AV Priority for Queuing */ @@ -169,91 +169,91 @@ typedef struct emac_ptp_dev_s { uint32_t val; } av_mac_ctrl; uint32_t reserved1[9]; /* Reserved */ - volatile union{ + volatile union { struct { uint32_t pps0_interval : 32; /* PPS0 Output Signal Interval */ }; uint32_t val; } pps0_interval; - volatile union{ + volatile union { struct { uint32_t pps0_width : 32; /* PPS0 Output Signal Width */ }; uint32_t val; } pps0_width; uint32_t reserved2[6]; /* Reserved */ - volatile union{ + volatile union { struct { uint32_t pps1_tgt_seconds : 32; /* PPS1 Target Time Seconds Register */ }; uint32_t val; } pps1_tgt_seconds; - volatile union{ + volatile union { struct { uint32_t pps1_tgt_nanosec : 31; /* Target Time Low for PPS1 Register */ uint32_t pps1_tgt_time_busy : 1; /* PPS1 Target Time Register Busy */ }; uint32_t val; } pps1_tgt_nanosec; - volatile union{ + volatile union { struct { uint32_t pps1_interval : 32; /* PPS1 Output Signal Interval */ }; uint32_t val; } pps1_interval; - volatile union{ + volatile union { struct { uint32_t pps1_width : 32; /* PPS1 Output Signal Width */ }; uint32_t val; } pps1_width; uint32_t reserved3[4]; /* Reserved */ - volatile union{ + volatile union { struct { uint32_t pps2_tgt_seconds : 32; /* PPS2 Target Time Seconds Register */ }; uint32_t val; } pps2_tgt_seconds; - volatile union{ + volatile union { struct { uint32_t pps2_tgt_nanosec : 31; /* Target Time Low for PPS2 Register */ uint32_t pps2_tgt_time_busy : 1; /* PPS2 Target Time Register Busy */ }; uint32_t val; } pps2_tgt_nanosec; - volatile union{ + volatile union { struct { uint32_t pps2_interval : 32; /* PPS2 Output Signal Interval */ }; uint32_t val; } pps2_interval; - volatile union{ + volatile union { struct { uint32_t pps2_width : 32; /* PPS2 Output Signal Width */ }; uint32_t val; } pps2_width; uint32_t reserved4[4]; /* Reserved */ - volatile union{ + volatile union { struct { uint32_t pps3_tgt_seconds : 32; /* PPS3 Target Time Seconds Register */ }; uint32_t val; } pps3_tgt_seconds; - volatile union{ + volatile union { struct { uint32_t pps3_tgt_nanosec : 31; /* Target Time Low for PPS3 Register */ uint32_t pps3_tgt_time_busy : 1; /* PPS3 Target Time Register Busy */ }; uint32_t val; } pps3_tgt_nanosec; - volatile union{ + volatile union { struct { uint32_t pps3_interval : 32; /* PPS3 Output Signal Interval */ }; uint32_t val; } pps3_interval; - volatile union{ + volatile union { struct { uint32_t pps3_width : 32; /* PPS3 Output Signal Width */ }; diff --git a/components/soc/esp32p4/include/soc/usb_utmi_struct.h b/components/soc/esp32p4/register/soc/usb_utmi_struct.h similarity index 83% rename from components/soc/esp32p4/include/soc/usb_utmi_struct.h rename to components/soc/esp32p4/register/soc/usb_utmi_struct.h index 29c8ff745d..0fa6df41de 100644 --- a/components/soc/esp32p4/include/soc/usb_utmi_struct.h +++ b/components/soc/esp32p4/register/soc/usb_utmi_struct.h @@ -25,26 +25,26 @@ typedef union { * 2'b1 Lowest power consumption mode * 2'b2 Normal power consumption mode */ - uint32_t clk_gate_rx:2; + uint32_t clk_gate_rx: 2; /** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0; * Clock Gating Control Signal for Rx. * 1'b0 Low power consumption mode * 1'b1 Normal power consumption mode */ - uint32_t clk_gate_tx:1; + uint32_t clk_gate_tx: 1; /** adj_res_fs : Reserved; bitpos: [3]; default: 0; * Fine tune the 45ohm termination resistor (FS) * Reserved */ - uint32_t adj_res_fs:2; + uint32_t adj_res_fs: 2; /** adj_res_hs : R/W; bitpos: [5]; default: 3'b100; * Fine tune the 45ohm termination resistor (HS) * 3'b000 40 Ohm * 3'b100 45 Ohm * 3'b110 50 Ohm */ - uint32_t adj_res_hs:3; - uint32_t reserved_8:24; + uint32_t adj_res_hs: 3; + uint32_t reserved_8: 24; }; uint32_t val; } usb_utmi_fc_00_reg_t; @@ -57,7 +57,7 @@ typedef union { * 4'b0010 124 mV * 4'b0011 152 mV */ - uint32_t adj_vref_sq:4; + uint32_t adj_vref_sq: 4; /** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111; * Super power saving with reduced output swing mode control bits (for HS mode only) * 4'b0001 100 mV output swing @@ -65,8 +65,8 @@ typedef union { * 4'b0111 300 mV output swing * 4'b1111 400 mV output swing */ - uint32_t adj_pw_hs:4; - uint32_t reserved_8:24; + uint32_t adj_pw_hs: 4; + uint32_t reserved_8: 24; }; uint32_t val; } usb_utmi_fc_01_reg_t; @@ -79,15 +79,15 @@ typedef union { * 4'b0111 100 uA * 4'b1111 78 uA */ - uint32_t adj_iref_res:4; + uint32_t adj_iref_res: 4; /** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100 * Output eye shape adjustment control bits * 3'b000 320 mV * 3'b100 400 mV * 3'b111 460 mV */ - uint32_t adj_vsw_hs:3; - uint32_t reserved_7:25; + uint32_t adj_vsw_hs: 3; + uint32_t reserved_7: 25; }; uint32_t val; } usb_utmi_fc_02_reg_t; @@ -97,12 +97,12 @@ typedef union { /** adj_pll : R/W; bitpos: [0]; default: 4'b0101 * PLL adjustment signal */ - uint32_t adj_pll:4; + uint32_t adj_pll: 4; /** adj_osc : R/W; bitpos: [4]; default: 3'b000 * TX Clock phase adjust signal */ - uint32_t adj_txclk_phase:3; - uint32_t reserved_7:25; + uint32_t adj_txclk_phase: 3; + uint32_t reserved_7: 25; }; uint32_t val; } usb_utmi_fc_03_reg_t; @@ -114,8 +114,8 @@ typedef union { * In our implementation output of this register is left floating and DTO is driven from Probe module. * Thus writing to this register has no effect and is renamed to 'reserved' */ - uint32_t reserved:8; - uint32_t reserved_8:24; + uint32_t reserved: 8; + uint32_t reserved_8: 24; }; uint32_t val; } usb_utmi_fc_04_reg_t; @@ -125,36 +125,36 @@ typedef union { /** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1 * RXGAP fix enable */ - uint32_t rxgap_fix_en:1; + uint32_t rxgap_fix_en: 1; /** counter_sel : R/W; bitpos: [1]; default: 1'b0 * SIE_input sample enable */ - uint32_t counter_sel:1; + uint32_t counter_sel: 1; /** clk_sel : R/W; bitpos: [2]; default: 1'b0 * CLK60_30 source select */ - uint32_t clk_sel:1; + uint32_t clk_sel: 1; /** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0 * PHY MODE select */ - uint32_t phy_mode_sel:1; + uint32_t phy_mode_sel: 1; /** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0 * UNI_BIDI signal */ - uint32_t uni_bidi_i:1; + uint32_t uni_bidi_i: 1; /** short_5v : R/W; bitpos: [5]; default: 1'b0 * SHORT_5V signal */ - uint32_t short_5v:1; + uint32_t short_5v: 1; /** short_5v_enable : R/W; bitpos: [6]; default: 1'b1 * SHORT_5V_ENABLE signal */ - uint32_t short_5v_enable:1; + uint32_t short_5v_enable: 1; /** usable_en : R/W; bitpos: [7]; default: 1'b1 * compare_begin delay time select */ - uint32_t usable_en:1; - uint32_t reserved_8:24; + uint32_t usable_en: 1; + uint32_t reserved_8: 24; }; uint32_t val; } usb_utmi_fc_05_reg_t; @@ -164,24 +164,24 @@ typedef union { /** ls_par_en : R/W; bitpos: [0]; default: 1'b0 * LS mode with parallel enable */ - uint32_t ls_par_en:1; + uint32_t ls_par_en: 1; /** det_fseop_en : R/W; bitpos: [1]; default: 1'b0 * FS EOP detect enable */ - uint32_t det_fseop_en:1; + uint32_t det_fseop_en: 1; /** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0 * Dis_preamble enable */ - uint32_t pre_hphy_lsie:1; + uint32_t pre_hphy_lsie: 1; /** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0 * LS mode keep alive enable */ - uint32_t ls_kpalv_en:1; + uint32_t ls_kpalv_en: 1; /** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100 * PHY High-SPeed bus turn-around time select */ - uint32_t hs_tx2rx_dly_cnt_sel:3; - uint32_t reserved_7:25; + uint32_t hs_tx2rx_dly_cnt_sel: 3; + uint32_t reserved_7: 25; }; uint32_t val; } usb_utmi_fc_06_reg_t; @@ -195,14 +195,14 @@ typedef union { * 10: 1.36ms * 11: 2.72ms */ - uint32_t cnt_num:2; + uint32_t cnt_num: 2; /** clk480_sel : R/W; bitpos: [2]; default: 1'b0 * CLK_480 output time select * 0: CLK_480 is valid after a delay time when PLL is locked * 1: CLK_480 is valid immediately after PLL is locked */ - uint32_t clk480_sel:1; - uint32_t reserved_3:29; + uint32_t clk480_sel: 1; + uint32_t reserved_3: 29; }; uint32_t val; } usb_utmi_fc_07_reg_t; diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c index e838ccb182..e59476ae2b 100644 --- a/components/soc/esp32p4/rmt_periph.c +++ b/components/soc/esp32p4/rmt_periph.c @@ -66,10 +66,10 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { // restore stage: restore the configuration registers [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_RMT_LINK(0x00), - RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, - RMT_RETENTION_REGS_CNT, 0, 0, - rmt_regs_map[0], rmt_regs_map[1], - rmt_regs_map[2], rmt_regs_map[3]), + RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE, + RMT_RETENTION_REGS_CNT, 0, 0, + rmt_regs_map[0], rmt_regs_map[1], + rmt_regs_map[2], rmt_regs_map[3]), .owner = ENTRY(0), }, }; diff --git a/components/soc/esp32p4/system_retention_periph.c b/components/soc/esp32p4/system_retention_periph.c index 18a2ea302f..abe5aa3e79 100644 --- a/components/soc/esp32p4/system_retention_periph.c +++ b/components/soc/esp32p4/system_retention_periph.c @@ -78,7 +78,7 @@ const regdma_entries_config_t flash_spimem_regs_retention[] = { [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG, SPI_MEM_C_FMEM__PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) }, [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) }, }; _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions"); @@ -117,23 +117,23 @@ _Static_assert(ARRAY_SIZE(psram_spimem_regs_retention) == SPIMEM_PSRAM_RETENTION /* Systimer Registers Context */ #define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) const regdma_entries_config_t systimer_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, /* Systimer */ - [1] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, /* Systimer */ + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) }, [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) }, [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) }, /* Systimer target value & period */ - [9] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) }, - [10] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) }, - [11] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) }, - [12] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, - [13] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, - [14] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, - [15] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, - [16] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) }, + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, + [16] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) }, [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) }, /* Systimer work enable */ [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) } /* Systimer intr enable */ }; diff --git a/components/soc/esp32p4/timer_periph.c b/components/soc/esp32p4/timer_periph.c index 6ce81ed966..f2af239c87 100644 --- a/components/soc/esp32p4/timer_periph.c +++ b/components/soc/esp32p4/timer_periph.c @@ -41,56 +41,56 @@ const regdma_entries_config_t tg0_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, // backup stage: wait for the capture done [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, [3] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), + TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) }, [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x05), - TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), + TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x06), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) }, [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x07), - TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), + TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), .owner = ENTRY(0) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [8] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x08), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) }, }; @@ -99,55 +99,55 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = { // backup stage: trigger a soft capture [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, // backup stage: wait for the capture done [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) }, [3] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), + TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), .owner = ENTRY(0) }, // backup stage: save the captured counter value // restore stage: store the captured counter value to the loader register [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) }, [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x05), - TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), + TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) }, // restore stage: trigger a soft reload, so the timer can continue from where it was backed up [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x06), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) }, [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x07), - TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), + TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), .owner = ENTRY(0) }, // backup stage: save other configuration and status registers // restore stage: restore the configuration and status registers [8] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x08), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) }, }; diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c index c28c0be814..51bc85bbe1 100644 --- a/components/soc/esp32p4/uart_periph.c +++ b/components/soc/esp32p4/uart_periph.c @@ -12,7 +12,8 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { // HP UART0 + { + // HP UART0 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U0TXD_GPIO_NUM, @@ -45,7 +46,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART0_INTR_SOURCE, }, - { // HP UART1 + { + // HP UART1 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U1TXD_GPIO_NUM, @@ -78,7 +80,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART1_INTR_SOURCE, }, - { // HP UART2 + { + // HP UART2 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U2TXD_GPIO_NUM, @@ -111,7 +114,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART2_INTR_SOURCE, }, - { // HP UART3 + { + // HP UART3 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U3TXD_GPIO_NUM, @@ -144,7 +148,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART3_INTR_SOURCE, }, - { // HP UART4 + { + // HP UART4 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = U4TXD_GPIO_NUM, @@ -176,7 +181,8 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { }, .irq = ETS_UART4_INTR_SOURCE, }, - { // LP UART0 + { + // LP UART0 .pins = { [SOC_UART_TX_PIN_IDX] = { .default_gpio = LP_U0TXD_GPIO_NUM, diff --git a/components/soc/esp32p4/wdt_periph.c b/components/soc/esp32p4/wdt_periph.c index 1660f25c4a..8d082d6e92 100644 --- a/components/soc/esp32p4/wdt_periph.c +++ b/components/soc/esp32p4/wdt_periph.c @@ -6,25 +6,24 @@ #include "soc/wdt_periph.h" - #define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { diff --git a/components/soc/esp32s2/adc_periph.c b/components/soc/esp32s2/adc_periph.c index 7c1314b6ff..4822580a78 100644 --- a/components/soc/esp32s2/adc_periph.c +++ b/components/soc/esp32s2/adc_periph.c @@ -1,25 +1,21 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/adc_periph.h" /* Store IO number corresponding to the ADC channel number. */ const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { /* ADC1 */ - {ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM, - ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, ADC1_CHANNEL_8_GPIO_NUM, ADC1_CHANNEL_9_GPIO_NUM}, + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM, + ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, ADC1_CHANNEL_8_GPIO_NUM, ADC1_CHANNEL_9_GPIO_NUM + }, /* ADC2 */ - {ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM, - ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM} + { + ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM, + ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM + } }; diff --git a/components/soc/esp32s2/include/soc/bb_reg.h b/components/soc/esp32s2/include/soc/bb_reg.h index 62828b89e5..51ae751d0f 100644 --- a/components/soc/esp32s2/include/soc/bb_reg.h +++ b/components/soc/esp32s2/include/soc/bb_reg.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_BB_REG_H_ #define _SOC_BB_REG_H_ @@ -37,5 +29,4 @@ #define BB_DC_EST_FORCE_PD_V 1 #define BB_DC_EST_FORCE_PD_S 0 - #endif /* _SOC_BB_REG_H_ */ diff --git a/components/soc/esp32s2/include/soc/boot_mode.h b/components/soc/esp32s2/include/soc/boot_mode.h index bba7f4c182..958e8f2037 100644 --- a/components/soc/esp32s2/include/soc/boot_mode.h +++ b/components/soc/esp32s2/include/soc/boot_mode.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_BOOT_MODE_H_ #define _SOC_BOOT_MODE_H_ @@ -47,8 +39,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32s2/include/soc/clk_tree_defs.h b/components/soc/esp32s2/include/soc/clk_tree_defs.h index 51331a5578..abdb2cc7ff 100644 --- a/components/soc/esp32s2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s2/include/soc/clk_tree_defs.h @@ -397,7 +397,6 @@ typedef enum { ADC_RTC_CLK_SRC_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the default clock choice */ } soc_periph_adc_rtc_clk_src_t; - //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index acb7870688..248528a586 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -13,32 +13,32 @@ extern "C" { #endif /*IRAM0 is connected with Cache IBUS0*/ -#define SOC_IRAM0_ADDRESS_LOW 0x40000000 -#define SOC_IRAM0_ADDRESS_HIGH 0x40400000 -#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x40080000 -#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x40400000 +#define SOC_IRAM0_ADDRESS_LOW 0x40000000 +#define SOC_IRAM0_ADDRESS_HIGH 0x40400000 +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x40080000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x40400000 /*IRAM1 is connected with Cache IBUS1*/ -#define SOC_IRAM1_ADDRESS_LOW 0x40400000 -#define SOC_IRAM1_ADDRESS_HIGH 0x40800000 +#define SOC_IRAM1_ADDRESS_LOW 0x40400000 +#define SOC_IRAM1_ADDRESS_HIGH 0x40800000 /*DROM0 is connected with Cache IBUS2*/ -#define SOC_DROM0_ADDRESS_LOW 0x3f000000 -#define SOC_DROM0_ADDRESS_HIGH 0x3f400000 +#define SOC_DROM0_ADDRESS_LOW 0x3f000000 +#define SOC_DROM0_ADDRESS_HIGH 0x3f400000 /*DRAM0 is connected with Cache DBUS0*/ -#define SOC_DRAM0_ADDRESS_LOW 0x3fc00000 -#define SOC_DRAM0_ADDRESS_HIGH 0x40000000 +#define SOC_DRAM0_ADDRESS_LOW 0x3fc00000 +#define SOC_DRAM0_ADDRESS_HIGH 0x40000000 #define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3fc00000 #define SOC_DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000 /*DRAM1 is connected with Cache DBUS1*/ -#define SOC_DRAM1_ADDRESS_LOW 0x3f800000 -#define SOC_DRAM1_ADDRESS_HIGH 0x3fc00000 +#define SOC_DRAM1_ADDRESS_LOW 0x3f800000 +#define SOC_DRAM1_ADDRESS_HIGH 0x3fc00000 /*DPORT is connected with Cache DBUS2*/ -#define SOC_DPORT_ADDRESS_LOW 0x3f400000 -#define SOC_DPORT_ADDRESS_HIGH 0x3f800000 +#define SOC_DPORT_ADDRESS_LOW 0x3f400000 +#define SOC_DPORT_ADDRESS_HIGH 0x3f800000 #define SOC_DPORT_CACHE_ADDRESS_LOW 0x3f500000 #define SOC_DPORT_CACHE_ADDRESS_HIGH 0x3f800000 @@ -140,7 +140,6 @@ extern "C" { #define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000 #define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000 - #define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 #define SOC_MMU_IBUS_VADDR_BASE 0x40000000 diff --git a/components/soc/esp32s2/include/soc/gpio_sig_map.h b/components/soc/esp32s2/include/soc/gpio_sig_map.h index 5b7e9e8cbb..bed622f9c8 100644 --- a/components/soc/esp32s2/include/soc/gpio_sig_map.h +++ b/components/soc/esp32s2/include/soc/gpio_sig_map.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_SIG_MAP_H_ #define _SOC_GPIO_SIG_MAP_H_ #define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX @@ -315,5 +307,5 @@ #define PRO_ALONEGPIO_OUT7_IDX 242 #define CLK_I2S_MUX_IDX 251 #define SIG_GPIO_OUT_IDX 256 -#define GPIO_MAP_DATE_IDX 0x1904100 +#define GPIO_MAP_DATE_IDX 0x1904100 #endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32s2/include/soc/hwcrypto_reg.h b/components/soc/esp32s2/include/soc/hwcrypto_reg.h index 942083731e..ff3c31e56b 100644 --- a/components/soc/esp32s2/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s2/include/soc/hwcrypto_reg.h @@ -100,7 +100,6 @@ #define AES_STATE_BUSY 1 #define AES_STATE_DONE 2 - /* Crypto DMA */ #define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) #define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) diff --git a/components/soc/esp32s2/include/soc/interrupts.h b/components/soc/esp32s2/include/soc/interrupts.h index b39d606445..d866480192 100644 --- a/components/soc/esp32s2/include/soc/interrupts.h +++ b/components/soc/esp32s2/include/soc/interrupts.h @@ -18,7 +18,7 @@ typedef enum { ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibration*/ ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ @@ -59,12 +59,12 @@ typedef enum { ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ ETS_LEDC_INTR_SOURCE = 45, /**< interrupt of LED PWM, level*/ ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of twai, level*/ ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pulse count, level*/ ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ @@ -84,7 +84,7 @@ typedef enum { ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalid Access, LEVEL*/ ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */ ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */ ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */ diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index eb4d0eef06..3db86f2de7 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -399,7 +399,6 @@ #define SOC_SHA_SUPPORT_SHA512_256 (1) #define SOC_SHA_SUPPORT_SHA512_T (1) - /*--------------------------- MPI CAPS ---------------------------------------*/ #define SOC_MPI_MEM_BLOCKS_NUM (4) #define SOC_MPI_OPERATIONS_NUM (3) @@ -407,7 +406,6 @@ /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (4096) - /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) #define SOC_AES_SUPPORT_GCM (1) diff --git a/components/soc/esp32s2/include/soc/uart_pins.h b/components/soc/esp32s2/include/soc/uart_pins.h index a6a7d18724..f31a54dde7 100644 --- a/components/soc/esp32s2/include/soc/uart_pins.h +++ b/components/soc/esp32s2/include/soc/uart_pins.h @@ -1,16 +1,8 @@ -// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32s2/include/soc/usb_dwc_struct.h b/components/soc/esp32s2/include/soc/usb_dwc_struct.h index 4d8f3e4a79..340ce02bc4 100644 --- a/components/soc/esp32s2/include/soc/usb_dwc_struct.h +++ b/components/soc/esp32s2/include/soc/usb_dwc_struct.h @@ -67,7 +67,7 @@ typedef union { } usb_dwc_gotgint_reg_t; typedef union { - struct { + struct { uint32_t glbllntrmsk: 1; uint32_t hbstlen: 4; uint32_t dmaen: 1; diff --git a/components/soc/esp32s2/include/soc/wdev_reg.h b/components/soc/esp32s2/include/soc/wdev_reg.h index a1400e415f..c8b79b104d 100644 --- a/components/soc/esp32s2/include/soc/wdev_reg.h +++ b/components/soc/esp32s2/include/soc/wdev_reg.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32s2/ledc_periph.c b/components/soc/esp32s2/ledc_periph.c index a7aed94896..d508be2a32 100644 --- a/components/soc/esp32s2/ledc_periph.c +++ b/components/soc/esp32s2/ledc_periph.c @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/ledc_periph.h" #include "soc/gpio_sig_map.h" @@ -19,7 +11,7 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { + { .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + } }; diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 9097e814ef..c2f300189e 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -3,26 +3,6 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED - bool - default n - -config SOC_MPU_MIN_REGION_SIZE - hex - default 0x20000000 - -config SOC_MPU_REGIONS_MAX_NUM - int - default 8 - -config SOC_MPU_REGION_RO_SUPPORTED - bool - default n - -config SOC_MPU_REGION_WO_SUPPORTED - bool - default n - config SOC_ADC_SUPPORTED bool default y @@ -683,6 +663,26 @@ config SOC_MMU_PERIPH_NUM int default 1 +config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED + bool + default n + +config SOC_MPU_MIN_REGION_SIZE + hex + default 0x20000000 + +config SOC_MPU_REGIONS_MAX_NUM + int + default 8 + +config SOC_MPU_REGION_RO_SUPPORTED + bool + default n + +config SOC_MPU_REGION_WO_SUPPORTED + bool + default n + config SOC_PCNT_GROUPS int default 1 diff --git a/components/soc/esp32s3/include/soc/boot_mode.h b/components/soc/esp32s3/include/soc/boot_mode.h index d66451f43b..62575616c0 100644 --- a/components/soc/esp32s3/include/soc/boot_mode.h +++ b/components/soc/esp32s3/include/soc/boot_mode.h @@ -1,16 +1,8 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -46,8 +38,6 @@ /*Diagnostic Mode+UART0 download Mode*/ #define IS_0111(v) (((v)&0x0f)==0x07) - - #define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index 9f9e36390b..bca5d544a0 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -109,7 +109,6 @@ extern "C" { _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); #endif - /** * ROM flash mmap driver needs below definitions */ diff --git a/components/soc/esp32s3/include/soc/gpio_pins.h b/components/soc/esp32s3/include/soc/gpio_pins.h index 9b96fa7bd3..1c07923ad8 100644 --- a/components/soc/esp32s3/include/soc/gpio_pins.h +++ b/components/soc/esp32s3/include/soc/gpio_pins.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/hwcrypto_reg.h b/components/soc/esp32s3/include/soc/hwcrypto_reg.h index 6aadd19a05..24730d0b8d 100644 --- a/components/soc/esp32s3/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s3/include/soc/hwcrypto_reg.h @@ -88,7 +88,6 @@ #define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) #define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) - /* HMAC Module */ #define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) #define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44) diff --git a/components/soc/esp32s3/include/soc/interrupt_reg.h b/components/soc/esp32s3/include/soc/interrupt_reg.h index df8e7fdb66..2036636bb1 100644 --- a/components/soc/esp32s3/include/soc/interrupt_reg.h +++ b/components/soc/esp32s3/include/soc/interrupt_reg.h @@ -15,11 +15,8 @@ extern "C" { #endif - #ifdef __cplusplus } #endif - - #endif /*_SOC_INTERRUPT_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/interrupt_struct.h b/components/soc/esp32s3/include/soc/interrupt_struct.h index 03bf5df953..8e75201434 100644 --- a/components/soc/esp32s3/include/soc/interrupt_struct.h +++ b/components/soc/esp32s3/include/soc/interrupt_struct.h @@ -1,20 +1,11 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_STRUCT_H_ #define _SOC_INTERRUPT_STRUCT_H_ - #include #ifdef __cplusplus extern "C" { @@ -27,6 +18,4 @@ extern interrupt_dev_t INTERRUPT; } #endif - - #endif /*_SOC_INTERRUPT_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/mpu_caps.h b/components/soc/esp32s3/include/soc/mpu_caps.h deleted file mode 100644 index 1d23e37507..0000000000 --- a/components/soc/esp32s3/include/soc/mpu_caps.h +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 -#define SOC_MPU_MIN_REGION_SIZE 0x20000000U -#define SOC_MPU_REGIONS_MAX_NUM 8 -#define SOC_MPU_REGION_RO_SUPPORTED 0 -#define SOC_MPU_REGION_WO_SUPPORTED 0 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 78a29ee2c3..1955df7db0 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -26,7 +26,6 @@ #define DR_REG_DTAG_TABLE 0x600C8000 #define DR_REG_EXT_MEM_ENC 0x600CC000 - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) @@ -190,7 +189,6 @@ #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space - //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40378000 #define SOC_DIRAM_IRAM_HIGH 0x403E0000 @@ -209,7 +207,6 @@ #define SOC_DMA_EXT_LOW SOC_EXTRAM_DATA_LOW #define SOC_DMA_EXT_HIGH SOC_EXTRAM_DATA_HIGH - // Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). #define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 #define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 5fdf7c1422..29936d51c0 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -262,7 +262,11 @@ #define SOC_MMU_PERIPH_NUM (1U) /*-------------------------- MPU CAPS ----------------------------------------*/ -#include "mpu_caps.h" +#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +#define SOC_MPU_MIN_REGION_SIZE 0x20000000U +#define SOC_MPU_REGIONS_MAX_NUM 8 +#define SOC_MPU_REGION_RO_SUPPORTED 0 +#define SOC_MPU_REGION_WO_SUPPORTED 0 /*-------------------------- PCNT CAPS ---------------------------------------*/ #define SOC_PCNT_GROUPS (1U) diff --git a/components/soc/esp32s3/include/soc/usb_dwc_struct.h b/components/soc/esp32s3/include/soc/usb_dwc_struct.h index 1910ca2049..1d84a6b85b 100644 --- a/components/soc/esp32s3/include/soc/usb_dwc_struct.h +++ b/components/soc/esp32s3/include/soc/usb_dwc_struct.h @@ -67,7 +67,7 @@ typedef union { } usb_dwc_gotgint_reg_t; typedef union { - struct { + struct { uint32_t glbllntrmsk: 1; uint32_t hbstlen: 4; uint32_t dmaen: 1; diff --git a/components/soc/esp32s3/ledc_periph.c b/components/soc/esp32s3/ledc_periph.c index fa3c729eea..d508be2a32 100644 --- a/components/soc/esp32s3/ledc_periph.c +++ b/components/soc/esp32s3/ledc_periph.c @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/ledc_periph.h" #include "soc/gpio_sig_map.h" @@ -19,7 +11,7 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { + { .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + } }; diff --git a/components/soc/include/soc/emac_periph.h b/components/soc/include/soc/emac_periph.h index bccc1ccb1f..ad18070643 100644 --- a/components/soc/include/soc/emac_periph.h +++ b/components/soc/include/soc/emac_periph.h @@ -10,7 +10,6 @@ #include "soc/gpio_sig_map.h" #include "soc/gpio_num.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/include/soc/gpio_periph.h b/components/soc/include/soc/gpio_periph.h index ae0ed73ec9..c9a88a50d8 100644 --- a/components/soc/include/soc/gpio_periph.h +++ b/components/soc/include/soc/gpio_periph.h @@ -1,19 +1,11 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include "stdint.h" +#include #include "soc/io_mux_reg.h" #include "soc/gpio_struct.h" #include "soc/gpio_reg.h" @@ -21,8 +13,7 @@ #include "soc/gpio_sig_map.h" #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif extern const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT]; diff --git a/components/soc/include/soc/mipi_csi_periph.h b/components/soc/include/soc/mipi_csi_periph.h index d4fd660535..40283c0f99 100644 --- a/components/soc/include/soc/mipi_csi_periph.h +++ b/components/soc/include/soc/mipi_csi_periph.h @@ -25,7 +25,6 @@ typedef struct { extern const soc_mipi_csi_phy_pll_freq_range_t soc_mipi_csi_phy_pll_ranges[]; extern const size_t num_of_soc_mipi_csi_phy_pll_ranges; - #ifdef __cplusplus } #endif diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index 3a89917367..1a6da446e9 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -100,7 +100,6 @@ typedef enum { REGDMA_LINK_PRI_7, } regdma_link_priority_t; - typedef void * regdma_entry_buf_t[REGDMA_LINK_ENTRY_NUM]; typedef enum regdma_link_mode { @@ -110,7 +109,6 @@ typedef enum regdma_link_mode { REGDMA_LINK_MODE_WAIT /*!< Link used to wait for register value to meet condition*/ } regdma_link_mode_t; - typedef struct regdma_link_head { volatile uint32_t length: 10, /* total count of registers that need to be backup or restore, unit: 1 word = 4 bytes */ reserve0: 6, @@ -176,7 +174,7 @@ ESP_STATIC_ASSERT(REGDMA_LINK_ENTRY_NUM <= 16, "regdma link entry number should typedef struct regdma_link_stats { volatile uint32_t ref: REGDMA_LINK_ENTRY_NUM, /* a bitmap, identifies which entry has referenced the current link */ #if REGDMA_LINK_ENTRY_NUM < 16 - reserve: 16-REGDMA_LINK_ENTRY_NUM, + reserve: 16 - REGDMA_LINK_ENTRY_NUM, #endif id: 16; /* REGDMA linked list node unique identifier */ volatile int module; /* a number used to identify the module to which the current node belongs */ diff --git a/components/soc/linux/include/soc/gpio_num.h b/components/soc/linux/include/soc/gpio_num.h index cf7eb496da..1061636c22 100644 --- a/components/soc/linux/include/soc/gpio_num.h +++ b/components/soc/linux/include/soc/gpio_num.h @@ -61,7 +61,6 @@ typedef enum { GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ GPIO_NUM_MAX, -/** @endcond */ } gpio_num_t; #ifdef __cplusplus diff --git a/components/soc/lldesc.c b/components/soc/lldesc.c index 3e27537e05..7850d78799 100644 --- a/components/soc/lldesc.c +++ b/components/soc/lldesc.c @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + #include "soc/lldesc.h" void lldesc_setup_link_constrained(lldesc_t *dmadesc, const void *data, int len, int max_desc_size, bool isrx) @@ -33,11 +39,13 @@ int lldesc_get_received_len(lldesc_t* head, lldesc_t** out_next) { lldesc_t* desc = head; int len = 0; - while(desc) { + while (desc) { len += desc->length; bool eof = desc->eof; desc = STAILQ_NEXT(desc, qe); - if (eof) break; + if (eof) { + break; + } } if (out_next) { *out_next = desc; diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index 12da05ef74..ad50bb3fb0 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -84,7 +84,6 @@ components_not_formatted_temporary: - "/components/protocomm/" - "/components/riscv/" - "/components/sdmmc/" - - "/components/soc/" - "/components/spi_flash/" - "/components/spiffs/" - "/components/tcp_transport/" @@ -155,7 +154,7 @@ components_not_formatted_permanent: # FreeRTOS-Plux-POSIX files (upstream source code) - "/components/rt/" # SoC header files (generated) - - "/components/soc/*/include/soc/" + - "/components/soc/*/register/soc/" # Example resource files (generated) - "/examples/peripherals/lcd/i80_controller/main/images/" - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 712e7b5791..54b8ab8fbb 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -509,39 +509,19 @@ components/sdmmc/sdmmc_init.c components/sdmmc/sdmmc_io.c components/sdmmc/sdmmc_mmc.c components/sdmmc/sdmmc_sd.c -components/soc/esp32/adc_periph.c -components/soc/esp32/include/soc/bb_reg.h -components/soc/esp32/include/soc/boot_mode.h components/soc/esp32/include/soc/fe_reg.h components/soc/esp32/include/soc/flash_encryption_reg.h components/soc/esp32/include/soc/gpio_sig_map.h -components/soc/esp32/include/soc/pid.h components/soc/esp32/include/soc/reset_reasons.h components/soc/esp32/include/soc/sdmmc_pins.h -components/soc/esp32/include/soc/soc_pins.h components/soc/esp32/include/soc/soc_ulp.h components/soc/esp32/include/soc/touch_sensor_channel.h -components/soc/esp32/include/soc/uart_pins.h -components/soc/esp32/include/soc/wdev_reg.h -components/soc/esp32/ledc_periph.c -components/soc/esp32c3/ledc_periph.c -components/soc/esp32s2/adc_periph.c -components/soc/esp32s2/include/soc/bb_reg.h -components/soc/esp32s2/include/soc/boot_mode.h components/soc/esp32s2/include/soc/fe_reg.h -components/soc/esp32s2/include/soc/gpio_sig_map.h components/soc/esp32s2/include/soc/memprot_defs.h components/soc/esp32s2/include/soc/nrx_reg.h components/soc/esp32s2/include/soc/soc_ulp.h components/soc/esp32s2/include/soc/touch_sensor_channel.h components/soc/esp32s2/include/soc/touch_sensor_pins.h -components/soc/esp32s2/include/soc/uart_pins.h -components/soc/esp32s2/include/soc/wdev_reg.h -components/soc/esp32s2/ledc_periph.c -components/soc/esp32s3/include/soc/mpu_caps.h -components/soc/esp32s3/ledc_periph.c -components/soc/include/soc/gpio_periph.h -components/soc/lldesc.c components/spi_flash/include/spi_flash_chip_boya.h components/spi_flash/include/spi_flash_chip_gd.h components/spi_flash/include/spi_flash_chip_generic.h