i2s: Fix esp32c6 get I2S_CLK_SRC_PLL_160M clock frequency value wrong issue

components/driver/i2s/i2s_common.c

@@ -488,8 +488,19 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
         (void)mclk_freq_hz;
         return esp_clk_xtal_freq();
 #endif
-    default: // I2S_CLK_SRC_PLL_160M
+#if SOC_I2S_SUPPORTS_PLL_F160M
-        return esp_clk_apb_freq() * 2;
+    case I2S_CLK_SRC_PLL_160M:
+        (void)mclk_freq_hz;
+        return I2S_LL_PLL_F160M_CLK_FREQ;
+#endif
+#if SOC_I2S_SUPPORTS_PLL_F96M
+    case I2S_CLK_SRC_PLL_96M:
+        (void)mclk_freq_hz;
+        return I2S_LL_PLL_F96M_CLK_FREQ;
+#endif
+    default:
+        // Invalid clock source
+        return 0;
     }
 }
 

components/hal/esp32/include/hal/i2s_ll.h

@@ -45,6 +45,8 @@ extern "C" {
 #define I2S_LL_TX_EVENT_MASK        I2S_LL_EVENT_TX_EOF
 #define I2S_LL_RX_EVENT_MASK        I2S_LL_EVENT_RX_EOF
 
+#define I2S_LL_PLL_F160M_CLK_FREQ   (160 * 1000000) // PLL_F160M_CLK: 160MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/hal/esp32c3/include/hal/i2s_ll.h

@@ -32,6 +32,8 @@ extern "C" {
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
 
+#define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/hal/esp32c6/include/hal/i2s_ll.h

@@ -33,6 +33,8 @@ extern "C" {
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
 
+#define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/hal/esp32h4/include/hal/i2s_ll.h

@@ -33,6 +33,8 @@ extern "C" {
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
 
+#define I2S_LL_PLL_F96M_CLK_FREQ       (96 * 1000000) // PLL_F96M_CLK: 96MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/hal/esp32s2/include/hal/i2s_ll.h

@@ -42,6 +42,8 @@ extern "C" {
 #define I2S_LL_TX_EVENT_MASK        I2S_LL_EVENT_TX_EOF
 #define I2S_LL_RX_EVENT_MASK        I2S_LL_EVENT_RX_EOF
 
+#define I2S_LL_PLL_F160M_CLK_FREQ   (160 * 1000000) // PLL_F160M_CLK: 160MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/hal/esp32s3/include/hal/i2s_ll.h

@@ -33,6 +33,8 @@ extern "C" {
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
 
+#define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -299,6 +299,10 @@ config SOC_I2S_SUPPORTS_APLL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PDM
     bool
     default y

components/soc/esp32/include/soc/clk_tree_defs.h

@@ -244,15 +244,15 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL}
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL}
 
 /**
  * @brief I2S clock source enum
  *
  */
 typedef enum {
-    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2,                   /*!< Select PLL_D2 as the default source clock  */
+    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
-    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_D2,                  /*!< Select PLL_D2 as the source clock */
+    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
     I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL,                        /*!< Select APLL as the source clock */
 } soc_periph_i2s_clk_src_t;
 

components/soc/esp32/include/soc/soc_caps.h

@@ -185,6 +185,7 @@
 #define SOC_I2S_NUM                 (2U)
 #define SOC_I2S_HW_VERSION_1        (1)
 #define SOC_I2S_SUPPORTS_APLL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)
 #define SOC_I2S_PDM_MAX_TX_LINES    (1U)

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -375,6 +375,10 @@ config SOC_I2S_SUPPORTS_XTAL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -184,6 +184,7 @@
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -367,6 +367,10 @@ config SOC_I2S_SUPPORTS_XTAL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -205,6 +205,7 @@
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -351,6 +351,10 @@ config SOC_I2S_SUPPORTS_XTAL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F96M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32h4/include/soc/soc_caps.h

@@ -191,6 +191,7 @@
 #define SOC_I2S_NUM                 (1)
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F96M   (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -363,6 +363,10 @@ config SOC_I2S_SUPPORTS_APLL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_DMA_EQUAL
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -181,6 +181,7 @@
 #define SOC_I2S_NUM                 (1U)
 #define SOC_I2S_HW_VERSION_1        (1)
 #define SOC_I2S_SUPPORTS_APLL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_DMA_EQUAL  (1)
 #define SOC_I2S_SUPPORTS_LCD_CAMERA (1)
 #define SOC_I2S_APLL_MIN_FREQ       (250000000)

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -419,6 +419,10 @@ config SOC_I2S_SUPPORTS_XTAL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -185,6 +185,7 @@
 #define SOC_I2S_NUM                 (2)
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)