forked from espressif/esp-idf
codeclean: add sleep_mode args to esp_sleep_start()
This commit is contained in:
@@ -98,6 +98,14 @@ typedef enum {
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ESP_SLEEP_WAKEUP_BT, //!< Wakeup caused by BT (light sleep only)
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ESP_SLEEP_WAKEUP_BT, //!< Wakeup caused by BT (light sleep only)
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} esp_sleep_source_t;
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} esp_sleep_source_t;
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/**
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* @brief Sleep mode
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*/
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typedef enum {
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ESP_SLEEP_MODE_LIGHT_SLEEP, //!< light sleep mode
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ESP_SLEEP_MODE_DEEP_SLEEP //!< deep sleep mode
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} esp_sleep_mode_t;
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/* Leave this type define for compatibility */
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/* Leave this type define for compatibility */
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typedef esp_sleep_source_t esp_sleep_wakeup_cause_t;
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typedef esp_sleep_source_t esp_sleep_wakeup_cause_t;
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@@ -394,23 +394,25 @@ inline static void IRAM_ATTR misc_modules_wake_prepare(void)
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inline static uint32_t call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu, bool dslp);
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inline static uint32_t call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu, bool dslp);
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inline static bool is_light_sleep(uint32_t pd_flags)
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static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mode)
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{
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return (pd_flags & RTC_SLEEP_PD_DIG) == 0;
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}
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static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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{
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{
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// Stop UART output so that output is not lost due to APB frequency change.
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// Stop UART output so that output is not lost due to APB frequency change.
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// For light sleep, suspend UART output — it will resume after wakeup.
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// For light sleep, suspend UART output — it will resume after wakeup.
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
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bool deep_sleep = (mode == ESP_SLEEP_MODE_DEEP_SLEEP);
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if (deep_sleep) {
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if (deep_sleep) {
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flush_uarts();
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flush_uarts();
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} else {
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} else {
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#if SOC_PM_SUPPORT_TOP_PD
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if (pd_flags & PMU_SLEEP_PD_TOP) {
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flush_uarts();
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} else
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#endif
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{
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suspend_uarts();
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suspend_uarts();
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}
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}
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}
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#if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
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#if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
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//Keep the RTC8M_CLK on if RTC clock is rc_fast_d256.
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//Keep the RTC8M_CLK on if RTC clock is rc_fast_d256.
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@@ -484,7 +486,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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#endif
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#endif
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uint32_t reject_triggers = 0;
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uint32_t reject_triggers = 0;
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if (is_light_sleep(pd_flags)) {
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if (!deep_sleep) {
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/* Light sleep, enable sleep reject for faster return from this function,
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/* Light sleep, enable sleep reject for faster return from this function,
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* in case the wakeup is already triggerred.
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* in case the wakeup is already triggerred.
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*/
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*/
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@@ -544,14 +546,14 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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size_t rtc_fast_length = (size_t)_rtc_force_fast_end - (size_t)_rtc_text_start;
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size_t rtc_fast_length = (size_t)_rtc_force_fast_end - (size_t)_rtc_text_start;
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#endif
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#endif
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esp_rom_set_rtc_wake_addr((esp_rom_wake_func_t)esp_wake_stub_entry, rtc_fast_length);
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esp_rom_set_rtc_wake_addr((esp_rom_wake_func_t)esp_wake_stub_entry, rtc_fast_length);
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, 0);
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
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#else
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#else
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#if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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#if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
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/* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
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#if SOC_RTC_FAST_MEM_SUPPORTED
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#if SOC_RTC_FAST_MEM_SUPPORTED
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set_rtc_memory_crc();
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set_rtc_memory_crc();
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#endif
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#endif
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, 0);
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
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#else
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#else
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/* Otherwise, need to call the dedicated soc function for this */
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/* Otherwise, need to call the dedicated soc function for this */
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result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
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result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
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@@ -569,7 +571,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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result = call_rtc_sleep_start(reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
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result = call_rtc_sleep_start(reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
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}
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}
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#else
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#else
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, 0);
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result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
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#endif
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#endif
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}
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}
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@@ -643,7 +645,7 @@ void IRAM_ATTR esp_deep_sleep_start(void)
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#endif
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#endif
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// Enter sleep
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// Enter sleep
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esp_sleep_start(force_pd_flags | pd_flags);
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esp_sleep_start(force_pd_flags | pd_flags, ESP_SLEEP_MODE_DEEP_SLEEP);
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// Because RTC is in a slower clock domain than the CPU, it
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// Because RTC is in a slower clock domain than the CPU, it
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// can take several CPU cycles for the sleep mode to start.
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// can take several CPU cycles for the sleep mode to start.
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@@ -666,7 +668,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
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uint32_t flash_enable_time_us)
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uint32_t flash_enable_time_us)
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{
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{
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// Enter sleep
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// Enter sleep
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uint32_t reject = esp_sleep_start(pd_flags);
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uint32_t reject = esp_sleep_start(pd_flags, ESP_SLEEP_MODE_LIGHT_SLEEP);
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#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
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#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
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rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
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rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
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