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Merge branch 'bugfix/fix_uart_disabled_in_driver_cause_restart_stuck' into 'master'

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fix(esp_system): fix uart clock disabled in driver cause esp_restart stuck

Closes IDF-8738

See merge request espressif/esp-idf!27409
This commit is contained in:
Wu Zheng Hui
2023-11-27 16:47:25 +08:00
parent feb62db338 04fcfff5e0
commit 24a000d2fa
8 changed files with 45 additions and 23 deletions
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10
components/esp_system/port/soc/esp32/system_internal.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -32,9 +32,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(2); esp_rom_uart_tx_wait_idle(i);
}
}
// Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,

9
components/esp_system/port/soc/esp32c2/system_internal.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -30,8 +30,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
// Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Reset wifi/bluetooth/ethernet/sdio (bb/mac)

9
components/esp_system/port/soc/esp32c3/system_internal.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -31,8 +31,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
// Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,

7
components/esp_system/port/soc/esp32c6/system_internal.c
View File

@@ -31,8 +31,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
modem_syscon_ll_reset_all(&MODEM_SYSCON); modem_syscon_ll_reset_all(&MODEM_SYSCON);
modem_lpcon_ll_reset_all(&MODEM_LPCON); modem_lpcon_ll_reset_all(&MODEM_LPCON);

7
components/esp_system/port/soc/esp32h2/system_internal.c
View File

@@ -32,8 +32,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
// Set Peripheral clk rst // Set Peripheral clk rst
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);

7
components/esp_system/port/soc/esp32p4/system_internal.c
View File

@@ -31,8 +31,11 @@
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs // Flush any data left in UART FIFOs
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
// Set Peripheral clk rst // Set Peripheral clk rst
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0);

9
components/esp_system/port/soc/esp32s2/system_internal.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -34,8 +34,11 @@ extern int _bss_end;
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
}
// Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,

10
components/esp_system/port/soc/esp32s3/system_internal.c
View File

@@ -1,6 +1,6 @@
/* /*
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -34,9 +34,11 @@ extern int _bss_end;
void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_system_reset_modules_on_exit(void)
{ {
// Flush any data left in UART FIFOs before reset the UART peripheral // Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_uart_tx_wait_idle(0); for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
esp_rom_uart_tx_wait_idle(1); if (uart_ll_is_enabled(i)) {
esp_rom_uart_tx_wait_idle(2); esp_rom_uart_tx_wait_idle(i);
}
}
// Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,