From 473e7268fdf41a6c2cefb7a16c524b61f8cd1324 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 19 Jul 2024 11:49:49 +0800 Subject: [PATCH 1/2] feat(gdma): add GDMA link list driver --- components/esp_hw_support/CMakeLists.txt | 1 + components/esp_hw_support/dma/dw_gdma.c | 4 +- components/esp_hw_support/dma/gdma_link.c | 246 ++++++++++++++++++ .../dma/include/esp_private/dw_gdma.h | 2 +- .../dma/include/esp_private/gdma_link.h | 144 ++++++++++ .../test_apps/dma/main/test_gdma.c | 151 ++++++----- 6 files changed, 479 insertions(+), 69 deletions(-) create mode 100644 components/esp_hw_support/dma/gdma_link.c create mode 100644 components/esp_hw_support/dma/include/esp_private/gdma_link.h diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index c872e56b71..7ede9c33d7 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -38,6 +38,7 @@ if(NOT BOOTLOADER_BUILD) "port/${target}/esp_clk_tree.c" "port/esp_clk_tree_common.c" "dma/esp_dma_utils.c" + "dma/gdma_link.c" "spi_share_hw_ctrl.c" "spi_bus_lock.c") diff --git a/components/esp_hw_support/dma/dw_gdma.c b/components/esp_hw_support/dma/dw_gdma.c index 765d931c0d..f76f1245eb 100644 --- a/components/esp_hw_support/dma/dw_gdma.c +++ b/components/esp_hw_support/dma/dw_gdma.c @@ -381,7 +381,7 @@ esp_err_t dw_gdma_channel_continue(dw_gdma_channel_handle_t chan) esp_err_t dw_gdma_new_link_list(const dw_gdma_link_list_config_t *config, dw_gdma_link_list_handle_t *ret_list) { esp_err_t ret = ESP_OK; - ESP_RETURN_ON_FALSE(ret_list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(config && ret_list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); dw_gdma_link_list_item_t *items = NULL; dw_gdma_link_list_t *list = NULL; uint32_t num_items = config->num_items; @@ -531,7 +531,7 @@ esp_err_t dw_gdma_channel_set_block_markers(dw_gdma_channel_handle_t chan, dw_gd return ESP_OK; } -esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, dw_gdma_block_transfer_config_t *config) +esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, const dw_gdma_block_transfer_config_t *config) { ESP_RETURN_ON_FALSE(lli && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c new file mode 100644 index 0000000000..d13b62e64d --- /dev/null +++ b/components/esp_hw_support/dma/gdma_link.c @@ -0,0 +1,246 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "soc/soc_caps.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_memory_utils.h" +#include "esp_heap_caps.h" +#include "esp_private/gdma_link.h" +#include "hal/cache_hal.h" +#include "hal/cache_ll.h" +#include "esp_cache.h" + +static const char *TAG = "gdma"; + +#if SOC_NON_CACHEABLE_OFFSET +#define GDMA_CACHE_ADDR_TO_NON_CACHE_ADDR(addr) ((addr) + SOC_NON_CACHEABLE_OFFSET) +#else +#define GDMA_CACHE_ADDR_TO_NON_CACHE_ADDR(addr) (addr) +#endif + +#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) + +// GDMA link list item definition +// TODO: this type will eventually become target specific, we need to move it to the LL layer or soc layer +typedef struct gdma_link_list_item_t gdma_link_list_item_t; +struct gdma_link_list_item_t { + struct { + uint32_t size : 12; /*!< Buffer size */ + uint32_t length : 12; /*!< Number of valid bytes in the buffer */ + uint32_t reversed24 : 4; /*!< Reserved */ + uint32_t err_eof : 1; /*!< Whether the received buffer contains error, the error was reported by the peripheral */ + uint32_t reserved29 : 1; /*!< Reserved */ + uint32_t suc_eof : 1; /*!< Whether the list item should notify the peripheral an "EOF" event */ + uint32_t owner : 1; /*!< Who is allowed to access the buffer */ + } dw0; /*!< list item Word 0 */ + void *buffer; /*!< Pointer to the buffer */ + gdma_link_list_item_t *next; /*!< Pointer to the next list item (set to NULL if the list item is the last one of the link) */ +}; + +///< Maximum size of the buffer that can be carried by a DMA link list item +#define GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM 4095 + +typedef struct gdma_link_list_t { + uint32_t num_items; // number of items in the link list + size_t item_size; // size of each item + size_t buffer_alignment; // Alignment of each buffer + uint8_t *items; // pointer to the link list items + uint8_t *items_nc; // pointer to the link list items, non-cached + struct { + uint32_t check_owner: 1; // Whether the link list is responsible for checking the ownership when mount data buffers + } flags; +} gdma_link_list_t; + +esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_list_handle_t *ret_list) +{ + esp_err_t ret = ESP_OK; + uint8_t *items = NULL; + gdma_link_list_t *list = NULL; + ESP_RETURN_ON_FALSE(config && ret_list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(config->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid number of items"); + size_t buffer_alignment = config->buffer_alignment; + if (buffer_alignment == 0) { + buffer_alignment = 1; + } + ESP_RETURN_ON_FALSE((buffer_alignment & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "invalid buffer alignment: %zu", buffer_alignment); + + // the link list container is allocated from internal memory + list = heap_caps_calloc(1, sizeof(gdma_link_list_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + ESP_GOTO_ON_FALSE(list, ESP_ERR_NO_MEM, err, TAG, "no mem for link list"); + + uint32_t num_items = config->num_items; + size_t item_alignment = config->item_alignment ? config->item_alignment : 4; + // each list item should align to the specified alignment + size_t item_size = ALIGN_UP(sizeof(gdma_link_list_item_t), item_alignment); + + uint32_t list_items_mem_caps = MALLOC_CAP_8BIT | MALLOC_CAP_DMA; + if (config->flags.items_in_ext_mem) { + list_items_mem_caps |= MALLOC_CAP_SPIRAM; + } else { + list_items_mem_caps |= MALLOC_CAP_INTERNAL; + } + items = heap_caps_aligned_calloc(item_alignment, num_items, item_size, list_items_mem_caps); + ESP_GOTO_ON_FALSE(items, ESP_ERR_NO_MEM, err, TAG, "no mem for link list items"); + + // do memory sync if the list items are in the cache + uint32_t data_cache_line_size = 0; + if (config->flags.items_in_ext_mem) { + data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); + } else { + data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); + } + if (data_cache_line_size) { + // write back and then invalidate the cache, because later we will read/write the link list items by non-cached address + ESP_GOTO_ON_ERROR(esp_cache_msync(items, ALIGN_UP(num_items * item_size, data_cache_line_size), + ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE), + err, TAG, "cache sync failed"); + } + + list->num_items = num_items; + list->item_size = item_size; + list->items = items; + // calculate the non-cached address + list->items_nc = GDMA_CACHE_ADDR_TO_NON_CACHE_ADDR(items); + list->buffer_alignment = buffer_alignment; + list->flags.check_owner = config->flags.check_owner; + + ESP_LOGD(TAG, "new link list @%p, items @%p", list, items); + *ret_list = list; + return ESP_OK; + +err: + if (list) { + free(list); + } + if (items) { + free(items); + } + return ret; +} + +esp_err_t gdma_del_link_list(gdma_link_list_handle_t list) +{ + ESP_RETURN_ON_FALSE(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_LOGD(TAG, "del link list at %p", list); + free(list->items); + free(list); + return ESP_OK; +} + +esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, uint32_t start_item_index, const gdma_buffer_mount_config_t *buf_config_array, size_t num_buf, uint32_t *end_item_index) +{ + ESP_RETURN_ON_FALSE(list && buf_config_array && num_buf, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(start_item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid start item index"); + size_t buffer_alignment = list->buffer_alignment; + size_t item_size = list->item_size; + uint32_t list_item_capacity = list->num_items; + size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); + uint32_t begin_item_idx = start_item_index; + gdma_link_list_item_t *lli_nc = NULL; + + uint32_t num_items_avail = 0; + // if the link list is responsible for checking the ownership, we need to skip the items that are owned by the DMA + if (list->flags.check_owner) { + for (uint32_t i = 0; i < list_item_capacity; i++) { + lli_nc = (gdma_link_list_item_t *)(list->items_nc + (i + start_item_index) % list_item_capacity * item_size); + if (lli_nc->dw0.owner == GDMA_LLI_OWNER_CPU) { + num_items_avail++; + } + } + } else { + num_items_avail = list_item_capacity; + } + + // check alignment and length for each buffer + for (size_t i = 0; i < num_buf; i++) { + const gdma_buffer_mount_config_t *config = &buf_config_array[i]; + uint8_t *buf = (uint8_t *)config->buffer; + size_t len = config->length; + // check the buffer alignment + ESP_RETURN_ON_FALSE(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer not aligned to %zu", buffer_alignment); + uint32_t num_items_need = (len + max_buffer_mount_length - 1) / max_buffer_mount_length; + // check if there are enough link list items + ESP_RETURN_ON_FALSE((begin_item_idx + num_items_need) <= (start_item_index + num_items_avail), ESP_ERR_INVALID_ARG, TAG, "no more space for buffer mounting"); + begin_item_idx += num_items_need; + } + + // link_nodes[start_item_index-1] --> link_nodes[start_item_index] + lli_nc = (gdma_link_list_item_t *)(list->items_nc + (start_item_index + list_item_capacity - 1) % list_item_capacity * item_size); + lli_nc->next = (gdma_link_list_item_t *)(list->items + start_item_index * item_size); + + begin_item_idx = start_item_index; + for (size_t i = 0; i < num_buf; i++) { + const gdma_buffer_mount_config_t *config = &buf_config_array[i]; + uint8_t *buf = (uint8_t *)config->buffer; + size_t len = config->length; + // skip zero-length buffer + if (len == 0 || buf == NULL) { + continue; + } + uint32_t num_items_need = (len + max_buffer_mount_length - 1) / max_buffer_mount_length; + // mount the buffer to the link list + for (uint32_t i = 0; i < num_items_need; i++) { + lli_nc = (gdma_link_list_item_t *)(list->items_nc + (i + begin_item_idx) % list_item_capacity * item_size); + lli_nc->buffer = buf; + lli_nc->dw0.length = len > max_buffer_mount_length ? max_buffer_mount_length : len; + // in fact the DMA doesn't check the "size" field, but we still set it to "length" for consistency + // it's the user's responsibility to make sure the buffer size is sufficient + lli_nc->dw0.size = lli_nc->dw0.length; + // mark the EOF node + lli_nc->dw0.suc_eof = (config->flags.mark_eof == 1) && (i == num_items_need - 1); + // mark the final node + if ((config->flags.mark_final == 1) && (i == num_items_need - 1)) { + lli_nc->next = NULL; + } else { + lli_nc->next = (gdma_link_list_item_t *)(list->items + (i + begin_item_idx + 1) % list_item_capacity * item_size); + } + lli_nc->dw0.owner = GDMA_LLI_OWNER_DMA; + buf += max_buffer_mount_length; + len -= max_buffer_mount_length; + } + begin_item_idx += num_items_need; + } + + // return the index of the last modified list item + if (end_item_index) { + *end_item_index = (begin_item_idx - 1 + list_item_capacity) % list_item_capacity; + } + return ESP_OK; +} + +uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list) +{ + ESP_RETURN_ON_FALSE(list, 0, TAG, "invalid argument"); + return (uintptr_t)(list->items); +} + +esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t owner) +{ + ESP_RETURN_ON_FALSE_ISR(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index"); + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + lli->dw0.owner = owner; + return ESP_OK; +} + +esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t *owner) +{ + ESP_RETURN_ON_FALSE_ISR(list && owner, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index"); + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + *owner = lli->dw0.owner; + return ESP_OK; +} diff --git a/components/esp_hw_support/dma/include/esp_private/dw_gdma.h b/components/esp_hw_support/dma/include/esp_private/dw_gdma.h index dd9105e9d3..6351833846 100644 --- a/components/esp_hw_support/dma/include/esp_private/dw_gdma.h +++ b/components/esp_hw_support/dma/include/esp_private/dw_gdma.h @@ -361,7 +361,7 @@ dw_gdma_lli_handle_t dw_gdma_link_list_get_item(dw_gdma_link_list_handle_t list, * - ESP_ERR_INVALID_ARG: Configure link list item block transfer failed because of invalid argument * - ESP_FAIL: Configure link list item block transfer failed because of other error */ -esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, dw_gdma_block_transfer_config_t *config); +esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, const dw_gdma_block_transfer_config_t *config); /** * @brief Set the next link list item for a given DMA link list item diff --git a/components/esp_hw_support/dma/include/esp_private/gdma_link.h b/components/esp_hw_support/dma/include/esp_private/gdma_link.h new file mode 100644 index 0000000000..94a13651c4 --- /dev/null +++ b/components/esp_hw_support/dma/include/esp_private/gdma_link.h @@ -0,0 +1,144 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of GDMA link list handle + */ +typedef struct gdma_link_list_t *gdma_link_list_handle_t; + +/** + * @brief DMA link list configurations + */ +typedef struct { + uint32_t num_items; //!< Number of nodes in the link list + size_t item_alignment; //!< Alignment of each list item required by the DMA. By default, it's 4 bytes alignment. + size_t buffer_alignment; //!< Alignment of each buffer required by the DMA. By default, it's 1 byte alignment. + struct gdma_link_list_flags { + uint32_t items_in_ext_mem: 1; //!< Whether the link list items are allocated from external memory + uint32_t check_owner: 1; //!< Whether the link list is responsible for checking the ownership when mount data buffers + } flags; +} gdma_link_list_config_t; + +/** + * @brief Create a DMA link list + * + * @note This function will allocate memory for the link list. + * + * @param[in] config Link list configurations + * @param[out] ret_list Returned link list handle + * @return + * - ESP_OK: Create DMA link list successfully + * - ESP_ERR_INVALID_ARG: Create DMA link list failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA link list failed because out of memory + * - ESP_FAIL: Create DMA link list failed because of other error + */ +esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_list_handle_t *ret_list); + +/** + * @brief Delete a DMA link list + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @return + * - ESP_OK: Delete DMA link list successfully + * - ESP_ERR_INVALID_ARG: Delete DMA link list failed because of invalid argument + * - ESP_FAIL: Delete DMA link list failed because of other error + */ +esp_err_t gdma_del_link_list(gdma_link_list_handle_t list); + +/** + * @brief DMA buffer mount configurations + */ +typedef struct { + void *buffer; //!< Buffer to be mounted to the DMA link list + size_t length; //!< Number of bytes that are expected to be transferred + struct gdma_buffer_mount_flags { + uint32_t mark_eof: 1; /*!< Whether to mark the list item as the "EOF" item. + Note, an "EOF" descriptor can be interrupted differently by peripheral. + But it doesn't mean to terminate a DMA link (use `mark_final` instead). + EOF link list item can also trigger an interrupt. */ + uint32_t mark_final: 1; /*!< Whether to terminate the DMA link list at this item. + Note, DMA engine will stop at this item and trigger an interrupt. + If `mark_final` is not set, this list item will point to the next item, and + wrap around to the head item if it's the one in the list. */ + } flags; //!< Flags for buffer mount configurations +} gdma_buffer_mount_config_t; + +/** + * @brief Mount one or more buffers to a given link list + * + * @note Different buffers won't be mounted to the same DMA link list item + * @note After mount to the last list item, the next list item will be the head item (wrap around) + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] start_item_index Index of the first item in the link list to be mounted + * @param[in] buf_config_array Array of buffer mount configurations + * @param[in] num_buf Number of buffers to be mounted + * @param[out] end_item_index Index of the last item in the link list that has been mounted + * @return + * - ESP_OK: Mount the buffer successfully + * - ESP_ERR_INVALID_ARG: Mount the buffer failed because of invalid argument + * - ESP_FAIL: Mount the buffer failed because of other error + */ +esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, uint32_t start_item_index, const gdma_buffer_mount_config_t *buf_config_array, size_t num_buf, uint32_t *end_item_index); + +/** + * @brief Get the address of the head item in the link list + * + * @note The head address can be used to start a DMA transfer + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @return + * - Address of the head item in the link list + * - NULL: Get the address failed + */ +uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list); + +/** + * @brief GDMA link list item owner + */ +typedef enum { + GDMA_LLI_OWNER_CPU = 0, /*!< GDMA link list item is only allowed to be accessed by CPU */ + GDMA_LLI_OWNER_DMA = 1, /*!< GDMA link list item is only allowed to be accessed by DMA */ +} gdma_lli_owner_t; + +/** + * @brief Set the ownership for a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item + * @param[in] owner Ownership + * @return + * - ESP_OK: Set the ownership successfully + * - ESP_ERR_INVALID_ARG: Set the ownership failed because of invalid argument + * - ESP_FAIL: Set the ownership failed because of other error + */ +esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t owner); + +/** + * @brief Get the ownership of a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item + * @param[out] owner Ownership + * @return + * - ESP_OK: Get the ownership successfully + * - ESP_ERR_INVALID_ARG: Get the ownership failed because of invalid argument + * - ESP_FAIL: Get the ownership failed because of other error + */ +esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t *owner); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c index d68d3a2ea0..b5638f6f5e 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -13,6 +13,7 @@ #include "unity.h" #include "esp_heap_caps.h" #include "esp_private/gdma.h" +#include "esp_private/gdma_link.h" #include "hal/dma_types.h" #include "soc/soc_caps.h" #include "hal/gdma_ll.h" @@ -20,7 +21,6 @@ #include "hal/cache_hal.h" #include "esp_cache.h" #include "esp_memory_utils.h" -#include "soc/soc_caps.h" TEST_CASE("GDMA channel allocation", "[GDMA]") { @@ -155,8 +155,9 @@ static bool test_gdma_m2m_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_e return task_woken == pdTRUE; } -static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan) +static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan, bool dma_link_in_ext_mem) { + size_t sram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); gdma_rx_event_callbacks_t rx_cbs = { .on_recv_eof = test_gdma_m2m_rx_eof_callback, }; @@ -178,20 +179,37 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger)); TEST_ESP_OK(gdma_connect(rx_chan, m2m_trigger)); - // allocate the source and destination buffer from SRAM - // |--------------------------------------------------| - // | 128 bytes DMA descriptor | 128 bytes data buffer | - // |--------------------------------------------------| - size_t sram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); - size_t alignment = MAX(sram_alignment, 8); - uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); - uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 384, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); - TEST_ASSERT_NOT_NULL(src_buf); - TEST_ASSERT_NOT_NULL(dst_buf); - dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf; - dma_descriptor_align8_t *rx_descs = (dma_descriptor_align8_t *) dst_buf; - uint8_t *src_data = src_buf + 128; - uint8_t *dst_data = dst_buf + 128; + // create DMA link list for TX channel (a singly link with 3 nodes) + gdma_link_list_config_t tx_link_list_config = { + .buffer_alignment = 1, + .item_alignment = 8, // 8-byte alignment required by the AXI-GDMA + .num_items = 3, + .flags = { + .items_in_ext_mem = dma_link_in_ext_mem, + .check_owner = true, + } + }; + gdma_link_list_handle_t tx_link_list = NULL; + TEST_ESP_OK(gdma_new_link_list(&tx_link_list_config, &tx_link_list)); + // allocate the source buffer from SRAM + uint8_t *src_data = heap_caps_calloc(1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_data); + + // create DMA link list for RX channel + gdma_link_list_config_t rx_link_list_config = { + .buffer_alignment = sram_alignment, // RX buffer should be aligned to the cache line size, because we will do cache invalidate later + .item_alignment = 8, // 8-byte alignment required by the AXI-GDMA + .num_items = 1, + .flags = { + .items_in_ext_mem = dma_link_in_ext_mem, + .check_owner = true, + }, + }; + gdma_link_list_handle_t rx_link_list = NULL; + TEST_ESP_OK(gdma_new_link_list(&rx_link_list_config, &rx_link_list)); + // allocate the destination buffer from SRAM + uint8_t *dst_data = heap_caps_calloc(1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(dst_data); // prepare the source data for (int i = 0; i < 128; i++) { @@ -199,64 +217,58 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl } if (sram_alignment) { // do write-back for the source data because it's in the cache - TEST_ESP_OK(esp_cache_msync((void *)src_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); + TEST_ESP_OK(esp_cache_msync(src_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); } + // test DMA can read data from main flash #if SOC_DMA_CAN_ACCESS_FLASH - const char *src_string = "GDMA can fetch data from MSPI Flash"; + const char *src_string = "GDMA can read data from MSPI Flash"; size_t src_string_len = strlen(src_string); TEST_ASSERT_TRUE(esp_ptr_in_drom(src_string)); - // Only gonna copy length = src_string_len, set the character after to be 0xFF - // So that we can check if the copied length is correct + // Only gonna copy length = src_string_len, set the character after to be 0xFF as a canary dst_data[128 + src_string_len] = 0xFF; if (sram_alignment) { // do write-back for the dst data because it's in the cache - TEST_ESP_OK(esp_cache_msync((void *)dst_data, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); + TEST_ESP_OK(esp_cache_msync(dst_data, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); } #endif -#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR - dma_descriptor_align8_t *tx_descs_nc = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(tx_descs)); - dma_descriptor_align8_t *rx_descs_nc = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(rx_descs)); -#else - dma_descriptor_align8_t *tx_descs_nc = tx_descs; - dma_descriptor_align8_t *rx_descs_nc = rx_descs; -#endif - - tx_descs_nc[0].buffer = src_data; - tx_descs_nc[0].dw0.size = 64; - tx_descs_nc[0].dw0.length = 64; - tx_descs_nc[0].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - tx_descs_nc[0].dw0.suc_eof = 0; - tx_descs_nc[0].next = &tx_descs[1]; // Note, the DMA doesn't recognize a non-cacheable address, here must be the cached address - - tx_descs_nc[1].buffer = src_data + 64; - tx_descs_nc[1].dw0.size = 64; - tx_descs_nc[1].dw0.length = 64; - tx_descs_nc[1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + gdma_buffer_mount_config_t tx_buf_mount_config[] = { + [0] = { + .buffer = src_data, + .length = 64, + }, + [1] = { + .buffer = src_data + 64, + .length = 64, #if !SOC_DMA_CAN_ACCESS_FLASH - tx_descs_nc[1].dw0.suc_eof = 1; - tx_descs_nc[1].next = NULL; -#else - tx_descs_nc[1].dw0.suc_eof = 0; - tx_descs_nc[1].next = &tx_descs[2]; - - tx_descs_nc[2].buffer = (void *)src_string; - tx_descs_nc[2].dw0.size = src_string_len + 1; // +1 for '\0' - tx_descs_nc[2].dw0.length = src_string_len; - tx_descs_nc[2].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - tx_descs_nc[2].dw0.suc_eof = 1; - tx_descs_nc[2].next = NULL; + .flags = { + .mark_eof = true, + .mark_final = true, // using singly list, so terminate the link here + } #endif + }, +#if SOC_DMA_CAN_ACCESS_FLASH + [2] = { + .buffer = (void *)src_string, + .length = src_string_len, + .flags = { + .mark_eof = true, + .mark_final = true, // using singly list, so terminate the link here + } + }, +#endif + }; + TEST_ESP_OK(gdma_link_mount_buffers(tx_link_list, 0, tx_buf_mount_config, sizeof(tx_buf_mount_config) / sizeof(gdma_buffer_mount_config_t), NULL)); - rx_descs_nc->buffer = dst_data; - rx_descs_nc->dw0.size = 256; - rx_descs_nc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - rx_descs_nc->dw0.suc_eof = 1; - rx_descs_nc->next = NULL; + gdma_buffer_mount_config_t rx_buf_mount_config = { + .buffer = dst_data, + .length = 256, + }; + TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, &rx_buf_mount_config, 1, NULL)); - TEST_ESP_OK(gdma_start(rx_chan, (intptr_t)rx_descs)); - TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs)); + TEST_ESP_OK(gdma_start(rx_chan, gdma_link_get_head_addr(rx_link_list))); + TEST_ESP_OK(gdma_start(tx_chan, gdma_link_get_head_addr(tx_link_list))); xSemaphoreTake(done_sem, portMAX_DELAY); @@ -265,10 +277,14 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl TEST_ESP_OK(esp_cache_msync((void *)dst_data, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); } - // check the DMA descriptor write-back feature - TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, tx_descs_nc[0].dw0.owner); - TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, rx_descs_nc[0].dw0.owner); + // The owner bit should been written back by the DMA + gdma_lli_owner_t owner = GDMA_LLI_OWNER_DMA; + TEST_ESP_OK(gdma_link_get_owner(tx_link_list, 0, &owner)); + TEST_ASSERT_EQUAL(GDMA_LLI_OWNER_CPU, owner); + TEST_ESP_OK(gdma_link_get_owner(rx_link_list, 0, &owner)); + TEST_ASSERT_EQUAL(GDMA_LLI_OWNER_CPU, owner); + // validate the destination data for (int i = 0; i < 128; i++) { TEST_ASSERT_EQUAL(i, dst_data[i]); } @@ -277,8 +293,10 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl dst_data[128 + src_string_len] = '\0'; TEST_ASSERT_TRUE(strcmp(src_string, (const char *)((uint32_t)dst_data + 128)) == 0); #endif - free((void *)src_buf); - free((void *)dst_buf); + free(src_data); + free(dst_data); + TEST_ESP_OK(gdma_del_link_list(tx_link_list)); + TEST_ESP_OK(gdma_del_link_list(rx_link_list)); vSemaphoreDelete(done_sem); } @@ -301,7 +319,7 @@ TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") }; TEST_ESP_OK(gdma_new_ahb_channel(&rx_chan_alloc_config, &rx_chan)); - test_gdma_m2m_mode(tx_chan, rx_chan); + test_gdma_m2m_mode(tx_chan, rx_chan, false); TEST_ESP_OK(gdma_del_channel(tx_chan)); TEST_ESP_OK(gdma_del_channel(rx_chan)); @@ -319,7 +337,8 @@ TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") }; TEST_ESP_OK(gdma_new_axi_channel(&rx_chan_alloc_config, &rx_chan)); - test_gdma_m2m_mode(tx_chan, rx_chan); + // the AXI GDMA allows to put the DMA link list in the external memory + test_gdma_m2m_mode(tx_chan, rx_chan, true); TEST_ESP_OK(gdma_del_channel(tx_chan)); TEST_ESP_OK(gdma_del_channel(rx_chan)); From 80bc9a38450af87280c90f3549fac384424b510e Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 24 Jul 2024 18:53:38 +0800 Subject: [PATCH 2/2] refactor(i80): use the gdma link list driver --- components/esp_lcd/i80/esp_lcd_panel_io_i2s.c | 92 ++++++++++++++----- 1 file changed, 70 insertions(+), 22 deletions(-) diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c index 68db94d8b3..2086182842 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c @@ -33,17 +33,20 @@ #include "esp_lcd_common.h" #include "esp_rom_gpio.h" #include "soc/soc_caps.h" -#include "hal/dma_types.h" #include "hal/gpio_hal.h" #include "driver/gpio.h" #include "esp_clk_tree.h" #include "esp_private/periph_ctrl.h" #include "esp_private/i2s_platform.h" +#include "esp_private/gdma_link.h" #include "soc/lcd_periph.h" #include "hal/i2s_hal.h" #include "hal/i2s_ll.h" #include "hal/i2s_types.h" +// the DMA descriptor used by esp32 and esp32s2, each descriptor can carry 4095 bytes at most +#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095 + static const char *TAG = "lcd_panel.io.i80"; typedef struct esp_lcd_i80_bus_t esp_lcd_i80_bus_t; @@ -71,6 +74,7 @@ struct esp_lcd_i80_bus_t { intr_handle_t intr; // LCD peripheral interrupt handle esp_pm_lock_handle_t pm_lock; // lock APB frequency when necessary size_t num_dma_nodes; // Number of DMA descriptors + gdma_link_list_handle_t dma_link; // DMA link list handle uint8_t *format_buffer;// The driver allocates an internal buffer for DMA to do data format transformer unsigned long resolution_hz; // LCD_CLK resolution, determined by selected clock source lcd_i80_trans_descriptor_t *cur_trans; // Current transaction @@ -79,7 +83,6 @@ struct esp_lcd_i80_bus_t { struct { unsigned int exclusive: 1; // Indicate whether the I80 bus is owned by one device (whose CS GPIO is not assigned) exclusively } flags; - dma_descriptor_t dma_nodes[]; // DMA descriptor pool, the descriptors are shared by all i80 devices }; struct lcd_i80_trans_descriptor_t { @@ -137,18 +140,28 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc // because one I2S FIFO (4 bytes) will only contain two bytes of valid data max_transfer_bytes = max_transfer_bytes * 16 / bus_config->bus_width + 4; #endif - size_t num_dma_nodes = max_transfer_bytes / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; - // DMA descriptors must be placed in internal SRAM - bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t) + num_dma_nodes * sizeof(dma_descriptor_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + // allocate i80 bus memory + bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t), LCD_I80_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(bus, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 bus"); - bus->num_dma_nodes = num_dma_nodes; + size_t num_dma_nodes = max_transfer_bytes / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; + // create DMA link list + gdma_link_list_config_t dma_link_config = { + .buffer_alignment = 1, // no special buffer alignment for LCD TX buffer + .item_alignment = 4, // 4 bytes alignment for each DMA descriptor + .num_items = num_dma_nodes, + .flags = { + .check_owner = true, + }, + }; + ESP_GOTO_ON_ERROR(gdma_new_link_list(&dma_link_config, &bus->dma_link), err, TAG, "create DMA link list failed"); bus->bus_id = -1; + bus->num_dma_nodes = num_dma_nodes; #if SOC_I2S_TRANS_SIZE_ALIGN_WORD // transform format for LCD commands, parameters and color data, so we need a big buffer - bus->format_buffer = heap_caps_calloc(1, max_transfer_bytes, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + bus->format_buffer = heap_caps_calloc(1, max_transfer_bytes, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); #else // only transform format for LCD parameters, buffer size depends on specific LCD, set at compile time - bus->format_buffer = heap_caps_calloc(1, CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + bus->format_buffer = heap_caps_calloc(1, CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); #endif // SOC_I2S_TRANS_SIZE_ALIGN_WORD ESP_GOTO_ON_FALSE(bus->format_buffer, ESP_ERR_NO_MEM, err, TAG, "no mem for format buffer"); // LCD mode can't work with other modes at the same time, we need to register the driver object to the I2S platform @@ -207,11 +220,14 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc bus->dc_gpio_num = bus_config->dc_gpio_num; bus->wr_gpio_num = bus_config->wr_gpio_num; *ret_bus = bus; - ESP_LOGD(TAG, "new i80 bus(%d) @%p, %zu dma nodes, resolution %luHz", bus->bus_id, bus, bus->num_dma_nodes, bus->resolution_hz); + ESP_LOGD(TAG, "new i80 bus(%d) @%p, %zu dma nodes, resolution %luHz", bus->bus_id, bus, num_dma_nodes, bus->resolution_hz); return ESP_OK; err: if (bus) { + if (bus->dma_link) { + gdma_del_link_list(bus->dma_link); + } if (bus->intr) { esp_intr_free(bus->intr); } @@ -241,6 +257,7 @@ esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus) esp_pm_lock_delete(bus->pm_lock); } free(bus->format_buffer); + gdma_del_link_list(bus->dma_link); free(bus); ESP_LOGD(TAG, "del i80 bus(%d)", bus_id); err: @@ -497,7 +514,7 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons esp_lcd_i80_bus_t *bus = next_device->bus; lcd_panel_io_i80_t *cur_device = bus->cur_device; lcd_i80_trans_descriptor_t *trans_desc = NULL; - assert(param_size <= (bus->num_dma_nodes * DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "parameter bytes too long, enlarge max_transfer_bytes"); + assert(param_size <= (bus->num_dma_nodes * LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "parameter bytes too long, enlarge max_transfer_bytes"); assert(param_size <= CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE && "format buffer too small, increase CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE"); size_t num_trans_inflight = next_device->num_trans_inflight; // before issue a polling transaction, need to wait queued transactions finished @@ -507,6 +524,13 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons next_device->num_trans_inflight--; } + gdma_buffer_mount_config_t mount_config = { + .flags = { + .mark_eof = true, + .mark_final = true, // singly link list, mark final descriptor + } + }; + i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF); // switch devices if necessary lcd_i80_switch_devices(cur_device, next_device); @@ -519,7 +543,9 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons i2s_ll_tx_set_bits_mod(bus->hal.dev, 32); #endif i2s_lcd_prepare_cmd_buffer(trans_desc, &lcd_cmd); - lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length); + mount_config.buffer = (void *)trans_desc->data; + mount_config.length = trans_desc->data_length; + gdma_link_mount_buffers(bus->dma_link, 0, &mount_config, 1, NULL); gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_cmd_level); i2s_ll_tx_stop(bus->hal.dev); i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first @@ -539,7 +565,9 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons if (param && param_size) { i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF); i2s_lcd_prepare_param_buffer(trans_desc, param, param_size * 8 / next_device->lcd_param_bits); - lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length); + mount_config.buffer = (void *)trans_desc->data; + mount_config.length = trans_desc->data_length; + gdma_link_mount_buffers(bus->dma_link, 0, &mount_config, 1, NULL); gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_data_level); i2s_ll_tx_stop(bus->hal.dev); i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first @@ -563,7 +591,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons esp_lcd_i80_bus_t *bus = next_device->bus; lcd_panel_io_i80_t *cur_device = bus->cur_device; lcd_i80_trans_descriptor_t *trans_desc = NULL; - assert(color_size <= (bus->num_dma_nodes * DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "color bytes too long, enlarge max_transfer_bytes"); + assert(color_size <= (bus->num_dma_nodes * LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "color bytes too long, enlarge max_transfer_bytes"); size_t num_trans_inflight = next_device->num_trans_inflight; // before issue a polling transaction, need to wait queued transactions finished for (size_t i = 0; i < num_trans_inflight; i++) { @@ -572,6 +600,13 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons next_device->num_trans_inflight--; } + gdma_buffer_mount_config_t mount_config = { + .flags = { + .mark_eof = true, + .mark_final = true, // singly link list, mark final descriptor + } + }; + i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF); // switch devices if necessary lcd_i80_switch_devices(cur_device, next_device); @@ -584,7 +619,9 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons i2s_ll_tx_set_bits_mod(bus->hal.dev, 32); #endif i2s_lcd_prepare_cmd_buffer(trans_desc, &lcd_cmd); - lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length); + mount_config.buffer = (void *)trans_desc->data; + mount_config.length = trans_desc->data_length; + gdma_link_mount_buffers(bus->dma_link, 0, &mount_config, 1, NULL); gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_cmd_level); i2s_ll_tx_stop(bus->hal.dev); i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first @@ -640,15 +677,10 @@ static esp_err_t i2s_lcd_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c static esp_err_t i2s_lcd_init_dma_link(esp_lcd_i80_bus_handle_t bus) { - for (int i = 0; i < bus->num_dma_nodes; i++) { - bus->dma_nodes[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU; - bus->dma_nodes[i].next = &bus->dma_nodes[i + 1]; - } - bus->dma_nodes[bus->num_dma_nodes - 1].next = NULL; // one-off DMA chain i2s_ll_dma_enable_eof_on_fifo_empty(bus->hal.dev, true); i2s_ll_dma_enable_owner_check(bus->hal.dev, true); i2s_ll_dma_enable_auto_write_back(bus->hal.dev, true); - i2s_ll_set_out_link_addr(bus->hal.dev, (uint32_t)bus->dma_nodes); + i2s_ll_set_out_link_addr(bus->hal.dev, gdma_link_get_head_addr(bus->dma_link)); i2s_ll_enable_dma(bus->hal.dev, true); return ESP_OK; } @@ -691,7 +723,15 @@ static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus) // next time when esp_intr_enable is invoked, we can go into interrupt handler immediately // where we dispatch transactions for i80 devices static uint32_t fake_trigger = 0; - lcd_com_mount_dma_data(bus->dma_nodes, &fake_trigger, 4); + gdma_buffer_mount_config_t mount_config = { + .buffer = &fake_trigger, + .length = 4, + .flags = { + .mark_eof = true, // mark the "EOF" flag to trigger I2S EOF interrupt + .mark_final = true, // singly link list, mark final descriptor + } + }; + gdma_link_mount_buffers(bus->dma_link, 0, &mount_config, 1, NULL); i2s_ll_start_out_link(bus->hal.dev); i2s_ll_tx_start(bus->hal.dev); while (!(i2s_ll_get_intr_status(bus->hal.dev) & I2S_LL_EVENT_TX_EOF)) {} @@ -769,7 +809,15 @@ static IRAM_ATTR void lcd_default_isr_handler(void *args) bus->cur_trans = trans_desc; gpio_set_level(bus->dc_gpio_num, trans_desc->flags.dc_level); // mount data to DMA links - lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length); + gdma_buffer_mount_config_t mount_config = { + .buffer = (void *)trans_desc->data, + .length = trans_desc->data_length, + .flags = { + .mark_eof = true, + .mark_final = true, // singly link list, mark final descriptor + } + }; + gdma_link_mount_buffers(bus->dma_link, 0, &mount_config, 1, NULL); #if SOC_I2S_TRANS_SIZE_ALIGN_WORD // switch to I2S 16bits mode, two WS cycle <=> one I2S FIFO i2s_ll_tx_set_bits_mod(bus->hal.dev, 16);