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fix(mipi_dsi): only wait ready for enabled data lane

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This commit is contained in:
morris
2024-04-29 18:37:50 +08:00
parent 4c6b375666
commit 28073d9991
4 changed files with 21 additions and 6 deletions
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11
components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
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@@ -21,6 +21,8 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
{ {
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(bus_config->num_data_lanes <= MIPI_DSI_LL_MAX_DATA_LANES,
ESP_ERR_INVALID_ARG, TAG, "invalid number of data lanes %d", bus_config->num_data_lanes);
ESP_RETURN_ON_FALSE(bus_config->lane_bit_rate_mbps >= MIPI_DSI_LL_MIN_PHY_MBPS && ESP_RETURN_ON_FALSE(bus_config->lane_bit_rate_mbps >= MIPI_DSI_LL_MIN_PHY_MBPS &&
bus_config->lane_bit_rate_mbps <= MIPI_DSI_LL_MAX_PHY_MBPS, ESP_ERR_INVALID_ARG, TAG, bus_config->lane_bit_rate_mbps <= MIPI_DSI_LL_MAX_PHY_MBPS, ESP_ERR_INVALID_ARG, TAG,
"invalid lane bit rate %"PRIu32, bus_config->lane_bit_rate_mbps); "invalid lane bit rate %"PRIu32, bus_config->lane_bit_rate_mbps);
@@ -64,11 +66,16 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
esp_pm_lock_acquire(dsi_bus->pm_lock); esp_pm_lock_acquire(dsi_bus->pm_lock);
#endif #endif
// if the number of data lanes is not assigned, fallback to the maximum number of data lanes
int num_data_lanes = bus_config->num_data_lanes;
if (num_data_lanes == 0) {
num_data_lanes = MIPI_DSI_LL_MAX_DATA_LANES;
}
// initialize HAL context // initialize HAL context
mipi_dsi_hal_config_t hal_config = { mipi_dsi_hal_config_t hal_config = {
.bus_id = bus_id, .bus_id = bus_id,
.lane_bit_rate_mbps = bus_config->lane_bit_rate_mbps, .lane_bit_rate_mbps = bus_config->lane_bit_rate_mbps,
.num_data_lanes = bus_config->num_data_lanes, .num_data_lanes = num_data_lanes,
}; };
mipi_dsi_hal_init(&dsi_bus->hal, &hal_config); mipi_dsi_hal_init(&dsi_bus->hal, &hal_config);
mipi_dsi_hal_context_t *hal = &dsi_bus->hal; mipi_dsi_hal_context_t *hal = &dsi_bus->hal;
@@ -84,7 +91,7 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
while (!mipi_dsi_phy_ll_is_pll_locked(hal->host)) { while (!mipi_dsi_phy_ll_is_pll_locked(hal->host)) {
vTaskDelay(pdMS_TO_TICKS(1)); vTaskDelay(pdMS_TO_TICKS(1));
} }
while (!mipi_dsi_phy_ll_are_lanes_stopped(hal->host)) { while (!mipi_dsi_phy_ll_are_lanes_stopped(hal->host, num_data_lanes)) {
vTaskDelay(pdMS_TO_TICKS(1)); vTaskDelay(pdMS_TO_TICKS(1));
} }

2
components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
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@@ -21,7 +21,7 @@ extern "C" {
*/ */
typedef struct { typedef struct {
int bus_id; /*!< Select which DSI controller, index from 0 */ int bus_id; /*!< Select which DSI controller, index from 0 */
uint8_t num_data_lanes; /*!< Number of data lanes */ uint8_t num_data_lanes; /*!< Number of data lanes, if set to 0, the driver will fallback to use maximum number of lanes */
mipi_dsi_phy_clock_source_t phy_clk_src; /*!< MIPI DSI PHY clock source */ mipi_dsi_phy_clock_source_t phy_clk_src; /*!< MIPI DSI PHY clock source */
uint32_t lane_bit_rate_mbps; /*!< Lane bit rate in Mbps */ uint32_t lane_bit_rate_mbps; /*!< Lane bit rate in Mbps */
} esp_lcd_dsi_bus_config_t; } esp_lcd_dsi_bus_config_t;

3
components/hal/esp32p4/include/hal/mipi_dsi_ll.h
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@@ -14,7 +14,8 @@
#include "hal/mipi_dsi_brg_ll.h" #include "hal/mipi_dsi_brg_ll.h"
#include "hal/mipi_dsi_phy_ll.h" #include "hal/mipi_dsi_phy_ll.h"
#define MIPI_DSI_LL_NUM_BUS 1 // 1 MIPI DSI bus #define MIPI_DSI_LL_NUM_BUS 1 // support only 1 MIPI DSI bus
#define MIPI_DSI_LL_MAX_DATA_LANES 2 // support up to 2 data lanes
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

11
components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h
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@@ -81,12 +81,19 @@ static inline bool mipi_dsi_phy_ll_is_pll_locked(dsi_host_dev_t *dev)
* @brief Check if the all active lanes are in the stop state * @brief Check if the all active lanes are in the stop state
* *
* @param dev Pointer to the DSI Host controller register base address * @param dev Pointer to the DSI Host controller register base address
* @param num_data_lanes Number of data lanes
* @return True if the lanes are all in stop state, False otherwise * @return True if the lanes are all in stop state, False otherwise
*/ */
static inline bool mipi_dsi_phy_ll_are_lanes_stopped(dsi_host_dev_t *dev) static inline bool mipi_dsi_phy_ll_are_lanes_stopped(dsi_host_dev_t *dev, uint8_t num_data_lanes)
{ {
uint32_t status = dev->phy_status.val; uint32_t status = dev->phy_status.val;
const uint32_t mask = 1 << 2 | 1 << 4 | 1 << 7; uint32_t mask = 1 << 2;
if (num_data_lanes > 0) {
mask |= 1 << 4;
}
if (num_data_lanes > 1) {
mask |= 1 << 7;
}
return (status & mask) == mask; return (status & mask) == mask;
} }