From a6979eba9c0294927f4273db0109041a70e7b9a9 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Fri, 10 Jan 2025 14:13:16 +0530 Subject: [PATCH] feat: enabled aes and sha support for esp32h21 This commit enabled AES and SHA support for ESP32H21 --- .../esp32h21/include/esp32h21/rom/aes.h | 45 +++ components/hal/esp32h21/include/hal/aes_ll.h | 277 ++++++++++++++++++ components/hal/esp32h21/include/hal/sha_ll.h | 173 +++++++++++ .../esp32h21/include/soc/Kconfig.soc_caps.in | 12 + .../soc/esp32h21/include/soc/hwcrypto_reg.h | 12 + .../soc/esp32h21/include/soc/soc_caps.h | 6 +- .../soc/esp32h21/register/soc/aes_reg.h | 4 +- 7 files changed, 525 insertions(+), 4 deletions(-) create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/aes.h create mode 100644 components/hal/esp32h21/include/hal/aes_ll.h create mode 100644 components/hal/esp32h21/include/hal/sha_ll.h create mode 100644 components/soc/esp32h21/include/soc/hwcrypto_reg.h diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/aes.h b/components/esp_rom/esp32h21/include/esp32h21/rom/aes.h new file mode 100644 index 0000000000..6a33212503 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/aes.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_AES_H_ +#define _ROM_AES_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE 16 + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */ +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); + +int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_AES_H_ */ diff --git a/components/hal/esp32h21/include/hal/aes_ll.h b/components/hal/esp32h21/include/hal/aes_ll.h new file mode 100644 index 0000000000..40f159977f --- /dev/null +++ b/components/hal/esp32h21/include/hal/aes_ll.h @@ -0,0 +1,277 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/hwcrypto_reg.h" +#include "soc/pcr_struct.h" +#include "hal/aes_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief State of AES accelerator, busy, idle or done + * + */ +typedef enum { + ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */ + ESP_AES_STATE_BUSY, /* Transform in progress */ + ESP_AES_STATE_DONE, /* Transform completed */ +} esp_aes_state_t; + +/** + * @brief Enable the bus clock for AES peripheral module + * + * @param enable true to enable the module, false to disable the module + */ +static inline void aes_ll_enable_bus_clock(bool enable) +{ + PCR.aes_conf.aes_clk_en = enable; +} + +/** + * @brief Reset the AES peripheral module + */ +static inline void aes_ll_reset_register(void) +{ + PCR.aes_conf.aes_rst_en = 1; + PCR.aes_conf.aes_rst_en = 0; + + // Clear reset on digital signature also, otherwise AES is held in reset + PCR.ds_conf.ds_rst_en = 0; +} + +/** + * @brief Write the encryption/decryption key to hardware + * + * @param key Key to be written to the AES hardware + * @param key_word_len Number of words in the key + * + * @return Number of bytes written to hardware, used for fault injection check + */ +static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len) +{ + /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + volatile uint8_t key_in_hardware = 0; + /* Memcpy to avoid potential unaligned access */ + uint32_t key_word; + for (int i = 0; i < key_word_len; i++) { + memcpy(&key_word, key + 4 * i, 4); + REG_WRITE(AES_KEY_0_REG + i * 4, key_word); + key_in_hardware += 4; + } + return key_in_hardware; +} + +/** + * @brief Sets the mode + * + * @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0 + * @param key_bytes Number of bytes in the key + */ +static inline void aes_ll_set_mode(int mode, uint8_t key_bytes) +{ + const uint32_t MODE_DECRYPT_BIT = 4; + unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; + + /* See TRM for the mapping between keylength and mode bit */ + REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); +} + +/** + * @brief Writes message block to AES hardware + * + * @param input Block to be written + */ +static inline void aes_ll_write_block(const void *input) +{ + uint32_t input_word; + + for (int i = 0; i < AES_BLOCK_WORDS; i++) { + memcpy(&input_word, (uint8_t*)input + 4 * i, 4); + REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word); + } +} + +/** + * @brief Read the AES block + * + * @param output the output of the transform, length = AES_BLOCK_BYTES + */ +static inline void aes_ll_read_block(void *output) +{ + uint32_t output_word; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < AES_BLOCK_WORDS; i++) { + output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH)); + /* Memcpy to avoid potential unaligned access */ + memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word)); + } +} + +/** + * @brief Starts block transform + * + */ +static inline void aes_ll_start_transform(void) +{ + REG_WRITE(AES_TRIGGER_REG, 1); +} + + +/** + * @brief Read state of AES accelerator + * + * @return esp_aes_state_t + */ +static inline esp_aes_state_t aes_ll_get_state(void) +{ + return (esp_aes_state_t)REG_READ(AES_STATE_REG); +} + + +/** + * @brief Set mode of operation + * + * @note Only used for DMA transforms + * + * @param mode + */ +static inline void aes_ll_set_block_mode(esp_aes_mode_t mode) +{ + REG_WRITE(AES_BLOCK_MODE_REG, mode); +} + +/** + * @brief Set AES-CTR counter to INC32 + * + * @note Only affects AES-CTR mode + * + */ +static inline void aes_ll_set_inc(void) +{ + REG_WRITE(AES_INC_SEL_REG, 0); +} + +/** + * @brief Release the DMA + * + */ +static inline void aes_ll_dma_exit(void) +{ + REG_WRITE(AES_DMA_EXIT_REG, 0); +} + +/** + * @brief Sets the number of blocks to be transformed + * + * @note Only used for DMA transforms + * + * @param num_blocks Number of blocks to transform + */ +static inline void aes_ll_set_num_blocks(size_t num_blocks) +{ + REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); +} + +/* + * Write IV to hardware iv registers + */ +static inline void aes_ll_set_iv(const uint8_t *iv) +{ + uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM); + uint32_t iv_word; + + for (int i = 0; i < IV_WORDS; i++ ) { + /* Memcpy to avoid potential unaligned access */ + memcpy(&iv_word, iv + 4 * i, sizeof(iv_word)); + REG_WRITE(®_addr_buf[i], iv_word); + } +} + +/* + * Read IV from hardware iv registers + */ +static inline void aes_ll_read_iv(uint8_t *iv) +{ + uint32_t iv_word; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < IV_WORDS; i++) { + iv_word = REG_READ(AES_IV_MEM + (i * REG_WIDTH)); + /* Memcpy to avoid potential unaligned access */ + memcpy(iv + i * 4, &iv_word, sizeof(iv_word)); + } +} + +/** + * @brief Enable or disable DMA mode + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_dma_enable(bool enable) +{ + REG_WRITE(AES_DMA_ENABLE_REG, enable); +} + +/** + * @brief Enable or disable transform completed interrupt + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_interrupt_enable(bool enable) +{ + REG_WRITE(AES_INT_ENA_REG, enable); +} + +/** + * @brief Clears the interrupt + * + */ +static inline void aes_ll_interrupt_clear(void) +{ + REG_WRITE(AES_INT_CLEAR_REG, 1); +} + +/** + * @brief Enable the pseudo-round function during AES operations + * + * @param enable true to enable, false to disable + * @param base basic number of pseudo rounds, zero if disable + * @param increment increment number of pseudo rounds, zero if disable + * @param key_rng_cnt update frequency of the pseudo-key, zero if disable + */ +static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +{ + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable); + + if (enable) { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt); + } else { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0); + } +} + +/** + * @brief Check if the pseudo round function is supported + */ +static inline bool aes_ll_is_pseudo_rounds_function_supported(void) +{ + return true; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h21/include/hal/sha_ll.h b/components/hal/esp32h21/include/hal/sha_ll.h new file mode 100644 index 0000000000..29762922a1 --- /dev/null +++ b/components/hal/esp32h21/include/hal/sha_ll.h @@ -0,0 +1,173 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/hwcrypto_reg.h" +#include "soc/pcr_struct.h" +#include "hal/sha_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for SHA peripheral module + * + * @param enable true to enable the module, false to disable the module + */ +static inline void sha_ll_enable_bus_clock(bool enable) +{ + PCR.sha_conf.sha_clk_en = enable; +} + +/** + * @brief Reset the SHA peripheral module + */ +static inline void sha_ll_reset_register(void) +{ + PCR.sha_conf.sha_rst_en = 1; + PCR.sha_conf.sha_rst_en = 0; + + // Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset + PCR.ds_conf.ds_rst_en = 0; + PCR.hmac_conf.hmac_rst_en = 0; + PCR.ecdsa_conf.ecdsa_rst_en = 0; +} + +/** + * @brief Start a new SHA block conversions (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_START_REG, 1); +} + +/** + * @brief Continue a SHA block conversion (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_CONTINUE_REG, 1); +} + +/** + * @brief Start a new SHA message conversion using DMA (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_START_REG, 1); +} + +/** + * @brief Continue a SHA message conversion using DMA (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); +} + +/** + * @brief Load the current hash digest to digest register + * + * @note Happens automatically on ESP32H2 + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_load(esp_sha_type sha_type) +{ +} + +/** + * @brief Sets the number of message blocks to be hashed + * + * @note DMA operation only + * + * @param num_blocks Number of message blocks to process + */ +static inline void sha_ll_set_block_num(size_t num_blocks) +{ + REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks); +} + +/** + * @brief Checks if the SHA engine is currently busy hashing a block + * + * @return true SHA engine busy + * @return false SHA engine idle + */ +static inline bool sha_ll_busy(void) +{ + return REG_READ(SHA_BUSY_REG); +} + +/** + * @brief Write a text (message) block to the SHA engine + * + * @param input_text Input buffer to be written to the SHA engine + * @param block_word_len Number of words in block + */ +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) +{ + uint32_t *data_words = (uint32_t *)input_text; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM); + + for (int i = 0; i < block_word_len; i++) { + REG_WRITE(®_addr_buf[i], data_words[i]); + } +} + +/** + * @brief Read the message digest from the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Buffer that message digest will be written to + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < digest_word_len; i++) { + digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH)); + } + +} + +/** + * @brief Write the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM); + + for (int i = 0; i < digest_word_len; i++) { + REG_WRITE(®_addr_buf[i], digest_state_words[i]); + } +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index face9d8316..1d84edc1f5 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -43,6 +43,10 @@ config SOC_MPI_SUPPORTED bool default y +config SOC_SHA_SUPPORTED + bool + default y + config SOC_ECC_SUPPORTED bool default y @@ -63,6 +67,10 @@ config SOC_MODEM_CLOCK_SUPPORTED bool default y +config SOC_AES_SUPPORTED + bool + default y + config SOC_PAU_SUPPORTED bool default y @@ -87,6 +95,10 @@ config SOC_AES_SUPPORT_AES_256 bool default y +config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 diff --git a/components/soc/esp32h21/include/soc/hwcrypto_reg.h b/components/soc/esp32h21/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..e8af9c1d30 --- /dev/null +++ b/components/soc/esp32h21/include/soc/hwcrypto_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/aes_reg.h" +#include "soc/ds_reg.h" +#include "soc/hmac_reg.h" +#include "soc/rsa_reg.h" +#include "soc/sha_reg.h" diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 279e9f5207..ce568f4f1e 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -44,7 +44,7 @@ #define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598 // #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660 #define SOC_MPI_SUPPORTED 1 -// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501 +#define SOC_SHA_SUPPORTED 1 // #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495 // #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497 #define SOC_ECC_SUPPORTED 1 @@ -72,7 +72,7 @@ // #define SOC_ETM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11576 // #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572 // #define SOC_RMT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11622 -// #define SOC_AES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11504 +#define SOC_AES_SUPPORTED 1 // #define SOC_SDIO_SLAVE_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 // #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11517, IDF-11520 @@ -92,6 +92,8 @@ #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_256 (1) +#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1) + /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ // #define SOC_ADC_DIG_CTRL_SUPPORTED 1 diff --git a/components/soc/esp32h21/register/soc/aes_reg.h b/components/soc/esp32h21/register/soc/aes_reg.h index d8209c110c..dc47b6725d 100644 --- a/components/soc/esp32h21/register/soc/aes_reg.h +++ b/components/soc/esp32h21/register/soc/aes_reg.h @@ -210,11 +210,11 @@ extern "C" { /** AES_MODE : R/W; bitpos: [2:0]; default: 0; * Configures the key length and encryption / decryption of the AES accelerator. * 0: AES-128 encryption - * 1: AES-192 encryption + * 1: Reserved * 2: AES-256 encryption * 3: Reserved * 4: AES-128 decryption - * 5: AES-192 decryption + * 5: Reserved * 6: AES-256 decryption * 7: Reserved */