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component/bt : new coexist lib

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change boot loader.ld , the 0x40098000 may set other instructions
This commit is contained in:
Tian Hao
2016-10-17 15:47:45 +08:00
parent bee1be67da
commit 28fa3c1a70
4 changed files with 3 additions and 4 deletions
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2
components/bootloader/src/main/esp32.bootloader.ld
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@@ -15,7 +15,7 @@ MEMORY
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */ are connected to the data port of the CPU and eg allow bytewise access. */
dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */ dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */
iram_seg (RWX) : org = 0x40098000, len = 0x1000 iram_seg (RWX) : org = 0x4009A000, len = 0x1000
iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */ iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
} }

2
components/bt/lib

Submodule components/bt/lib updated: 079b86ab34...0c3df46cb3

2
components/esp32/lib

Submodule components/esp32/lib updated: ae7d66f7ed...0ee9babfd9

1
examples/07_blufi/main/demo_main.c
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@@ -113,7 +113,6 @@ void app_main()
{ {
esp_err_t ret; esp_err_t ret;
phy_set_wifi_mode_only(0);
nvs_flash_init(); nvs_flash_init();
system_init(); system_init();
initialise_wifi(); initialise_wifi();