diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h
index 768bbabdf2..ad09743b85 100644
--- a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h
+++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h
@@ -86,7 +86,6 @@ typedef enum {
     RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
     RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
-    SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
     EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
     USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core */
     USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core */
@@ -107,7 +106,6 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_
 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
-ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
 ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
diff --git a/components/esp_system/port/soc/esp32h21/reset_reason.c b/components/esp_system/port/soc/esp32h21/reset_reason.c
index c09a8de157..00f4255276 100644
--- a/components/esp_system/port/soc/esp32h21/reset_reason.c
+++ b/components/esp_system/port/soc/esp32h21/reset_reason.c
@@ -10,8 +10,6 @@
 #include "soc/rtc_periph.h"
 #include "esp32h21/rom/rtc.h"
 
-// TODO: [ESP32H21] IDF-11900, IDF-11910
-
 static void esp_reset_reason_clear_hint(void);
 
 static esp_reset_reason_t s_reset_reason;
@@ -43,7 +41,6 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
 
     case RESET_REASON_CORE_RTC_WDT:
     case RESET_REASON_SYS_RTC_WDT:
-    case RESET_REASON_SYS_SUPER_WDT:
     case RESET_REASON_CPU0_RTC_WDT:
     case RESET_REASON_CPU0_MWDT0:
     case RESET_REASON_CPU0_MWDT1:
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
index 491c3299b4..63bbdd9f5e 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -109,7 +109,11 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason]",
 static void do_exception(void)
 {
     setup_values();
-    *(int*)(0x0) = 0;
+#ifdef __XTENSA__
+    asm("ill");     // should be an invalid operation on xtensa targets
+#elif __riscv
+    asm("unimp");   // should be an invalid operation on RISC-V targets
+#endif
 }
 
 static void do_abort(void)