diff --git a/components/esp_rom/test_apps/.build-test-rules.yml b/components/esp_rom/test_apps/.build-test-rules.yml index 4f7be93788..7d6745313d 100644 --- a/components/esp_rom/test_apps/.build-test-rules.yml +++ b/components/esp_rom/test_apps/.build-test-rules.yml @@ -7,9 +7,6 @@ components/esp_rom/test_apps/linux_rom_apis: components/esp_rom/test_apps/rom_impl_components: disable: # For ROM impl build tests, disable them if none of the tested features are supported in the ROM - - if: CONFIG_NAME == "no_rom_impl_components" and IDF_TARGET == "esp32c5" - temporary: true - reason: build failed. track in IDFCI-2204 - if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: SOC_WDT_SUPPORTED != 1 diff --git a/components/esp_rom/test_apps/rom_impl_components/README.md b/components/esp_rom/test_apps/rom_impl_components/README.md index bf47d80ec6..3a502b1f86 100644 --- a/components/esp_rom/test_apps/rom_impl_components/README.md +++ b/components/esp_rom/test_apps/rom_impl_components/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index f13473b237..3008f15b62 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -28,76 +28,11 @@ #define CHECK_RTC_MEM 1 #endif //CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED -#if CONFIG_IDF_TARGET_ESP32 -#define DEEPSLEEP "DEEPSLEEP_RESET" -#define LOAD_STORE_ERROR "LoadStoreError" -#define RESET "SW_CPU_RESET" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "TG1WDT_SYS_RESET" -#define RTC_WDT "RTCWDT_RTC_RESET" -#if CONFIG_ESP32_REV_MIN_FULL >= 300 -#define BROWNOUT "RTCWDT_BROWN_OUT_RESET" -#else -#define BROWNOUT "SW_CPU_RESET" -#endif // CONFIG_ESP32_REV_MIN_FULL >= 300 -#define STORE_ERROR "StoreProhibited" -#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT - -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 -#define DEEPSLEEP "DSLEEP" -#define LOAD_STORE_ERROR "LoadStoreError" -#define RESET "RTC_SW_CPU_RST" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "TG1WDT_SYS_RST" -#define RTC_WDT "RTCWDT_RTC_RST" -#define BROWNOUT "BROWN_OUT_RST" -#define STORE_ERROR "StoreProhibited" -#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT - -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 -#define DEEPSLEEP "DSLEEP" -#define LOAD_STORE_ERROR "Store access fault" -#define RESET "RTC_SW_CPU_RST" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "TG1WDT_SYS_RST" -#define RTC_WDT "RTCWDT_RTC_RST" -#define BROWNOUT "BROWNOUT_RST" -#define STORE_ERROR LOAD_STORE_ERROR -#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT -#elif CONFIG_IDF_TARGET_ESP32C2 -#define DEEPSLEEP "DSLEEP" -#define LOAD_STORE_ERROR "Store access fault" -#define RESET "RTC_SW_CPU_RST" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "TG0WDT_SYS_RST" -#define RTC_WDT "RTCWDT_RTC_RST" -#define BROWNOUT "BROWNOUT_RST" -#define STORE_ERROR LOAD_STORE_ERROR -#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT - -#elif CONFIG_IDF_TARGET_ESP32C6 -#define DEEPSLEEP "DSLEEP" -#define LOAD_STORE_ERROR "Store access fault" -#define RESET "SW_CPU" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "TG1_WDT_HPSYS" -#define RTC_WDT "LP_WDT_SYS" -#define BROWNOUT "LP_BOD_SYS" -#define STORE_ERROR LOAD_STORE_ERROR -#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT - -#elif CONFIG_IDF_TARGET_ESP32P4 -#define DEEPSLEEP "DSLEEP" -#define LOAD_STORE_ERROR "Store access fault" -#define RESET "SW_CPU_RESET" -#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" -#define INT_WDT "HP_SYS_HP_WDT_RESET" -#define RTC_WDT "LP_WDT_SYS" -#define BROWNOUT "LP_BOD_SYS" -#define STORE_ERROR LOAD_STORE_ERROR +#if CONFIG_IDF_TARGET_ESP32P4 #define INT_WDT_HW_ESP_RST ESP_RST_WDT // On P4 there is only one reset reason for MWDT0/1 - -#endif // CONFIG_IDF_TARGET_ESP32 +#else +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT +#endif // CONFIG_IDF_TARGET_ESP32P4 /* This test needs special test runners: rev1 silicon, and SPI flash with * fast start-up time. Otherwise reset reason will be RTCWDT_RESET. @@ -165,7 +100,7 @@ static void check_reset_reason_deep_sleep(void) } -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][reset="DEEPSLEEP"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason]", do_deep_sleep, check_reset_reason_deep_sleep); @@ -198,11 +133,11 @@ static void check_reset_reason_panic(void) #endif //CHECK_RTC_MEM } -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after exception", "[reset_reason][reset="LOAD_STORE_ERROR","RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after exception", "[reset_reason]", do_exception, check_reset_reason_panic); -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after abort", "[reset_reason][reset=abort,"RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after abort", "[reset_reason]", do_abort, check_reset_reason_panic); @@ -236,12 +171,12 @@ static void check_reset_reason_sw(void) #endif //CHECK_RTC_MEM } -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart", "[reset_reason][reset="RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart", "[reset_reason]", do_restart, check_reset_reason_sw); #if CONFIG_FREERTOS_NUMBER_OF_CORES > 1 -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart from APP CPU", "[reset_reason][reset="RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart from APP CPU", "[reset_reason]", do_restart_from_app_cpu, check_reset_reason_sw); #endif @@ -286,12 +221,12 @@ static void check_reset_reason_int_wdt_hw(void) } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)", - "[reset_reason][reset="INT_WDT_PANIC","RESET"]", + "[reset_reason]", do_int_wdt, check_reset_reason_int_wdt_sw); TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (hw)", - "[reset_reason][reset="INT_WDT"]", + "[reset_reason]", do_int_wdt_hw, check_reset_reason_int_wdt_hw); @@ -324,7 +259,7 @@ static void check_reset_reason_task_wdt(void) } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog", - "[reset_reason][reset="RESET"]", + "[reset_reason]", do_task_wdt, check_reset_reason_task_wdt); #endif // CONFIG_ESP_TASK_WDT_EN @@ -352,7 +287,7 @@ static void check_reset_reason_any_wdt(void) } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_WDT after RTC watchdog", - "[reset_reason][reset="RTC_WDT"]", + "[reset_reason]", do_rtc_wdt, check_reset_reason_any_wdt); @@ -379,7 +314,7 @@ static void check_reset_reason_brownout(void) } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event", - "[reset_reason][ignore][reset="BROWNOUT"]", + "[reset_reason][ignore]", do_brownout, check_reset_reason_brownout); @@ -457,11 +392,11 @@ static void test2_finish(void) printf("test - OK\n"); } -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart in a task with spiram stack", "[spiram_stack][reset="RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart in a task with spiram stack", "[spiram_stack]", init_restart_task, test1_finish); -TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a task with spiram stack", "[spiram_stack][reset="STORE_ERROR","RESET"]", +TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a task with spiram stack", "[spiram_stack]", init_task_do_exception, test2_finish); diff --git a/components/hal/esp32c5/include/hal/lpwdt_ll.h b/components/hal/esp32c5/include/hal/lpwdt_ll.h index c2c5008bae..2df130e8f9 100644 --- a/components/hal/esp32c5/include/hal/lpwdt_ll.h +++ b/components/hal/esp32c5/include/hal/lpwdt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,9 +68,7 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Ad */ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_en = 1; - abort(); + hw->config0.wdt_en = 1; } /** @@ -83,9 +81,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_en = 0; - abort(); + hw->config0.wdt_en = 0; } /** @@ -96,10 +92,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // return (hw->config0.wdt_en) ? true : false; - abort(); - return (bool)0; + return (hw->config0.wdt_en) ? true : false; } /** @@ -122,29 +115,27 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) { - // TODO: [ESP32C5] IDF-8635 - // switch (stage) { - // case WDT_STAGE0: - // hw->config0.wdt_stg0 = behavior; - // //Account of implicty multiplier applied to stage 0 timeout tick config value - // hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); - // break; - // case WDT_STAGE1: - // hw->config0.wdt_stg1 = behavior; - // hw->config2.val = timeout_ticks; - // break; - // case WDT_STAGE2: - // hw->config0.wdt_stg2 = behavior; - // hw->config3.val = timeout_ticks; - // break; - // case WDT_STAGE3: - // hw->config0.wdt_stg3 = behavior; - // hw->config4.val = timeout_ticks; - // break; - // default: - // abort(); - // } - abort(); + switch (stage) { + case WDT_STAGE0: + hw->config0.wdt_stg0 = behavior; + //Account of implicty multiplier applied to stage 0 timeout tick config value + hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + break; + case WDT_STAGE1: + hw->config0.wdt_stg1 = behavior; + hw->config2.val = timeout_ticks; + break; + case WDT_STAGE2: + hw->config0.wdt_stg2 = behavior; + hw->config3.val = timeout_ticks; + break; + case WDT_STAGE3: + hw->config0.wdt_stg3 = behavior; + hw->config4.val = timeout_ticks; + break; + default: + abort(); + } } /** @@ -155,24 +146,22 @@ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage */ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) { - // TODO: [ESP32C5] IDF-8635 - // switch (stage) { - // case WDT_STAGE0: - // hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE1: - // hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE2: - // hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE3: - // hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF; - // break; - // default: - // abort(); - // } - abort(); + switch (stage) { + case WDT_STAGE0: + hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + abort(); + } } /** @@ -183,9 +172,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stag */ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_cpu_reset_length = length; - abort(); + hw->config0.wdt_cpu_reset_length = length; } /** @@ -196,9 +183,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset */ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_sys_reset_length = length; - abort(); + hw->config0.wdt_sys_reset_length = length; } /** @@ -213,9 +198,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset */ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; - abort(); + hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; } /** @@ -226,9 +209,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; - abort(); + hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; } /** @@ -239,9 +220,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enabl */ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; - abort(); + hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; } /** @@ -252,9 +231,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enabl */ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; - abort(); + hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; } /** @@ -268,9 +245,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool ena */ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; - abort(); + hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; } /** @@ -281,9 +256,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) { - // TODO: [ESP32C5] IDF-8635 - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); - abort(); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); } /** @@ -295,9 +268,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t */ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->feed.rtc_wdt_feed = 1; - abort(); + hw->feed.rtc_wdt_feed = 1; } /** @@ -307,9 +278,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->wprotect.val = 0; - abort(); + hw->wprotect.val = 0; } /** @@ -319,9 +288,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->wprotect.val = LP_WDT_WKEY_VALUE; - abort(); + hw->wprotect.val = LP_WDT_WKEY_VALUE; } /** @@ -332,9 +299,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 - // hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; - abort(); + hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; } /** @@ -345,10 +310,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // return (hw->int_st.lp_wdt_int_st) ? true : false; - abort(); - return (bool)0; + return (hw->int_st.lp_wdt_int_st) ? true : false; } /** @@ -358,9 +320,7 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 - // hw->int_clr.lp_wdt_int_clr = 1; - abort(); + hw->int_clr.lp_wdt_int_clr = 1; } #ifdef __cplusplus diff --git a/components/hal/esp32c5/include/hal/mwdt_ll.h b/components/hal/esp32c5/include/hal/mwdt_ll.h index c4e386a664..c4665a2eed 100644 --- a/components/hal/esp32c5/include/hal/mwdt_ll.h +++ b/components/hal/esp32c5/include/hal/mwdt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,7 @@ extern "C" { #include "hal/misc.h" /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */ -#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000 +#define MWDT_LL_DEFAULT_CLK_PRESCALER 24000 /* Possible values for TIMG_WDT_STGx */ #define TIMG_WDT_STG_SEL_OFF 0 @@ -64,9 +64,7 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, " */ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtconfig0.wdt_en = 1; - abort(); + hw->wdtconfig0.wdt_en = 1; } /** @@ -79,9 +77,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtconfig0.wdt_en = 0; - abort(); + hw->wdtconfig0.wdt_en = 0; } /** @@ -92,10 +88,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) */ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // return (hw->wdtconfig0.wdt_en) ? true : false; - abort(); - return (bool)0; + return (hw->wdtconfig0.wdt_en) ? true : false; } /** @@ -108,31 +101,29 @@ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) { - // TODO: [ESP32C5] IDF-8650 - // switch (stage) { - // case WDT_STAGE0: - // hw->wdtconfig0.wdt_stg0 = behavior; - // hw->wdtconfig2.wdt_stg0_hold = timeout; - // break; - // case WDT_STAGE1: - // hw->wdtconfig0.wdt_stg1 = behavior; - // hw->wdtconfig3.wdt_stg1_hold = timeout; - // break; - // case WDT_STAGE2: - // hw->wdtconfig0.wdt_stg2 = behavior; - // hw->wdtconfig4.wdt_stg2_hold = timeout; - // break; - // case WDT_STAGE3: - // hw->wdtconfig0.wdt_stg3 = behavior; - // hw->wdtconfig5.wdt_stg3_hold = timeout; - // break; - // default: - // HAL_ASSERT(false && "unsupported WDT stage"); - // break; - // } - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + switch (stage) { + case WDT_STAGE0: + hw->wdtconfig0.wdt_stg0 = behavior; + hw->wdtconfig2.wdt_stg0_hold = timeout; + break; + case WDT_STAGE1: + hw->wdtconfig0.wdt_stg1 = behavior; + hw->wdtconfig3.wdt_stg1_hold = timeout; + break; + case WDT_STAGE2: + hw->wdtconfig0.wdt_stg2 = behavior; + hw->wdtconfig4.wdt_stg2_hold = timeout; + break; + case WDT_STAGE3: + hw->wdtconfig0.wdt_stg3 = behavior; + hw->wdtconfig5.wdt_stg3_hold = timeout; + break; + default: + HAL_ASSERT(false && "unsupported WDT stage"); + break; + } + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -143,27 +134,25 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u */ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) { - // TODO: [ESP32C5] IDF-8650 - // switch (stage) { - // case WDT_STAGE0: - // hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE1: - // hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE2: - // hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; - // break; - // case WDT_STAGE3: - // hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; - // break; - // default: - // HAL_ASSERT(false && "unsupported WDT stage"); - // break; - // } - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + switch (stage) { + case WDT_STAGE0: + hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + HAL_ASSERT(false && "unsupported WDT stage"); + break; + } + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -174,11 +163,9 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) */ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtconfig0.wdt_cpu_reset_length = length; - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + hw->wdtconfig0.wdt_cpu_reset_length = length; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -189,11 +176,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si */ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtconfig0.wdt_sys_reset_length = length; - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + hw->wdtconfig0.wdt_sys_reset_length = length; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -208,11 +193,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si */ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -223,13 +206,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) { - // TODO: [ESP32C5] IDF-8650 - // // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) - // // We take care of the "read-modify-write" procedure by ourselves. - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); - // //Config registers are updated asynchronously - // hw->wdtconfig0.wdt_conf_update_en = 1; - abort(); + // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) + // We take care of the "read-modify-write" procedure by ourselves. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; } /** @@ -241,9 +222,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) */ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtfeed.wdt_feed = 1; - abort(); + hw->wdtfeed.wdt_feed = 1; } /** @@ -255,9 +234,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtwprotect.wdt_wkey = 0; - abort(); + hw->wdtwprotect.wdt_wkey = 0; } /** @@ -267,9 +244,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; - abort(); + hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; } /** @@ -279,9 +254,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 - // hw->int_clr_timers.wdt_int_clr = 1; - abort(); + hw->int_clr_timers.wdt_int_clr = 1; } /** @@ -292,9 +265,7 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8650 - // hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; - abort(); + hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; } /** @@ -305,28 +276,27 @@ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src) { - // TODO: [ESP32C5] IDF-8650 - // uint8_t clk_id = 0; - // switch (clk_src) { - // case MWDT_CLK_SRC_XTAL: - // clk_id = 0; - // break; - // case MWDT_CLK_SRC_PLL_F80M: - // clk_id = 1; - // break; - // case MWDT_CLK_SRC_RC_FAST: - // clk_id = 2; - // break; - // default: - // HAL_ASSERT(false); - // break; - // } - // // if (hw == &TIMERG0) { - // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id; - // } else { - // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id; - // } - abort(); + uint8_t clk_id = 0; + switch (clk_src) { + case MWDT_CLK_SRC_XTAL: + clk_id = 0; + break; + case MWDT_CLK_SRC_PLL_F80M: + clk_id = 1; + break; + case MWDT_CLK_SRC_RC_FAST: + clk_id = 2; + break; + default: + HAL_ASSERT(false); + break; + } + + if (hw == &TIMERG0) { + PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id; + } else { + PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id; + } } /** @@ -338,13 +308,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc __attribute__((always_inline)) static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) { - // TODO: [ESP32C5] IDF-8650 - // if (hw == &TIMERG0) { - // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en; - // } else { - // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en; - // } - abort(); + if (hw == &TIMERG0) { + PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en; + } else { + PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en; + } } diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 93af5d0285..62b05f280d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -147,6 +147,10 @@ config SOC_CLK_TREE_SUPPORTED bool default y +config SOC_WDT_SUPPORTED + bool + default y + config SOC_SPI_FLASH_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 05cb03e456..7772be7095 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -482,11 +482,11 @@ typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6 /** * @brief MWDT clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6) +typedef enum { MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ - MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL fixed 48 MHz as the default clock choice */ } soc_periph_mwdt_clk_src_t; //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index d4e4cea349..9ae9117a5c 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -67,7 +67,7 @@ // #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633 #define SOC_CLK_TREE_SUPPORTED 1 // #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663 -// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8650 +#define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 // #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8711 #define SOC_ECDSA_SUPPORTED 1