refactor(regi2c): ana i2c master clock is enabled per request

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -46,6 +46,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
@@ -94,6 +97,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -40,6 +40,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR   , 1);
@@ -88,6 +91,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 

components/bootloader_support/src/bootloader_random_esp32c61.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -45,6 +45,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR   , 1);
@@ -93,6 +96,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,9 @@ void bootloader_random_enable(void)
     // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
@@ -80,6 +83,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -62,6 +62,9 @@ void bootloader_random_enable(void)
 
     SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
 
     //  cfg pattern table
@@ -94,6 +97,9 @@ void bootloader_random_enable(void)
 
 void bootloader_random_disable(void)
 {
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // No-op for now TODO IDF-6497
     // ADC should be set to defaults here, once ADC API is implemented
     // OR just keep this empty and let application continue to use RNG initialized by the bootloader

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -85,7 +85,7 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -96,7 +96,7 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 }
 

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -86,7 +86,7 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -90,7 +90,7 @@ static inline void bootloader_hardware_init(void)
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
 
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 }
 

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -95,8 +95,7 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_enable_clock(true);
     regi2c_ctrl_ll_master_configure_clock();
 
     unsigned chip_version = efuse_hal_chip_revision();

components/driver/deprecated/adc_dma_legacy.c

@@ -27,6 +27,7 @@
 #include "hal/adc_hal.h"
 #include "hal/dma_types.h"
 #include "hal/adc_hal_common.h"
+#include "esp_private/regi2c_ctrl.h"
 
 #include "driver/gpio.h"
 #include "driver/adc_types_legacy.h"
@@ -212,6 +213,8 @@ esp_err_t adc_digi_deinitialize(void)
     }
 #endif  //CONFIG_PM_ENABLE
 
+    ANALOG_CLOCK_DISABLE();
+
     free(s_adc_digi_ctx->rx_dma_buf);
     free(s_adc_digi_ctx->hal.rx_desc);
     free(s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern);
@@ -355,6 +358,8 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
 
     adc_apb_periph_claim();
 
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_hal_calibration_init(ADC_UNIT_1);
     adc_hal_calibration_init(ADC_UNIT_2);

components/driver/deprecated/adc_legacy.c

@@ -28,6 +28,7 @@
 #include "hal/adc_ll.h"
 #include "hal/adc_hal_common.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/periph_ctrl.h"
 #include "driver/adc_types_legacy.h"
 #include "esp_clk_tree.h"
@@ -292,10 +293,6 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
     adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
     SARADC1_EXIT();
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-#endif
-
     return ESP_OK;
 }
 
@@ -385,11 +382,16 @@ int adc1_get_raw(adc1_channel_t channel)
     ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
     adc1_rtc_mode_acquire();
 
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
     adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_1, channel);
     adc_set_hw_calibration_code(ADC_UNIT_1, atten);
 #endif  //SOC_ADC_CALIBRATION_V1_SUPPORTED
 
+    ANALOG_CLOCK_DISABLE();
+
     SARADC1_ENTER();
 #ifdef CONFIG_IDF_TARGET_ESP32
     adc_ll_hall_disable(); //Disable other peripherals.
@@ -760,10 +762,6 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
     s_atten1_single[channel] = atten;
     ret = adc_digi_gpio_init(ADC_UNIT_1, BIT(channel));
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-#endif
-
     return ret;
 }
 
@@ -781,10 +779,16 @@ int adc1_get_raw(adc1_channel_t channel)
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
     adc_atten_t atten = s_atten1_single[channel];
+
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
     adc_set_hw_calibration_code(ADC_UNIT_1, atten);
 #endif
 
+    ANALOG_CLOCK_DISABLE();
+
     ADC_REG_LOCK_ENTER();
     adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
     adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out);
@@ -938,6 +942,7 @@ static void check_adc_oneshot_driver_conflict(void)
 ---------------------------------------------------------------*/
 static __attribute__((constructor)) void adc_hw_calibration(void)
 {
+    ANALOG_CLOCK_ENABLE();
     //Calculate all ICode
     for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
         adc_hal_calibration_init(i);
@@ -955,5 +960,6 @@ static __attribute__((constructor)) void adc_hw_calibration(void)
 #endif
         }
     }
+    ANALOG_CLOCK_DISABLE();
 }
 #endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED

components/driver/deprecated/rtc_temperature_legacy.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,6 @@
 #include "freertos/FreeRTOS.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
-#include "esp_log.h"
 #include "esp_efuse_rtc_calib.h"
 #include "hal/temperature_sensor_ll.h"
 #include "driver/temp_sensor_types_legacy.h"
@@ -111,6 +110,10 @@ esp_err_t temp_sensor_stop(void)
 esp_err_t temp_sensor_read_raw(uint32_t *tsens_out)
 {
     ESP_RETURN_ON_FALSE(tsens_out != NULL, ESP_ERR_INVALID_ARG, TAG, "no tsens_out specified");
+    if (tsens_hw_state != TSENS_HW_STATE_STARTED) {
+        ESP_LOGE(TAG, "Has not been started");
+        return ESP_ERR_INVALID_STATE;
+    }
     ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-use-of-uninitialized-value") // False-positive detection. TODO GCC-366
     *tsens_out = temperature_sensor_ll_get_raw_value();
     ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-use-of-uninitialized-value")

components/esp_adc/adc_common.c

@@ -15,6 +15,7 @@
 #include "driver/gpio.h"
 #include "hal/adc_hal.h"
 #include "hal/adc_hal_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "soc/adc_periph.h"
 
 static const char *TAG = "adc_common";
@@ -57,6 +58,7 @@ esp_err_t adc_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * con
 static __attribute__((constructor)) void adc_hw_calibration(void)
 {
     adc_apb_periph_claim();
+    ANALOG_CLOCK_ENABLE();
     //Calculate all ICode
     for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
         adc_hal_calibration_init(i);
@@ -74,5 +76,6 @@ static __attribute__((constructor)) void adc_hw_calibration(void)
 #endif
         }
     }
+    ANALOG_CLOCK_DISABLE();
 }
 #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED

components/esp_adc/adc_continuous.c

@@ -24,6 +24,7 @@
 #include "freertos/timers.h"
 #include "freertos/ringbuf.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/adc_private.h"
 #include "esp_private/adc_share_hw_ctrl.h"
@@ -242,11 +243,6 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi
 
     adc_apb_periph_claim();
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-    adc_hal_calibration_init(ADC_UNIT_2);
-#endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-
     return ret;
 
 cleanup:
@@ -259,6 +255,12 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
     ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
     ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
 
+    ANALOG_CLOCK_ENABLE();
+#if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
+    adc_hal_calibration_init(ADC_UNIT_2);
+#endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
+
     //reset ADC digital part to reset ADC sampling EOF counter
     ADC_BUS_CLK_ATOMIC() {
         adc_ll_reset_register();
@@ -356,6 +358,8 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
         ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed");
     }
 
+    ANALOG_CLOCK_DISABLE();
+
     return ESP_OK;
 }
 

components/esp_adc/adc_oneshot.c

@@ -23,6 +23,7 @@
 #include "esp_clk_tree.h"
 #include "esp_private/adc_private.h"
 #include "esp_private/adc_share_hw_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "esp_private/esp_clk_tree_common.h"
 #include "esp_private/esp_sleep_internal.h"
@@ -192,6 +193,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true);
 #endif
+    ANALOG_CLOCK_ENABLE();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
@@ -200,6 +202,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
 #endif  // SOC_ADC_CALIBRATION_V1_SUPPORTED
     bool valid = false;
     valid = adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    ANALOG_CLOCK_DISABLE();
 
     portEXIT_CRITICAL(&rtc_spinlock);
     adc_lock_release(handle->unit_id);
@@ -218,6 +221,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true);
 #endif
+    ANALOG_CLOCK_ENABLE();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
@@ -225,6 +229,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
     adc_set_hw_calibration_code(handle->unit_id, atten);
 #endif
     adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    ANALOG_CLOCK_DISABLE();
 
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 

components/esp_hw_support/include/esp_private/regi2c_ctrl.h

@@ -10,11 +10,50 @@
 #include "sdkconfig.h"
 #include "esp_rom_regi2c.h"
 #include "soc/regi2c_defs.h"
+#include "soc/soc_caps.h"
+#include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#ifdef BOOTLOADER_BUILD
+
+// For bootloader, the strategy is to keep the analog i2c master clock always enabled if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (in bootloader_hardware_init())
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+
+#else // !BOOTLOADER_BUILD
+
+#if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+// This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc.
+// Use reference count to manage the analog i2c master clock
+#define ANALOG_CLOCK_ENABLE() \
+      PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(true); \
+            } \
+      }
+
+#define ANALOG_CLOCK_DISABLE() \
+      PERIPH_RCC_RELEASE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(false); \
+            } \
+      }
+
+#else
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+#endif
+
+#endif // BOOTLOADER_BUILD
+
+// regi2c write/read requires analog i2c master clock enabled
+#define REGI2C_CLOCK_ENABLE()      ANALOG_CLOCK_ENABLE()
+#define REGI2C_CLOCK_DISABLE()     ANALOG_CLOCK_DISABLE()
+
 
 #define regi2c_read_reg_raw        esp_rom_regi2c_read
 #define regi2c_read_reg_mask_raw   esp_rom_regi2c_read_mask

components/esp_hw_support/modem_clock.c

@@ -18,6 +18,7 @@
 #include "hal/efuse_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
+#include "esp_private/regi2c_ctrl.h"
 
 // Please define the frequently called modules in the low bit,
 // which will improve the execution efficiency
@@ -118,7 +119,11 @@ static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context
 
 static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)
 {
-    regi2c_ctrl_ll_master_enable_clock(enable);
+    if (enable) {
+        ANALOG_CLOCK_ENABLE();
+    } else {
+        ANALOG_CLOCK_DISABLE();
+    }
 }
 
 static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable)

components/esp_hw_support/periph_ctrl.c

@@ -31,25 +31,25 @@ IRAM_ATTR void periph_rcc_exit(void)
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
 }
 
-uint8_t periph_rcc_acquire_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_acquire_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph];
 }
 
-void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ++ref_count;
     periph_rcc_exit();
 }
 
-uint8_t periph_rcc_release_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_release_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph] - 1;
 }
 
-void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ref_count;
     periph_rcc_exit();

components/esp_hw_support/port/esp32c5/rtc_clk.c

@@ -22,10 +22,7 @@
 #include "esp_private/sleep_event.h"
 #include "hal/efuse_hal.h"
 #include "soc/chip_revision.h"
-
+#include "esp_private/regi2c_ctrl.h"
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -133,27 +130,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -162,7 +145,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32c5/rtc_clk_init.c

@@ -79,6 +79,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+
     uint32_t hp_cali_dbias = get_act_hp_dbias();
     uint32_t lp_cali_dbias = get_act_lp_dbias();
 

components/esp_hw_support/port/esp32c6/ocode_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,10 +11,9 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
-
 static const char *TAG = "ocode_init";
 
 static void set_ocode_by_efuse(int ocode_scheme_ver)
@@ -57,6 +56,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -73,6 +73,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 

components/esp_hw_support/port/esp32c6/pmu_init.c

@@ -211,6 +211,7 @@ void pmu_init(void)
     /* Peripheral reg i2c power up */
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -139,25 +139,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -166,7 +154,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32c61/ocode_init.c

@@ -11,7 +11,7 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
 // TODO: IDF-9303
@@ -58,6 +58,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -74,6 +75,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 

components/esp_hw_support/port/esp32c61/rtc_clk.c

@@ -20,10 +20,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-
+#include "esp_private/regi2c_ctrl.h"
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -131,27 +128,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif  //SOC_MODEM_CLOCK_SUPPORTED
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -160,7 +143,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -155,25 +155,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -182,7 +170,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -21,6 +21,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/io_mux_reg.h"
 #include "esp_private/sleep_event.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -141,7 +142,9 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
 {
     /* Digital part */
     clk_ll_cpll_set_freq_mhz(cpll_freq);
+
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* CPLL CALIBRATION START */
     regi2c_ctrl_ll_cpll_calibration_start();
     clk_ll_cpll_set_config(cpll_freq, xtal_freq);
@@ -150,6 +153,7 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* CPLL CALIBRATION STOP */
     regi2c_ctrl_ll_cpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
 
     s_cur_cpll_freq = cpll_freq;
 }
@@ -362,34 +366,42 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
     }
 }
 
+static uint32_t rtc_clk_hp_root_get_freq_mhz(soc_cpu_clk_src_t clk_src)
+{
+    uint32_t source_freq_mhz = 0;
+    switch (clk_src) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+        break;
+    case SOC_CPU_CLK_SRC_CPLL:
+        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        source_freq_mhz = 20;
+        break;
+    default:
+        // Unknown HP_ROOT clock source
+        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
+        break;
+    }
+    return source_freq_mhz;
+}
+
 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
+    if (source_freq_mhz == 0) {
+        // unsupported frequency configuration
+        abort();
+    }
     hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
-    uint32_t freq_mhz;
     clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator);
     if (div.denominator == 0) {
         div.denominator = 1;
         div.numerator = 0;
     }
-    switch (source) {
+    uint32_t freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
-    case SOC_CPU_CLK_SRC_XTAL: {
-        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
-        break;
-    }
-    case SOC_CPU_CLK_SRC_CPLL: {
-        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
-        break;
-    }
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        source_freq_mhz = 20;
-        break;
-    default:
-        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
-        abort();
-    }
-    freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
     *out_config = (rtc_cpu_freq_config_t) {
         .source = source,
         .source_freq_mhz = source_freq_mhz,
@@ -447,23 +459,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
 uint32_t rtc_clk_apb_freq_get(void)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
-    switch (source) {
-    case SOC_CPU_CLK_SRC_XTAL:
-        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
-        break;
-    case SOC_CPU_CLK_SRC_CPLL:
-        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
-        break;
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        source_freq_mhz = 20;
-        break;
-    default:
-        // Unknown HP_ROOT clock source
-        source_freq_mhz = 0;
-        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
-        break;
-    }
     uint32_t integer, numerator, denominator;
     clk_ll_cpu_get_divider(&integer, &numerator, &denominator);
     if (denominator == 0) {
@@ -549,6 +545,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
     clk_ll_apll_set_config(o_div, sdm0, sdm1, sdm2);
 
     /* calibration */
+    ANALOG_CLOCK_ENABLE();
     clk_ll_apll_set_calibration();
 
     /* wait for calibration end */
@@ -556,6 +553,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
         /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
         esp_rom_delay_us(1);
     }
+    ANALOG_CLOCK_DISABLE();
 }
 
 void rtc_dig_clk8m_enable(void)
@@ -590,6 +588,7 @@ TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
 void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
 {
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* MPLL calibration start */
     regi2c_ctrl_ll_mpll_calibration_start();
     clk_ll_mpll_set_config(mpll_freq, xtal_freq);
@@ -597,6 +596,8 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
     while(!regi2c_ctrl_ll_mpll_calibration_is_done());
     /* MPLL calibration stop */
     regi2c_ctrl_ll_mpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_mpll_freq = mpll_freq;
 }
 

components/esp_hw_support/regi2c_ctrl.c

@@ -20,32 +20,40 @@ static DRAM_ATTR __attribute__((unused)) const char *TAG = "REGI2C";
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_raw(block, host_id, reg_add, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_enter_critical(void)

components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c

@@ -74,8 +74,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
-    regi2c_ctrl_ll_master_enable_clock(true);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c

@@ -85,8 +85,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
-    regi2c_ctrl_ll_master_enable_clock(true);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_regi2c_esp32c61.c

@@ -74,8 +74,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
-    regi2c_ctrl_ll_master_enable_clock(true);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_regi2c_esp32h2.c

@@ -86,7 +86,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_regi2c_esp32p4.c

@@ -87,8 +87,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
-    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // Right now this patch in rom can not depend on esp_hw_support, after IDF-10110 is done, this should be removed, should have spinlock protection
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
-    regi2c_ctrl_ll_master_enable_clock(true);
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0);
 

components/hal/esp32c5/include/hal/adc_ll.h

@@ -129,7 +129,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 

components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h

@@ -21,20 +21,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */

components/hal/esp32c6/include/hal/adc_ll.h

@@ -128,7 +128,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 

components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h

@@ -19,20 +19,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */

components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h

@@ -21,20 +21,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */

components/hal/esp32h2/include/hal/adc_ll.h

@@ -129,7 +129,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 

components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h

@@ -20,20 +20,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */

components/hal/esp32p4/include/hal/adc_ll.h

@@ -135,7 +135,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 

components/hal/esp32p4/include/hal/clk_tree_ll.h

@@ -347,7 +347,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u
     unsigned chip_version = efuse_hal_chip_revision();
     if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         return xtal_freq_mhz * (div + 4) / (ref_div + 1);
-    } else
+    }
     return xtal_freq_mhz * div / (ref_div + 1);
 }
 

components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h

@@ -21,25 +21,33 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     LPPERI.clk_en.ck_en_lp_i2cmst = en;
 }
 
 // LPPERI.clk_en is a shared register, so this function must be used in an atomic way
-#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return LPPERI.clk_en.ck_en_lp_i2cmst;
+}
 
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     LPPERI.reset_en.rst_en_lp_i2cmst = 1;
     LPPERI.reset_en.rst_en_lp_i2cmst = 0;
 }
 
 // LPPERI.reset_en is a shared register, so this function must be used in an atomic way
-#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
 
 /**
  * @brief Configure analog I2C master clock

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1427,6 +1427,10 @@ config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -597,6 +597,8 @@
 
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -1471,6 +1471,10 @@ config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -577,6 +577,8 @@
 
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -1039,6 +1039,10 @@ config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_WIFI_HW_TSF
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -467,6 +467,8 @@
 
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 // #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 // #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -1435,6 +1435,10 @@ config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -561,6 +561,8 @@
 
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1935,10 +1935,6 @@ config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y
 
-config SOC_MODEM_CLOCK_IS_INDEPENDENT
-    bool
-    default n
-
 config SOC_CLK_APLL_SUPPORTED
     bool
     default y
@@ -1967,6 +1963,10 @@ config SOC_PERIPH_CLK_CTRL_SHARED
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT
     bool
     default y

components/soc/esp32p4/include/soc/periph_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,9 +69,14 @@ typedef enum {
     PERIPH_UHCI_MODULE,
     PERIPH_PCNT_MODULE,
     PERIPH_ASSIST_DEBUG_MODULE,
+
     /* LP peripherals */
     PERIPH_LP_I2C0_MODULE,
     PERIPH_LP_UART0_MODULE,
+
+    /* MISC */
+    PERIPH_ANA_I2C_MASTER_MODULE,
+
     PERIPH_MODULE_MAX
 } periph_module_t;
 

components/soc/esp32p4/include/soc/soc_caps.h

@@ -728,7 +728,6 @@
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
-#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
 
 #define SOC_CLK_APLL_SUPPORTED                    (1)     /*!< Support Audio PLL */
 #define SOC_CLK_MPLL_SUPPORTED                    (1)     /*!< Support MSPI PLL */
@@ -740,6 +739,8 @@
 
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT                (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                  (1)