diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 052ad8d1d7..ce54b71127 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1606,3 +1606,7 @@ config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR config SOC_LP_CORE_SUPPORT_ETM bool default y + +config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS + bool + default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index f0268d7f38..2934a3d8e7 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -670,5 +670,6 @@ // #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ /*------------------------------------- ULP CAPS -------------------------------------*/ -#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */ -#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ +#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */ +#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ +#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */ diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index bb8beacb02..bbbd79ff16 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -2190,3 +2190,7 @@ config SOC_LP_CORE_SUPPORT_LP_ADC config SOC_LP_CORE_SUPPORT_LP_VAD bool default y + +config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS + bool + default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 2798dce731..8cea9db7c3 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -810,6 +810,7 @@ #define SOC_I3C_MASTER_COMMAND_TABLE_NUM (12) /*------------------------------------- ULP CAPS -------------------------------------*/ -#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ -#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */ -#define SOC_LP_CORE_SUPPORT_LP_VAD (1) /*!< LP VAD can be accessed from the LP-Core */ +#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ +#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */ +#define SOC_LP_CORE_SUPPORT_LP_VAD (1) /*!< LP VAD can be accessed from the LP-Core */ +#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */ diff --git a/components/ulp/Kconfig b/components/ulp/Kconfig index 29ea2b645f..f4728ad835 100644 --- a/components/ulp/Kconfig +++ b/components/ulp/Kconfig @@ -97,7 +97,7 @@ menu "Ultra Low Power (ULP) Co-processor" depends on ULP_COPROC_TYPE_LP_CORE && SOC_ULP_LP_UART_SUPPORTED bool prompt "Enable panic handler which outputs over LP UART" - default "y" if IDF_TARGET_ESP32P4 + default "y" if SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS help Set this option to enable panic handler functionality. If this option is enabled then the LP Core will output a panic dump over LP UART, diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 35b75c0cb8..a8ff663a16 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -273,6 +273,10 @@ examples/system/ulp/lp_core/build_system: examples/system/ulp/lp_core/debugging: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable: + - if: IDF_TARGET == "esp32c5" + temporary: true + reason: binary size too large TODO IDF-13063 depends_components: - ulp diff --git a/examples/system/ulp/lp_core/debugging/README.md b/examples/system/ulp/lp_core/debugging/README.md index 585d4233e8..3b2c99e071 100644 --- a/examples/system/ulp/lp_core/debugging/README.md +++ b/examples/system/ulp/lp_core/debugging/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C6 | ESP32-P4 | +| ----------------- | -------- | -------- | # LP Core Debugging Example